From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx list <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes
Date: Mon, 18 Jun 2018 15:52:55 -0400 [thread overview]
Message-ID: <CADnq5_M2fKOCWz6gmCeHqjKOwnC1BuxjO59G_MLLX9wq+dNTtg@mail.gmail.com> (raw)
In-Reply-To: <1529320685-20342-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> change function parameter type from dm_pp_wm_sets_with_clock_ranges * to
> void *. so this interface can be supported on AI/RV.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
but should probably be approved by the DC team as well.
Alex
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 2 +-
> drivers/gpu/drm/amd/display/dc/dm_services.h | 2 +-
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 +-
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +++---
> drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 4 ++--
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 3 ++-
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 ++-
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 ++-
> drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 2 +-
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +--
> 10 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> index 37f6a5f..92d36fe 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
> @@ -408,7 +408,7 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>
> bool dm_pp_notify_wm_clock_changes(
> const struct dc_context *ctx,
> - struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
> + void *clock_ranges)
> {
> /* TODO: to be implemented */
> return false;
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
> index 4ff9b2b..535b415 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
> @@ -217,7 +217,7 @@ bool dm_pp_get_clock_levels_by_type_with_voltage(
>
> bool dm_pp_notify_wm_clock_changes(
> const struct dc_context *ctx,
> - struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
> + void *clock_ranges);
>
> void dm_pp_get_funcs_rv(struct dc_context *ctx,
> struct pp_smu_funcs_rv *funcs);
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 4535756..06f7ef2 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -261,7 +261,7 @@ struct amd_pm_funcs {
> enum amd_pp_clock_type type,
> struct pp_clock_levels_with_voltage *clocks);
> int (*set_watermarks_for_clocks_ranges)(void *handle,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> + void *clock_ranges);
> int (*display_clock_voltage_request)(void *handle,
> struct pp_display_clock_request *clock);
> int (*get_display_mode_validation_clocks)(void *handle,
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 7b0ff9d..ba5e0e2 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1103,17 +1103,17 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
> }
>
> static int pp_set_watermarks_for_clocks_ranges(void *handle,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> + void *clock_ranges)
> {
> struct pp_hwmgr *hwmgr = handle;
> int ret = 0;
>
> - if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
> + if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
> return -EINVAL;
>
> mutex_lock(&hwmgr->smu_lock);
> ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
> - wm_with_clock_ranges);
> + clock_ranges);
> mutex_unlock(&hwmgr->smu_lock);
>
> return ret;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index a0bb921..53207e7 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -435,7 +435,7 @@ int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
> }
>
> int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> + void *clock_ranges)
> {
> PHM_FUNC_CHECK(hwmgr);
>
> @@ -443,7 +443,7 @@ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> return -EINVAL;
>
> return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
> - wm_with_clock_ranges);
> + clock_ranges);
> }
>
> int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 08690c9..4ca8033 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1131,9 +1131,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
> }
>
> static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> + void *clock_ranges)
> {
> struct smu10_hwmgr *data = hwmgr->backend;
> + struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
> Watermarks_t *table = &(data->water_marks_table);
> int result = 0;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 198c7ed..8554ede 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4195,9 +4195,10 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
> }
>
> static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> + void *clock_range)
> {
> struct vega10_hwmgr *data = hwmgr->backend;
> + struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
> Watermarks_t *table = &(data->smc_state_table.water_marks_table);
> int result = 0;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index d685ce7..bcb64cd 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1713,10 +1713,11 @@ static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
> }
>
> static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
> + void *clock_ranges)
> {
> struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
> Watermarks_t *table = &(data->smc_state_table.water_marks_table);
> + struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
> int result = 0;
> uint32_t i;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index a202247..429c9c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -455,7 +455,7 @@ extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
> enum amd_pp_clock_type type,
> struct pp_clock_levels_with_voltage *clocks);
> extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> + void *clock_ranges);
> extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
> struct pp_display_clock_request *clock);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index fe549ac..29d1481 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -293,8 +293,7 @@ struct pp_hwmgr_func {
> int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
> enum amd_pp_clock_type type,
> struct pp_clock_levels_with_voltage *clocks);
> - int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
> - struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> + int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
> int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
> struct pp_display_clock_request *clock);
> int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2018-06-18 19:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-18 11:18 [PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Rex Zhu
[not found] ` <1529320685-20342-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 11:18 ` [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display Rex Zhu
[not found] ` <1529320685-20342-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:50 ` Alex Deucher
2018-06-18 11:18 ` [PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10 Rex Zhu
[not found] ` <1529320685-20342-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:49 ` Alex Deucher
2018-06-18 11:18 ` [PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib Rex Zhu
[not found] ` <1529320685-20342-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:50 ` Alex Deucher
2018-06-18 11:18 ` [PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes Rex Zhu
[not found] ` <1529320685-20342-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:52 ` Alex Deucher [this message]
2018-06-18 19:46 ` [PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Alex Deucher
2018-06-18 23:53 ` Harry Wentland
2018-06-19 21:17 [PATCH 0/5] Rex's pplib/dc changes rebased on latest DC Harry Wentland
[not found] ` <20180619211732.10012-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-06-19 21:17 ` [PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes Harry Wentland
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CADnq5_M2fKOCWz6gmCeHqjKOwnC1BuxjO59G_MLLX9wq+dNTtg@mail.gmail.com \
--to=alexdeucher-re5jqeeqqe8avxtiumwx3w@public.gmane.org \
--cc=Rex.Zhu-5C7GfCeVMHo@public.gmane.org \
--cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.