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From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx list <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display
Date: Mon, 18 Jun 2018 15:50:59 -0400	[thread overview]
Message-ID: <CADnq5_MXSxD818gnPhx_Lu9rBp_cJ9f-oSsBn7VmwoSvzfNfaw@mail.gmail.com> (raw)
In-Reply-To: <1529320685-20342-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>

On Mon, Jun 18, 2018 at 7:18 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Transfer 10KHz (requested by smu) to KHz needed by Display
> component.
>
> This can fix the issue 4k Monitor can't be lit up on Vega/Raven.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c  |  4 ++--
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++-----
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 10 +++++-----
>  3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 6d5e042..08690c9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1014,7 +1014,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
>
>         clocks->num_levels = 0;
>         for (i = 0; i < pclk_vol_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
>                 clocks->data[i].latency_in_us = latency_required ?
>                                                 smu10_get_mem_latency(hwmgr,
>                                                 pclk_vol_table->entries[i].clk) :
> @@ -1065,7 +1065,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>
>         clocks->num_levels = 0;
>         for (i = 0; i < pclk_vol_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
>                 clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
>                 clocks->num_levels++;
>         }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index f97fce6..6057b59 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4067,7 +4067,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
>         for (i = 0; i < dep_table->count; i++) {
>                 if (dep_table->entries[i].clk) {
>                         clocks->data[clocks->num_levels].clocks_in_khz =
> -                                       dep_table->entries[i].clk;
> +                                       dep_table->entries[i].clk * 10;
>                         clocks->num_levels++;
>                 }
>         }
> @@ -4104,7 +4104,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
>                         clocks->data[clocks->num_levels].clocks_in_khz =
>                         data->mclk_latency_table.entries
>                         [data->mclk_latency_table.count].frequency =
> -                                       dep_table->entries[i].clk;
> +                                       dep_table->entries[i].clk * 10;
>                         clocks->data[clocks->num_levels].latency_in_us =
>                         data->mclk_latency_table.entries
>                         [data->mclk_latency_table.count].latency =
> @@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
>         uint32_t i;
>
>         for (i = 0; i < dep_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
>                 clocks->data[i].latency_in_us = 0;
>                 clocks->num_levels++;
>         }
> @@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
>         uint32_t i;
>
>         for (i = 0; i < dep_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
>                 clocks->data[i].latency_in_us = 0;
>                 clocks->num_levels++;
>         }
> @@ -4202,7 +4202,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>         }
>
>         for (i = 0; i < dep_table->count; i++) {
> -               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> +               clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
>                 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
>                                 entries[dep_table->entries[i].vddInd].us_vdd);
>                 clocks->num_levels++;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 782e209..d685ce7 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1576,7 +1576,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us = 0;
>         }
> @@ -1608,7 +1608,7 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us =
>                         data->mclk_latency_table.entries[i].latency =
> @@ -1638,7 +1638,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us = 0;
>         }
> @@ -1666,7 +1666,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
>
>         for (i = 0; i < ucount; i++) {
>                 clocks->data[i].clocks_in_khz =
> -                       dpm_table->dpm_levels[i].value * 100;
> +                       dpm_table->dpm_levels[i].value * 1000;
>
>                 clocks->data[i].latency_in_us = 0;
>         }
> @@ -1838,7 +1838,7 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
>                                 return -1);
>                 for (i = 0; i < clocks.num_levels; i++)
>                         size += sprintf(buf + size, "%d: %uMhz %s\n",
> -                               i, clocks.data[i].clocks_in_khz / 100,
> +                               i, clocks.data[i].clocks_in_khz / 1000,
>                                 (clocks.data[i].clocks_in_khz == now) ? "*" : "");
>                 break;
>
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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  parent reply	other threads:[~2018-06-18 19:50 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-18 11:18 [PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Rex Zhu
     [not found] ` <1529320685-20342-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 11:18   ` [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display Rex Zhu
     [not found]     ` <1529320685-20342-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:50       ` Alex Deucher [this message]
2018-06-18 11:18   ` [PATCH 3/5] drm/amd/pp: Memory Latency is always 25us on Vega10 Rex Zhu
     [not found]     ` <1529320685-20342-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:49       ` Alex Deucher
2018-06-18 11:18   ` [PATCH 4/5] drm/amd/display: Delete old implementation of bw_calcs_data_update_from_pplib Rex Zhu
     [not found]     ` <1529320685-20342-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:50       ` Alex Deucher
2018-06-18 11:18   ` [PATCH 5/5] drm/amd/display: Refine the interface dm_pp_notify_wm_clock_changes Rex Zhu
     [not found]     ` <1529320685-20342-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-06-18 19:52       ` Alex Deucher
2018-06-18 19:46   ` [PATCH 1/5] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Alex Deucher
2018-06-18 23:53   ` Harry Wentland
2018-06-19 21:17 [PATCH 0/5] Rex's pplib/dc changes rebased on latest DC Harry Wentland
     [not found] ` <20180619211732.10012-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-06-19 21:17   ` [PATCH 2/5] drm/amd/pp: Fix wrong clock-unit exported to Display Harry Wentland
     [not found]     ` <20180619211732.10012-3-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-06-20  3:47       ` Alex Deucher
     [not found]         ` <CADnq5_MubdXkZHwP982PvHLfrwCQo4KvFzk8egTdK4RGuCkY4g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-06-20 14:51           ` Zhu, Rex
     [not found]             ` <CY4PR12MB1687C87330C2D926DD39BC94FB770-rpdhrqHFk06Y0SjTqZDccQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-06-20 15:19               ` Alex Deucher

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