* [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init
@ 2020-02-28 14:39 Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 2/4] drm/scheduler: implement a function to modify sched list Nirmoy Das
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Nirmoy Das @ 2020-02-28 14:39 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Ray.Huang, nirmoy.das, christian.koenig
We were changing compute ring priority while rings were being used
before every job submission which is not recommended. This patch
sets compute queue priority at mqd initialization for gfx8, gfx9 and
gfx10.
Policy: make queue 0 of each pipe as high priority compute queue
High/normal priority compute sched lists are generated from set of high/normal
priority compute queues. At context creation, entity of compute queue
get a sched list from high or normal priority depending on ctx->priority
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++++++++++++++++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +++++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 13 +++++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 ----
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 +++++++++++
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 ++++++++++++
9 files changed, 113 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index f397ff97b4e4..8304d0c87899 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1205,7 +1205,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
struct drm_sched_entity *entity = p->entity;
enum drm_sched_priority priority;
- struct amdgpu_ring *ring;
struct amdgpu_bo_list_entry *e;
struct amdgpu_job *job;
uint64_t seq;
@@ -1258,9 +1257,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
priority = job->base.s_priority;
drm_sched_entity_push_job(&job->base, entity);
- ring = to_amdgpu_ring(entity->rq->sched);
- amdgpu_ring_priority_get(ring, priority);
-
amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 94a6c42f29ea..b21771b37300 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -85,8 +85,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const
num_scheds = 1;
break;
case AMDGPU_HW_IP_COMPUTE:
- scheds = adev->gfx.compute_sched;
- num_scheds = adev->gfx.num_compute_sched;
+ scheds = adev->gfx.compute_prio_sched[priority];
+ num_scheds = adev->gfx.num_compute_sched[priority];
break;
case AMDGPU_HW_IP_DMA:
scheds = adev->sdma.sdma_sched;
@@ -628,20 +628,46 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
mutex_destroy(&mgr->lock);
}
+
+static void amdgpu_ctx_init_compute_sched(struct amdgpu_device *adev)
+{
+ int num_compute_sched_normal = 0;
+ int num_compute_sched_high = AMDGPU_MAX_COMPUTE_RINGS - 1;
+ int i;
+
+
+ for (i = 0; i < adev->gfx.num_compute_rings; i++) {
+ if (adev->gfx.compute_ring[i].high_priority)
+ adev->gfx.compute_sched[num_compute_sched_normal++] =
+ &adev->gfx.compute_ring[i].sched;
+ else
+ adev->gfx.compute_sched[num_compute_sched_high--] =
+ &adev->gfx.compute_ring[i].sched;
+ }
+
+ for (i = DRM_SCHED_PRIORITY_MIN; i <= DRM_SCHED_PRIORITY_NORMAL; i++) {
+ adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0];
+ adev->gfx.num_compute_sched[i] = num_compute_sched_normal;
+ }
+
+ for (i = DRM_SCHED_PRIORITY_NORMAL + 1; i < DRM_SCHED_PRIORITY_MAX; i++) {
+ adev->gfx.compute_prio_sched[i] =
+ &adev->gfx.compute_sched[num_compute_sched_high - 1];
+ adev->gfx.num_compute_sched[i] =
+ adev->gfx.num_compute_rings - num_compute_sched_normal;
+ }
+}
+
void amdgpu_ctx_init_sched(struct amdgpu_device *adev)
{
int i, j;
+ amdgpu_ctx_init_compute_sched(adev);
for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;
adev->gfx.num_gfx_sched++;
}
- for (i = 0; i < adev->gfx.num_compute_rings; i++) {
- adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched;
- adev->gfx.num_compute_sched++;
- }
-
for (i = 0; i < adev->sdma.num_instances; i++) {
adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched;
adev->sdma.num_sdma_sched++;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 7403588684b3..952725e7243c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -192,6 +192,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
return adev->gfx.mec.num_mec > 1;
}
+bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
+ int queue)
+{
+ /* Policy: make queue 0 of each pipe as high priority compute queue */
+ return (queue == 0);
+
+}
+
void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
{
int i, queue, pipe, mec;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 37ba05b63b2a..f87b6df67694 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -41,6 +41,14 @@
#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
+#define AMDGPU_GFX_PIPE_PRIO_LOW 0
+#define AMDGPU_GFX_PIPE_PRIO_NORMAL 1
+#define AMDGPU_GFX_PIPE_PRIO_HIGH 2
+
+#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
+#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
+
+
struct amdgpu_mec {
struct amdgpu_bo *hpd_eop_obj;
u64 hpd_eop_gpu_addr;
@@ -280,8 +288,9 @@ struct amdgpu_gfx {
uint32_t num_gfx_sched;
unsigned num_gfx_rings;
struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
+ struct drm_gpu_scheduler **compute_prio_sched[DRM_SCHED_PRIORITY_MAX];
struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS];
- uint32_t num_compute_sched;
+ uint32_t num_compute_sched[DRM_SCHED_PRIORITY_MAX];
unsigned num_compute_rings;
struct amdgpu_irq_src eop_irq;
struct amdgpu_irq_src priv_reg_irq;
@@ -363,6 +372,8 @@ void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
int *mec, int *pipe, int *queue);
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
int pipe, int queue);
+bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
+ int queue);
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
int pipe, int queue);
void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index d42be880a236..4981e443a884 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -117,12 +117,10 @@ void amdgpu_job_free_resources(struct amdgpu_job *job)
static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
{
- struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
struct amdgpu_job *job = to_amdgpu_job(s_job);
drm_sched_job_cleanup(s_job);
- amdgpu_ring_priority_put(ring, s_job->s_priority);
dma_fence_put(job->fence);
amdgpu_sync_free(&job->sync);
amdgpu_sync_free(&job->sched_sync);
@@ -143,7 +141,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
void *owner, struct dma_fence **f)
{
enum drm_sched_priority priority;
- struct amdgpu_ring *ring;
int r;
if (!f)
@@ -158,9 +155,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
priority = job->base.s_priority;
drm_sched_entity_push_job(&job->base, entity);
- ring = to_amdgpu_ring(entity->rq->sched);
- amdgpu_ring_priority_get(ring, priority);
-
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 24caff085d00..34fcd467f18d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -222,6 +222,7 @@ struct amdgpu_ring {
struct mutex priority_mutex;
/* protected by priority_mutex */
int priority;
+ bool high_priority;
#if defined(CONFIG_DEBUG_FS)
struct dentry *ent;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 94ca9ffa0ccb..0e6ce65e1e54 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3211,6 +3211,22 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
return r;
}
+static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+ mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
+ ring->high_priority = true;
+ mqd->cp_hqd_queue_priority =
+ AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
+ }
+ else
+ ring->high_priority = false;
+ }
+}
+
static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
@@ -3336,6 +3352,9 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
mqd->cp_hqd_ib_control = tmp;
+ /* set static priority for a queue/ring */
+ gfx_v10_0_compute_mqd_set_priority(ring, mqd);
+
/* map_queues packet doesn't need activate the queue,
* so only kiq need set this field.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 393a1324daa9..6c4b7e49f97f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4430,6 +4430,22 @@ static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
return r;
}
+static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+ mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
+ ring->high_priority = true;
+ mqd->cp_hqd_queue_priority =
+ AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
+ }
+ else
+ ring->high_priority = false;
+ }
+}
+
static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
@@ -4553,9 +4569,6 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
/* defaults */
mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
- mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
- mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
- mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
@@ -4567,6 +4580,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
+ /* set static priority for a queue/ring */
+ gfx_v8_0_mqd_set_priority(ring, mqd);
+ mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+
/* map_queues packet doesn't need activate the queue,
* so only kiq need set this field.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 015647959d69..ff5e913f244d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3314,6 +3314,22 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
}
+static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
+ mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
+ ring->high_priority = true;
+ mqd->cp_hqd_queue_priority =
+ AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
+ }
+ else
+ ring->high_priority = false;
+ }
+}
+
static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
@@ -3450,6 +3466,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
mqd->cp_hqd_ib_control = tmp;
+ /* set static priority for a queue/ring */
+ gfx_v9_0_mqd_set_priority(ring, mqd);
+ mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+
/* map_queues packet doesn't need activate the queue,
* so only kiq need set this field.
*/
--
2.25.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/4] drm/scheduler: implement a function to modify sched list
2020-02-28 14:39 [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Nirmoy Das
@ 2020-02-28 14:39 ` Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 3/4] drm/amdgpu: change hw sched list on ctx priority override Nirmoy Das
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Nirmoy Das @ 2020-02-28 14:39 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Ray.Huang, nirmoy.das, christian.koenig
implement drm_sched_entity_modify_sched() which can modify existing
sched_list with a different one. This is going to be helpful when
userspace changes priority of a ctx/entity then driver can switch to
corresponding hw shced list for that priority
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/scheduler/sched_entity.c | 19 +++++++++++++++++++
include/drm/gpu_scheduler.h | 4 ++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
index 63bccd201b97..b94312154e56 100644
--- a/drivers/gpu/drm/scheduler/sched_entity.c
+++ b/drivers/gpu/drm/scheduler/sched_entity.c
@@ -83,6 +83,25 @@ int drm_sched_entity_init(struct drm_sched_entity *entity,
}
EXPORT_SYMBOL(drm_sched_entity_init);
+/**
+ * drm_sched_entity_modify_sched - Modify sched of an entity
+ *
+ * @entity: scheduler entity to init
+ * @sched_list: the list of new drm scheds which will replace
+ * existing entity->sched_list
+ * @num_sched_list: number of drm sched in sched_list
+ */
+void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
+ struct drm_gpu_scheduler **sched_list,
+ unsigned int num_sched_list)
+{
+ WARN_ON(!num_sched_list || !sched_list);
+
+ entity->sched_list = sched_list;
+ entity->num_sched_list = num_sched_list;
+}
+EXPORT_SYMBOL(drm_sched_entity_modify_sched);
+
/**
* drm_sched_entity_is_idle - Check if entity is idle
*
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 589be851f8a1..f70a84aaaf7a 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -297,6 +297,10 @@ void drm_sched_fini(struct drm_gpu_scheduler *sched);
int drm_sched_job_init(struct drm_sched_job *job,
struct drm_sched_entity *entity,
void *owner);
+void drm_sched_entity_modify_sched(struct drm_sched_entity *entity,
+ struct drm_gpu_scheduler **sched_list,
+ unsigned int num_sched_list);
+
void drm_sched_job_cleanup(struct drm_sched_job *job);
void drm_sched_wakeup(struct drm_gpu_scheduler *sched);
void drm_sched_stop(struct drm_gpu_scheduler *sched, struct drm_sched_job *bad);
--
2.25.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/4] drm/amdgpu: change hw sched list on ctx priority override
2020-02-28 14:39 [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 2/4] drm/scheduler: implement a function to modify sched list Nirmoy Das
@ 2020-02-28 14:39 ` Nirmoy Das
2020-02-28 14:39 ` [PATCH 4/4] drm/amdgpu: remove unused functions Nirmoy Das
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Nirmoy Das @ 2020-02-28 14:39 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Ray.Huang, nirmoy.das, christian.koenig
Switch to appropriate sched list for an entity on priority override.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 27 +++++++++++++++++++++----
1 file changed, 23 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index b21771b37300..3744c689affc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -502,6 +502,27 @@ struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
return fence;
}
+static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx,
+ struct amdgpu_ctx_entity *aentity,
+ int hw_ip, enum drm_sched_priority priority)
+{
+ struct amdgpu_device *adev = ctx->adev;
+ struct drm_gpu_scheduler **scheds = NULL;
+ unsigned num_scheds = 0;
+
+ switch (hw_ip) {
+ case AMDGPU_HW_IP_COMPUTE:
+ scheds = adev->gfx.compute_prio_sched[priority];
+ num_scheds = adev->gfx.num_compute_sched[priority];
+ break;
+ default:
+ return;
+ }
+
+ drm_sched_entity_modify_sched(&aentity->entity, scheds, num_scheds);
+ drm_sched_entity_set_priority(&aentity->entity, priority);
+}
+
void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
enum drm_sched_priority priority)
{
@@ -514,13 +535,11 @@ void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
ctx->init_priority : ctx->override_priority;
for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) {
for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) {
- struct drm_sched_entity *entity;
-
if (!ctx->entities[i][j])
continue;
- entity = &ctx->entities[i][j]->entity;
- drm_sched_entity_set_priority(entity, ctx_prio);
+ amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j],
+ i, ctx_prio);
}
}
}
--
2.25.0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/4] drm/amdgpu: remove unused functions
2020-02-28 14:39 [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 2/4] drm/scheduler: implement a function to modify sched list Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 3/4] drm/amdgpu: change hw sched list on ctx priority override Nirmoy Das
@ 2020-02-28 14:39 ` Nirmoy Das
2020-02-28 14:44 ` [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Christian König
2020-02-28 15:56 ` Alex Deucher
4 siblings, 0 replies; 7+ messages in thread
From: Nirmoy Das @ 2020-02-28 14:39 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Ray.Huang, nirmoy.das, christian.koenig
amdgpu statically set priority for compute queues
at initialization so remove all the functions
responsible changing compute queue priority dynamically
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 70 ----------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 7 --
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 99 ----------------------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 100 -----------------------
4 files changed, 276 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index ca6b52054b4b..a7e1d0425ed0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -150,76 +150,6 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring)
ring->funcs->end_use(ring);
}
-/**
- * amdgpu_ring_priority_put - restore a ring's priority
- *
- * @ring: amdgpu_ring structure holding the information
- * @priority: target priority
- *
- * Release a request for executing at @priority
- */
-void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
- enum drm_sched_priority priority)
-{
- int i;
-
- if (!ring->funcs->set_priority)
- return;
-
- if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
- return;
-
- /* no need to restore if the job is already at the lowest priority */
- if (priority == DRM_SCHED_PRIORITY_NORMAL)
- return;
-
- mutex_lock(&ring->priority_mutex);
- /* something higher prio is executing, no need to decay */
- if (ring->priority > priority)
- goto out_unlock;
-
- /* decay priority to the next level with a job available */
- for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) {
- if (i == DRM_SCHED_PRIORITY_NORMAL
- || atomic_read(&ring->num_jobs[i])) {
- ring->priority = i;
- ring->funcs->set_priority(ring, i);
- break;
- }
- }
-
-out_unlock:
- mutex_unlock(&ring->priority_mutex);
-}
-
-/**
- * amdgpu_ring_priority_get - change the ring's priority
- *
- * @ring: amdgpu_ring structure holding the information
- * @priority: target priority
- *
- * Request a ring's priority to be raised to @priority (refcounted).
- */
-void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
- enum drm_sched_priority priority)
-{
- if (!ring->funcs->set_priority)
- return;
-
- if (atomic_inc_return(&ring->num_jobs[priority]) <= 0)
- return;
-
- mutex_lock(&ring->priority_mutex);
- if (priority <= ring->priority)
- goto out_unlock;
-
- ring->priority = priority;
- ring->funcs->set_priority(ring, priority);
-
-out_unlock:
- mutex_unlock(&ring->priority_mutex);
-}
-
/**
* amdgpu_ring_init - init driver ring struct.
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 34fcd467f18d..87ec35b68bfd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -167,9 +167,6 @@ struct amdgpu_ring_funcs {
uint32_t reg0, uint32_t reg1,
uint32_t ref, uint32_t mask);
void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
- /* priority functions */
- void (*set_priority) (struct amdgpu_ring *ring,
- enum drm_sched_priority priority);
/* Try to soft recover the ring to make the fence signal */
void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
int (*preempt_ib)(struct amdgpu_ring *ring);
@@ -259,10 +256,6 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
-void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
- enum drm_sched_priority priority);
-void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
- enum drm_sched_priority priority);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
unsigned ring_size, struct amdgpu_irq_src *irq_src,
unsigned irq_type);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6c4b7e49f97f..ed9aff72350d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6275,104 +6275,6 @@ static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
}
-static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
- bool acquire)
-{
- struct amdgpu_device *adev = ring->adev;
- int pipe_num, tmp, reg;
- int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
-
- pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
-
- /* first me only has 2 entries, GFX and HP3D */
- if (ring->me > 0)
- pipe_num -= 2;
-
- reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
- tmp = RREG32(reg);
- tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
- WREG32(reg, tmp);
-}
-
-static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
- struct amdgpu_ring *ring,
- bool acquire)
-{
- int i, pipe;
- bool reserve;
- struct amdgpu_ring *iring;
-
- mutex_lock(&adev->gfx.pipe_reserve_mutex);
- pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0);
- if (acquire)
- set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
- else
- clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
-
- if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
- /* Clear all reservations - everyone reacquires all resources */
- for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
- gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
- true);
-
- for (i = 0; i < adev->gfx.num_compute_rings; ++i)
- gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
- true);
- } else {
- /* Lower all pipes without a current reservation */
- for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
- iring = &adev->gfx.gfx_ring[i];
- pipe = amdgpu_gfx_mec_queue_to_bit(adev,
- iring->me,
- iring->pipe,
- 0);
- reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
- gfx_v8_0_ring_set_pipe_percent(iring, reserve);
- }
-
- for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
- iring = &adev->gfx.compute_ring[i];
- pipe = amdgpu_gfx_mec_queue_to_bit(adev,
- iring->me,
- iring->pipe,
- 0);
- reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
- gfx_v8_0_ring_set_pipe_percent(iring, reserve);
- }
- }
-
- mutex_unlock(&adev->gfx.pipe_reserve_mutex);
-}
-
-static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
- struct amdgpu_ring *ring,
- bool acquire)
-{
- uint32_t pipe_priority = acquire ? 0x2 : 0x0;
- uint32_t queue_priority = acquire ? 0xf : 0x0;
-
- mutex_lock(&adev->srbm_mutex);
- vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-
- WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
- WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
-
- vi_srbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
-}
-static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
- enum drm_sched_priority priority)
-{
- struct amdgpu_device *adev = ring->adev;
- bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
-
- if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
- return;
-
- gfx_v8_0_hqd_set_priority(adev, ring, acquire);
- gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
-}
-
static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
u64 addr, u64 seq,
unsigned flags)
@@ -7005,7 +6907,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
.test_ib = gfx_v8_0_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
- .set_priority = gfx_v8_0_ring_set_priority_compute,
.emit_wreg = gfx_v8_0_ring_emit_wreg,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ff5e913f244d..a662c4712b1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5130,105 +5130,6 @@ static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
return wptr;
}
-static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
- bool acquire)
-{
- struct amdgpu_device *adev = ring->adev;
- int pipe_num, tmp, reg;
- int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
-
- pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
-
- /* first me only has 2 entries, GFX and HP3D */
- if (ring->me > 0)
- pipe_num -= 2;
-
- reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
- tmp = RREG32(reg);
- tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
- WREG32(reg, tmp);
-}
-
-static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
- struct amdgpu_ring *ring,
- bool acquire)
-{
- int i, pipe;
- bool reserve;
- struct amdgpu_ring *iring;
-
- mutex_lock(&adev->gfx.pipe_reserve_mutex);
- pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0);
- if (acquire)
- set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
- else
- clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
-
- if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
- /* Clear all reservations - everyone reacquires all resources */
- for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
- gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
- true);
-
- for (i = 0; i < adev->gfx.num_compute_rings; ++i)
- gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
- true);
- } else {
- /* Lower all pipes without a current reservation */
- for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
- iring = &adev->gfx.gfx_ring[i];
- pipe = amdgpu_gfx_mec_queue_to_bit(adev,
- iring->me,
- iring->pipe,
- 0);
- reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
- gfx_v9_0_ring_set_pipe_percent(iring, reserve);
- }
-
- for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
- iring = &adev->gfx.compute_ring[i];
- pipe = amdgpu_gfx_mec_queue_to_bit(adev,
- iring->me,
- iring->pipe,
- 0);
- reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
- gfx_v9_0_ring_set_pipe_percent(iring, reserve);
- }
- }
-
- mutex_unlock(&adev->gfx.pipe_reserve_mutex);
-}
-
-static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
- struct amdgpu_ring *ring,
- bool acquire)
-{
- uint32_t pipe_priority = acquire ? 0x2 : 0x0;
- uint32_t queue_priority = acquire ? 0xf : 0x0;
-
- mutex_lock(&adev->srbm_mutex);
- soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
-
- WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
- WREG32_SOC15_RLC(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
-
- soc15_grbm_select(adev, 0, 0, 0, 0);
- mutex_unlock(&adev->srbm_mutex);
-}
-
-static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
- enum drm_sched_priority priority)
-{
- struct amdgpu_device *adev = ring->adev;
- bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
-
- if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
- return;
-
- gfx_v9_0_hqd_set_priority(adev, ring, acquire);
- gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
-}
-
static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
@@ -6599,7 +6500,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
.test_ib = gfx_v9_0_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
.pad_ib = amdgpu_ring_generic_pad_ib,
- .set_priority = gfx_v9_0_ring_set_priority_compute,
.emit_wreg = gfx_v9_0_ring_emit_wreg,
.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
--
2.25.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init
2020-02-28 14:39 [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Nirmoy Das
` (2 preceding siblings ...)
2020-02-28 14:39 ` [PATCH 4/4] drm/amdgpu: remove unused functions Nirmoy Das
@ 2020-02-28 14:44 ` Christian König
2020-02-28 15:22 ` Nirmoy
2020-02-28 15:56 ` Alex Deucher
4 siblings, 1 reply; 7+ messages in thread
From: Christian König @ 2020-02-28 14:44 UTC (permalink / raw)
To: Nirmoy Das, amd-gfx; +Cc: alexander.deucher, Ray.Huang, nirmoy.das
Am 28.02.20 um 15:39 schrieb Nirmoy Das:
> We were changing compute ring priority while rings were being used
> before every job submission which is not recommended. This patch
> sets compute queue priority at mqd initialization for gfx8, gfx9 and
> gfx10.
>
> Policy: make queue 0 of each pipe as high priority compute queue
>
> High/normal priority compute sched lists are generated from set of high/normal
> priority compute queues. At context creation, entity of compute queue
> get a sched list from high or normal priority depending on ctx->priority
>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++++++++++++++++++-----
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 13 +++++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 ----
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 +++++++++++
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 ++++++++++++
> 9 files changed, 113 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index f397ff97b4e4..8304d0c87899 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1205,7 +1205,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> struct drm_sched_entity *entity = p->entity;
> enum drm_sched_priority priority;
> - struct amdgpu_ring *ring;
> struct amdgpu_bo_list_entry *e;
> struct amdgpu_job *job;
> uint64_t seq;
> @@ -1258,9 +1257,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> priority = job->base.s_priority;
> drm_sched_entity_push_job(&job->base, entity);
>
> - ring = to_amdgpu_ring(entity->rq->sched);
> - amdgpu_ring_priority_get(ring, priority);
> -
> amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
>
> ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index 94a6c42f29ea..b21771b37300 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -85,8 +85,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const
> num_scheds = 1;
> break;
> case AMDGPU_HW_IP_COMPUTE:
> - scheds = adev->gfx.compute_sched;
> - num_scheds = adev->gfx.num_compute_sched;
> + scheds = adev->gfx.compute_prio_sched[priority];
> + num_scheds = adev->gfx.num_compute_sched[priority];
> break;
> case AMDGPU_HW_IP_DMA:
> scheds = adev->sdma.sdma_sched;
> @@ -628,20 +628,46 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
> mutex_destroy(&mgr->lock);
> }
>
> +
> +static void amdgpu_ctx_init_compute_sched(struct amdgpu_device *adev)
> +{
> + int num_compute_sched_normal = 0;
> + int num_compute_sched_high = AMDGPU_MAX_COMPUTE_RINGS - 1;
> + int i;
> +
> +
> + for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> + if (adev->gfx.compute_ring[i].high_priority)
> + adev->gfx.compute_sched[num_compute_sched_normal++] =
> + &adev->gfx.compute_ring[i].sched;
> + else
> + adev->gfx.compute_sched[num_compute_sched_high--] =
> + &adev->gfx.compute_ring[i].sched;
> + }
> +
> + for (i = DRM_SCHED_PRIORITY_MIN; i <= DRM_SCHED_PRIORITY_NORMAL; i++) {
> + adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0];
> + adev->gfx.num_compute_sched[i] = num_compute_sched_normal;
> + }
> +
> + for (i = DRM_SCHED_PRIORITY_NORMAL + 1; i < DRM_SCHED_PRIORITY_MAX; i++) {
> + adev->gfx.compute_prio_sched[i] =
> + &adev->gfx.compute_sched[num_compute_sched_high - 1];
> + adev->gfx.num_compute_sched[i] =
> + adev->gfx.num_compute_rings - num_compute_sched_normal;
> + }
> +}
> +
> void amdgpu_ctx_init_sched(struct amdgpu_device *adev)
> {
> int i, j;
>
> + amdgpu_ctx_init_compute_sched(adev);
> for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;
> adev->gfx.num_gfx_sched++;
> }
>
> - for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> - adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched;
> - adev->gfx.num_compute_sched++;
> - }
> -
> for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched;
> adev->sdma.num_sdma_sched++;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 7403588684b3..952725e7243c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -192,6 +192,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> return adev->gfx.mec.num_mec > 1;
> }
>
> +bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> + int queue)
> +{
> + /* Policy: make queue 0 of each pipe as high priority compute queue */
> + return (queue == 0);
> +
> +}
> +
> void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
> {
> int i, queue, pipe, mec;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 37ba05b63b2a..f87b6df67694 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -41,6 +41,14 @@
> #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
> #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
>
> +#define AMDGPU_GFX_PIPE_PRIO_LOW 0
> +#define AMDGPU_GFX_PIPE_PRIO_NORMAL 1
> +#define AMDGPU_GFX_PIPE_PRIO_HIGH 2
> +
> +#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
> +#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
> +
> +
> struct amdgpu_mec {
> struct amdgpu_bo *hpd_eop_obj;
> u64 hpd_eop_gpu_addr;
> @@ -280,8 +288,9 @@ struct amdgpu_gfx {
> uint32_t num_gfx_sched;
> unsigned num_gfx_rings;
> struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
> + struct drm_gpu_scheduler **compute_prio_sched[DRM_SCHED_PRIORITY_MAX];
Mhm, that mixes the middle layer implementation with the hardware backend.
Can you instead use an enum for AMDGPU_GFX_PIPE_PRIO_* and a switch to
map the scheduler priority to the hardware priority?
Alternatively using something like compute_lo, compute, compute_high
should work as well.
Regards,
Christian.
> struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS];
> - uint32_t num_compute_sched;
> + uint32_t num_compute_sched[DRM_SCHED_PRIORITY_MAX];
> unsigned num_compute_rings;
> struct amdgpu_irq_src eop_irq;
> struct amdgpu_irq_src priv_reg_irq;
> @@ -363,6 +372,8 @@ void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
> int *mec, int *pipe, int *queue);
> bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
> int pipe, int queue);
> +bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> + int queue);
> int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> int pipe, int queue);
> void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index d42be880a236..4981e443a884 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -117,12 +117,10 @@ void amdgpu_job_free_resources(struct amdgpu_job *job)
>
> static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
> {
> - struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
> struct amdgpu_job *job = to_amdgpu_job(s_job);
>
> drm_sched_job_cleanup(s_job);
>
> - amdgpu_ring_priority_put(ring, s_job->s_priority);
> dma_fence_put(job->fence);
> amdgpu_sync_free(&job->sync);
> amdgpu_sync_free(&job->sched_sync);
> @@ -143,7 +141,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
> void *owner, struct dma_fence **f)
> {
> enum drm_sched_priority priority;
> - struct amdgpu_ring *ring;
> int r;
>
> if (!f)
> @@ -158,9 +155,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
> priority = job->base.s_priority;
> drm_sched_entity_push_job(&job->base, entity);
>
> - ring = to_amdgpu_ring(entity->rq->sched);
> - amdgpu_ring_priority_get(ring, priority);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 24caff085d00..34fcd467f18d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -222,6 +222,7 @@ struct amdgpu_ring {
> struct mutex priority_mutex;
> /* protected by priority_mutex */
> int priority;
> + bool high_priority;
>
> #if defined(CONFIG_DEBUG_FS)
> struct dentry *ent;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 94ca9ffa0ccb..0e6ce65e1e54 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3211,6 +3211,22 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
> return r;
> }
>
> +static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> + ring->high_priority = true;
> + mqd->cp_hqd_queue_priority =
> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> + }
> + else
> + ring->high_priority = false;
> + }
> +}
> +
> static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -3336,6 +3352,9 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
> mqd->cp_hqd_ib_control = tmp;
>
> + /* set static priority for a queue/ring */
> + gfx_v10_0_compute_mqd_set_priority(ring, mqd);
> +
> /* map_queues packet doesn't need activate the queue,
> * so only kiq need set this field.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 393a1324daa9..6c4b7e49f97f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4430,6 +4430,22 @@ static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
> return r;
> }
>
> +static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> + ring->high_priority = true;
> + mqd->cp_hqd_queue_priority =
> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> + }
> + else
> + ring->high_priority = false;
> + }
> +}
> +
> static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -4553,9 +4569,6 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
> /* defaults */
> mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
> mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
> - mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
> - mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
> - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
> mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
> mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
> mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
> @@ -4567,6 +4580,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
> mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
> mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
>
> + /* set static priority for a queue/ring */
> + gfx_v8_0_mqd_set_priority(ring, mqd);
> + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
> +
> /* map_queues packet doesn't need activate the queue,
> * so only kiq need set this field.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 015647959d69..ff5e913f244d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3314,6 +3314,22 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
> WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
> }
>
> +static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> + ring->high_priority = true;
> + mqd->cp_hqd_queue_priority =
> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> + }
> + else
> + ring->high_priority = false;
> + }
> +}
> +
> static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -3450,6 +3466,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
> mqd->cp_hqd_ib_control = tmp;
>
> + /* set static priority for a queue/ring */
> + gfx_v9_0_mqd_set_priority(ring, mqd);
> + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
> +
> /* map_queues packet doesn't need activate the queue,
> * so only kiq need set this field.
> */
> --
> 2.25.0
>
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init
2020-02-28 14:44 ` [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Christian König
@ 2020-02-28 15:22 ` Nirmoy
0 siblings, 0 replies; 7+ messages in thread
From: Nirmoy @ 2020-02-28 15:22 UTC (permalink / raw)
To: Christian König, Nirmoy Das, amd-gfx
Cc: alexander.deucher, Ray.Huang, nirmoy.das
Thanks Christian, I will send a updated one soon.
On 2/28/20 3:44 PM, Christian König wrote:
> Am 28.02.20 um 15:39 schrieb Nirmoy Das:
>> We were changing compute ring priority while rings were being used
>> before every job submission which is not recommended. This patch
>> sets compute queue priority at mqd initialization for gfx8, gfx9 and
>> gfx10.
>>
>> Policy: make queue 0 of each pipe as high priority compute queue
>>
>> High/normal priority compute sched lists are generated from set of
>> high/normal
>> priority compute queues. At context creation, entity of compute queue
>> get a sched list from high or normal priority depending on ctx->priority
>>
>> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++++++++++++++++++-----
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +++++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 13 +++++++-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 ----
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 +++++++++++
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 ++++++++++++
>> 9 files changed, 113 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> index f397ff97b4e4..8304d0c87899 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> @@ -1205,7 +1205,6 @@ static int amdgpu_cs_submit(struct
>> amdgpu_cs_parser *p,
>> struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
>> struct drm_sched_entity *entity = p->entity;
>> enum drm_sched_priority priority;
>> - struct amdgpu_ring *ring;
>> struct amdgpu_bo_list_entry *e;
>> struct amdgpu_job *job;
>> uint64_t seq;
>> @@ -1258,9 +1257,6 @@ static int amdgpu_cs_submit(struct
>> amdgpu_cs_parser *p,
>> priority = job->base.s_priority;
>> drm_sched_entity_push_job(&job->base, entity);
>>
>> - ring = to_amdgpu_ring(entity->rq->sched);
>> - amdgpu_ring_priority_get(ring, priority);
>> -
>> amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
>>
>> ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> index 94a6c42f29ea..b21771b37300 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
>> @@ -85,8 +85,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx
>> *ctx, const u32 hw_ip, const
>> num_scheds = 1;
>> break;
>> case AMDGPU_HW_IP_COMPUTE:
>> - scheds = adev->gfx.compute_sched;
>> - num_scheds = adev->gfx.num_compute_sched;
>> + scheds = adev->gfx.compute_prio_sched[priority];
>> + num_scheds = adev->gfx.num_compute_sched[priority];
>> break;
>> case AMDGPU_HW_IP_DMA:
>> scheds = adev->sdma.sdma_sched;
>> @@ -628,20 +628,46 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
>> *mgr)
>> mutex_destroy(&mgr->lock);
>> }
>>
>> +
>> +static void amdgpu_ctx_init_compute_sched(struct amdgpu_device *adev)
>> +{
>> + int num_compute_sched_normal = 0;
>> + int num_compute_sched_high = AMDGPU_MAX_COMPUTE_RINGS - 1;
>> + int i;
>> +
>> +
>> + for (i = 0; i < adev->gfx.num_compute_rings; i++) {
>> + if (adev->gfx.compute_ring[i].high_priority)
>> + adev->gfx.compute_sched[num_compute_sched_normal++] =
>> + &adev->gfx.compute_ring[i].sched;
>> + else
>> + adev->gfx.compute_sched[num_compute_sched_high--] =
>> + &adev->gfx.compute_ring[i].sched;
>> + }
>> +
>> + for (i = DRM_SCHED_PRIORITY_MIN; i <= DRM_SCHED_PRIORITY_NORMAL;
>> i++) {
>> + adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0];
>> + adev->gfx.num_compute_sched[i] = num_compute_sched_normal;
>> + }
>> +
>> + for (i = DRM_SCHED_PRIORITY_NORMAL + 1; i <
>> DRM_SCHED_PRIORITY_MAX; i++) {
>> + adev->gfx.compute_prio_sched[i] =
>> + &adev->gfx.compute_sched[num_compute_sched_high - 1];
>> + adev->gfx.num_compute_sched[i] =
>> + adev->gfx.num_compute_rings - num_compute_sched_normal;
>> + }
>> +}
>> +
>> void amdgpu_ctx_init_sched(struct amdgpu_device *adev)
>> {
>> int i, j;
>>
>> + amdgpu_ctx_init_compute_sched(adev);
>> for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
>> adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;
>> adev->gfx.num_gfx_sched++;
>> }
>>
>> - for (i = 0; i < adev->gfx.num_compute_rings; i++) {
>> - adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched;
>> - adev->gfx.num_compute_sched++;
>> - }
>> -
>> for (i = 0; i < adev->sdma.num_instances; i++) {
>> adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched;
>> adev->sdma.num_sdma_sched++;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 7403588684b3..952725e7243c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -192,6 +192,14 @@ static bool
>> amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
>> return adev->gfx.mec.num_mec > 1;
>> }
>>
>> +bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device
>> *adev,
>> + int queue)
>> +{
>> + /* Policy: make queue 0 of each pipe as high priority compute
>> queue */
>> + return (queue == 0);
>> +
>> +}
>> +
>> void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
>> {
>> int i, queue, pipe, mec;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> index 37ba05b63b2a..f87b6df67694 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> @@ -41,6 +41,14 @@
>> #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
>> #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
>>
>> +#define AMDGPU_GFX_PIPE_PRIO_LOW 0
>> +#define AMDGPU_GFX_PIPE_PRIO_NORMAL 1
>> +#define AMDGPU_GFX_PIPE_PRIO_HIGH 2
>> +
>> +#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
>> +#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
>> +
>> +
>> struct amdgpu_mec {
>> struct amdgpu_bo *hpd_eop_obj;
>> u64 hpd_eop_gpu_addr;
>> @@ -280,8 +288,9 @@ struct amdgpu_gfx {
>> uint32_t num_gfx_sched;
>> unsigned num_gfx_rings;
>> struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
>> + struct drm_gpu_scheduler
>> **compute_prio_sched[DRM_SCHED_PRIORITY_MAX];
>
> Mhm, that mixes the middle layer implementation with the hardware
> backend.
>
> Can you instead use an enum for AMDGPU_GFX_PIPE_PRIO_* and a switch to
> map the scheduler priority to the hardware priority?
>
> Alternatively using something like compute_lo, compute, compute_high
> should work as well.
>
> Regards,
> Christian.
>
>> struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS];
>> - uint32_t num_compute_sched;
>> + uint32_t num_compute_sched[DRM_SCHED_PRIORITY_MAX];
>> unsigned num_compute_rings;
>> struct amdgpu_irq_src eop_irq;
>> struct amdgpu_irq_src priv_reg_irq;
>> @@ -363,6 +372,8 @@ void amdgpu_gfx_bit_to_mec_queue(struct
>> amdgpu_device *adev, int bit,
>> int *mec, int *pipe, int *queue);
>> bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
>> int mec,
>> int pipe, int queue);
>> +bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device
>> *adev,
>> + int queue);
>> int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
>> int pipe, int queue);
>> void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> index d42be880a236..4981e443a884 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> @@ -117,12 +117,10 @@ void amdgpu_job_free_resources(struct
>> amdgpu_job *job)
>>
>> static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
>> {
>> - struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
>> struct amdgpu_job *job = to_amdgpu_job(s_job);
>>
>> drm_sched_job_cleanup(s_job);
>>
>> - amdgpu_ring_priority_put(ring, s_job->s_priority);
>> dma_fence_put(job->fence);
>> amdgpu_sync_free(&job->sync);
>> amdgpu_sync_free(&job->sched_sync);
>> @@ -143,7 +141,6 @@ int amdgpu_job_submit(struct amdgpu_job *job,
>> struct drm_sched_entity *entity,
>> void *owner, struct dma_fence **f)
>> {
>> enum drm_sched_priority priority;
>> - struct amdgpu_ring *ring;
>> int r;
>>
>> if (!f)
>> @@ -158,9 +155,6 @@ int amdgpu_job_submit(struct amdgpu_job *job,
>> struct drm_sched_entity *entity,
>> priority = job->base.s_priority;
>> drm_sched_entity_push_job(&job->base, entity);
>>
>> - ring = to_amdgpu_ring(entity->rq->sched);
>> - amdgpu_ring_priority_get(ring, priority);
>> -
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> index 24caff085d00..34fcd467f18d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
>> @@ -222,6 +222,7 @@ struct amdgpu_ring {
>> struct mutex priority_mutex;
>> /* protected by priority_mutex */
>> int priority;
>> + bool high_priority;
>>
>> #if defined(CONFIG_DEBUG_FS)
>> struct dentry *ent;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index 94ca9ffa0ccb..0e6ce65e1e54 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -3211,6 +3211,22 @@ static int
>> gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
>> return r;
>> }
>>
>> +static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring
>> *ring, struct v10_compute_mqd *mqd)
>> +{
>> + struct amdgpu_device *adev = ring->adev;
>> +
>> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
>> + if (amdgpu_gfx_is_high_priority_compute_queue(adev,
>> ring->queue)) {
>> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
>> + ring->high_priority = true;
>> + mqd->cp_hqd_queue_priority =
>> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
>> + }
>> + else
>> + ring->high_priority = false;
>> + }
>> +}
>> +
>> static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> @@ -3336,6 +3352,9 @@ static int gfx_v10_0_compute_mqd_init(struct
>> amdgpu_ring *ring)
>> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
>> mqd->cp_hqd_ib_control = tmp;
>>
>> + /* set static priority for a queue/ring */
>> + gfx_v10_0_compute_mqd_set_priority(ring, mqd);
>> +
>> /* map_queues packet doesn't need activate the queue,
>> * so only kiq need set this field.
>> */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index 393a1324daa9..6c4b7e49f97f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -4430,6 +4430,22 @@ static int gfx_v8_0_deactivate_hqd(struct
>> amdgpu_device *adev, u32 req)
>> return r;
>> }
>>
>> +static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring,
>> struct vi_mqd *mqd)
>> +{
>> + struct amdgpu_device *adev = ring->adev;
>> +
>> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
>> + if (amdgpu_gfx_is_high_priority_compute_queue(adev,
>> ring->queue)) {
>> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
>> + ring->high_priority = true;
>> + mqd->cp_hqd_queue_priority =
>> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
>> + }
>> + else
>> + ring->high_priority = false;
>> + }
>> +}
>> +
>> static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> @@ -4553,9 +4569,6 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring
>> *ring)
>> /* defaults */
>> mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
>> mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
>> - mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
>> - mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
>> - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
>> mqd->cp_hqd_ctx_save_base_addr_lo =
>> RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
>> mqd->cp_hqd_ctx_save_base_addr_hi =
>> RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
>> mqd->cp_hqd_cntl_stack_offset =
>> RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
>> @@ -4567,6 +4580,10 @@ static int gfx_v8_0_mqd_init(struct
>> amdgpu_ring *ring)
>> mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
>> mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
>>
>> + /* set static priority for a queue/ring */
>> + gfx_v8_0_mqd_set_priority(ring, mqd);
>> + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
>> +
>> /* map_queues packet doesn't need activate the queue,
>> * so only kiq need set this field.
>> */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 015647959d69..ff5e913f244d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3314,6 +3314,22 @@ static void gfx_v9_0_kiq_setting(struct
>> amdgpu_ring *ring)
>> WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
>> }
>>
>> +static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring,
>> struct v9_mqd *mqd)
>> +{
>> + struct amdgpu_device *adev = ring->adev;
>> +
>> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
>> + if (amdgpu_gfx_is_high_priority_compute_queue(adev,
>> ring->queue)) {
>> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
>> + ring->high_priority = true;
>> + mqd->cp_hqd_queue_priority =
>> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
>> + }
>> + else
>> + ring->high_priority = false;
>> + }
>> +}
>> +
>> static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> @@ -3450,6 +3466,10 @@ static int gfx_v9_0_mqd_init(struct
>> amdgpu_ring *ring)
>> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
>> mqd->cp_hqd_ib_control = tmp;
>>
>> + /* set static priority for a queue/ring */
>> + gfx_v9_0_mqd_set_priority(ring, mqd);
>> + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
>> +
>> /* map_queues packet doesn't need activate the queue,
>> * so only kiq need set this field.
>> */
>> --
>> 2.25.0
>>
>
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init
2020-02-28 14:39 [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Nirmoy Das
` (3 preceding siblings ...)
2020-02-28 14:44 ` [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Christian König
@ 2020-02-28 15:56 ` Alex Deucher
4 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2020-02-28 15:56 UTC (permalink / raw)
To: Nirmoy Das
Cc: Deucher, Alexander, Huang Rui, Nirmoy Das, Christian Koenig,
amd-gfx list
On Fri, Feb 28, 2020 at 9:36 AM Nirmoy Das <nirmoy.aiemd@gmail.com> wrote:
>
> We were changing compute ring priority while rings were being used
> before every job submission which is not recommended. This patch
> sets compute queue priority at mqd initialization for gfx8, gfx9 and
> gfx10.
>
> Policy: make queue 0 of each pipe as high priority compute queue
>
> High/normal priority compute sched lists are generated from set of high/normal
> priority compute queues. At context creation, entity of compute queue
> get a sched list from high or normal priority depending on ctx->priority
>
> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 40 +++++++++++++++++++-----
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 +++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 13 +++++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 ----
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 19 +++++++++++
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 20 ++++++++++++
> 9 files changed, 113 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index f397ff97b4e4..8304d0c87899 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -1205,7 +1205,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> struct drm_sched_entity *entity = p->entity;
> enum drm_sched_priority priority;
> - struct amdgpu_ring *ring;
> struct amdgpu_bo_list_entry *e;
> struct amdgpu_job *job;
> uint64_t seq;
> @@ -1258,9 +1257,6 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
> priority = job->base.s_priority;
> drm_sched_entity_push_job(&job->base, entity);
>
> - ring = to_amdgpu_ring(entity->rq->sched);
> - amdgpu_ring_priority_get(ring, priority);
> -
> amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
>
> ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> index 94a6c42f29ea..b21771b37300 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
> @@ -85,8 +85,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const
> num_scheds = 1;
> break;
> case AMDGPU_HW_IP_COMPUTE:
> - scheds = adev->gfx.compute_sched;
> - num_scheds = adev->gfx.num_compute_sched;
> + scheds = adev->gfx.compute_prio_sched[priority];
> + num_scheds = adev->gfx.num_compute_sched[priority];
> break;
> case AMDGPU_HW_IP_DMA:
> scheds = adev->sdma.sdma_sched;
> @@ -628,20 +628,46 @@ void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr)
> mutex_destroy(&mgr->lock);
> }
>
> +
> +static void amdgpu_ctx_init_compute_sched(struct amdgpu_device *adev)
> +{
> + int num_compute_sched_normal = 0;
> + int num_compute_sched_high = AMDGPU_MAX_COMPUTE_RINGS - 1;
> + int i;
> +
> +
> + for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> + if (adev->gfx.compute_ring[i].high_priority)
> + adev->gfx.compute_sched[num_compute_sched_normal++] =
> + &adev->gfx.compute_ring[i].sched;
> + else
> + adev->gfx.compute_sched[num_compute_sched_high--] =
> + &adev->gfx.compute_ring[i].sched;
> + }
> +
> + for (i = DRM_SCHED_PRIORITY_MIN; i <= DRM_SCHED_PRIORITY_NORMAL; i++) {
> + adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0];
> + adev->gfx.num_compute_sched[i] = num_compute_sched_normal;
> + }
> +
> + for (i = DRM_SCHED_PRIORITY_NORMAL + 1; i < DRM_SCHED_PRIORITY_MAX; i++) {
> + adev->gfx.compute_prio_sched[i] =
> + &adev->gfx.compute_sched[num_compute_sched_high - 1];
> + adev->gfx.num_compute_sched[i] =
> + adev->gfx.num_compute_rings - num_compute_sched_normal;
> + }
> +}
> +
> void amdgpu_ctx_init_sched(struct amdgpu_device *adev)
> {
> int i, j;
>
> + amdgpu_ctx_init_compute_sched(adev);
> for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched;
> adev->gfx.num_gfx_sched++;
> }
>
> - for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> - adev->gfx.compute_sched[i] = &adev->gfx.compute_ring[i].sched;
> - adev->gfx.num_compute_sched++;
> - }
> -
> for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched;
> adev->sdma.num_sdma_sched++;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 7403588684b3..952725e7243c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -192,6 +192,14 @@ static bool amdgpu_gfx_is_multipipe_capable(struct amdgpu_device *adev)
> return adev->gfx.mec.num_mec > 1;
> }
>
> +bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> + int queue)
> +{
> + /* Policy: make queue 0 of each pipe as high priority compute queue */
> + return (queue == 0);
> +
> +}
> +
> void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
> {
> int i, queue, pipe, mec;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 37ba05b63b2a..f87b6df67694 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -41,6 +41,14 @@
> #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
> #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
>
> +#define AMDGPU_GFX_PIPE_PRIO_LOW 0
> +#define AMDGPU_GFX_PIPE_PRIO_NORMAL 1
> +#define AMDGPU_GFX_PIPE_PRIO_HIGH 2
> +
> +#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
> +#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
> +
> +
> struct amdgpu_mec {
> struct amdgpu_bo *hpd_eop_obj;
> u64 hpd_eop_gpu_addr;
> @@ -280,8 +288,9 @@ struct amdgpu_gfx {
> uint32_t num_gfx_sched;
> unsigned num_gfx_rings;
> struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
> + struct drm_gpu_scheduler **compute_prio_sched[DRM_SCHED_PRIORITY_MAX];
> struct drm_gpu_scheduler *compute_sched[AMDGPU_MAX_COMPUTE_RINGS];
> - uint32_t num_compute_sched;
> + uint32_t num_compute_sched[DRM_SCHED_PRIORITY_MAX];
> unsigned num_compute_rings;
> struct amdgpu_irq_src eop_irq;
> struct amdgpu_irq_src priv_reg_irq;
> @@ -363,6 +372,8 @@ void amdgpu_gfx_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
> int *mec, int *pipe, int *queue);
> bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
> int pipe, int queue);
> +bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
> + int queue);
> int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
> int pipe, int queue);
> void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index d42be880a236..4981e443a884 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -117,12 +117,10 @@ void amdgpu_job_free_resources(struct amdgpu_job *job)
>
> static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
> {
> - struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
> struct amdgpu_job *job = to_amdgpu_job(s_job);
>
> drm_sched_job_cleanup(s_job);
>
> - amdgpu_ring_priority_put(ring, s_job->s_priority);
> dma_fence_put(job->fence);
> amdgpu_sync_free(&job->sync);
> amdgpu_sync_free(&job->sched_sync);
> @@ -143,7 +141,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
> void *owner, struct dma_fence **f)
> {
> enum drm_sched_priority priority;
> - struct amdgpu_ring *ring;
> int r;
>
> if (!f)
> @@ -158,9 +155,6 @@ int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
> priority = job->base.s_priority;
> drm_sched_entity_push_job(&job->base, entity);
>
> - ring = to_amdgpu_ring(entity->rq->sched);
> - amdgpu_ring_priority_get(ring, priority);
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 24caff085d00..34fcd467f18d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -222,6 +222,7 @@ struct amdgpu_ring {
> struct mutex priority_mutex;
> /* protected by priority_mutex */
> int priority;
> + bool high_priority;
>
> #if defined(CONFIG_DEBUG_FS)
> struct dentry *ent;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 94ca9ffa0ccb..0e6ce65e1e54 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3211,6 +3211,22 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
> return r;
> }
>
> +static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> + ring->high_priority = true;
> + mqd->cp_hqd_queue_priority =
> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> + }
> + else
> + ring->high_priority = false;
Coding style. If any clause has parens, the whole thing should have
them. Also conditions should be on the same line as the parens.
E.g.,
if () {
...
} else {
...
}
Same comment on the other gfx* functions below.
Alex
> + }
> +}
> +
> static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -3336,6 +3352,9 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
> mqd->cp_hqd_ib_control = tmp;
>
> + /* set static priority for a queue/ring */
> + gfx_v10_0_compute_mqd_set_priority(ring, mqd);
> +
> /* map_queues packet doesn't need activate the queue,
> * so only kiq need set this field.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 393a1324daa9..6c4b7e49f97f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4430,6 +4430,22 @@ static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
> return r;
> }
>
> +static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> + ring->high_priority = true;
> + mqd->cp_hqd_queue_priority =
> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> + }
> + else
> + ring->high_priority = false;
> + }
> +}
> +
> static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -4553,9 +4569,6 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
> /* defaults */
> mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
> mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
> - mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
> - mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
> - mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
> mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
> mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
> mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
> @@ -4567,6 +4580,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
> mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
> mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
>
> + /* set static priority for a queue/ring */
> + gfx_v8_0_mqd_set_priority(ring, mqd);
> + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
> +
> /* map_queues packet doesn't need activate the queue,
> * so only kiq need set this field.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 015647959d69..ff5e913f244d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3314,6 +3314,22 @@ static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
> WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
> }
>
> +static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
> + if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
> + mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
> + ring->high_priority = true;
> + mqd->cp_hqd_queue_priority =
> + AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
> + }
> + else
> + ring->high_priority = false;
> + }
> +}
> +
> static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -3450,6 +3466,10 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
> tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
> mqd->cp_hqd_ib_control = tmp;
>
> + /* set static priority for a queue/ring */
> + gfx_v9_0_mqd_set_priority(ring, mqd);
> + mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
> +
> /* map_queues packet doesn't need activate the queue,
> * so only kiq need set this field.
> */
> --
> 2.25.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-02-28 15:56 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-28 14:39 [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 2/4] drm/scheduler: implement a function to modify sched list Nirmoy Das
2020-02-28 14:39 ` [PATCH v2 3/4] drm/amdgpu: change hw sched list on ctx priority override Nirmoy Das
2020-02-28 14:39 ` [PATCH 4/4] drm/amdgpu: remove unused functions Nirmoy Das
2020-02-28 14:44 ` [PATCH v2 1/4] drm/amdgpu: set compute queue priority at mqd_init Christian König
2020-02-28 15:22 ` Nirmoy
2020-02-28 15:56 ` Alex Deucher
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