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* [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h
@ 2020-02-06 19:55 Alex Deucher
  2020-02-06 19:55 ` [PATCH 2/2] drm/amdgpu:/navi10: use the ODCAP enum to index the caps array Alex Deucher
  2020-02-07  7:36 ` [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Quan, Evan
  0 siblings, 2 replies; 5+ messages in thread
From: Alex Deucher @ 2020-02-06 19:55 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

Update to the latest changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../drm/amd/powerplay/inc/smu_v11_0_pptable.h | 46 +++++++++++++------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
index b2f96a101124..7a63cf8e85ed 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
@@ -39,21 +39,39 @@
 #define SMU_11_0_PP_OVERDRIVE_VERSION                   0x0800
 #define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION            0x0100
 
+enum SMU_11_0_ODFEATURE_CAP {
+    SMU_11_0_ODCAP_GFXCLK_LIMITS = 0,
+    SMU_11_0_ODCAP_GFXCLK_CURVE,
+    SMU_11_0_ODCAP_UCLK_MAX,
+    SMU_11_0_ODCAP_POWER_LIMIT,
+    SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,
+    SMU_11_0_ODCAP_FAN_SPEED_MIN,
+    SMU_11_0_ODCAP_TEMPERATURE_FAN,
+    SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,
+    SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,
+    SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,
+    SMU_11_0_ODCAP_AUTO_UV_ENGINE,
+    SMU_11_0_ODCAP_AUTO_OC_ENGINE,
+    SMU_11_0_ODCAP_AUTO_OC_MEMORY,
+    SMU_11_0_ODCAP_FAN_CURVE,
+    SMU_11_0_ODCAP_COUNT,
+};
+
 enum SMU_11_0_ODFEATURE_ID {
-    SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 << 0,         //GFXCLK Limit feature
-    SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 << 1,         //GFXCLK Curve feature
-    SMU_11_0_ODFEATURE_UCLK_MAX             = 1 << 2,         //UCLK Limit feature
-    SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 << 3,         //Power Limit feature
-    SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 << 4,         //Fan Acoustic RPM feature
-    SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 << 5,         //Minimum Fan Speed feature
-    SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 << 6,         //Fan Target Temperature Limit feature
-    SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 << 7,         //Operating Temperature Limit feature
-    SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 << 8,         //AC Timing Tuning feature
-    SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << 9,         //Zero RPM feature
-    SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 << 10,        //Auto Under Volt GFXCLK feature
-    SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 << 11,        //Auto Over Clock GFXCLK feature
-    SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 << 12,        //Auto Over Clock MCLK feature
-    SMU_11_0_ODFEATURE_FAN_CURVE            = 1 << 13,        //VICTOR TODO
+    SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 << SMU_11_0_ODCAP_GFXCLK_LIMITS,            //GFXCLK Limit feature
+    SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 << SMU_11_0_ODCAP_GFXCLK_CURVE,             //GFXCLK Curve feature
+    SMU_11_0_ODFEATURE_UCLK_MAX             = 1 << SMU_11_0_ODCAP_UCLK_MAX,                 //UCLK Limit feature
+    SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 << SMU_11_0_ODCAP_POWER_LIMIT,              //Power Limit feature
+    SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 << SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,       //Fan Acoustic RPM feature
+    SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 << SMU_11_0_ODCAP_FAN_SPEED_MIN,            //Minimum Fan Speed feature
+    SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 << SMU_11_0_ODCAP_TEMPERATURE_FAN,          //Fan Target Temperature Limit feature
+    SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 << SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,       //Operating Temperature Limit feature
+    SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 << SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,       //AC Timing Tuning feature
+    SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,     //Zero RPM feature
+    SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 << SMU_11_0_ODCAP_AUTO_UV_ENGINE,           //Auto Under Volt GFXCLK feature
+    SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 << SMU_11_0_ODCAP_AUTO_OC_ENGINE,           //Auto Over Clock GFXCLK feature
+    SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 << SMU_11_0_ODCAP_AUTO_OC_MEMORY,           //Auto Over Clock MCLK feature
+    SMU_11_0_ODFEATURE_FAN_CURVE            = 1 << SMU_11_0_ODCAP_FAN_CURVE,                //Fan Curve feature
     SMU_11_0_ODFEATURE_COUNT                = 14,
 };
 #define SMU_11_0_MAX_ODFEATURE    32          //Maximum Number of OD Features
-- 
2.24.1

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^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/amdgpu:/navi10: use the ODCAP enum to index the caps array
  2020-02-06 19:55 [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Alex Deucher
@ 2020-02-06 19:55 ` Alex Deucher
  2020-02-09 22:03   ` Matt Coffin
  2020-02-07  7:36 ` [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Quan, Evan
  1 sibling, 1 reply; 5+ messages in thread
From: Alex Deucher @ 2020-02-06 19:55 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher, Aleksandr Mezin

Rather than the FEATURE_ID flags.  Avoids a possible reading past
the end of the array.

Reported-by: Aleksandr Mezin <mezin.alexander@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 19a9846b730e..0d73a49166af 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -736,9 +736,9 @@ static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu
 	return dpm_desc->SnapToDiscrete == 0 ? true : false;
 }
 
-static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_ID feature)
+static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
 {
-	return od_table->cap[feature];
+	return od_table->cap[cap];
 }
 
 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
@@ -846,7 +846,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 	case SMU_OD_SCLK:
 		if (!smu->od_enabled || !od_table || !od_settings)
 			break;
-		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS))
+		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
 			break;
 		size += sprintf(buf + size, "OD_SCLK:\n");
 		size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
@@ -854,7 +854,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 	case SMU_OD_MCLK:
 		if (!smu->od_enabled || !od_table || !od_settings)
 			break;
-		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX))
+		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
 			break;
 		size += sprintf(buf + size, "OD_MCLK:\n");
 		size += sprintf(buf + size, "1: %uMHz\n", od_table->UclkFmax);
@@ -862,7 +862,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 	case SMU_OD_VDDC_CURVE:
 		if (!smu->od_enabled || !od_table || !od_settings)
 			break;
-		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE))
+		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
 			break;
 		size += sprintf(buf + size, "OD_VDDC_CURVE:\n");
 		for (i = 0; i < 3; i++) {
@@ -887,7 +887,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 			break;
 		size = sprintf(buf, "%s:\n", "OD_RANGE");
 
-		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
+		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
 						    &min_value, NULL);
 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
@@ -896,14 +896,14 @@ static int navi10_print_clk_levels(struct smu_context *smu,
 					min_value, max_value);
 		}
 
-		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
+		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
 						    &min_value, &max_value);
 			size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
 					min_value, max_value);
 		}
 
-		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
+		if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
 			navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
 						    &min_value, &max_value);
 			size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
@@ -2056,7 +2056,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
 
 	switch (type) {
 	case PP_OD_EDIT_SCLK_VDDC_TABLE:
-		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_LIMITS)) {
+		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
 			pr_warn("GFXCLK_LIMITS not supported!\n");
 			return -ENOTSUPP;
 		}
@@ -2102,7 +2102,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
 		}
 		break;
 	case PP_OD_EDIT_MCLK_VDDC_TABLE:
-		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_UCLK_MAX)) {
+		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
 			pr_warn("UCLK_MAX not supported!\n");
 			return -ENOTSUPP;
 		}
@@ -2143,7 +2143,7 @@ static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABL
 		}
 		break;
 	case PP_OD_EDIT_VDDC_CURVE:
-		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODFEATURE_GFXCLK_CURVE)) {
+		if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
 			pr_warn("GFXCLK_CURVE not supported!\n");
 			return -ENOTSUPP;
 		}
-- 
2.24.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h
  2020-02-06 19:55 [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Alex Deucher
  2020-02-06 19:55 ` [PATCH 2/2] drm/amdgpu:/navi10: use the ODCAP enum to index the caps array Alex Deucher
@ 2020-02-07  7:36 ` Quan, Evan
  2020-02-07 15:47   ` Alex Deucher
  1 sibling, 1 reply; 5+ messages in thread
From: Quan, Evan @ 2020-02-07  7:36 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander

>     SMU_11_0_ODFEATURE_COUNT                = 14,
This seems a little weird. 
Maybe it should be "SMU_11_0_ODFEATURE_COUNT = 1 << SMU_11_0_ODCAP_COUNT, "
With above confirmed, the patch series is reviewed-by: Evan Quan <evan.quan@amd.com>

>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
>Deucher
>Sent: Friday, February 7, 2020 3:55 AM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
>Subject: [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h
>
>Update to the latest changes.
>
>Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>---
> .../drm/amd/powerplay/inc/smu_v11_0_pptable.h | 46 +++++++++++++-----
>-
> 1 file changed, 32 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
>b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
>index b2f96a101124..7a63cf8e85ed 100644
>--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
>+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
>@@ -39,21 +39,39 @@
> #define SMU_11_0_PP_OVERDRIVE_VERSION                   0x0800
> #define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION            0x0100
>
>+enum SMU_11_0_ODFEATURE_CAP {
>+    SMU_11_0_ODCAP_GFXCLK_LIMITS = 0,
>+    SMU_11_0_ODCAP_GFXCLK_CURVE,
>+    SMU_11_0_ODCAP_UCLK_MAX,
>+    SMU_11_0_ODCAP_POWER_LIMIT,
>+    SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,
>+    SMU_11_0_ODCAP_FAN_SPEED_MIN,
>+    SMU_11_0_ODCAP_TEMPERATURE_FAN,
>+    SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,
>+    SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,
>+    SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,
>+    SMU_11_0_ODCAP_AUTO_UV_ENGINE,
>+    SMU_11_0_ODCAP_AUTO_OC_ENGINE,
>+    SMU_11_0_ODCAP_AUTO_OC_MEMORY,
>+    SMU_11_0_ODCAP_FAN_CURVE,
>+    SMU_11_0_ODCAP_COUNT,
>+};
>+
> enum SMU_11_0_ODFEATURE_ID {
>-    SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 << 0,         //GFXCLK Limit
>feature
>-    SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 << 1,         //GFXCLK Curve
>feature
>-    SMU_11_0_ODFEATURE_UCLK_MAX             = 1 << 2,         //UCLK Limit
>feature
>-    SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 << 3,         //Power Limit
>feature
>-    SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 << 4,         //Fan
>Acoustic RPM feature
>-    SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 << 5,         //Minimum
>Fan Speed feature
>-    SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 << 6,         //Fan Target
>Temperature Limit feature
>-    SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 << 7,
>//Operating Temperature Limit feature
>-    SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 << 8,         //AC
>Timing Tuning feature
>-    SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << 9,         //Zero
>RPM feature
>-    SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 << 10,        //Auto
>Under Volt GFXCLK feature
>-    SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 << 11,        //Auto Over
>Clock GFXCLK feature
>-    SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 << 12,        //Auto
>Over Clock MCLK feature
>-    SMU_11_0_ODFEATURE_FAN_CURVE            = 1 << 13,        //VICTOR TODO
>+    SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 <<
>SMU_11_0_ODCAP_GFXCLK_LIMITS,            //GFXCLK Limit feature
>+    SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 <<
>SMU_11_0_ODCAP_GFXCLK_CURVE,             //GFXCLK Curve feature
>+    SMU_11_0_ODFEATURE_UCLK_MAX             = 1 <<
>SMU_11_0_ODCAP_UCLK_MAX,                 //UCLK Limit feature
>+    SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 <<
>SMU_11_0_ODCAP_POWER_LIMIT,              //Power Limit feature
>+    SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 <<
>SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,       //Fan Acoustic RPM feature
>+    SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 <<
>SMU_11_0_ODCAP_FAN_SPEED_MIN,            //Minimum Fan Speed feature
>+    SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 <<
>SMU_11_0_ODCAP_TEMPERATURE_FAN,          //Fan Target Temperature
>Limit feature
>+    SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 <<
>SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,       //Operating Temperature
>Limit feature
>+    SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 <<
>SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,       //AC Timing Tuning feature
>+    SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 <<
>SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,     //Zero RPM feature
>+    SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 <<
>SMU_11_0_ODCAP_AUTO_UV_ENGINE,           //Auto Under Volt GFXCLK
>feature
>+    SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 <<
>SMU_11_0_ODCAP_AUTO_OC_ENGINE,           //Auto Over Clock GFXCLK
>feature
>+    SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 <<
>SMU_11_0_ODCAP_AUTO_OC_MEMORY,           //Auto Over Clock MCLK
>feature
>+    SMU_11_0_ODFEATURE_FAN_CURVE            = 1 <<
>SMU_11_0_ODCAP_FAN_CURVE,                //Fan Curve feature
>     SMU_11_0_ODFEATURE_COUNT                = 14,
> };
> #define SMU_11_0_MAX_ODFEATURE    32          //Maximum Number of OD
>Features
>--
>2.24.1
>
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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h
  2020-02-07  7:36 ` [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Quan, Evan
@ 2020-02-07 15:47   ` Alex Deucher
  0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2020-02-07 15:47 UTC (permalink / raw)
  To: Quan, Evan; +Cc: Deucher, Alexander, amd-gfx

On Fri, Feb 7, 2020 at 2:36 AM Quan, Evan <Evan.Quan@amd.com> wrote:
>
> >     SMU_11_0_ODFEATURE_COUNT                = 14,
> This seems a little weird.
> Maybe it should be "SMU_11_0_ODFEATURE_COUNT = 1 << SMU_11_0_ODCAP_COUNT, "

I copied it verbatim.  The naming makes more sense as 14 (number of
features) as opposed to 1 << 14.  I agree it's not consistent though.
I'd prefer to stay consistent with the internal headers.

Alex

> With above confirmed, the patch series is reviewed-by: Evan Quan <evan.quan@amd.com>
>
> >-----Original Message-----
> >From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> >Deucher
> >Sent: Friday, February 7, 2020 3:55 AM
> >To: amd-gfx@lists.freedesktop.org
> >Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> >Subject: [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h
> >
> >Update to the latest changes.
> >
> >Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >---
> > .../drm/amd/powerplay/inc/smu_v11_0_pptable.h | 46 +++++++++++++-----
> >-
> > 1 file changed, 32 insertions(+), 14 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
> >b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
> >index b2f96a101124..7a63cf8e85ed 100644
> >--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
> >+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0_pptable.h
> >@@ -39,21 +39,39 @@
> > #define SMU_11_0_PP_OVERDRIVE_VERSION                   0x0800
> > #define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION            0x0100
> >
> >+enum SMU_11_0_ODFEATURE_CAP {
> >+    SMU_11_0_ODCAP_GFXCLK_LIMITS = 0,
> >+    SMU_11_0_ODCAP_GFXCLK_CURVE,
> >+    SMU_11_0_ODCAP_UCLK_MAX,
> >+    SMU_11_0_ODCAP_POWER_LIMIT,
> >+    SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,
> >+    SMU_11_0_ODCAP_FAN_SPEED_MIN,
> >+    SMU_11_0_ODCAP_TEMPERATURE_FAN,
> >+    SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,
> >+    SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,
> >+    SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,
> >+    SMU_11_0_ODCAP_AUTO_UV_ENGINE,
> >+    SMU_11_0_ODCAP_AUTO_OC_ENGINE,
> >+    SMU_11_0_ODCAP_AUTO_OC_MEMORY,
> >+    SMU_11_0_ODCAP_FAN_CURVE,
> >+    SMU_11_0_ODCAP_COUNT,
> >+};
> >+
> > enum SMU_11_0_ODFEATURE_ID {
> >-    SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 << 0,         //GFXCLK Limit
> >feature
> >-    SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 << 1,         //GFXCLK Curve
> >feature
> >-    SMU_11_0_ODFEATURE_UCLK_MAX             = 1 << 2,         //UCLK Limit
> >feature
> >-    SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 << 3,         //Power Limit
> >feature
> >-    SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 << 4,         //Fan
> >Acoustic RPM feature
> >-    SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 << 5,         //Minimum
> >Fan Speed feature
> >-    SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 << 6,         //Fan Target
> >Temperature Limit feature
> >-    SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 << 7,
> >//Operating Temperature Limit feature
> >-    SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 << 8,         //AC
> >Timing Tuning feature
> >-    SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << 9,         //Zero
> >RPM feature
> >-    SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 << 10,        //Auto
> >Under Volt GFXCLK feature
> >-    SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 << 11,        //Auto Over
> >Clock GFXCLK feature
> >-    SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 << 12,        //Auto
> >Over Clock MCLK feature
> >-    SMU_11_0_ODFEATURE_FAN_CURVE            = 1 << 13,        //VICTOR TODO
> >+    SMU_11_0_ODFEATURE_GFXCLK_LIMITS        = 1 <<
> >SMU_11_0_ODCAP_GFXCLK_LIMITS,            //GFXCLK Limit feature
> >+    SMU_11_0_ODFEATURE_GFXCLK_CURVE         = 1 <<
> >SMU_11_0_ODCAP_GFXCLK_CURVE,             //GFXCLK Curve feature
> >+    SMU_11_0_ODFEATURE_UCLK_MAX             = 1 <<
> >SMU_11_0_ODCAP_UCLK_MAX,                 //UCLK Limit feature
> >+    SMU_11_0_ODFEATURE_POWER_LIMIT          = 1 <<
> >SMU_11_0_ODCAP_POWER_LIMIT,              //Power Limit feature
> >+    SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 <<
> >SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT,       //Fan Acoustic RPM feature
> >+    SMU_11_0_ODFEATURE_FAN_SPEED_MIN        = 1 <<
> >SMU_11_0_ODCAP_FAN_SPEED_MIN,            //Minimum Fan Speed feature
> >+    SMU_11_0_ODFEATURE_TEMPERATURE_FAN      = 1 <<
> >SMU_11_0_ODCAP_TEMPERATURE_FAN,          //Fan Target Temperature
> >Limit feature
> >+    SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 <<
> >SMU_11_0_ODCAP_TEMPERATURE_SYSTEM,       //Operating Temperature
> >Limit feature
> >+    SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 <<
> >SMU_11_0_ODCAP_MEMORY_TIMING_TUNE,       //AC Timing Tuning feature
> >+    SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 <<
> >SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL,     //Zero RPM feature
> >+    SMU_11_0_ODFEATURE_AUTO_UV_ENGINE       = 1 <<
> >SMU_11_0_ODCAP_AUTO_UV_ENGINE,           //Auto Under Volt GFXCLK
> >feature
> >+    SMU_11_0_ODFEATURE_AUTO_OC_ENGINE       = 1 <<
> >SMU_11_0_ODCAP_AUTO_OC_ENGINE,           //Auto Over Clock GFXCLK
> >feature
> >+    SMU_11_0_ODFEATURE_AUTO_OC_MEMORY       = 1 <<
> >SMU_11_0_ODCAP_AUTO_OC_MEMORY,           //Auto Over Clock MCLK
> >feature
> >+    SMU_11_0_ODFEATURE_FAN_CURVE            = 1 <<
> >SMU_11_0_ODCAP_FAN_CURVE,                //Fan Curve feature
> >     SMU_11_0_ODFEATURE_COUNT                = 14,
> > };
> > #define SMU_11_0_MAX_ODFEATURE    32          //Maximum Number of OD
> >Features
> >--
> >2.24.1
> >
> >_______________________________________________
> >amd-gfx mailing list
> >amd-gfx@lists.freedesktop.org
> >https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f
> >reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> >gfx&amp;data=02%7C01%7Cevan.quan%40amd.com%7C99774c3d5dfa4e98e6
> >e408d7ab3e83c6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637
> >166157332486214&amp;sdata=n8ey1rnXwX3JLecL%2BWnNSV6cNNGTagtn2lR
> >ORmI%2Bb%2Bk%3D&amp;reserved=0
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^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu:/navi10: use the ODCAP enum to index the caps array
  2020-02-06 19:55 ` [PATCH 2/2] drm/amdgpu:/navi10: use the ODCAP enum to index the caps array Alex Deucher
@ 2020-02-09 22:03   ` Matt Coffin
  0 siblings, 0 replies; 5+ messages in thread
From: Matt Coffin @ 2020-02-09 22:03 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx; +Cc: Alex Deucher, Aleksandr Mezin


[-- Attachment #1.1.1: Type: text/plain, Size: 519 bytes --]

On 2/6/20 12:55 PM, Alex Deucher wrote:
> Rather than the FEATURE_ID flags.  Avoids a possible reading past
> the end of the array.

Just to make sure I understand, this has been broken the whole time,
right, and just happened to be working because we were only using the
lower-end values and happened to not read past the end of the array?

I'll do some testing for navi10, and play around with actually disabling
the capabilities manually to make sure we're responding correctly.

Thanks for fixing it!


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^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-09 22:03 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-06 19:55 [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Alex Deucher
2020-02-06 19:55 ` [PATCH 2/2] drm/amdgpu:/navi10: use the ODCAP enum to index the caps array Alex Deucher
2020-02-09 22:03   ` Matt Coffin
2020-02-07  7:36 ` [PATCH 1/2] drm/amdgpu: update smu_v11_0_pptable.h Quan, Evan
2020-02-07 15:47   ` Alex Deucher

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