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* [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting
@ 2023-06-07 16:46 Alex Deucher
  2023-06-12 21:47 ` Alex Deucher
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2023-06-07 16:46 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

DDR5 channels are 32 bit rather than 64, report the width properly
in the log.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 20 +++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index ef4b9a41f20a..6b3bdc27f778 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -327,10 +327,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 					mem_channel_number = igp_info->v11.umachannelnumber;
 					if (!mem_channel_number)
 						mem_channel_number = 1;
-					/* channel width is 64 */
-					if (vram_width)
-						*vram_width = mem_channel_number * 64;
 					mem_type = igp_info->v11.memorytype;
+					if ((mem_type == Ddr5MemType) ||
+					    (mem_type == LpDdr5MemType))
+						mem_channel_width = 32;
+					else
+						mem_channel_width = 64;
+					if (vram_width)
+						*vram_width = mem_channel_number * mem_channel_width;
 					if (vram_type)
 						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 					break;
@@ -345,10 +349,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
 					mem_channel_number = igp_info->v21.umachannelnumber;
 					if (!mem_channel_number)
 						mem_channel_number = 1;
-					/* channel width is 64 */
-					if (vram_width)
-						*vram_width = mem_channel_number * 64;
 					mem_type = igp_info->v21.memorytype;
+					if ((mem_type == Ddr5MemType) ||
+					    (mem_type == LpDdr5MemType))
+						mem_channel_width = 32;
+					else
+						mem_channel_width = 64;
+					if (vram_width)
+						*vram_width = mem_channel_number * mem_channel_width;
 					if (vram_type)
 						*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
 					break;
-- 
2.40.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting
  2023-06-07 16:46 [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting Alex Deucher
@ 2023-06-12 21:47 ` Alex Deucher
  2023-06-15 13:17   ` Alex Deucher
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2023-06-12 21:47 UTC (permalink / raw)
  To: Alex Deucher; +Cc: amd-gfx

Ping?

On Wed, Jun 7, 2023 at 12:46 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> DDR5 channels are 32 bit rather than 64, report the width properly
> in the log.
>
> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 20 +++++++++++++------
>  1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> index ef4b9a41f20a..6b3bdc27f778 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> @@ -327,10 +327,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
>                                         mem_channel_number = igp_info->v11.umachannelnumber;
>                                         if (!mem_channel_number)
>                                                 mem_channel_number = 1;
> -                                       /* channel width is 64 */
> -                                       if (vram_width)
> -                                               *vram_width = mem_channel_number * 64;
>                                         mem_type = igp_info->v11.memorytype;
> +                                       if ((mem_type == Ddr5MemType) ||
> +                                           (mem_type == LpDdr5MemType))
> +                                               mem_channel_width = 32;
> +                                       else
> +                                               mem_channel_width = 64;
> +                                       if (vram_width)
> +                                               *vram_width = mem_channel_number * mem_channel_width;
>                                         if (vram_type)
>                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
>                                         break;
> @@ -345,10 +349,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
>                                         mem_channel_number = igp_info->v21.umachannelnumber;
>                                         if (!mem_channel_number)
>                                                 mem_channel_number = 1;
> -                                       /* channel width is 64 */
> -                                       if (vram_width)
> -                                               *vram_width = mem_channel_number * 64;
>                                         mem_type = igp_info->v21.memorytype;
> +                                       if ((mem_type == Ddr5MemType) ||
> +                                           (mem_type == LpDdr5MemType))
> +                                               mem_channel_width = 32;
> +                                       else
> +                                               mem_channel_width = 64;
> +                                       if (vram_width)
> +                                               *vram_width = mem_channel_number * mem_channel_width;
>                                         if (vram_type)
>                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
>                                         break;
> --
> 2.40.1
>

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting
  2023-06-12 21:47 ` Alex Deucher
@ 2023-06-15 13:17   ` Alex Deucher
  2023-06-15 13:56     ` Zhang, Hawking
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2023-06-15 13:17 UTC (permalink / raw)
  To: Alex Deucher; +Cc: amd-gfx

Ping?

On Mon, Jun 12, 2023 at 5:47 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> Ping?
>
> On Wed, Jun 7, 2023 at 12:46 PM Alex Deucher <alexander.deucher@amd.com> wrote:
> >
> > DDR5 channels are 32 bit rather than 64, report the width properly
> > in the log.
> >
> > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 20 +++++++++++++------
> >  1 file changed, 14 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > index ef4b9a41f20a..6b3bdc27f778 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > @@ -327,10 +327,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> >                                         mem_channel_number = igp_info->v11.umachannelnumber;
> >                                         if (!mem_channel_number)
> >                                                 mem_channel_number = 1;
> > -                                       /* channel width is 64 */
> > -                                       if (vram_width)
> > -                                               *vram_width = mem_channel_number * 64;
> >                                         mem_type = igp_info->v11.memorytype;
> > +                                       if ((mem_type == Ddr5MemType) ||
> > +                                           (mem_type == LpDdr5MemType))
> > +                                               mem_channel_width = 32;
> > +                                       else
> > +                                               mem_channel_width = 64;
> > +                                       if (vram_width)
> > +                                               *vram_width = mem_channel_number * mem_channel_width;
> >                                         if (vram_type)
> >                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
> >                                         break;
> > @@ -345,10 +349,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> >                                         mem_channel_number = igp_info->v21.umachannelnumber;
> >                                         if (!mem_channel_number)
> >                                                 mem_channel_number = 1;
> > -                                       /* channel width is 64 */
> > -                                       if (vram_width)
> > -                                               *vram_width = mem_channel_number * 64;
> >                                         mem_type = igp_info->v21.memorytype;
> > +                                       if ((mem_type == Ddr5MemType) ||
> > +                                           (mem_type == LpDdr5MemType))
> > +                                               mem_channel_width = 32;
> > +                                       else
> > +                                               mem_channel_width = 64;
> > +                                       if (vram_width)
> > +                                               *vram_width = mem_channel_number * mem_channel_width;
> >                                         if (vram_type)
> >                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
> >                                         break;
> > --
> > 2.40.1
> >

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting
  2023-06-15 13:17   ` Alex Deucher
@ 2023-06-15 13:56     ` Zhang, Hawking
  0 siblings, 0 replies; 4+ messages in thread
From: Zhang, Hawking @ 2023-06-15 13:56 UTC (permalink / raw)
  To: Alex Deucher, Deucher, Alexander; +Cc: amd-gfx

[AMD Official Use Only - General]

Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Thursday, June 15, 2023 21:18
To: Deucher, Alexander <Alexander.Deucher@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting

Ping?

On Mon, Jun 12, 2023 at 5:47 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> Ping?
>
> On Wed, Jun 7, 2023 at 12:46 PM Alex Deucher <alexander.deucher@amd.com> wrote:
> >
> > DDR5 channels are 32 bit rather than 64, report the width properly
> > in the log.
> >
> > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2468
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >  .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 20
> > +++++++++++++------
> >  1 file changed, 14 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > index ef4b9a41f20a..6b3bdc27f778 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> > @@ -327,10 +327,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> >                                         mem_channel_number = igp_info->v11.umachannelnumber;
> >                                         if (!mem_channel_number)
> >                                                 mem_channel_number = 1;
> > -                                       /* channel width is 64 */
> > -                                       if (vram_width)
> > -                                               *vram_width = mem_channel_number * 64;
> >                                         mem_type =
> > igp_info->v11.memorytype;
> > +                                       if ((mem_type == Ddr5MemType) ||
> > +                                           (mem_type == LpDdr5MemType))
> > +                                               mem_channel_width = 32;
> > +                                       else
> > +                                               mem_channel_width = 64;
> > +                                       if (vram_width)
> > +                                               *vram_width =
> > + mem_channel_number * mem_channel_width;
> >                                         if (vram_type)
> >                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
> >                                         break; @@ -345,10 +349,14 @@
> > amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
> >                                         mem_channel_number = igp_info->v21.umachannelnumber;
> >                                         if (!mem_channel_number)
> >                                                 mem_channel_number = 1;
> > -                                       /* channel width is 64 */
> > -                                       if (vram_width)
> > -                                               *vram_width = mem_channel_number * 64;
> >                                         mem_type =
> > igp_info->v21.memorytype;
> > +                                       if ((mem_type == Ddr5MemType) ||
> > +                                           (mem_type == LpDdr5MemType))
> > +                                               mem_channel_width = 32;
> > +                                       else
> > +                                               mem_channel_width = 64;
> > +                                       if (vram_width)
> > +                                               *vram_width =
> > + mem_channel_number * mem_channel_width;
> >                                         if (vram_type)
> >                                                 *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
> >                                         break;
> > --
> > 2.40.1
> >

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-06-15 13:56 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-07 16:46 [PATCH] drm/amdgpu/atomfirmware: fix DDR5 width reporting Alex Deucher
2023-06-12 21:47 ` Alex Deucher
2023-06-15 13:17   ` Alex Deucher
2023-06-15 13:56     ` Zhang, Hawking

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