[PATCH 1/9] drm/amd/powerplay: export new smu messages for vega10

[PATCH 1/9] drm/amd/powerplay: export new smu messages for vega10

[Rex Zhu]

Change-Id: I5afa09980174ef191c7aa4e4f9dadaaa189783ca
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
index cb070eb..d06ece4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
@@ -124,6 +124,8 @@
 #define PPSMC_MSG_NumOfDisplays                  0x56
 #define PPSMC_MSG_ReadSerialNumTop32             0x58
 #define PPSMC_MSG_ReadSerialNumBottom32          0x59
+#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x5A
+#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x5B
 #define PPSMC_MSG_RunAcgBtc                      0x5C
 #define PPSMC_MSG_RunAcgInClosedLoop             0x5D
 #define PPSMC_MSG_RunAcgInOpenLoop               0x5E
-- 
1.9.1

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[PATCH 2/9] drm/amd/powerplay: add new function point in hwmgr.

[Rex Zhu]

used for notify SMU the allocated buffer address.

Change-Id: I91badca7729b8d9c35faf7fc09dbdee70c26099a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 126b44d..004a40e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -363,6 +363,12 @@ struct pp_hwmgr_func {
 	int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
 	int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
 	int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
+	int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
+					uint32_t virtual_addr_low,
+					uint32_t virtual_addr_hi,
+					uint32_t mc_addr_low,
+					uint32_t mc_addr_hi,
+					uint32_t size);
 };
 
 struct pp_table_func {
-- 
1.9.1

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[PATCH 3/9] drm/amd/powrplay: implement function notify_cac_buffer_info on Vega

[Rex Zhu]

Change-Id: I4d50bf04ba6f5caf6919b6177517c7b38b9a606a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 48de45e..ebaea5c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4994,6 +4994,33 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
 	return 0;
 }
 
+static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+					uint32_t virtual_addr_low,
+					uint32_t virtual_addr_hi,
+					uint32_t mc_addr_low,
+					uint32_t mc_addr_hi,
+					uint32_t size)
+{
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_SetSystemVirtualDramAddrHigh,
+					virtual_addr_hi);
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_SetSystemVirtualDramAddrLow,
+					virtual_addr_low);
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramLogSetDramAddrHigh,
+					mc_addr_hi);
+
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramLogSetDramAddrLow,
+					mc_addr_low);
+
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramLogSetDramSize,
+					size);
+	return 0;
+}
+
 static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
 		const void *info)
 {
@@ -5079,6 +5106,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
 	.get_mclk_od = vega10_get_mclk_od,
 	.set_mclk_od = vega10_set_mclk_od,
 	.avfs_control = vega10_avfs_enable,
+	.notify_cac_buffer_info = vega10_notify_cac_buffer_info,
 	.register_internal_thermal_interrupt = vega10_register_thermal_interrupt,
 };
 
-- 
1.9.1

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[PATCH 4/9] drm/amd/powerplay: implement function notify_cac_buffer_info on VI

[Rex Zhu]

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 28 +++++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 42 ++++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h         |  5 +++
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c      | 10 ++++++
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c    | 10 ++++++
 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c | 10 ++++++
 .../gpu/drm/amd/powerplay/smumgr/polaris10_smc.c   | 10 ++++++
 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c   | 10 ++++++
 8 files changed, 125 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 189f3b5..a91b58d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1871,6 +1871,33 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	}
 }
 
+static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+					uint32_t virtual_addr_low,
+					uint32_t virtual_addr_hi,
+					uint32_t mc_addr_low,
+					uint32_t mc_addr_hi,
+					uint32_t size)
+{
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramAddrHiVirtual,
+					mc_addr_hi);
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramAddrLoVirtual,
+					mc_addr_low);
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramAddrHiPhysical,
+					virtual_addr_hi);
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramAddrLoPhysical,
+					virtual_addr_low);
+
+	smum_send_msg_to_smc_with_parameter(hwmgr,
+					PPSMC_MSG_DramBufferSize,
+					size);
+	return 0;
+}
+
+
 static const struct pp_hwmgr_func cz_hwmgr_funcs = {
 	.backend_init = cz_hwmgr_backend_init,
 	.backend_fini = cz_hwmgr_backend_fini,
@@ -1900,6 +1927,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	.dynamic_state_management_enable = cz_enable_dpm_tasks,
 	.power_state_set = cz_set_power_state_tasks,
 	.dynamic_state_management_disable = cz_disable_dpm_tasks,
+	.notify_cac_buffer_info = cz_notify_cac_buffer_info,
 };
 
 int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4826b29..e32f18a 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4645,6 +4645,47 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
 	return 0;
 }
 
+static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
+					uint32_t virtual_addr_low,
+					uint32_t virtual_addr_hi,
+					uint32_t mc_addr_low,
+					uint32_t mc_addr_hi,
+					uint32_t size)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+					data->soft_regs_start +
+					smum_get_offsetof(hwmgr,
+					SMU_SoftRegisters, DRAM_LOG_ADDR_H),
+					mc_addr_hi);
+
+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+					data->soft_regs_start +
+					smum_get_offsetof(hwmgr,
+					SMU_SoftRegisters, DRAM_LOG_ADDR_L),
+					mc_addr_low);
+
+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+					data->soft_regs_start +
+					smum_get_offsetof(hwmgr,
+					SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
+					virtual_addr_hi);
+
+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+					data->soft_regs_start +
+					smum_get_offsetof(hwmgr,
+					SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
+					virtual_addr_low);
+
+	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
+					data->soft_regs_start +
+					smum_get_offsetof(hwmgr,
+					SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
+					size);
+	return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
 	.backend_init = &smu7_hwmgr_backend_init,
 	.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4696,6 +4737,7 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
 	.avfs_control = smu7_avfs_control,
 	.disable_smc_firmware_ctf = smu7_thermal_disable_alert,
 	.start_thermal_controller = smu7_start_thermal_controller,
+	.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index 7c9aba8..b1b27b2 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -75,6 +75,11 @@ enum SMU_MEMBER {
 	VceBootLevel,
 	SamuBootLevel,
 	LowSclkInterruptThreshold,
+	DRAM_LOG_ADDR_H,
+	DRAM_LOG_ADDR_L,
+	DRAM_LOG_PHY_ADDR_H,
+	DRAM_LOG_PHY_ADDR_L,
+	DRAM_LOG_BUFF_SIZE,
 };
 
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
index 0017b9e..4d672cd 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
@@ -2266,6 +2266,16 @@ static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
 			return offsetof(SMU7_SoftRegisters, PreVBlankGap);
 		case VBlankTimeout:
 			return offsetof(SMU7_SoftRegisters, VBlankTimeout);
+		case DRAM_LOG_ADDR_H:
+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);
+		case DRAM_LOG_ADDR_L:
+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);
+		case DRAM_LOG_PHY_ADDR_H:
+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+		case DRAM_LOG_PHY_ADDR_L:
+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+		case DRAM_LOG_BUFF_SIZE:
+			return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
 		}
 	case SMU_Discrete_DpmTable:
 		switch (member) {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
index b1a66b5..e130b77 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
@@ -2199,6 +2199,16 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
 			return offsetof(SMU73_SoftRegisters, VBlankTimeout);
 		case UcodeLoadStatus:
 			return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
+		case DRAM_LOG_ADDR_H:
+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
+		case DRAM_LOG_ADDR_L:
+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
+		case DRAM_LOG_PHY_ADDR_H:
+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+		case DRAM_LOG_PHY_ADDR_L:
+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+		case DRAM_LOG_BUFF_SIZE:
+			return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
 		}
 	case SMU_Discrete_DpmTable:
 		switch (member) {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
index efb0fc0..da0c93b 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
@@ -2125,6 +2125,16 @@ uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
 			return offsetof(SMU71_SoftRegisters, VBlankTimeout);
 		case UcodeLoadStatus:
 			return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
+		case DRAM_LOG_ADDR_H:
+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
+		case DRAM_LOG_ADDR_L:
+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
+		case DRAM_LOG_PHY_ADDR_H:
+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+		case DRAM_LOG_PHY_ADDR_L:
+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+		case DRAM_LOG_BUFF_SIZE:
+			return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
 		}
 	case SMU_Discrete_DpmTable:
 		switch (member) {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
index c92ea38..113cadb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
@@ -2190,6 +2190,16 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
 			return offsetof(SMU74_SoftRegisters, VBlankTimeout);
 		case UcodeLoadStatus:
 			return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
+		case DRAM_LOG_ADDR_H:
+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
+		case DRAM_LOG_ADDR_L:
+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
+		case DRAM_LOG_PHY_ADDR_H:
+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+		case DRAM_LOG_PHY_ADDR_L:
+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+		case DRAM_LOG_BUFF_SIZE:
+			return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
 		}
 	case SMU_Discrete_DpmTable:
 		switch (member) {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
index 1f720cc..6675a85 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
@@ -2668,6 +2668,16 @@ uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
 			return offsetof(SMU72_SoftRegisters, VBlankTimeout);
 		case UcodeLoadStatus:
 			return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
+		case DRAM_LOG_ADDR_H:
+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H);
+		case DRAM_LOG_ADDR_L:
+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L);
+		case DRAM_LOG_PHY_ADDR_H:
+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
+		case DRAM_LOG_PHY_ADDR_L:
+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
+		case DRAM_LOG_BUFF_SIZE:
+			return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE);
 		}
 	case SMU_Discrete_DpmTable:
 		switch (member) {
-- 
1.9.1

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[PATCH 5/9] drm/amdgpu: add new pp function point notify_smu_memory_info

[Rex Zhu]

Change-Id: Ib915cd5ac32a6b75667ff6e8ddafcea61e06cd67
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h        | 6 ++++++
 drivers/gpu/drm/amd/include/kgd_pp_interface.h | 5 +++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 56caaee..a8437a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -360,6 +360,12 @@ enum amdgpu_pcie_gen {
 		((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\
 			(adev)->powerplay.pp_handle, msg_id))
 
+#define amdgpu_dpm_notify_smu_memory_info(adev, virtual_addr_low, \
+			virtual_addr_hi, mc_addr_low, mc_addr_hi, size) \
+		((adev)->powerplay.pp_funcs->notify_smu_memory_info)( \
+			(adev)->powerplay.pp_handle, virtual_addr_low, \
+			virtual_addr_hi, mc_addr_low, mc_addr_hi, size)
+
 struct amdgpu_dpm {
 	struct amdgpu_ps        *ps;
 	/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index f104668..eab504e 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -260,6 +260,11 @@ struct amd_pm_funcs {
 	int (*load_firmware)(void *handle);
 	int (*wait_for_fw_loading_complete)(void *handle);
 	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
+	int (*notify_smu_memory_info)(void *handle, uint32_t virtual_addr_low,
+					uint32_t virtual_addr_hi,
+					uint32_t mc_addr_low,
+					uint32_t mc_addr_hi,
+					uint32_t size);
 /* export to DC */
 	u32 (*get_sclk)(void *handle, bool low);
 	u32 (*get_mclk)(void *handle, bool low);
-- 
1.9.1

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[PATCH 6/9] drm/amd/powerplay: implement notify_smu_memory_info on Powerplay

[Rex Zhu]

Change-Id: I69a8a7637be35b9b03d7f7390cd3571cd24f9781
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 36 +++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 463905b..c7ab8b3 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1163,6 +1163,41 @@ static int pp_dpm_switch_power_profile(void *handle,
 	return 0;
 }
 
+static int pp_dpm_notify_smu_memory_info(void *handle,
+					uint32_t virtual_addr_low,
+					uint32_t virtual_addr_hi,
+					uint32_t mc_addr_low,
+					uint32_t mc_addr_hi,
+					uint32_t size)
+{
+	struct pp_hwmgr  *hwmgr;
+	struct pp_instance *pp_handle = (struct pp_instance *)handle;
+	int ret = 0;
+
+	ret = pp_check(pp_handle);
+
+	if (ret)
+		return ret;
+
+	hwmgr = pp_handle->hwmgr;
+
+	if (hwmgr->hwmgr_func->notify_cac_buffer_info == NULL) {
+		pr_info("%s was not implemented.\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&pp_handle->pp_lock);
+
+	ret = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, virtual_addr_low,
+					virtual_addr_hi, mc_addr_low, mc_addr_hi,
+					size);
+
+	mutex_unlock(&pp_handle->pp_lock);
+
+	return ret;
+}
+
+
 /* export this function to DAL */
 
 static int pp_display_configuration_change(void *handle,
@@ -1434,6 +1469,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
 	.set_power_profile_state = pp_dpm_set_power_profile_state,
 	.switch_power_profile = pp_dpm_switch_power_profile,
 	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
+	.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
 /* export to DC */
 	.get_sclk = pp_dpm_get_sclk,
 	.get_mclk = pp_dpm_get_mclk,
-- 
1.9.1

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[PATCH 7/9] drm/amdgpu: add smu_memory_pool_size module parameter

[Rex Zhu]

this allow allocate system memmoy for smu
debug usage.

Change-Id: Iac0489e528395448abeaf23a22cd6a1031a5b55b
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 07a699d..3a79d41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -132,6 +132,7 @@
 #ifdef CONFIG_DRM_AMDGPU_CIK
 extern int amdgpu_cik_support;
 #endif
+extern uint amdgpu_smu_memory_pool_size;
 
 #define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 374a7a1..a7b6732 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -125,6 +125,7 @@
 int amdgpu_job_hang_limit = 0;
 int amdgpu_lbpw = -1;
 int amdgpu_compute_multipipe = -1;
+uint amdgpu_smu_memory_pool_size = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -300,6 +301,10 @@
 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 #endif
 
+MODULE_PARM_DESC(smu_memory_pool_size,
+	"Allocate system memory for smu debug usage, 0 = disable,"
+		"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
+module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
 
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
-- 
1.9.1

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[PATCH 8/9] drm/amdgpu: allocate requested gtt buffer for smu

[Rex Zhu]

v2: simplify check smu_memory_size code.
    simplify allocate smu memroy code.

Change-Id: I8eb4f542dc2351c6393e4723f4985df92ff527cd
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 79 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  3 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |  2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |  3 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |  2 +
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  2 +
 7 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3a79d41..534b313 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1615,6 +1615,8 @@ struct amdgpu_device {
 	bool has_hw_reset;
 	u8				reset_magic[AMDGPU_RESET_MAGIC_NUM];
 
+	struct amdgpu_bo		*smu_prv_buffer;
+
 	/* record last mm index being written through WREG32*/
 	unsigned long last_mm_index;
 	bool                            in_sriov_reset;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 24f6e3c..9311096 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1077,6 +1077,46 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
 	amdgpu_vm_size = -1;
 }
 
+static void amdgpu_check_smu_prv_buffer_size(struct amdgpu_device *adev)
+{
+	struct sysinfo si;
+	bool is_os_64 = (sizeof(void *) == 8) ? true : false;
+	uint64_t total_memory;
+	uint64_t dram_size_seven_GB = 0x1B8000000;
+	uint64_t dram_size_three_GB = 0xB8000000;
+
+	if (amdgpu_smu_memory_pool_size == 0)
+		return;
+
+	if (!is_os_64) {
+		DRM_WARN("Not 64-bit OS, feature not supported\n");
+		goto def_value;
+	}
+	si_meminfo(&si);
+	total_memory = (uint64_t)si.totalram * si.mem_unit;
+
+	if ((amdgpu_smu_memory_pool_size == 1) ||
+		(amdgpu_smu_memory_pool_size == 2)) {
+		if (total_memory < dram_size_three_GB)
+			goto def_value1;
+	} else if ((amdgpu_smu_memory_pool_size == 4) ||
+		(amdgpu_smu_memory_pool_size == 8)) {
+		if (total_memory < dram_size_seven_GB)
+			goto def_value1;
+	} else {
+		DRM_WARN("Smu memory pool size not supported\n");
+		goto def_value;
+	}
+	amdgpu_smu_memory_pool_size = amdgpu_smu_memory_pool_size << 28;
+
+	return;
+
+def_value1:
+	DRM_WARN("No enough system memory\n");
+def_value:
+	amdgpu_smu_memory_pool_size = 0;
+}
+
 /**
  * amdgpu_check_arguments - validate module params
  *
@@ -1118,6 +1158,8 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
 		amdgpu_vm_fragment_size = -1;
 	}
 
+	amdgpu_check_smu_prv_buffer_size(adev);
+
 	amdgpu_check_vm_size(adev);
 
 	amdgpu_check_block_size(adev);
@@ -2027,6 +2069,36 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
 	return amdgpu_device_asic_has_dc_support(adev->asic_type);
 }
 
+static void amdgpu_alloc_mem_for_smu(struct amdgpu_device *adev)
+{
+	int r = -EINVAL;
+	void *cpu_ptr = NULL;
+	uint64_t gpu_addr;
+
+	if (amdgpu_bo_create_kernel(adev, amdgpu_smu_memory_pool_size,
+				       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
+				       &adev->smu_prv_buffer,
+				       &gpu_addr,
+				       &cpu_ptr)) {
+		DRM_ERROR("amdgpu: failed to create smu prv buffer (%d).\n", r);
+		return;
+	}
+
+	if (adev->powerplay.pp_funcs->notify_smu_memory_info)
+		r = amdgpu_dpm_notify_smu_memory_info(adev,
+					lower_32_bits((unsigned long)cpu_ptr),
+					upper_32_bits((unsigned long)cpu_ptr),
+					lower_32_bits(gpu_addr),
+					upper_32_bits(gpu_addr),
+					amdgpu_smu_memory_pool_size);
+
+	if (r) {
+		amdgpu_bo_free_kernel(&adev->smu_prv_buffer, NULL, NULL);
+		adev->smu_prv_buffer = NULL;
+		DRM_ERROR("amdgpu: failed to notify SMU buffer address.\n");
+	}
+}
+
 /**
  * amdgpu_device_init - initialize the driver
  *
@@ -2307,6 +2379,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 			DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
 	}
 
+	if (amdgpu_smu_memory_pool_size)
+		amdgpu_alloc_mem_for_smu(adev);
+
 	/* enable clockgating, etc. after ib tests, etc. since some blocks require
 	 * explicit gating rather than handling it automatically.
 	 */
@@ -2352,6 +2427,10 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
 		release_firmware(adev->firmware.gpu_info_fw);
 		adev->firmware.gpu_info_fw = NULL;
 	}
+	if (adev->smu_prv_buffer) {
+		amdgpu_bo_free_kernel(&adev->smu_prv_buffer, NULL, NULL);
+		adev->smu_prv_buffer = NULL;
+	}
 	adev->accel_working = false;
 	cancel_delayed_work_sync(&adev->late_init_work);
 	/* free i2c buses */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 1086f03..75e10b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1270,6 +1270,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 			       adev->mc.mc_vram_size);
 	else
 		gtt_size = (uint64_t)amdgpu_gtt_size << 20;
+
+	gtt_size = gtt_size + amdgpu_smu_memory_pool_size;
+
 	r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
 	if (r) {
 		DRM_ERROR("Failed initializing GTT heap.\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index f4603a7..e1f97b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -350,6 +350,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 		adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 	}
 
+	adev->mc.gart_size += amdgpu_smu_memory_pool_size;
+
 	gmc_v6_0_vram_gtt_location(adev, &adev->mc);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index b0528ca..ac481a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -407,6 +407,9 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 		adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 	}
 
+
+	adev->mc.gart_size += amdgpu_smu_memory_pool_size;
+
 	gmc_v7_0_vram_gtt_location(adev, &adev->mc);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index f368cfe..0f5bccc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -582,6 +582,8 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 		adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 	}
 
+	adev->mc.gart_size += amdgpu_smu_memory_pool_size;
+
 	gmc_v8_0_vram_gtt_location(adev, &adev->mc);
 
 	return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 6216993..09cf381 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -511,6 +511,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
 		adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
 	}
 
+	adev->mc.gart_size += amdgpu_smu_memory_pool_size;
+
 	gmc_v9_0_vram_gtt_location(adev, &adev->mc);
 
 	return 0;
-- 
1.9.1

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[PATCH 9/9] drm/amd/powerplay: delete an outdated comment in amd_powerplay.c

[Rex Zhu]

Change-Id: I96abfea4eb7d257d2b6461392683c280b268ef76
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index c7ab8b3..6b0cf8e 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1197,9 +1197,6 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
 	return ret;
 }
 
-
-/* export this function to DAL */
-
 static int pp_display_configuration_change(void *handle,
 	const struct amd_pp_display_configuration *display_config)
 {
-- 
1.9.1

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Re: [PATCH 1/9] drm/amd/powerplay: export new smu messages for vega10

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:41 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I5afa09980174ef191c7aa4e4f9dadaaa189783ca
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
> index cb070eb..d06ece4 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
> @@ -124,6 +124,8 @@
>  #define PPSMC_MSG_NumOfDisplays                  0x56
>  #define PPSMC_MSG_ReadSerialNumTop32             0x58
>  #define PPSMC_MSG_ReadSerialNumBottom32          0x59
> +#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x5A
> +#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x5B
>  #define PPSMC_MSG_RunAcgBtc                      0x5C
>  #define PPSMC_MSG_RunAcgInClosedLoop             0x5D
>  #define PPSMC_MSG_RunAcgInOpenLoop               0x5E
> --
> 1.9.1
>
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Re: [PATCH 2/9] drm/amd/powerplay: add new function point in hwmgr.

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:41 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> used for notify SMU the allocated buffer address.
>
> Change-Id: I91badca7729b8d9c35faf7fc09dbdee70c26099a
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 126b44d..004a40e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -363,6 +363,12 @@ struct pp_hwmgr_func {
>         int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
>         int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
>         int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
> +       int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
> +                                       uint32_t virtual_addr_low,
> +                                       uint32_t virtual_addr_hi,
> +                                       uint32_t mc_addr_low,
> +                                       uint32_t mc_addr_hi,
> +                                       uint32_t size);
>  };
>
>  struct pp_table_func {
> --
> 1.9.1
>
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Re: [PATCH 3/9] drm/amd/powrplay: implement function notify_cac_buffer_info on Vega

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:42 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I4d50bf04ba6f5caf6919b6177517c7b38b9a606a
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 28 ++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 48de45e..ebaea5c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4994,6 +4994,33 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
>         return 0;
>  }
>
> +static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> +                                       uint32_t virtual_addr_low,
> +                                       uint32_t virtual_addr_hi,
> +                                       uint32_t mc_addr_low,
> +                                       uint32_t mc_addr_hi,
> +                                       uint32_t size)
> +{
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_SetSystemVirtualDramAddrHigh,
> +                                       virtual_addr_hi);
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_SetSystemVirtualDramAddrLow,
> +                                       virtual_addr_low);
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramLogSetDramAddrHigh,
> +                                       mc_addr_hi);
> +
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramLogSetDramAddrLow,
> +                                       mc_addr_low);
> +
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramLogSetDramSize,
> +                                       size);
> +       return 0;
> +}
> +
>  static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
>                 const void *info)
>  {
> @@ -5079,6 +5106,7 @@ static int vega10_register_thermal_interrupt(struct pp_hwmgr *hwmgr,
>         .get_mclk_od = vega10_get_mclk_od,
>         .set_mclk_od = vega10_set_mclk_od,
>         .avfs_control = vega10_avfs_enable,
> +       .notify_cac_buffer_info = vega10_notify_cac_buffer_info,
>         .register_internal_thermal_interrupt = vega10_register_thermal_interrupt,
>  };
>
> --
> 1.9.1
>
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Re: [PATCH 4/9] drm/amd/powerplay: implement function notify_cac_buffer_info on VI

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:42 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c     | 28 +++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 42 ++++++++++++++++++++++
>  drivers/gpu/drm/amd/powerplay/inc/smumgr.h         |  5 +++
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c      | 10 ++++++
>  drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c    | 10 ++++++
>  drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c | 10 ++++++
>  .../gpu/drm/amd/powerplay/smumgr/polaris10_smc.c   | 10 ++++++
>  drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c   | 10 ++++++
>  8 files changed, 125 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 189f3b5..a91b58d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1871,6 +1871,33 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>         }
>  }
>
> +static int cz_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> +                                       uint32_t virtual_addr_low,
> +                                       uint32_t virtual_addr_hi,
> +                                       uint32_t mc_addr_low,
> +                                       uint32_t mc_addr_hi,
> +                                       uint32_t size)
> +{
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramAddrHiVirtual,
> +                                       mc_addr_hi);
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramAddrLoVirtual,
> +                                       mc_addr_low);
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramAddrHiPhysical,
> +                                       virtual_addr_hi);
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramAddrLoPhysical,
> +                                       virtual_addr_low);
> +
> +       smum_send_msg_to_smc_with_parameter(hwmgr,
> +                                       PPSMC_MSG_DramBufferSize,
> +                                       size);
> +       return 0;
> +}
> +
> +
>  static const struct pp_hwmgr_func cz_hwmgr_funcs = {
>         .backend_init = cz_hwmgr_backend_init,
>         .backend_fini = cz_hwmgr_backend_fini,
> @@ -1900,6 +1927,7 @@ static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>         .dynamic_state_management_enable = cz_enable_dpm_tasks,
>         .power_state_set = cz_set_power_state_tasks,
>         .dynamic_state_management_disable = cz_disable_dpm_tasks,
> +       .notify_cac_buffer_info = cz_notify_cac_buffer_info,
>  };
>
>  int cz_init_function_pointers(struct pp_hwmgr *hwmgr)
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 4826b29..e32f18a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4645,6 +4645,47 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
>         return 0;
>  }
>
> +static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> +                                       uint32_t virtual_addr_low,
> +                                       uint32_t virtual_addr_hi,
> +                                       uint32_t mc_addr_low,
> +                                       uint32_t mc_addr_hi,
> +                                       uint32_t size)
> +{
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> +       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                       data->soft_regs_start +
> +                                       smum_get_offsetof(hwmgr,
> +                                       SMU_SoftRegisters, DRAM_LOG_ADDR_H),
> +                                       mc_addr_hi);
> +
> +       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                       data->soft_regs_start +
> +                                       smum_get_offsetof(hwmgr,
> +                                       SMU_SoftRegisters, DRAM_LOG_ADDR_L),
> +                                       mc_addr_low);
> +
> +       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                       data->soft_regs_start +
> +                                       smum_get_offsetof(hwmgr,
> +                                       SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H),
> +                                       virtual_addr_hi);
> +
> +       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                       data->soft_regs_start +
> +                                       smum_get_offsetof(hwmgr,
> +                                       SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L),
> +                                       virtual_addr_low);
> +
> +       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
> +                                       data->soft_regs_start +
> +                                       smum_get_offsetof(hwmgr,
> +                                       SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE),
> +                                       size);
> +       return 0;
> +}
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>         .backend_init = &smu7_hwmgr_backend_init,
>         .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -4696,6 +4737,7 @@ static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
>         .avfs_control = smu7_avfs_control,
>         .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
>         .start_thermal_controller = smu7_start_thermal_controller,
> +       .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> index 7c9aba8..b1b27b2 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> @@ -75,6 +75,11 @@ enum SMU_MEMBER {
>         VceBootLevel,
>         SamuBootLevel,
>         LowSclkInterruptThreshold,
> +       DRAM_LOG_ADDR_H,
> +       DRAM_LOG_ADDR_L,
> +       DRAM_LOG_PHY_ADDR_H,
> +       DRAM_LOG_PHY_ADDR_L,
> +       DRAM_LOG_BUFF_SIZE,
>  };
>
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> index 0017b9e..4d672cd 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smc.c
> @@ -2266,6 +2266,16 @@ static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
>                         return offsetof(SMU7_SoftRegisters, PreVBlankGap);
>                 case VBlankTimeout:
>                         return offsetof(SMU7_SoftRegisters, VBlankTimeout);
> +               case DRAM_LOG_ADDR_H:
> +                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_H);
> +               case DRAM_LOG_ADDR_L:
> +                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_ADDR_L);
> +               case DRAM_LOG_PHY_ADDR_H:
> +                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
> +               case DRAM_LOG_PHY_ADDR_L:
> +                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
> +               case DRAM_LOG_BUFF_SIZE:
> +                       return offsetof(SMU7_SoftRegisters, DRAM_LOG_BUFF_SIZE);
>                 }
>         case SMU_Discrete_DpmTable:
>                 switch (member) {
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
> index b1a66b5..e130b77 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
> @@ -2199,6 +2199,16 @@ uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
>                         return offsetof(SMU73_SoftRegisters, VBlankTimeout);
>                 case UcodeLoadStatus:
>                         return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
> +               case DRAM_LOG_ADDR_H:
> +                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
> +               case DRAM_LOG_ADDR_L:
> +                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
> +               case DRAM_LOG_PHY_ADDR_H:
> +                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
> +               case DRAM_LOG_PHY_ADDR_L:
> +                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
> +               case DRAM_LOG_BUFF_SIZE:
> +                       return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
>                 }
>         case SMU_Discrete_DpmTable:
>                 switch (member) {
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
> index efb0fc0..da0c93b 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
> @@ -2125,6 +2125,16 @@ uint32_t iceland_get_offsetof(uint32_t type, uint32_t member)
>                         return offsetof(SMU71_SoftRegisters, VBlankTimeout);
>                 case UcodeLoadStatus:
>                         return offsetof(SMU71_SoftRegisters, UcodeLoadStatus);
> +               case DRAM_LOG_ADDR_H:
> +                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_H);
> +               case DRAM_LOG_ADDR_L:
> +                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_ADDR_L);
> +               case DRAM_LOG_PHY_ADDR_H:
> +                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
> +               case DRAM_LOG_PHY_ADDR_L:
> +                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
> +               case DRAM_LOG_BUFF_SIZE:
> +                       return offsetof(SMU71_SoftRegisters, DRAM_LOG_BUFF_SIZE);
>                 }
>         case SMU_Discrete_DpmTable:
>                 switch (member) {
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
> index c92ea38..113cadb 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
> @@ -2190,6 +2190,16 @@ uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
>                         return offsetof(SMU74_SoftRegisters, VBlankTimeout);
>                 case UcodeLoadStatus:
>                         return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
> +               case DRAM_LOG_ADDR_H:
> +                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
> +               case DRAM_LOG_ADDR_L:
> +                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
> +               case DRAM_LOG_PHY_ADDR_H:
> +                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
> +               case DRAM_LOG_PHY_ADDR_L:
> +                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
> +               case DRAM_LOG_BUFF_SIZE:
> +                       return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
>                 }
>         case SMU_Discrete_DpmTable:
>                 switch (member) {
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
> index 1f720cc..6675a85 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
> @@ -2668,6 +2668,16 @@ uint32_t tonga_get_offsetof(uint32_t type, uint32_t member)
>                         return offsetof(SMU72_SoftRegisters, VBlankTimeout);
>                 case UcodeLoadStatus:
>                         return offsetof(SMU72_SoftRegisters, UcodeLoadStatus);
> +               case DRAM_LOG_ADDR_H:
> +                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H);
> +               case DRAM_LOG_ADDR_L:
> +                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L);
> +               case DRAM_LOG_PHY_ADDR_H:
> +                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
> +               case DRAM_LOG_PHY_ADDR_L:
> +                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
> +               case DRAM_LOG_BUFF_SIZE:
> +                       return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE);
>                 }
>         case SMU_Discrete_DpmTable:
>                 switch (member) {
> --
> 1.9.1
>
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 9/9] drm/amd/powerplay: delete an outdated comment in amd_powerplay.c

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:42 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I96abfea4eb7d257d2b6461392683c280b268ef76
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index c7ab8b3..6b0cf8e 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1197,9 +1197,6 @@ static int pp_dpm_notify_smu_memory_info(void *handle,
>         return ret;
>  }
>
> -
> -/* export this function to DAL */
> -
>  static int pp_display_configuration_change(void *handle,
>         const struct amd_pp_display_configuration *display_config)
>  {
> --
> 1.9.1
>
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 7/9] drm/amdgpu: add smu_memory_pool_size module parameter

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:42 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> this allow allocate system memmoy for smu
> debug usage.
>
> Change-Id: Iac0489e528395448abeaf23a22cd6a1031a5b55b
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

I'd prefer to expose this via debugfs so we can enable/disable it on
the fly.  We can clamp the size based on the gart size and if we want
a larger buffer, just tell the user to change amdgpu.gart_size

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h     | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 07a699d..3a79d41 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -132,6 +132,7 @@
>  #ifdef CONFIG_DRM_AMDGPU_CIK
>  extern int amdgpu_cik_support;
>  #endif
> +extern uint amdgpu_smu_memory_pool_size;
>
>  #define AMDGPU_DEFAULT_GTT_SIZE_MB             3072ULL /* 3GB by default */
>  #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS         3000
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 374a7a1..a7b6732 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -125,6 +125,7 @@
>  int amdgpu_job_hang_limit = 0;
>  int amdgpu_lbpw = -1;
>  int amdgpu_compute_multipipe = -1;
> +uint amdgpu_smu_memory_pool_size = 0;
>
>  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
>  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
> @@ -300,6 +301,10 @@
>  module_param_named(cik_support, amdgpu_cik_support, int, 0444);
>  #endif
>
> +MODULE_PARM_DESC(smu_memory_pool_size,
> +       "Allocate system memory for smu debug usage, 0 = disable,"
> +               "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
> +module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
>
>  static const struct pci_device_id pciidlist[] = {
>  #ifdef  CONFIG_DRM_AMDGPU_SI
> --
> 1.9.1
>
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Re: [PATCH 8/9] drm/amdgpu: allocate requested gtt buffer for smu

[Alex Deucher]

On Mon, Oct 9, 2017 at 12:42 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> v2: simplify check smu_memory_size code.
>     simplify allocate smu memroy code.

See my comment in patch 7.  More comments below.

>
> Change-Id: I8eb4f542dc2351c6393e4723f4985df92ff527cd
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h        |  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 79 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c    |  3 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c      |  2 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c      |  3 ++
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c      |  2 +
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c      |  2 +
>  7 files changed, 93 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3a79d41..534b313 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1615,6 +1615,8 @@ struct amdgpu_device {
>         bool has_hw_reset;
>         u8                              reset_magic[AMDGPU_RESET_MAGIC_NUM];
>
> +       struct amdgpu_bo                *smu_prv_buffer;
> +
>         /* record last mm index being written through WREG32*/
>         unsigned long last_mm_index;
>         bool                            in_sriov_reset;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 24f6e3c..9311096 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1077,6 +1077,46 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
>         amdgpu_vm_size = -1;
>  }
>
> +static void amdgpu_check_smu_prv_buffer_size(struct amdgpu_device *adev)

For consistency, please prefix this function with amdgpu_device.  E.g.,
amdgpu_device_check_smu_prv_buffer_size()


> +{
> +       struct sysinfo si;
> +       bool is_os_64 = (sizeof(void *) == 8) ? true : false;
> +       uint64_t total_memory;
> +       uint64_t dram_size_seven_GB = 0x1B8000000;
> +       uint64_t dram_size_three_GB = 0xB8000000;
> +
> +       if (amdgpu_smu_memory_pool_size == 0)
> +               return;
> +
> +       if (!is_os_64) {
> +               DRM_WARN("Not 64-bit OS, feature not supported\n");
> +               goto def_value;
> +       }
> +       si_meminfo(&si);
> +       total_memory = (uint64_t)si.totalram * si.mem_unit;
> +
> +       if ((amdgpu_smu_memory_pool_size == 1) ||
> +               (amdgpu_smu_memory_pool_size == 2)) {
> +               if (total_memory < dram_size_three_GB)
> +                       goto def_value1;
> +       } else if ((amdgpu_smu_memory_pool_size == 4) ||
> +               (amdgpu_smu_memory_pool_size == 8)) {
> +               if (total_memory < dram_size_seven_GB)
> +                       goto def_value1;
> +       } else {
> +               DRM_WARN("Smu memory pool size not supported\n");
> +               goto def_value;
> +       }
> +       amdgpu_smu_memory_pool_size = amdgpu_smu_memory_pool_size << 28;
> +
> +       return;
> +
> +def_value1:
> +       DRM_WARN("No enough system memory\n");
> +def_value:
> +       amdgpu_smu_memory_pool_size = 0;
> +}
> +
>  /**
>   * amdgpu_check_arguments - validate module params
>   *
> @@ -1118,6 +1158,8 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
>                 amdgpu_vm_fragment_size = -1;
>         }
>
> +       amdgpu_check_smu_prv_buffer_size(adev);
> +
>         amdgpu_check_vm_size(adev);
>
>         amdgpu_check_block_size(adev);
> @@ -2027,6 +2069,36 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
>         return amdgpu_device_asic_has_dc_support(adev->asic_type);
>  }
>
> +static void amdgpu_alloc_mem_for_smu(struct amdgpu_device *adev)

amdgpu_device_alloc_mem_for_smu


> +{
> +       int r = -EINVAL;
> +       void *cpu_ptr = NULL;
> +       uint64_t gpu_addr;
> +
> +       if (amdgpu_bo_create_kernel(adev, amdgpu_smu_memory_pool_size,
> +                                      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
> +                                      &adev->smu_prv_buffer,
> +                                      &gpu_addr,
> +                                      &cpu_ptr)) {
> +               DRM_ERROR("amdgpu: failed to create smu prv buffer (%d).\n", r);
> +               return;
> +       }
> +
> +       if (adev->powerplay.pp_funcs->notify_smu_memory_info)
> +               r = amdgpu_dpm_notify_smu_memory_info(adev,
> +                                       lower_32_bits((unsigned long)cpu_ptr),
> +                                       upper_32_bits((unsigned long)cpu_ptr),
> +                                       lower_32_bits(gpu_addr),
> +                                       upper_32_bits(gpu_addr),
> +                                       amdgpu_smu_memory_pool_size);
> +
> +       if (r) {
> +               amdgpu_bo_free_kernel(&adev->smu_prv_buffer, NULL, NULL);
> +               adev->smu_prv_buffer = NULL;
> +               DRM_ERROR("amdgpu: failed to notify SMU buffer address.\n");
> +       }
> +}
> +
>  /**
>   * amdgpu_device_init - initialize the driver
>   *
> @@ -2307,6 +2379,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
>         }
>
> +       if (amdgpu_smu_memory_pool_size)
> +               amdgpu_alloc_mem_for_smu(adev);
> +
>         /* enable clockgating, etc. after ib tests, etc. since some blocks require
>          * explicit gating rather than handling it automatically.
>          */
> @@ -2352,6 +2427,10 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
>                 release_firmware(adev->firmware.gpu_info_fw);
>                 adev->firmware.gpu_info_fw = NULL;
>         }
> +       if (adev->smu_prv_buffer) {
> +               amdgpu_bo_free_kernel(&adev->smu_prv_buffer, NULL, NULL);
> +               adev->smu_prv_buffer = NULL;
> +       }
>         adev->accel_working = false;
>         cancel_delayed_work_sync(&adev->late_init_work);
>         /* free i2c buses */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 1086f03..75e10b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1270,6 +1270,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
>                                adev->mc.mc_vram_size);
>         else
>                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
> +
> +       gtt_size = gtt_size + amdgpu_smu_memory_pool_size;
> +
>         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
>         if (r) {
>                 DRM_ERROR("Failed initializing GTT heap.\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index f4603a7..e1f97b1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -350,6 +350,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
>                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
>         }
>
> +       adev->mc.gart_size += amdgpu_smu_memory_pool_size;
> +
>         gmc_v6_0_vram_gtt_location(adev, &adev->mc);
>
>         return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index b0528ca..ac481a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -407,6 +407,9 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
>                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
>         }
>
> +
> +       adev->mc.gart_size += amdgpu_smu_memory_pool_size;
> +
>         gmc_v7_0_vram_gtt_location(adev, &adev->mc);
>
>         return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index f368cfe..0f5bccc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -582,6 +582,8 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
>                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
>         }
>
> +       adev->mc.gart_size += amdgpu_smu_memory_pool_size;
> +
>         gmc_v8_0_vram_gtt_location(adev, &adev->mc);
>
>         return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 6216993..09cf381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -511,6 +511,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
>                 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
>         }
>
> +       adev->mc.gart_size += amdgpu_smu_memory_pool_size;
> +
>         gmc_v9_0_vram_gtt_location(adev, &adev->mc);
>
>         return 0;
> --
> 1.9.1
>
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> amd-gfx@lists.freedesktop.org
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