* [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1
@ 2024-04-17 12:51 Li Ma
2024-04-17 13:31 ` Alex Deucher
2024-04-18 5:43 ` Zhang, Yifan
0 siblings, 2 replies; 3+ messages in thread
From: Li Ma @ 2024-04-17 12:51 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, yifan1.zhang, kenneth.feng, likun.gao, Li Ma
smu v14.0.1 re-used smu v14.0.0
Signed-off-by: Li Ma <li.ma@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 3bc9662fbd28..3ad3d20830fc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -136,7 +136,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
for (i = 0; i < adev->usec_timeout; i++) {
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
else
@@ -209,7 +209,7 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags;
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
else
@@ -856,7 +856,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
// TODO
/* For MP1 SW irqs */
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
@@ -872,7 +872,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
// TODO
/* For MP1 SW irqs */
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1
2024-04-17 12:51 [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1 Li Ma
@ 2024-04-17 13:31 ` Alex Deucher
2024-04-18 5:43 ` Zhang, Yifan
1 sibling, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2024-04-17 13:31 UTC (permalink / raw)
To: Li Ma; +Cc: amd-gfx, alexander.deucher, yifan1.zhang, kenneth.feng, likun.gao
On Wed, Apr 17, 2024 at 9:02 AM Li Ma <li.ma@amd.com> wrote:
>
> smu v14.0.1 re-used smu v14.0.0
>
> Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> index 3bc9662fbd28..3ad3d20830fc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
> @@ -136,7 +136,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
> 1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
>
> for (i = 0; i < adev->usec_timeout; i++) {
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
> mp1_fw_flags = RREG32_PCIE(MP1_Public |
> (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
> else
> @@ -209,7 +209,7 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
> struct amdgpu_device *adev = smu->adev;
> uint32_t mp1_fw_flags;
>
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
> mp1_fw_flags = RREG32_PCIE(MP1_Public |
> (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
> else
> @@ -856,7 +856,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
> // TODO
>
> /* For MP1 SW irqs */
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
> val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
> val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
> WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
> @@ -872,7 +872,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
> // TODO
>
> /* For MP1 SW irqs */
> - if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
> + if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) || amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
> val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
> val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
> val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1
2024-04-17 12:51 [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1 Li Ma
2024-04-17 13:31 ` Alex Deucher
@ 2024-04-18 5:43 ` Zhang, Yifan
1 sibling, 0 replies; 3+ messages in thread
From: Zhang, Yifan @ 2024-04-18 5:43 UTC (permalink / raw)
To: Ma, Li, amd-gfx; +Cc: Deucher, Alexander, Feng, Kenneth, Gao, Likun
[AMD Official Use Only - General]
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Best Regards,
Yifan
-----Original Message-----
From: Ma, Li <Li.Ma@amd.com>
Sent: Wednesday, April 17, 2024 8:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Gao, Likun <Likun.Gao@amd.com>; Ma, Li <Li.Ma@amd.com>
Subject: [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1
smu v14.0.1 re-used smu v14.0.0
Signed-off-by: Li Ma <li.ma@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 3bc9662fbd28..3ad3d20830fc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -136,7 +136,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
for (i = 0; i < adev->usec_timeout; i++) {
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
else
@@ -209,7 +209,7 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags;
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
mp1_fw_flags = RREG32_PCIE(MP1_Public |
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
else
@@ -856,7 +856,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
// TODO
/* For MP1 SW irqs */
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val); @@ -872,7 +872,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
// TODO
/* For MP1 SW irqs */
- if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
+ if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-04-18 5:43 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2024-04-17 12:51 [PATCH] drm/amd/swsmu: add if condition for smu v14.0.1 Li Ma
2024-04-17 13:31 ` Alex Deucher
2024-04-18 5:43 ` Zhang, Yifan
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