* [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
@ 2018-01-16 12:02 Rex Zhu
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
when this bit was set on module load,
driver will allow the user over/under gpu
clock and voltage through sysfs.
by default, this bit was not set.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++----
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e679bb8..508a254 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -120,7 +120,7 @@
uint amdgpu_sdma_phase_quantum = 32;
char *amdgpu_disable_cu = NULL;
char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0xffffffff;
+uint amdgpu_pp_feature_mask = 0x2fff;
int amdgpu_ngg = 0;
int amdgpu_prim_buf_per_se = 0;
int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index e35bdc5..ebfbbcf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_CAC);
}
+ if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
+ hwmgr->od_enabled = true;
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 6f053fa..ce74e06 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3572,8 +3572,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->sclk_table.dpm_levels
[dpm_table->sclk_table.count - 1].value = sclk;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+ if (hwmgr->od_enabled) {
/* Need to do calculation based on the golden DPM table
* as the Heatmap GPU Clock axis is also based on the default values
*/
@@ -3618,8 +3617,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->mclk_table.dpm_levels
[dpm_table->mclk_table.count - 1].value = mclk;
- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+ if (hwmgr->od_enabled) {
PP_ASSERT_WITH_CODE(
(golden_dpm_table->mclk_table.dpm_levels
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index fadbc8a..12a31d1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3396,8 +3396,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
dpm_table->
gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
value = sclk;
- if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
- PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
+ if (hwmgr->od_enabled) {
/* Need to do calculation based on the golden DPM table
* as the Heatmap GPU Clock axis is also based on
* the default values
@@ -3451,9 +3450,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
mem_table.dpm_levels[dpm_table->mem_table.count - 1].
value = mclk;
- if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
- PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
+ if (hwmgr->od_enabled) {
PP_ASSERT_WITH_CODE(
golden_dpm_table->mem_table.dpm_levels
[golden_dpm_table->mem_table.count - 1].value,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 6d8183d..c496742 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
PP_SOCCLK_DPM_MASK = 0x1000,
PP_DCEFCLK_DPM_MASK = 0x2000,
+ PP_OVER_DRIVER_MASK = 0x4000,
};
enum PHM_BackEnd_Magic {
@@ -755,6 +756,7 @@ struct pp_hwmgr {
uint32_t power_profile_mode;
uint32_t pstate_sclk;
uint32_t pstate_mclk;
+ bool od_enabled;
};
struct cgs_irq_src_funcs {
--
1.9.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/8] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 12:02 ` Rex Zhu
2018-01-16 12:02 ` [PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7 Rex Zhu
` (7 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Add initial infrastructure for manual dpm control.
Change-Id: Id9d8dd3043d4c9b90854a94f9749bc70eaf9162e
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 75 ++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 14 +++++
2 files changed, 89 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index ce74e06..f3d9c64 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -793,6 +793,76 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
return 0;
}
+static int smu7_get_voltage_dependency_table(
+ const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+ uint8_t i = 0;
+ PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
+ "Voltage Lookup Table empty",
+ return -EINVAL);
+
+ dep_table->count = allowed_dep_table->count;
+ for (i=0; i<dep_table->count; i++) {
+ dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
+ dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
+ dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
+ dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
+ dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
+ dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
+ dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
+ dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
+ dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
+ dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
+ }
+
+ return 0;
+}
+
+static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)(hwmgr->pptable);
+ uint32_t i;
+
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+
+ if (table_info == NULL)
+ return -EINVAL;
+
+ dep_sclk_table = table_info->vdd_dep_on_sclk;
+ dep_mclk_table = table_info->vdd_dep_on_mclk;
+
+ odn_table->odn_core_clock_dpm_levels.num_of_pl =
+ data->golden_dpm_table.sclk_table.count;
+ for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
+ odn_table->odn_core_clock_dpm_levels.entries[i].clock =
+ data->golden_dpm_table.sclk_table.dpm_levels[i].value;
+ odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
+ odn_table->odn_core_clock_dpm_levels.entries[i].vddc = dep_sclk_table->entries[i].vddc;
+ }
+
+ smu7_get_voltage_dependency_table(dep_sclk_table,
+ (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
+
+ odn_table->odn_memory_clock_dpm_levels.num_of_pl =
+ data->golden_dpm_table.mclk_table.count;
+ for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
+ odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
+ data->golden_dpm_table.mclk_table.dpm_levels[i].value;
+ odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
+ odn_table->odn_memory_clock_dpm_levels.entries[i].vddc = dep_mclk_table->entries[i].vddc;
+ }
+
+ smu7_get_voltage_dependency_table(dep_mclk_table,
+ (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
+
+ return 0;
+}
+
static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -809,6 +879,11 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
/* save a copy of the default DPM table */
memcpy(&(data->golden_dpm_table), &(data->dpm_table),
sizeof(struct smu7_dpm_table));
+
+ /* initialize ODN table */
+ if (hwmgr->od_enabled)
+ smu7_odn_initial_default_setting(hwmgr);
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index beba25c..8eec974 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -178,9 +178,23 @@ struct smu7_pcie_perf_range {
uint16_t min;
};
+struct smu7_odn_clock_voltage_dependency_table {
+ uint32_t count;
+ phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct smu7_odn_dpm_table {
+ struct phm_odn_clock_levels odn_core_clock_dpm_levels;
+ struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
+ struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
+ struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
+ uint32_t odn_mclk_min_limit;
+};
+
struct smu7_hwmgr {
struct smu7_dpm_table dpm_table;
struct smu7_dpm_table golden_dpm_table;
+ struct smu7_odn_dpm_table odn_dpm_table;
uint32_t voting_rights_clients[8];
uint32_t static_screen_threshold_unit;
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 2/8] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI Rex Zhu
@ 2018-01-16 12:02 ` Rex Zhu
[not found] ` <1516104175-27651-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
` (6 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I54bb964a3905f675e93411f93810cc1aa1f67d12
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 401b895..fba44a5 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -107,6 +107,8 @@ enum pp_clock_type {
PP_SCLK,
PP_MCLK,
PP_PCIE,
+ OD_SCLK,
+ OD_MCLK,
};
enum amd_pp_sensors {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f3d9c64..a0007a8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4355,6 +4355,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+ struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
int i, now, size = 0;
uint32_t clock, pcie_speed;
@@ -4409,6 +4412,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
(pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
(i == now) ? "*" : "");
break;
+ case OD_SCLK:
+ if (hwmgr->od_enabled) {
+ size = sprintf(buf, "%s: \n", "OD_SCLK");
+ for (i = 0; i < odn_sclk_table->num_of_pl; i++)
+ size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+ i, odn_sclk_table->entries[i].clock / 100,
+ odn_sclk_table->entries[i].vddc);
+ }
+ break;
+ case OD_MCLK:
+ if (hwmgr->od_enabled) {
+ size = sprintf(buf, "%s: \n", "OD_MCLK");
+ for (i = 0; i < odn_mclk_table->num_of_pl; i++)
+ size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
+ i, odn_mclk_table->entries[i].clock / 100,
+ odn_mclk_table->entries[i].vddc);
+ }
+ break;
default:
break;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 2/8] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI Rex Zhu
2018-01-16 12:02 ` [PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7 Rex Zhu
@ 2018-01-16 12:02 ` Rex Zhu
[not found] ` <1516104175-27651-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file Rex Zhu
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Add odn_edit_dpm_table function
points for setting user assigned clock/voltage.
Change-Id: I7e49ffdc30b77d07b46bf12ebb275fa0ff901588
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index d6772a8..97d25cd 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -364,6 +364,12 @@ struct phm_odn_performance_level {
bool enabled;
};
+enum PHM_ODN_DPM_TABLE_TYPE {
+ PHM_ODN_SCLK_VDDC_TABLE,
+ PHM_ODN_MCLK_VDDC_TABLE,
+ PHM_ODN_RESET_DEFAULT_TABLE
+};
+
struct phm_odn_clock_levels {
uint32_t size;
uint32_t options;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index c496742..36e5378 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -345,6 +345,9 @@ struct pp_hwmgr_func {
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
+ int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
+ enum PHM_ODN_DPM_TABLE_TYPE type,
+ long *input, uint32_t size);
};
struct pp_table_func {
--
1.9.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-01-16 12:02 ` [PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
@ 2018-01-16 12:02 ` Rex Zhu
[not found] ` <1516104175-27651-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state Rex Zhu
` (4 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I46cdf4f39f4c9c448a2c76b67f1cbbfed26c7488
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 5 -----
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 6 ------
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 11 +++++++++++
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index 8eec974..1ce84cc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -34,11 +34,6 @@
#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
#define SMU7_VOLTAGE_CONTROL_MERGED 0x3
-#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
-#define DPMTABLE_UPDATE_SCLK 0x00000004
-#define DPMTABLE_UPDATE_MCLK 0x00000008
-
enum gpu_pt_config_reg_type {
GPU_CONFIGREG_MMR = 0,
GPU_CONFIGREG_SMC_IND,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 689fe9f..ab3e879 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
uint32_t dcef_clock;
};
-#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
-#define DPMTABLE_UPDATE_SCLK 0x00000004
-#define DPMTABLE_UPDATE_MCLK 0x00000008
-#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
-
struct vega10_smc_state_table {
uint32_t soc_boot_level;
uint32_t gfx_boot_level;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index 97d25cd..d846cbb 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -358,6 +358,17 @@ struct phm_clocks {
uint32_t clock[MAX_NUM_CLOCKS];
};
+#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
+#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
+#define DPMTABLE_UPDATE_SCLK 0x00000004
+#define DPMTABLE_UPDATE_MCLK 0x00000008
+#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
+
+/* To determine if sclk and mclk are in overdrive state */
+#define SCLK_OVERDRIVE_ENABLED 0x00000001
+#define MCLK_OVERDRIVE_ENABLED 0x00000002
+#define VDDC_OVERDRIVE_ENABLED 0x00000010
+
struct phm_odn_performance_level {
uint32_t clock;
uint32_t vddc;
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-01-16 12:02 ` [PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file Rex Zhu
@ 2018-01-16 12:02 ` Rex Zhu
[not found] ` <1516104175-27651-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
` (3 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
when Over-driver engine clock and voltage were set,
need to recalculate AVFS voltage on VI asics.
Change-Id: If2a2226d64c0c2aa37c2e84f36b0dad8b7dee25e
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 80 ++++++++++++++--------
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 1 +
2 files changed, 53 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index a0007a8..c69749d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
};
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -1351,6 +1350,53 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
return 0;
}
+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ if (smu_data == NULL)
+ return -EINVAL;
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ if (enable) {
+ if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_EnableAvfs),
+ "Failed to enable AVFS!",
+ return -EINVAL);
+ }
+ } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_DisableAvfs),
+ "Failed to disable AVFS!",
+ return -EINVAL);
+ }
+
+ return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ if (smu_data == NULL)
+ return -EINVAL;
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ if (smu_data->avfs.brecalculate_avfs) {
+ smu7_avfs_control(hwmgr, false);
+ smu7_avfs_control(hwmgr, true);
+ smu_data->avfs.brecalculate_avfs = true;
+ }
+ return 0;
+}
+
int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
@@ -3923,6 +3969,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
"Failed to populate and upload SCLK MCLK DPM levels!",
result = tmp_result);
+ tmp_result = smu7_update_avfs(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == tmp_result),
+ "Failed to update avfs voltages!",
+ result = tmp_result);
+
tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to generate DPM level enabled mask!",
@@ -4704,33 +4755,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
return result;
}
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-
- if (smu_data == NULL)
- return -EINVAL;
-
- if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
- return 0;
-
- if (enable) {
- if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_EnableAvfs),
- "Failed to enable AVFS!",
- return -EINVAL);
- } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_DisableAvfs),
- "Failed to disable AVFS!",
- return -EINVAL);
-
- return 0;
-}
-
static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
index c87263b..fd9ed20 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
@@ -40,6 +40,7 @@ struct smu7_buffer_entry {
struct smu7_avfs {
enum AVFS_BTC_STATUS avfs_btc_status;
uint32_t avfs_btc_param;
+ bool brecalculate_avfs;
};
struct smu7_smumgr {
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2018-01-16 12:02 ` [PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state Rex Zhu
@ 2018-01-16 12:02 ` Rex Zhu
[not found] ` <1516104175-27651-7-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs Rex Zhu
` (2 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I301be04db3c56e16e2c10091016efa5439fbc744
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 104 ++++++++++++++++++++++-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index c69749d..8dbec14 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4834,6 +4834,108 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
return 0;
}
+static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
+ enum PHM_ODN_DPM_TABLE_TYPE type,
+ uint32_t clk,
+ uint32_t voltage)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (hwmgr->dyn_state.max_clock_voltage_on_ac.vddc * 120 / 100 < voltage)
+ return false;
+
+ if (type == PHM_ODN_SCLK_VDDC_TABLE) {
+ if (data->vbios_boot_state.sclk_bootup_value > clk ||
+ hwmgr->dyn_state.max_clock_voltage_on_ac.sclk * 120 / 100 < clk)
+ return false;
+ } else if (type == PHM_ODN_MCLK_VDDC_TABLE) {
+ if (data->vbios_boot_state.mclk_bootup_value > clk ||
+ hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 120 / 100 < clk)
+ return false;
+ } else {
+ return false;
+ }
+
+ return true;
+}
+
+static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+ enum PHM_ODN_DPM_TABLE_TYPE type,
+ long *input, uint32_t size)
+{
+ uint32_t i;
+ const phm_ppt_v1_clock_voltage_dependency_table *pgolden_vdd_dep_table = NULL;
+ struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
+ struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)hwmgr->pptable;
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+ uint32_t input_clk;
+ uint32_t input_vol;
+ uint32_t input_level;
+
+ PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+ return -EINVAL);
+
+ if (PHM_ODN_SCLK_VDDC_TABLE == type) {
+ podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
+ podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
+ PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+ "Failed to get ODN SCLK and Voltage tables",
+ return -EINVAL);
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+ } else if (PHM_ODN_MCLK_VDDC_TABLE == type) {
+ podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
+ podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
+
+ PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+ "Failed to get ODN MCLK and Voltage tables",
+ return -EINVAL);
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+ } else if (PHM_ODN_RESET_DEFAULT_TABLE == type) {
+ smu7_odn_initial_default_setting(hwmgr);
+ data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_MCLK;
+ smu_data->avfs.brecalculate_avfs = true;
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+
+ if (hwmgr->pp_table_version == PP_TABLE_V1)
+ pgolden_vdd_dep_table = PHM_ODN_MCLK_VDDC_TABLE == type ?
+ table_info->vdd_dep_on_mclk:
+ table_info->vdd_dep_on_sclk;
+
+ PP_ASSERT_WITH_CODE(pgolden_vdd_dep_table
+ && pgolden_vdd_dep_table->count > 0,
+ "Invalid golden_vdd_dep_table",
+ return -EINVAL);
+
+ for (i = 0; i < size;) {
+ if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
+ pr_info("invalid clock voltage input \n");
+ return 0;
+ }
+ input_level = input[i];
+ input_clk = input[i+1] * 100;
+ input_vol = input[i+2];
+
+ if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
+ podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
+ podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
+ podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
+ podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
+ } else {
+ pr_info("invaid input clk/voltage");
+ }
+ i += 3;
+ }
+ smu_data->avfs.brecalculate_avfs = true;
+ return 0;
+}
+
+
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4888,6 +4990,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
.get_max_high_clocks = smu7_get_max_high_clocks,
.get_thermal_temperature_range = smu7_get_thermal_temperature_range,
+ .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
@@ -4919,4 +5022,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
return ret;
}
-
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2018-01-16 12:02 ` [PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
@ 2018-01-16 12:02 ` Rex Zhu
[not found] ` <1516104175-27651-8-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:12 ` [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature Alex Deucher
2018-01-16 17:53 ` Grazvydas Ignotas
8 siblings, 1 reply; 18+ messages in thread
From: Rex Zhu @ 2018-01-16 12:02 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
when cat pp_od_clk_voltage it show
OD_SCLK:
0: 300Mhz 800 mV
1: 466Mhz 818 mV
2: 751Mhz 824 mV
3: 1019Mhz 987 mV
4: 1074Mhz 1037 mV
5: 1126Mhz 1087 mV
6: 1169Mhz 1137 mV
7: 1206Mhz 1150 mV
OD_MCLK:
0: 300Mhz 800 mV
1: 1650Mhz 1000 mV
echo "s/m level clock voltage" to change
sclk/mclk's clock and voltage
echo "r" to restore default value.
Change-Id: I4d1e70aee31850694a0ff13db8bbfe2524a1d3ae
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 89 +++++++++++++++++++++++++-
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 ++++++
4 files changed, 112 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 986f1d5..4b5755e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_power_profile_mode(\
(adev)->powerplay.pp_handle, parameter, size))
+#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
+ ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
+ (adev)->powerplay.pp_handle, type, parameter, size))
+
struct amdgpu_dpm {
struct amdgpu_ps *ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ed9012a..f2d3987 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -360,6 +360,81 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
return count;
}
+static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ int ret;
+ uint32_t parameter_size = 0;
+ long parameter[64];
+ char buf_cpy[128];
+ char *tmp_str;
+ char *sub_str;
+ const char delimiter[3] = {' ', '\n', '\0'};
+ uint32_t type;
+
+ if (count > 127)
+ return -EINVAL;
+
+ pr_info("%c \n", *buf);
+ if (*buf == 's')
+ type = 0;
+ else if (*buf == 'm')
+ type = 1;
+ else if(*buf == 'r')
+ type = 2;
+ else {
+ pr_info("===== \n");
+ return -EINVAL;
+ }
+ memcpy(buf_cpy, buf, count+1);
+
+ tmp_str = buf_cpy;
+
+ while (isspace(*++tmp_str));
+
+ while (tmp_str[0]) {
+ sub_str = strsep(&tmp_str, delimiter);
+ ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
+ if (ret)
+ return -EINVAL;
+ parameter_size++;
+
+ while (isspace(*tmp_str))
+ tmp_str++;
+ }
+
+ if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
+ ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+ parameter, parameter_size);
+
+ if (ret)
+ return -EINVAL;
+
+ return count;
+}
+
+static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ uint32_t size = 0;
+
+ if (adev->powerplay.pp_funcs->print_clock_levels) {
+ size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
+ return size;
+ } else {
+ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+}
+
static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -842,6 +917,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
amdgpu_get_pp_power_profile_mode,
amdgpu_set_pp_power_profile_mode);
+static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
+ amdgpu_get_pp_od_clk_voltage,
+ amdgpu_set_pp_od_clk_voltage);
+
static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1481,7 +1560,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_power_profile_mode\n");
return ret;
}
-
+ ret = device_create_file(adev->dev,
+ &dev_attr_pp_od_clk_voltage);
+ if (ret) {
+ DRM_ERROR("failed to create device file "
+ "pp_od_clk_voltage\n");
+ return ret;
+ }
ret = amdgpu_debugfs_pm_init(adev);
if (ret) {
DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1519,6 +1604,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
&dev_attr_pp_compute_power_profile);
device_remove_file(adev->dev,
&dev_attr_pp_power_profile_mode);
+ device_remove_file(adev->dev,
+ &dev_attr_pp_od_clk_voltage);
}
void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index fba44a5..062fc03 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -302,6 +302,7 @@ struct amd_pm_funcs {
struct amd_pp_simple_clock_info *clocks);
int (*get_power_profile_mode)(void *handle, char *buf);
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+ int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
};
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d9cb424..854c43c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1122,6 +1122,24 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
}
+static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+ if (pp_check(pp_handle))
+ return -EINVAL;
+
+ hwmgr = pp_handle->hwmgr;
+
+ if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
+}
+
static int pp_dpm_set_power_profile_state(void *handle,
struct amd_pp_profile *request)
{
@@ -1507,6 +1525,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
.get_power_profile_mode = pp_get_power_profile_mode,
.set_power_profile_mode = pp_set_power_profile_mode,
+ .odn_edit_dpm_table = pp_odn_edit_dpm_table,
/* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7
[not found] ` <1516104175-27651-7-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 17:02 ` Alex Deucher
0 siblings, 0 replies; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:02 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I301be04db3c56e16e2c10091016efa5439fbc744
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 104 ++++++++++++++++++++++-
> 1 file changed, 103 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index c69749d..8dbec14 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4834,6 +4834,108 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> +static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
> + enum PHM_ODN_DPM_TABLE_TYPE type,
> + uint32_t clk,
> + uint32_t voltage)
> +{
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> + if (hwmgr->dyn_state.max_clock_voltage_on_ac.vddc * 120 / 100 < voltage)
> + return false;
> +
> + if (type == PHM_ODN_SCLK_VDDC_TABLE) {
> + if (data->vbios_boot_state.sclk_bootup_value > clk ||
> + hwmgr->dyn_state.max_clock_voltage_on_ac.sclk * 120 / 100 < clk)
> + return false;
> + } else if (type == PHM_ODN_MCLK_VDDC_TABLE) {
> + if (data->vbios_boot_state.mclk_bootup_value > clk ||
> + hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 120 / 100 < clk)
> + return false;
> + } else {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
> + enum PHM_ODN_DPM_TABLE_TYPE type,
> + long *input, uint32_t size)
> +{
> + uint32_t i;
> + const phm_ppt_v1_clock_voltage_dependency_table *pgolden_vdd_dep_table = NULL;
> + struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
> + struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> + struct phm_ppt_v1_information *table_info =
> + (struct phm_ppt_v1_information *)hwmgr->pptable;
> + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> + uint32_t input_clk;
> + uint32_t input_vol;
> + uint32_t input_level;
> +
> + PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
> + return -EINVAL);
> +
> + if (PHM_ODN_SCLK_VDDC_TABLE == type) {
> + podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
> + podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
> + PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
> + "Failed to get ODN SCLK and Voltage tables",
> + return -EINVAL);
> + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
> + } else if (PHM_ODN_MCLK_VDDC_TABLE == type) {
> + podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
> + podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
> +
> + PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
> + "Failed to get ODN MCLK and Voltage tables",
> + return -EINVAL);
> + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
> + } else if (PHM_ODN_RESET_DEFAULT_TABLE == type) {
> + smu7_odn_initial_default_setting(hwmgr);
> + data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_MCLK;
> + smu_data->avfs.brecalculate_avfs = true;
> + return 0;
> + } else {
> + return -EINVAL;
> + }
> +
> + if (hwmgr->pp_table_version == PP_TABLE_V1)
> + pgolden_vdd_dep_table = PHM_ODN_MCLK_VDDC_TABLE == type ?
> + table_info->vdd_dep_on_mclk:
> + table_info->vdd_dep_on_sclk;
> +
> + PP_ASSERT_WITH_CODE(pgolden_vdd_dep_table
> + && pgolden_vdd_dep_table->count > 0,
> + "Invalid golden_vdd_dep_table",
> + return -EINVAL);
> +
> + for (i = 0; i < size;) {
> + if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
> + pr_info("invalid clock voltage input \n");
> + return 0;
> + }
> + input_level = input[i];
> + input_clk = input[i+1] * 100;
> + input_vol = input[i+2];
> +
> + if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
> + podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
> + podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
> + podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
> + podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
> + } else {
> + pr_info("invaid input clk/voltage");
> + }
> + i += 3;
Move this up into the for loop start.
Alex
> + }
> + smu_data->avfs.brecalculate_avfs = true;
> + return 0;
> +}
> +
> +
> static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
> .backend_init = &smu7_hwmgr_backend_init,
> .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -4888,6 +4990,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
> .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
> .get_max_high_clocks = smu7_get_max_high_clocks,
> .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
> + .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
> };
>
> uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> @@ -4919,4 +5022,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
>
> return ret;
> }
> -
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state
[not found] ` <1516104175-27651-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 17:07 ` Alex Deucher
0 siblings, 0 replies; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:07 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when Over-driver engine clock and voltage were set,
> need to recalculate AVFS voltage on VI asics.
>
> Change-Id: If2a2226d64c0c2aa37c2e84f36b0dad8b7dee25e
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 80 ++++++++++++++--------
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h | 1 +
> 2 files changed, 53 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index a0007a8..c69749d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
> DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
> };
>
> -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
> static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
> static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
> enum pp_clock_type type, uint32_t mask);
> @@ -1351,6 +1350,53 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
> +{
> + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> +
> + if (smu_data == NULL)
> + return -EINVAL;
> +
> + if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> + return 0;
> +
> + if (enable) {
> + if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> + CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
> + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> + hwmgr, PPSMC_MSG_EnableAvfs),
> + "Failed to enable AVFS!",
> + return -EINVAL);
> + }
> + } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> + CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
> + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> + hwmgr, PPSMC_MSG_DisableAvfs),
> + "Failed to disable AVFS!",
> + return -EINVAL);
> + }
> +
> + return 0;
> +}
> +
> +static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
> +{
> + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> +
> + if (smu_data == NULL)
> + return -EINVAL;
> +
> + if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> + return 0;
> +
> + if (smu_data->avfs.brecalculate_avfs) {
> + smu7_avfs_control(hwmgr, false);
> + smu7_avfs_control(hwmgr, true);
> + smu_data->avfs.brecalculate_avfs = true;
do we need to set brecalculate_avfs here? Won't it effectively be set
permanently at this point? When does the driver ever set
brecalculate_avfs to false?
Alex
> + }
> + return 0;
> +}
> +
> int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
> {
> int tmp_result, result = 0;
> @@ -3923,6 +3969,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
> "Failed to populate and upload SCLK MCLK DPM levels!",
> result = tmp_result);
>
> + tmp_result = smu7_update_avfs(hwmgr);
> + PP_ASSERT_WITH_CODE((0 == tmp_result),
> + "Failed to update avfs voltages!",
> + result = tmp_result);
> +
> tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
> PP_ASSERT_WITH_CODE((0 == tmp_result),
> "Failed to generate DPM level enabled mask!",
> @@ -4704,33 +4755,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
> return result;
> }
>
> -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
> -{
> - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> -
> - if (smu_data == NULL)
> - return -EINVAL;
> -
> - if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> - return 0;
> -
> - if (enable) {
> - if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> - CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
> - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> - hwmgr, PPSMC_MSG_EnableAvfs),
> - "Failed to enable AVFS!",
> - return -EINVAL);
> - } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> - CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
> - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> - hwmgr, PPSMC_MSG_DisableAvfs),
> - "Failed to disable AVFS!",
> - return -EINVAL);
> -
> - return 0;
> -}
> -
> static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> uint32_t virtual_addr_low,
> uint32_t virtual_addr_hi,
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> index c87263b..fd9ed20 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h
> @@ -40,6 +40,7 @@ struct smu7_buffer_entry {
> struct smu7_avfs {
> enum AVFS_BTC_STATUS avfs_btc_status;
> uint32_t avfs_btc_param;
> + bool brecalculate_avfs;
> };
>
> struct smu7_smumgr {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2018-01-16 12:02 ` [PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs Rex Zhu
@ 2018-01-16 17:12 ` Alex Deucher
[not found] ` <CADnq5_N7pNmp8RaRGeRAcEsko1HGkLWSKq42o+m3JJBf9v6Vpg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-01-16 17:53 ` Grazvydas Ignotas
8 siblings, 1 reply; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:12 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu
> clock and voltage through sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
> uint amdgpu_sdma_phase_quantum = 32;
> char *amdgpu_disable_cu = NULL;
> char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0xffffffff;
> +uint amdgpu_pp_feature_mask = 0x2fff;
Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
Probably not intended. I think you want 0x3fff.
Alex
> int amdgpu_ngg = 0;
> int amdgpu_prim_buf_per_se = 0;
> int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> + if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
> + hwmgr->od_enabled = true;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 6f053fa..ce74e06 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3572,8 +3572,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->sclk_table.dpm_levels
> [dpm_table->sclk_table.count - 1].value = sclk;
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
> - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
> * as the Heatmap GPU Clock axis is also based on the default values
> */
> @@ -3618,8 +3617,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->mclk_table.dpm_levels
> [dpm_table->mclk_table.count - 1].value = mclk;
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
> - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
>
> PP_ASSERT_WITH_CODE(
> (golden_dpm_table->mclk_table.dpm_levels
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index fadbc8a..12a31d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3396,8 +3396,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->
> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
> value = sclk;
> - if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> - PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
> * as the Heatmap GPU Clock axis is also based on
> * the default values
> @@ -3451,9 +3450,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> mem_table.dpm_levels[dpm_table->mem_table.count - 1].
> value = mclk;
>
> - if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> - PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> -
> + if (hwmgr->od_enabled) {
> PP_ASSERT_WITH_CODE(
> golden_dpm_table->mem_table.dpm_levels
> [golden_dpm_table->mem_table.count - 1].value,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 6d8183d..c496742 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
> PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
> PP_SOCCLK_DPM_MASK = 0x1000,
> PP_DCEFCLK_DPM_MASK = 0x2000,
> + PP_OVER_DRIVER_MASK = 0x4000,
> };
>
> enum PHM_BackEnd_Magic {
> @@ -755,6 +756,7 @@ struct pp_hwmgr {
> uint32_t power_profile_mode;
> uint32_t pstate_sclk;
> uint32_t pstate_mclk;
> + bool od_enabled;
> };
>
> struct cgs_irq_src_funcs {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7
[not found] ` <1516104175-27651-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 17:14 ` Alex Deucher
0 siblings, 0 replies; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:14 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I54bb964a3905f675e93411f93810cc1aa1f67d12
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++++++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 401b895..fba44a5 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -107,6 +107,8 @@ enum pp_clock_type {
> PP_SCLK,
> PP_MCLK,
> PP_PCIE,
> + OD_SCLK,
> + OD_MCLK,
> };
>
> enum amd_pp_sensors {
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index f3d9c64..a0007a8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4355,6 +4355,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
> struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
> struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
> + struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> + struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
> + struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
> int i, now, size = 0;
> uint32_t clock, pcie_speed;
>
> @@ -4409,6 +4412,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "",
> (i == now) ? "*" : "");
> break;
> + case OD_SCLK:
> + if (hwmgr->od_enabled) {
> + size = sprintf(buf, "%s: \n", "OD_SCLK");
> + for (i = 0; i < odn_sclk_table->num_of_pl; i++)
> + size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
> + i, odn_sclk_table->entries[i].clock / 100,
> + odn_sclk_table->entries[i].vddc);
> + }
> + break;
> + case OD_MCLK:
> + if (hwmgr->od_enabled) {
> + size = sprintf(buf, "%s: \n", "OD_MCLK");
> + for (i = 0; i < odn_mclk_table->num_of_pl; i++)
> + size += sprintf(buf + size, "%d: %10uMhz %10u mV\n",
> + i, odn_mclk_table->entries[i].clock / 100,
> + odn_mclk_table->entries[i].vddc);
> + }
> + break;
> default:
> break;
> }
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table
[not found] ` <1516104175-27651-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 17:14 ` Alex Deucher
0 siblings, 0 replies; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:14 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Add odn_edit_dpm_table function
> points for setting user assigned clock/voltage.
>
> Change-Id: I7e49ffdc30b77d07b46bf12ebb275fa0ff901588
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 6 ++++++
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index d6772a8..97d25cd 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -364,6 +364,12 @@ struct phm_odn_performance_level {
> bool enabled;
> };
>
> +enum PHM_ODN_DPM_TABLE_TYPE {
> + PHM_ODN_SCLK_VDDC_TABLE,
> + PHM_ODN_MCLK_VDDC_TABLE,
> + PHM_ODN_RESET_DEFAULT_TABLE
> +};
> +
> struct phm_odn_clock_levels {
> uint32_t size;
> uint32_t options;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index c496742..36e5378 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -345,6 +345,9 @@ struct pp_hwmgr_func {
> struct PP_TemperatureRange *range);
> int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
> int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
> + int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
> + enum PHM_ODN_DPM_TABLE_TYPE type,
> + long *input, uint32_t size);
> };
>
> struct pp_table_func {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file
[not found] ` <1516104175-27651-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 17:15 ` Alex Deucher
0 siblings, 0 replies; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:15 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I46cdf4f39f4c9c448a2c76b67f1cbbfed26c7488
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 5 -----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 6 ------
> drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 11 +++++++++++
> 3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
> index 8eec974..1ce84cc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
> @@ -34,11 +34,6 @@
> #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
> #define SMU7_VOLTAGE_CONTROL_MERGED 0x3
>
> -#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
> -#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
> -#define DPMTABLE_UPDATE_SCLK 0x00000004
> -#define DPMTABLE_UPDATE_MCLK 0x00000008
> -
> enum gpu_pt_config_reg_type {
> GPU_CONFIGREG_MMR = 0,
> GPU_CONFIGREG_SMC_IND,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 689fe9f..ab3e879 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
> uint32_t dcef_clock;
> };
>
> -#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
> -#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
> -#define DPMTABLE_UPDATE_SCLK 0x00000004
> -#define DPMTABLE_UPDATE_MCLK 0x00000008
> -#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
> -
> struct vega10_smc_state_table {
> uint32_t soc_boot_level;
> uint32_t gfx_boot_level;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> index 97d25cd..d846cbb 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
> @@ -358,6 +358,17 @@ struct phm_clocks {
> uint32_t clock[MAX_NUM_CLOCKS];
> };
>
> +#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
> +#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
> +#define DPMTABLE_UPDATE_SCLK 0x00000004
> +#define DPMTABLE_UPDATE_MCLK 0x00000008
> +#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
> +
> +/* To determine if sclk and mclk are in overdrive state */
> +#define SCLK_OVERDRIVE_ENABLED 0x00000001
> +#define MCLK_OVERDRIVE_ENABLED 0x00000002
> +#define VDDC_OVERDRIVE_ENABLED 0x00000010
> +
> struct phm_odn_performance_level {
> uint32_t clock;
> uint32_t vddc;
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs
[not found] ` <1516104175-27651-8-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-16 17:17 ` Alex Deucher
0 siblings, 0 replies; 18+ messages in thread
From: Alex Deucher @ 2018-01-16 17:17 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when cat pp_od_clk_voltage it show
> OD_SCLK:
> 0: 300Mhz 800 mV
> 1: 466Mhz 818 mV
> 2: 751Mhz 824 mV
> 3: 1019Mhz 987 mV
> 4: 1074Mhz 1037 mV
> 5: 1126Mhz 1087 mV
> 6: 1169Mhz 1137 mV
> 7: 1206Mhz 1150 mV
> OD_MCLK:
> 0: 300Mhz 800 mV
> 1: 1650Mhz 1000 mV
>
> echo "s/m level clock voltage" to change
> sclk/mclk's clock and voltage
>
> echo "r" to restore default value.
How do the changes actually get applied? I don't see any calls to
power_state_set.
Alex
>
> Change-Id: I4d1e70aee31850694a0ff13db8bbfe2524a1d3ae
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 89 +++++++++++++++++++++++++-
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 ++++++
> 4 files changed, 112 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 986f1d5..4b5755e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
> ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> (adev)->powerplay.pp_handle, parameter, size))
>
> +#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
> + ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
> + (adev)->powerplay.pp_handle, type, parameter, size))
> +
> struct amdgpu_dpm {
> struct amdgpu_ps *ps;
> /* number of valid power states */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index ed9012a..f2d3987 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -360,6 +360,81 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
> return count;
> }
>
> +static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> + int ret;
> + uint32_t parameter_size = 0;
> + long parameter[64];
> + char buf_cpy[128];
> + char *tmp_str;
> + char *sub_str;
> + const char delimiter[3] = {' ', '\n', '\0'};
> + uint32_t type;
> +
> + if (count > 127)
> + return -EINVAL;
> +
> + pr_info("%c \n", *buf);
> + if (*buf == 's')
> + type = 0;
> + else if (*buf == 'm')
> + type = 1;
> + else if(*buf == 'r')
> + type = 2;
> + else {
> + pr_info("===== \n");
> + return -EINVAL;
> + }
> + memcpy(buf_cpy, buf, count+1);
> +
> + tmp_str = buf_cpy;
> +
> + while (isspace(*++tmp_str));
> +
> + while (tmp_str[0]) {
> + sub_str = strsep(&tmp_str, delimiter);
> + ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> + if (ret)
> + return -EINVAL;
> + parameter_size++;
> +
> + while (isspace(*tmp_str))
> + tmp_str++;
> + }
> +
> + if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
> + ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
> + parameter, parameter_size);
> +
> + if (ret)
> + return -EINVAL;
> +
> + return count;
> +}
> +
> +static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> + uint32_t size = 0;
> +
> + if (adev->powerplay.pp_funcs->print_clock_levels) {
> + size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
> + return size;
> + } else {
> + return snprintf(buf, PAGE_SIZE, "\n");
> + }
> +
> +}
> +
> static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -842,6 +917,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
> static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
> amdgpu_get_pp_power_profile_mode,
> amdgpu_set_pp_power_profile_mode);
> +static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
> + amdgpu_get_pp_od_clk_voltage,
> + amdgpu_set_pp_od_clk_voltage);
> +
> static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -1481,7 +1560,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
> "pp_power_profile_mode\n");
> return ret;
> }
> -
> + ret = device_create_file(adev->dev,
> + &dev_attr_pp_od_clk_voltage);
> + if (ret) {
> + DRM_ERROR("failed to create device file "
> + "pp_od_clk_voltage\n");
> + return ret;
> + }
> ret = amdgpu_debugfs_pm_init(adev);
> if (ret) {
> DRM_ERROR("Failed to register debugfs file for dpm!\n");
> @@ -1519,6 +1604,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
> &dev_attr_pp_compute_power_profile);
> device_remove_file(adev->dev,
> &dev_attr_pp_power_profile_mode);
> + device_remove_file(adev->dev,
> + &dev_attr_pp_od_clk_voltage);
> }
>
> void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index fba44a5..062fc03 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -302,6 +302,7 @@ struct amd_pm_funcs {
> struct amd_pp_simple_clock_info *clocks);
> int (*get_power_profile_mode)(void *handle, char *buf);
> int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
> + int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
> };
>
> #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index d9cb424..854c43c 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1122,6 +1122,24 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
> return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
> }
>
> +static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
> +{
> + struct pp_hwmgr *hwmgr;
> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
> +
> + if (pp_check(pp_handle))
> + return -EINVAL;
> +
> + hwmgr = pp_handle->hwmgr;
> +
> + if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
> + pr_info("%s was not implemented.\n", __func__);
> + return -EINVAL;
> + }
> +
> + return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
> +}
> +
> static int pp_dpm_set_power_profile_state(void *handle,
> struct amd_pp_profile *request)
> {
> @@ -1507,6 +1525,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
> .get_power_profile_mode = pp_get_power_profile_mode,
> .set_power_profile_mode = pp_set_power_profile_mode,
> + .odn_edit_dpm_table = pp_odn_edit_dpm_table,
> /* export to DC */
> .get_sclk = pp_dpm_get_sclk,
> .get_mclk = pp_dpm_get_mclk,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2018-01-16 17:12 ` [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature Alex Deucher
@ 2018-01-16 17:53 ` Grazvydas Ignotas
[not found] ` <CANOLnOOmS-uUXg=KdstpXw4ok8cMEQHo1JwLD9LDDfu7+X878w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
8 siblings, 1 reply; 18+ messages in thread
From: Grazvydas Ignotas @ 2018-01-16 17:53 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On Tue, Jan 16, 2018 at 2:02 PM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu
> clock and voltage through sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
> uint amdgpu_sdma_phase_quantum = 32;
> char *amdgpu_disable_cu = NULL;
> char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0xffffffff;
> +uint amdgpu_pp_feature_mask = 0x2fff;
> int amdgpu_ngg = 0;
> int amdgpu_prim_buf_per_se = 0;
> int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> + if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
PP_OVERDRIVE_MASK? I believe "overdrive" is a single word.
Gražvydas
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^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
[not found] ` <CADnq5_N7pNmp8RaRGeRAcEsko1HGkLWSKq42o+m3JJBf9v6Vpg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-01-17 4:47 ` Zhu, Rex
0 siblings, 0 replies; 18+ messages in thread
From: Zhu, Rex @ 2018-01-17 4:47 UTC (permalink / raw)
To: 'Alex Deucher'; +Cc: amd-gfx list
>>Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
>>Probably not intended. I think you want 0x3fff.
Yes, Thanks for pointing it out.
Best Regards
Rex
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com]
Sent: Wednesday, January 17, 2018 1:12 AM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
On Tue, Jan 16, 2018 at 7:02 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu clock and voltage through
> sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
> 5 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index e679bb8..508a254 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -120,7 +120,7 @@
> uint amdgpu_sdma_phase_quantum = 32;
> char *amdgpu_disable_cu = NULL;
> char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0xffffffff;
> +uint amdgpu_pp_feature_mask = 0x2fff;
Setting the feature mask to 0x2fff unsets PP_SOCCLK_DPM_MASK.
Probably not intended. I think you want 0x3fff.
Alex
> int amdgpu_ngg = 0;
> int amdgpu_prim_buf_per_se = 0;
> int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index e35bdc5..ebfbbcf 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
> PHM_PlatformCaps_CAC);
> }
>
> + if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
> + hwmgr->od_enabled = true;
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 6f053fa..ce74e06 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3572,8 +3572,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->sclk_table.dpm_levels
> [dpm_table->sclk_table.count - 1].value = sclk;
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
> - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
> * as the Heatmap GPU Clock axis is also based on the default values
> */
> @@ -3618,8 +3617,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->mclk_table.dpm_levels
> [dpm_table->mclk_table.count - 1].value =
> mclk;
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
> - phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
>
> PP_ASSERT_WITH_CODE(
>
> (golden_dpm_table->mclk_table.dpm_levels
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index fadbc8a..12a31d1 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3396,8 +3396,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> dpm_table->
> gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
> value = sclk;
> - if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> - PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> + if (hwmgr->od_enabled) {
> /* Need to do calculation based on the golden DPM table
> * as the Heatmap GPU Clock axis is also based on
> * the default values @@
> -3451,9 +3450,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
> mem_table.dpm_levels[dpm_table->mem_table.count - 1].
> value = mclk;
>
> - if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
> - PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
> -
> + if (hwmgr->od_enabled) {
> PP_ASSERT_WITH_CODE(
> golden_dpm_table->mem_table.dpm_levels
>
> [golden_dpm_table->mem_table.count - 1].value, diff --git
> a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 6d8183d..c496742 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
> PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
> PP_SOCCLK_DPM_MASK = 0x1000,
> PP_DCEFCLK_DPM_MASK = 0x2000,
> + PP_OVER_DRIVER_MASK = 0x4000,
> };
>
> enum PHM_BackEnd_Magic {
> @@ -755,6 +756,7 @@ struct pp_hwmgr {
> uint32_t power_profile_mode;
> uint32_t pstate_sclk;
> uint32_t pstate_mclk;
> + bool od_enabled;
> };
>
> struct cgs_irq_src_funcs {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
[not found] ` <CANOLnOOmS-uUXg=KdstpXw4ok8cMEQHo1JwLD9LDDfu7+X878w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-01-17 5:18 ` Zhu, Rex
0 siblings, 0 replies; 18+ messages in thread
From: Zhu, Rex @ 2018-01-17 5:18 UTC (permalink / raw)
To: 'Grazvydas Ignotas'; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
-----Original Message-----
From: Grazvydas Ignotas [mailto:notasas@gmail.com]
Sent: Wednesday, January 17, 2018 1:53 AM
To: Zhu, Rex
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature
On Tue, Jan 16, 2018 at 2:02 PM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when this bit was set on module load,
> driver will allow the user over/under gpu clock and voltage through
> sysfs.
>
> by default, this bit was not set.
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> + if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
>>PP_OVERDRIVE_MASK? I believe "overdrive" is a single word.
Yes, OverDrive as a power feature. So better change to PP_OVERDRIVE_MASK.
Thanks.
Best Regards
Rex
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-01-17 5:18 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-16 12:02 [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature Rex Zhu
[not found] ` <1516104175-27651-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 12:02 ` [PATCH 2/8] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI Rex Zhu
2018-01-16 12:02 ` [PATCH 3/8] drm/amd/pp: Add OD driver clock/voltage display on smu7 Rex Zhu
[not found] ` <1516104175-27651-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:14 ` Alex Deucher
2018-01-16 12:02 ` [PATCH 4/8] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
[not found] ` <1516104175-27651-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:14 ` Alex Deucher
2018-01-16 12:02 ` [PATCH 5/8] drm/amd/pp: Move DPMTABLE_* definitions to common header file Rex Zhu
[not found] ` <1516104175-27651-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:15 ` Alex Deucher
2018-01-16 12:02 ` [PATCH 6/8] drm/amd/pp: Update avfs voltage when set power state Rex Zhu
[not found] ` <1516104175-27651-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:07 ` Alex Deucher
2018-01-16 12:02 ` [PATCH 7/8] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
[not found] ` <1516104175-27651-7-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:02 ` Alex Deucher
2018-01-16 12:02 ` [PATCH 8/8] drm/amd/pp: Add edit/show OD clock/voltage support in sysfs Rex Zhu
[not found] ` <1516104175-27651-8-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-16 17:17 ` Alex Deucher
2018-01-16 17:12 ` [PATCH 1/8] drm/amd/pp: Add a new pp feature mask bit for OD feature Alex Deucher
[not found] ` <CADnq5_N7pNmp8RaRGeRAcEsko1HGkLWSKq42o+m3JJBf9v6Vpg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-01-17 4:47 ` Zhu, Rex
2018-01-16 17:53 ` Grazvydas Ignotas
[not found] ` <CANOLnOOmS-uUXg=KdstpXw4ok8cMEQHo1JwLD9LDDfu7+X878w-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-01-17 5:18 ` Zhu, Rex
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