* [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
@ 2020-09-24 10:10 Evan Quan
2020-09-24 13:00 ` Alex Deucher
0 siblings, 1 reply; 8+ messages in thread
From: Evan Quan @ 2020-09-24 10:10 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, Evan Quan
Revert the guilty change introduced by the commit below:
drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2)
Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 1695b36dc23c..be44cb941e73 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
if (smu->dc_controlled_by_gpio)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
+ if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
+
+ /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
+ if (!(is_asic_secure(smu) &&
+ (adev->asic_type == CHIP_NAVI10) &&
+ (adev->rev_id == 0)) &&
+ (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+
/* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
if (is_asic_secure(smu) &&
(adev->asic_type == CHIP_NAVI10) &&
@@ -2629,43 +2641,12 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
static int navi10_post_smu_init(struct smu_context *smu)
{
- struct smu_feature *feature = &smu->smu_feature;
struct amdgpu_device *adev = smu->adev;
- uint64_t feature_mask = 0;
int ret = 0;
if (amdgpu_sriov_vf(adev))
return 0;
- /* For Naiv1x, enable these features only after DAL initialization */
- if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
- feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
-
- /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
- if (!(is_asic_secure(smu) &&
- (adev->asic_type == CHIP_NAVI10) &&
- (adev->rev_id == 0)) &&
- (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
- feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
- | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
- | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
-
- if (!feature_mask)
- return 0;
-
- bitmap_or(feature->allowed,
- feature->allowed,
- (unsigned long *)(&feature_mask),
- SMU_FEATURE_MAX);
-
- ret = smu_cmn_feature_update_enable_state(smu,
- feature_mask,
- true);
- if (ret) {
- dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
- return ret;
- }
-
ret = navi10_run_umc_cdr_workaround(smu);
if (ret) {
dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
--
2.28.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-24 10:10 [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors Evan Quan
@ 2020-09-24 13:00 ` Alex Deucher
2020-09-25 3:38 ` Quan, Evan
0 siblings, 1 reply; 8+ messages in thread
From: Alex Deucher @ 2020-09-24 13:00 UTC (permalink / raw)
To: Evan Quan; +Cc: Deucher, Alexander, amd-gfx list
On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Revert the guilty change introduced by the commit below:
> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2)
>
> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Won't this effectively disable the potential fix for multiple monitors
at boot time?
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
> 1 file changed, 12 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 1695b36dc23c..be44cb941e73 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> if (smu->dc_controlled_by_gpio)
> *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
>
> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> +
> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> + if (!(is_asic_secure(smu) &&
> + (adev->asic_type == CHIP_NAVI10) &&
> + (adev->rev_id == 0)) &&
> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> + | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> +
> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> if (is_asic_secure(smu) &&
> (adev->asic_type == CHIP_NAVI10) &&
> @@ -2629,43 +2641,12 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>
> static int navi10_post_smu_init(struct smu_context *smu)
> {
> - struct smu_feature *feature = &smu->smu_feature;
> struct amdgpu_device *adev = smu->adev;
> - uint64_t feature_mask = 0;
> int ret = 0;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - /* For Naiv1x, enable these features only after DAL initialization */
> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> -
> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> - if (!(is_asic_secure(smu) &&
> - (adev->asic_type == CHIP_NAVI10) &&
> - (adev->rev_id == 0)) &&
> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> -
> - if (!feature_mask)
> - return 0;
> -
> - bitmap_or(feature->allowed,
> - feature->allowed,
> - (unsigned long *)(&feature_mask),
> - SMU_FEATURE_MAX);
> -
> - ret = smu_cmn_feature_update_enable_state(smu,
> - feature_mask,
> - true);
> - if (ret) {
> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
> - return ret;
> - }
> -
> ret = navi10_run_umc_cdr_workaround(smu);
> if (ret) {
> dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-24 13:00 ` Alex Deucher
@ 2020-09-25 3:38 ` Quan, Evan
2020-09-25 3:39 ` Deucher, Alexander
2020-09-25 21:05 ` Matt Coffin
0 siblings, 2 replies; 8+ messages in thread
From: Quan, Evan @ 2020-09-25 3:38 UTC (permalink / raw)
To: Alex Deucher; +Cc: Deucher, Alexander, amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
For now, we just revert it to get around the screen flicker issue introduced.
BR
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Thursday, September 24, 2020 9:01 PM
To: Quan, Evan <Evan.Quan@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Revert the guilty change introduced by the commit below:
> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> initialization(V2)
>
> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Won't this effectively disable the potential fix for multiple monitors at boot time?
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
> 1 file changed, 12 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 1695b36dc23c..be44cb941e73 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> if (smu->dc_controlled_by_gpio)
> *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_ACDC_BIT);
>
> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |=
> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> +
> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> + if (!(is_asic_secure(smu) &&
> + (adev->asic_type == CHIP_NAVI10) &&
> + (adev->rev_id == 0)) &&
> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> + |
> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> +
> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> if (is_asic_secure(smu) &&
> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>
> static int navi10_post_smu_init(struct smu_context *smu) {
> - struct smu_feature *feature = &smu->smu_feature;
> struct amdgpu_device *adev = smu->adev;
> - uint64_t feature_mask = 0;
> int ret = 0;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - /* For Naiv1x, enable these features only after DAL initialization */
> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> -
> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> - if (!(is_asic_secure(smu) &&
> - (adev->asic_type == CHIP_NAVI10) &&
> - (adev->rev_id == 0)) &&
> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> -
> - if (!feature_mask)
> - return 0;
> -
> - bitmap_or(feature->allowed,
> - feature->allowed,
> - (unsigned long *)(&feature_mask),
> - SMU_FEATURE_MAX);
> -
> - ret = smu_cmn_feature_update_enable_state(smu,
> - feature_mask,
> - true);
> - if (ret) {
> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
> - return ret;
> - }
> -
> ret = navi10_run_umc_cdr_workaround(smu);
> if (ret) {
> dev_err(adev->dev, "Failed to apply umc cdr
> workaround!\n");
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
> 08e11a82d994e183d%7C0%7C0%7C637365492561293539&sdata=J%2FM6YSLX6d%
> 2BMO%2B%2FWzdKAW7JlVZM%2FMFRDpTfi6UHkozk%3D&reserved=0
_______________________________________________
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-25 3:38 ` Quan, Evan
@ 2020-09-25 3:39 ` Deucher, Alexander
2020-09-25 21:05 ` Matt Coffin
1 sibling, 0 replies; 8+ messages in thread
From: Deucher, Alexander @ 2020-09-25 3:39 UTC (permalink / raw)
To: Quan, Evan, Alex Deucher; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 5343 bytes --]
[AMD Official Use Only - Internal Distribution Only]
Thanks.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
________________________________
From: Quan, Evan <Evan.Quan@amd.com>
Sent: Thursday, September 24, 2020 11:38 PM
To: Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: RE: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
[AMD Official Use Only - Internal Distribution Only]
That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
For now, we just revert it to get around the screen flicker issue introduced.
BR
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Thursday, September 24, 2020 9:01 PM
To: Quan, Evan <Evan.Quan@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
>
> Revert the guilty change introduced by the commit below:
> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> initialization(V2)
>
> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> Signed-off-by: Evan Quan <evan.quan@amd.com>
Won't this effectively disable the potential fix for multiple monitors at boot time?
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
> 1 file changed, 12 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 1695b36dc23c..be44cb941e73 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> if (smu->dc_controlled_by_gpio)
> *(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_ACDC_BIT);
>
> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> + *(uint64_t *)feature_mask |=
> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> +
> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> + if (!(is_asic_secure(smu) &&
> + (adev->asic_type == CHIP_NAVI10) &&
> + (adev->rev_id == 0)) &&
> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> + |
> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> +
> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> if (is_asic_secure(smu) &&
> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>
> static int navi10_post_smu_init(struct smu_context *smu) {
> - struct smu_feature *feature = &smu->smu_feature;
> struct amdgpu_device *adev = smu->adev;
> - uint64_t feature_mask = 0;
> int ret = 0;
>
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - /* For Naiv1x, enable these features only after DAL initialization */
> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> -
> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> - if (!(is_asic_secure(smu) &&
> - (adev->asic_type == CHIP_NAVI10) &&
> - (adev->rev_id == 0)) &&
> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> -
> - if (!feature_mask)
> - return 0;
> -
> - bitmap_or(feature->allowed,
> - feature->allowed,
> - (unsigned long *)(&feature_mask),
> - SMU_FEATURE_MAX);
> -
> - ret = smu_cmn_feature_update_enable_state(smu,
> - feature_mask,
> - true);
> - if (ret) {
> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
> - return ret;
> - }
> -
> ret = navi10_run_umc_cdr_workaround(smu);
> if (ret) {
> dev_err(adev->dev, "Failed to apply umc cdr
> workaround!\n");
> --
> 2.28.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
> 08e11a82d994e183d%7C0%7C0%7C637365492561293539&sdata=J%2FM6YSLX6d%
> 2BMO%2B%2FWzdKAW7JlVZM%2FMFRDpTfi6UHkozk%3D&reserved=0
[-- Attachment #1.2: Type: text/html, Size: 10631 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-25 3:38 ` Quan, Evan
2020-09-25 3:39 ` Deucher, Alexander
@ 2020-09-25 21:05 ` Matt Coffin
2020-09-25 21:09 ` Alex Deucher
1 sibling, 1 reply; 8+ messages in thread
From: Matt Coffin @ 2020-09-25 21:05 UTC (permalink / raw)
To: Quan, Evan, Alex Deucher; +Cc: Deucher, Alexander, amd-gfx list
[-- Attachment #1.1.1: Type: text/plain, Size: 5456 bytes --]
Sorry to bother you guys, but trying to learn about some of these
things, and I'm tracking the issue this relates to pretty closely on GitLab.
What does DAL stand for in this context?
Thanks in advance for the help,
Matt
On 9/24/20 9:38 PM, Quan, Evan wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
> For now, we just revert it to get around the screen flicker issue introduced.
>
> BR
> Evan
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, September 24, 2020 9:01 PM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
>
> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
>>
>> Revert the guilty change introduced by the commit below:
>> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
>> initialization(V2)
>>
>> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
>> Signed-off-by: Evan Quan <evan.quan@amd.com>
>
> Won't this effectively disable the potential fix for multiple monitors at boot time?
>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
>> 1 file changed, 12 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> index 1695b36dc23c..be44cb941e73 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>> if (smu->dc_controlled_by_gpio)
>> *(uint64_t *)feature_mask |=
>> FEATURE_MASK(FEATURE_ACDC_BIT);
>>
>> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>> + *(uint64_t *)feature_mask |=
>> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>> +
>> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
>> + if (!(is_asic_secure(smu) &&
>> + (adev->asic_type == CHIP_NAVI10) &&
>> + (adev->rev_id == 0)) &&
>> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
>> + |
>> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>> +
>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
>> if (is_asic_secure(smu) &&
>> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
>> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>>
>> static int navi10_post_smu_init(struct smu_context *smu) {
>> - struct smu_feature *feature = &smu->smu_feature;
>> struct amdgpu_device *adev = smu->adev;
>> - uint64_t feature_mask = 0;
>> int ret = 0;
>>
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>>
>> - /* For Naiv1x, enable these features only after DAL initialization */
>> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>> -
>> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
>> - if (!(is_asic_secure(smu) &&
>> - (adev->asic_type == CHIP_NAVI10) &&
>> - (adev->rev_id == 0)) &&
>> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
>> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>> -
>> - if (!feature_mask)
>> - return 0;
>> -
>> - bitmap_or(feature->allowed,
>> - feature->allowed,
>> - (unsigned long *)(&feature_mask),
>> - SMU_FEATURE_MAX);
>> -
>> - ret = smu_cmn_feature_update_enable_state(smu,
>> - feature_mask,
>> - true);
>> - if (ret) {
>> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
>> - return ret;
>> - }
>> -
>> ret = navi10_run_umc_cdr_workaround(smu);
>> if (ret) {
>> dev_err(adev->dev, "Failed to apply umc cdr
>> workaround!\n");
>> --
>> 2.28.0
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
>> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
>> 08e11a82d994e183d%7C0%7C0%7C637365492561293539&sdata=J%2FM6YSLX6d%
>> 2BMO%2B%2FWzdKAW7JlVZM%2FMFRDpTfi6UHkozk%3D&reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-25 21:05 ` Matt Coffin
@ 2020-09-25 21:09 ` Alex Deucher
2020-09-25 21:13 ` Matt Coffin
0 siblings, 1 reply; 8+ messages in thread
From: Alex Deucher @ 2020-09-25 21:09 UTC (permalink / raw)
To: Matt Coffin; +Cc: Deucher, Alexander, Quan, Evan, amd-gfx list
On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin <mcoffin13@gmail.com> wrote:
>
> Sorry to bother you guys, but trying to learn about some of these
> things, and I'm tracking the issue this relates to pretty closely on GitLab.
>
> What does DAL stand for in this context?
DAL is the name of the display team within AMD.
Alex
>
> Thanks in advance for the help,
> Matt
>
> On 9/24/20 9:38 PM, Quan, Evan wrote:
> > [AMD Official Use Only - Internal Distribution Only]
> >
> > That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
> > For now, we just revert it to get around the screen flicker issue introduced.
> >
> > BR
> > Evan
> > -----Original Message-----
> > From: Alex Deucher <alexdeucher@gmail.com>
> > Sent: Thursday, September 24, 2020 9:01 PM
> > To: Quan, Evan <Evan.Quan@amd.com>
> > Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
> > Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
> >
> > On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
> >>
> >> Revert the guilty change introduced by the commit below:
> >> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> >> initialization(V2)
> >>
> >> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> >> Signed-off-by: Evan Quan <evan.quan@amd.com>
> >
> > Won't this effectively disable the potential fix for multiple monitors at boot time?
> >
> > Acked-by: Alex Deucher <alexander.deucher@amd.com>
> >
> >> ---
> >> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
> >> 1 file changed, 12 insertions(+), 31 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> index 1695b36dc23c..be44cb941e73 100644
> >> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >> if (smu->dc_controlled_by_gpio)
> >> *(uint64_t *)feature_mask |=
> >> FEATURE_MASK(FEATURE_ACDC_BIT);
> >>
> >> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >> + *(uint64_t *)feature_mask |=
> >> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >> +
> >> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >> + if (!(is_asic_secure(smu) &&
> >> + (adev->asic_type == CHIP_NAVI10) &&
> >> + (adev->rev_id == 0)) &&
> >> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >> + |
> >> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >> +
> >> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> >> if (is_asic_secure(smu) &&
> >> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> >> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> >>
> >> static int navi10_post_smu_init(struct smu_context *smu) {
> >> - struct smu_feature *feature = &smu->smu_feature;
> >> struct amdgpu_device *adev = smu->adev;
> >> - uint64_t feature_mask = 0;
> >> int ret = 0;
> >>
> >> if (amdgpu_sriov_vf(adev))
> >> return 0;
> >>
> >> - /* For Naiv1x, enable these features only after DAL initialization */
> >> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >> -
> >> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >> - if (!(is_asic_secure(smu) &&
> >> - (adev->asic_type == CHIP_NAVI10) &&
> >> - (adev->rev_id == 0)) &&
> >> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >> -
> >> - if (!feature_mask)
> >> - return 0;
> >> -
> >> - bitmap_or(feature->allowed,
> >> - feature->allowed,
> >> - (unsigned long *)(&feature_mask),
> >> - SMU_FEATURE_MAX);
> >> -
> >> - ret = smu_cmn_feature_update_enable_state(smu,
> >> - feature_mask,
> >> - true);
> >> - if (ret) {
> >> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
> >> - return ret;
> >> - }
> >> -
> >> ret = navi10_run_umc_cdr_workaround(smu);
> >> if (ret) {
> >> dev_err(adev->dev, "Failed to apply umc cdr
> >> workaround!\n");
> >> --
> >> 2.28.0
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
> >> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
> >> 08e11a82d994e183d%7C0%7C0%7C637365492561293539&sdata=J%2FM6YSLX6d%
> >> 2BMO%2B%2FWzdKAW7JlVZM%2FMFRDpTfi6UHkozk%3D&reserved=0
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-25 21:09 ` Alex Deucher
@ 2020-09-25 21:13 ` Matt Coffin
2020-09-25 21:26 ` Alex Deucher
0 siblings, 1 reply; 8+ messages in thread
From: Matt Coffin @ 2020-09-25 21:13 UTC (permalink / raw)
To: Alex Deucher; +Cc: Deucher, Alexander, Quan, Evan, amd-gfx list
[-- Attachment #1.1.1: Type: text/plain, Size: 6468 bytes --]
Thanks for the quick reply,
Would it make sense, since there seem to be issues with both
before/after initialization, to (temporarily?) add a module parameter
for users so that they can switch between these two behaviors easily
based on what works for them?
If so, if you can toss me a hint at what name for the param would make
sense, I can take a crack at a patch for it, for debugging by the people
in the issue on GitLab.
Cheers, and thanks for the time,
Matt
GL issue for reference:
https://gitlab.freedesktop.org/drm/amd/-/issues/1260
On 9/25/20 3:09 PM, Alex Deucher wrote:
> On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin <mcoffin13@gmail.com> wrote:
>>
>> Sorry to bother you guys, but trying to learn about some of these
>> things, and I'm tracking the issue this relates to pretty closely on GitLab.
>>
>> What does DAL stand for in this context?
>
> DAL is the name of the display team within AMD.
>
> Alex
>
>>
>> Thanks in advance for the help,
>> Matt
>>
>> On 9/24/20 9:38 PM, Quan, Evan wrote:
>>> [AMD Official Use Only - Internal Distribution Only]
>>>
>>> That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
>>> For now, we just revert it to get around the screen flicker issue introduced.
>>>
>>> BR
>>> Evan
>>> -----Original Message-----
>>> From: Alex Deucher <alexdeucher@gmail.com>
>>> Sent: Thursday, September 24, 2020 9:01 PM
>>> To: Quan, Evan <Evan.Quan@amd.com>
>>> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
>>> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
>>>
>>> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
>>>>
>>>> Revert the guilty change introduced by the commit below:
>>>> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
>>>> initialization(V2)
>>>>
>>>> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
>>>> Signed-off-by: Evan Quan <evan.quan@amd.com>
>>>
>>> Won't this effectively disable the potential fix for multiple monitors at boot time?
>>>
>>> Acked-by: Alex Deucher <alexander.deucher@amd.com>
>>>
>>>> ---
>>>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
>>>> 1 file changed, 12 insertions(+), 31 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>>> index 1695b36dc23c..be44cb941e73 100644
>>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>>>> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
>>>> if (smu->dc_controlled_by_gpio)
>>>> *(uint64_t *)feature_mask |=
>>>> FEATURE_MASK(FEATURE_ACDC_BIT);
>>>>
>>>> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>>>> + *(uint64_t *)feature_mask |=
>>>> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>>>> +
>>>> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
>>>> + if (!(is_asic_secure(smu) &&
>>>> + (adev->asic_type == CHIP_NAVI10) &&
>>>> + (adev->rev_id == 0)) &&
>>>> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>>>> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>>>> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
>>>> + |
>>>> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>>>> +
>>>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
>>>> if (is_asic_secure(smu) &&
>>>> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
>>>> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
>>>>
>>>> static int navi10_post_smu_init(struct smu_context *smu) {
>>>> - struct smu_feature *feature = &smu->smu_feature;
>>>> struct amdgpu_device *adev = smu->adev;
>>>> - uint64_t feature_mask = 0;
>>>> int ret = 0;
>>>>
>>>> if (amdgpu_sriov_vf(adev))
>>>> return 0;
>>>>
>>>> - /* For Naiv1x, enable these features only after DAL initialization */
>>>> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
>>>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
>>>> -
>>>> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
>>>> - if (!(is_asic_secure(smu) &&
>>>> - (adev->asic_type == CHIP_NAVI10) &&
>>>> - (adev->rev_id == 0)) &&
>>>> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
>>>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>>>> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
>>>> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
>>>> -
>>>> - if (!feature_mask)
>>>> - return 0;
>>>> -
>>>> - bitmap_or(feature->allowed,
>>>> - feature->allowed,
>>>> - (unsigned long *)(&feature_mask),
>>>> - SMU_FEATURE_MAX);
>>>> -
>>>> - ret = smu_cmn_feature_update_enable_state(smu,
>>>> - feature_mask,
>>>> - true);
>>>> - if (ret) {
>>>> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
>>>> - return ret;
>>>> - }
>>>> -
>>>> ret = navi10_run_umc_cdr_workaround(smu);
>>>> if (ret) {
>>>> dev_err(adev->dev, "Failed to apply umc cdr
>>>> workaround!\n");
>>>> --
>>>> 2.28.0
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
>>>> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
>>>> 08e11a82d994e183d%7C0%7C0%7C637365492561293539&sdata=J%2FM6YSLX6d%
>>>> 2BMO%2B%2FWzdKAW7JlVZM%2FMFRDpTfi6UHkozk%3D&reserved=0
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>
>>
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
2020-09-25 21:13 ` Matt Coffin
@ 2020-09-25 21:26 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2020-09-25 21:26 UTC (permalink / raw)
To: Matt Coffin; +Cc: Deucher, Alexander, Quan, Evan, amd-gfx list
On Fri, Sep 25, 2020 at 5:13 PM Matt Coffin <mcoffin13@gmail.com> wrote:
>
> Thanks for the quick reply,
>
> Would it make sense, since there seem to be issues with both
> before/after initialization, to (temporarily?) add a module parameter
> for users so that they can switch between these two behaviors easily
> based on what works for them?
I'd rather work on a proper fix. module options tend to lead to more
problems than they solve as people tend blindly apply them.
Alex
>
> If so, if you can toss me a hint at what name for the param would make
> sense, I can take a crack at a patch for it, for debugging by the people
> in the issue on GitLab.
>
> Cheers, and thanks for the time,
> Matt
>
> GL issue for reference:
> https://gitlab.freedesktop.org/drm/amd/-/issues/1260
>
> On 9/25/20 3:09 PM, Alex Deucher wrote:
> > On Fri, Sep 25, 2020 at 5:05 PM Matt Coffin <mcoffin13@gmail.com> wrote:
> >>
> >> Sorry to bother you guys, but trying to learn about some of these
> >> things, and I'm tracking the issue this relates to pretty closely on GitLab.
> >>
> >> What does DAL stand for in this context?
> >
> > DAL is the name of the display team within AMD.
> >
> > Alex
> >
> >>
> >> Thanks in advance for the help,
> >> Matt
> >>
> >> On 9/24/20 9:38 PM, Quan, Evan wrote:
> >>> [AMD Official Use Only - Internal Distribution Only]
> >>>
> >>> That(postpone SOCCLK/UCLK enablement) will be revised and added back after confirmed with DAL team.
> >>> For now, we just revert it to get around the screen flicker issue introduced.
> >>>
> >>> BR
> >>> Evan
> >>> -----Original Message-----
> >>> From: Alex Deucher <alexdeucher@gmail.com>
> >>> Sent: Thursday, September 24, 2020 9:01 PM
> >>> To: Quan, Evan <Evan.Quan@amd.com>
> >>> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
> >>> Subject: Re: [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors
> >>>
> >>> On Thu, Sep 24, 2020 at 6:10 AM Evan Quan <evan.quan@amd.com> wrote:
> >>>>
> >>>> Revert the guilty change introduced by the commit below:
> >>>> drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL
> >>>> initialization(V2)
> >>>>
> >>>> Change-Id: I0cab619ffdf0f83b14ba5d2907e1b9c02a984e2f
> >>>> Signed-off-by: Evan Quan <evan.quan@amd.com>
> >>>
> >>> Won't this effectively disable the potential fix for multiple monitors at boot time?
> >>>
> >>> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> >>>
> >>>> ---
> >>>> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 43 ++++++-------------
> >>>> 1 file changed, 12 insertions(+), 31 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> index 1695b36dc23c..be44cb941e73 100644
> >>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> >>>> @@ -316,6 +316,18 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
> >>>> if (smu->dc_controlled_by_gpio)
> >>>> *(uint64_t *)feature_mask |=
> >>>> FEATURE_MASK(FEATURE_ACDC_BIT);
> >>>>
> >>>> + if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >>>> + *(uint64_t *)feature_mask |=
> >>>> + FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >>>> +
> >>>> + /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >>>> + if (!(is_asic_secure(smu) &&
> >>>> + (adev->asic_type == CHIP_NAVI10) &&
> >>>> + (adev->rev_id == 0)) &&
> >>>> + (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >>>> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >>>> + | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >>>> + |
> >>>> + FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >>>> +
> >>>> /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
> >>>> if (is_asic_secure(smu) &&
> >>>> (adev->asic_type == CHIP_NAVI10) && @@ -2629,43 +2641,12
> >>>> @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
> >>>>
> >>>> static int navi10_post_smu_init(struct smu_context *smu) {
> >>>> - struct smu_feature *feature = &smu->smu_feature;
> >>>> struct amdgpu_device *adev = smu->adev;
> >>>> - uint64_t feature_mask = 0;
> >>>> int ret = 0;
> >>>>
> >>>> if (amdgpu_sriov_vf(adev))
> >>>> return 0;
> >>>>
> >>>> - /* For Naiv1x, enable these features only after DAL initialization */
> >>>> - if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
> >>>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
> >>>> -
> >>>> - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
> >>>> - if (!(is_asic_secure(smu) &&
> >>>> - (adev->asic_type == CHIP_NAVI10) &&
> >>>> - (adev->rev_id == 0)) &&
> >>>> - (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
> >>>> - feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >>>> - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> >>>> - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
> >>>> -
> >>>> - if (!feature_mask)
> >>>> - return 0;
> >>>> -
> >>>> - bitmap_or(feature->allowed,
> >>>> - feature->allowed,
> >>>> - (unsigned long *)(&feature_mask),
> >>>> - SMU_FEATURE_MAX);
> >>>> -
> >>>> - ret = smu_cmn_feature_update_enable_state(smu,
> >>>> - feature_mask,
> >>>> - true);
> >>>> - if (ret) {
> >>>> - dev_err(adev->dev, "Failed to post uclk/socclk dpm enablement!\n");
> >>>> - return ret;
> >>>> - }
> >>>> -
> >>>> ret = navi10_run_umc_cdr_workaround(smu);
> >>>> if (ret) {
> >>>> dev_err(adev->dev, "Failed to apply umc cdr
> >>>> workaround!\n");
> >>>> --
> >>>> 2.28.0
> >>>>
> >>>> _______________________________________________
> >>>> amd-gfx mailing list
> >>>> amd-gfx@lists.freedesktop.org
> >>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >>>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cev
> >>>> an.quan%40amd.com%7C3899143b7990458f882c08d86089df67%7C3dd8961fe4884e6
> >>>> 08e11a82d994e183d%7C0%7C0%7C637365492561293539&sdata=J%2FM6YSLX6d%
> >>>> 2BMO%2B%2FWzdKAW7JlVZM%2FMFRDpTfi6UHkozk%3D&reserved=0
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >>>
> >>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-09-25 21:26 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-24 10:10 [PATCH] drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitors Evan Quan
2020-09-24 13:00 ` Alex Deucher
2020-09-25 3:38 ` Quan, Evan
2020-09-25 3:39 ` Deucher, Alexander
2020-09-25 21:05 ` Matt Coffin
2020-09-25 21:09 ` Alex Deucher
2020-09-25 21:13 ` Matt Coffin
2020-09-25 21:26 ` Alex Deucher
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