[PATCH 1/3] drm/amd/powerplay: set a default fclk/gfxclk ratio

[PATCH 1/3] drm/amd/powerplay: set a default fclk/gfxclk ratio

[Evan Quan]

Otherwise big gap between these two clocks may causes
some hangs.

Change-Id: Ifa3fafe2ee619d6231d5ecab61d3c68faa34abb6
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16 ++++++++++++++++
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h   |  1 +
 drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index d2da9e3fc827..4f0f444fd111 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -120,6 +120,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
 	data->registry_data.disable_auto_wattman = 1;
 	data->registry_data.auto_wattman_debug = 0;
 	data->registry_data.auto_wattman_sample_period = 100;
+	data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
 	data->registry_data.auto_wattman_threshold = 50;
 	data->registry_data.gfxoff_controlled_by_driver = 1;
 	data->gfxoff_allowed = false;
@@ -829,6 +830,16 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
+{
+	struct vega20_hwmgr *data =
+			(struct vega20_hwmgr *)(hwmgr->backend);
+
+	return smum_send_msg_to_smc_with_parameter(hwmgr,
+			PPSMC_MSG_SetFclkGfxClkRatio,
+			data->registry_data.fclk_gfxclk_ratio);
+}
+
 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 {
 	struct vega20_hwmgr *data =
@@ -1535,6 +1546,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 			"[EnableDPMTasks] Failed to enable all smu features!",
 			return result);
 
+	result = vega20_send_clock_ratio(hwmgr);
+	PP_ASSERT_WITH_CODE(!result,
+			"[EnableDPMTasks] Failed to send clock ratio!",
+			return result);
+
 	/* Initialize UVD/VCE powergating state */
 	vega20_init_powergate_state(hwmgr);
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 56fe6a0d42e8..25faaa5c5b10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -328,6 +328,7 @@ struct vega20_registry_data {
 	uint8_t   disable_auto_wattman;
 	uint32_t  auto_wattman_debug;
 	uint32_t  auto_wattman_sample_period;
+	uint32_t  fclk_gfxclk_ratio;
 	uint8_t   auto_wattman_threshold;
 	uint8_t   log_avfs_param;
 	uint8_t   enable_enginess;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 45d64a81e945..4f63a736ea0e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -105,7 +105,8 @@
 #define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x4B
 #define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x4C
 #define PPSMC_MSG_WaflTest                       0x4D
-// Unused ID 0x4E to 0x50
+#define PPSMC_MSG_SetFclkGfxClkRatio             0x4E
+// Unused ID 0x4F to 0x50
 #define PPSMC_MSG_AllowGfxOff                    0x51
 #define PPSMC_MSG_DisallowGfxOff                 0x52
 #define PPSMC_MSG_GetPptLimit                    0x53
-- 
2.19.1

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[PATCH 2/3] drm/amd/powerplay: always use fast UCLK switching when UCLK DPM enabled

[Evan Quan]

With UCLK DPM enabled, slow switching is not supported any more.

Change-Id: I6242e782441272487aebd161836868785a6f7ee8
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 37 +++++++++----------
 1 file changed, 17 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 4f0f444fd111..91956471cd0f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -830,6 +830,18 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
+{
+	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
+
+	if (data->smu_features[GNLD_DPM_UCLK].enabled)
+		return smum_send_msg_to_smc_with_parameter(hwmgr,
+			PPSMC_MSG_SetUclkFastSwitch,
+			1);
+
+	return 0;
+}
+
 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
 {
 	struct vega20_hwmgr *data =
@@ -1546,6 +1558,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 			"[EnableDPMTasks] Failed to enable all smu features!",
 			return result);
 
+	result = vega20_notify_smc_display_change(hwmgr);
+	PP_ASSERT_WITH_CODE(!result,
+			"[EnableDPMTasks] Failed to notify smc display change!",
+			return result);
+
 	result = vega20_send_clock_ratio(hwmgr);
 	PP_ASSERT_WITH_CODE(!result,
 			"[EnableDPMTasks] Failed to send clock ratio!",
@@ -1991,19 +2008,6 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	return ret;
 }
 
-static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
-		bool has_disp)
-{
-	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
-
-	if (data->smu_features[GNLD_DPM_UCLK].enabled)
-		return smum_send_msg_to_smc_with_parameter(hwmgr,
-			PPSMC_MSG_SetUclkFastSwitch,
-			has_disp ? 1 : 0);
-
-	return 0;
-}
-
 int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 		struct pp_display_clock_request *clock_req)
 {
@@ -2063,13 +2067,6 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
 	struct pp_display_clock_request clock_req;
 	int ret = 0;
 
-	if ((hwmgr->display_config->num_display > 1) &&
-	     !hwmgr->display_config->multi_monitor_in_sync &&
-	     !hwmgr->display_config->nb_pstate_switch_disable)
-		vega20_notify_smc_display_change(hwmgr, false);
-	else
-		vega20_notify_smc_display_change(hwmgr, true);
-
 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
-- 
2.19.1

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[PATCH 3/3] drm/amdgpu: set Vega20 LBPW as disabled at default

[Evan Quan]

For Vega20, LBPW feature is disabled at default.

Change-Id: I184520cbb03ab8cba9321cd94d1deb0ce38b7e17
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index dcf1f79ab347..5bb0cca5b71f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2503,6 +2503,20 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 			return r;
 	}
 
+	if (amdgpu_lbpw == -1) {
+		switch (adev->asic_type) {
+		case CHIP_RAVEN:
+			amdgpu_lbpw = 1;
+			break;
+		case CHIP_VEGA20:
+			amdgpu_lbpw = 0;
+			break;
+		default:
+			amdgpu_lbpw = 0;
+			break;
+		}
+	}
+
 	if (adev->asic_type == CHIP_RAVEN ||
 	    adev->asic_type == CHIP_VEGA20) {
 		if (amdgpu_lbpw != 0)
-- 
2.19.1

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RE: [PATCH 1/3] drm/amd/powerplay: set a default fclk/gfxclk ratio

[Xu, Feifei]

Seriel is reviewed-by: Feifei Xu <Feifei.Xu@amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
Sent: Wednesday, November 7, 2018 9:38 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 1/3] drm/amd/powerplay: set a default fclk/gfxclk ratio

Otherwise big gap between these two clocks may causes some hangs.

Change-Id: Ifa3fafe2ee619d6231d5ecab61d3c68faa34abb6
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16 ++++++++++++++++
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h   |  1 +
 drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
 3 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index d2da9e3fc827..4f0f444fd111 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -120,6 +120,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
 	data->registry_data.disable_auto_wattman = 1;
 	data->registry_data.auto_wattman_debug = 0;
 	data->registry_data.auto_wattman_sample_period = 100;
+	data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
 	data->registry_data.auto_wattman_threshold = 50;
 	data->registry_data.gfxoff_controlled_by_driver = 1;
 	data->gfxoff_allowed = false;
@@ -829,6 +830,16 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr) {
+	struct vega20_hwmgr *data =
+			(struct vega20_hwmgr *)(hwmgr->backend);
+
+	return smum_send_msg_to_smc_with_parameter(hwmgr,
+			PPSMC_MSG_SetFclkGfxClkRatio,
+			data->registry_data.fclk_gfxclk_ratio);
+}
+
 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)  {
 	struct vega20_hwmgr *data =
@@ -1535,6 +1546,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 			"[EnableDPMTasks] Failed to enable all smu features!",
 			return result);
 
+	result = vega20_send_clock_ratio(hwmgr);
+	PP_ASSERT_WITH_CODE(!result,
+			"[EnableDPMTasks] Failed to send clock ratio!",
+			return result);
+
 	/* Initialize UVD/VCE powergating state */
 	vega20_init_powergate_state(hwmgr);
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
index 56fe6a0d42e8..25faaa5c5b10 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
@@ -328,6 +328,7 @@ struct vega20_registry_data {
 	uint8_t   disable_auto_wattman;
 	uint32_t  auto_wattman_debug;
 	uint32_t  auto_wattman_sample_period;
+	uint32_t  fclk_gfxclk_ratio;
 	uint8_t   auto_wattman_threshold;
 	uint8_t   log_avfs_param;
 	uint8_t   enable_enginess;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
index 45d64a81e945..4f63a736ea0e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
@@ -105,7 +105,8 @@
 #define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x4B
 #define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x4C
 #define PPSMC_MSG_WaflTest                       0x4D
-// Unused ID 0x4E to 0x50
+#define PPSMC_MSG_SetFclkGfxClkRatio             0x4E
+// Unused ID 0x4F to 0x50
 #define PPSMC_MSG_AllowGfxOff                    0x51
 #define PPSMC_MSG_DisallowGfxOff                 0x52
 #define PPSMC_MSG_GetPptLimit                    0x53
--
2.19.1

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Re: [PATCH 3/3] drm/amdgpu: set Vega20 LBPW as disabled at default

[Alex Deucher]

On Tue, Nov 6, 2018 at 8:37 PM Evan Quan <evan.quan@amd.com> wrote:
>
> For Vega20, LBPW feature is disabled at default.
>
> Change-Id: I184520cbb03ab8cba9321cd94d1deb0ce38b7e17
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index dcf1f79ab347..5bb0cca5b71f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2503,6 +2503,20 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
>                         return r;
>         }
>
> +       if (amdgpu_lbpw == -1) {
> +               switch (adev->asic_type) {
> +               case CHIP_RAVEN:
> +                       amdgpu_lbpw = 1;
> +                       break;
> +               case CHIP_VEGA20:
> +                       amdgpu_lbpw = 0;
> +                       break;
> +               default:
> +                       amdgpu_lbpw = 0;
> +                       break;
> +               }
> +       }

I'd suggest using a local variable rather than changing the global one
since there may be multiple GPUs in the system.

Alex

> +
>         if (adev->asic_type == CHIP_RAVEN ||
>             adev->asic_type == CHIP_VEGA20) {
>                 if (amdgpu_lbpw != 0)
> --
> 2.19.1
>
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Re: [PATCH 2/3] drm/amd/powerplay: always use fast UCLK switching when UCLK DPM enabled

[Alex Deucher]

On Tue, Nov 6, 2018 at 8:37 PM Evan Quan <evan.quan@amd.com> wrote:
>
> With UCLK DPM enabled, slow switching is not supported any more.
>
> Change-Id: I6242e782441272487aebd161836868785a6f7ee8
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 37 +++++++++----------
>  1 file changed, 17 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 4f0f444fd111..91956471cd0f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -830,6 +830,18 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
>         return 0;
>  }
>
> +static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
> +{
> +       struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
> +
> +       if (data->smu_features[GNLD_DPM_UCLK].enabled)
> +               return smum_send_msg_to_smc_with_parameter(hwmgr,
> +                       PPSMC_MSG_SetUclkFastSwitch,
> +                       1);
> +
> +       return 0;
> +}
> +
>  static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
>  {
>         struct vega20_hwmgr *data =
> @@ -1546,6 +1558,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>                         "[EnableDPMTasks] Failed to enable all smu features!",
>                         return result);
>
> +       result = vega20_notify_smc_display_change(hwmgr);
> +       PP_ASSERT_WITH_CODE(!result,
> +                       "[EnableDPMTasks] Failed to notify smc display change!",
> +                       return result);
> +
>         result = vega20_send_clock_ratio(hwmgr);
>         PP_ASSERT_WITH_CODE(!result,
>                         "[EnableDPMTasks] Failed to send clock ratio!",
> @@ -1991,19 +2008,6 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>         return ret;
>  }
>
> -static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr,
> -               bool has_disp)
> -{
> -       struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
> -
> -       if (data->smu_features[GNLD_DPM_UCLK].enabled)
> -               return smum_send_msg_to_smc_with_parameter(hwmgr,
> -                       PPSMC_MSG_SetUclkFastSwitch,
> -                       has_disp ? 1 : 0);
> -
> -       return 0;
> -}
> -
>  int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
>                 struct pp_display_clock_request *clock_req)
>  {
> @@ -2063,13 +2067,6 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
>         struct pp_display_clock_request clock_req;
>         int ret = 0;
>
> -       if ((hwmgr->display_config->num_display > 1) &&
> -            !hwmgr->display_config->multi_monitor_in_sync &&
> -            !hwmgr->display_config->nb_pstate_switch_disable)
> -               vega20_notify_smc_display_change(hwmgr, false);
> -       else
> -               vega20_notify_smc_display_change(hwmgr, true);
> -
>         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
>         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
>         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
> --
> 2.19.1
>
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Re: [PATCH 1/3] drm/amd/powerplay: set a default fclk/gfxclk ratio

[Alex Deucher]

On Tue, Nov 6, 2018 at 8:42 PM Xu, Feifei <Feifei.Xu@amd.com> wrote:
>
> Seriel is reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Evan Quan
> Sent: Wednesday, November 7, 2018 9:38 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 1/3] drm/amd/powerplay: set a default fclk/gfxclk ratio
>
> Otherwise big gap between these two clocks may causes some hangs.
>
> Change-Id: Ifa3fafe2ee619d6231d5ecab61d3c68faa34abb6
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c   | 16 ++++++++++++++++
>  .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h   |  1 +
>  drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h |  3 ++-
>  3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index d2da9e3fc827..4f0f444fd111 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -120,6 +120,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
>         data->registry_data.disable_auto_wattman = 1;
>         data->registry_data.auto_wattman_debug = 0;
>         data->registry_data.auto_wattman_sample_period = 100;
> +       data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
>         data->registry_data.auto_wattman_threshold = 50;
>         data->registry_data.gfxoff_controlled_by_driver = 1;
>         data->gfxoff_allowed = false;
> @@ -829,6 +830,16 @@ static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
>         return 0;
>  }
>
> +static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr) {
> +       struct vega20_hwmgr *data =
> +                       (struct vega20_hwmgr *)(hwmgr->backend);
> +
> +       return smum_send_msg_to_smc_with_parameter(hwmgr,
> +                       PPSMC_MSG_SetFclkGfxClkRatio,
> +                       data->registry_data.fclk_gfxclk_ratio);
> +}
> +
>  static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)  {
>         struct vega20_hwmgr *data =
> @@ -1535,6 +1546,11 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
>                         "[EnableDPMTasks] Failed to enable all smu features!",
>                         return result);
>
> +       result = vega20_send_clock_ratio(hwmgr);
> +       PP_ASSERT_WITH_CODE(!result,
> +                       "[EnableDPMTasks] Failed to send clock ratio!",
> +                       return result);
> +
>         /* Initialize UVD/VCE powergating state */
>         vega20_init_powergate_state(hwmgr);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
> index 56fe6a0d42e8..25faaa5c5b10 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h
> @@ -328,6 +328,7 @@ struct vega20_registry_data {
>         uint8_t   disable_auto_wattman;
>         uint32_t  auto_wattman_debug;
>         uint32_t  auto_wattman_sample_period;
> +       uint32_t  fclk_gfxclk_ratio;
>         uint8_t   auto_wattman_threshold;
>         uint8_t   log_avfs_param;
>         uint8_t   enable_enginess;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> index 45d64a81e945..4f63a736ea0e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/vega20_ppsmc.h
> @@ -105,7 +105,8 @@
>  #define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x4B
>  #define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x4C
>  #define PPSMC_MSG_WaflTest                       0x4D
> -// Unused ID 0x4E to 0x50
> +#define PPSMC_MSG_SetFclkGfxClkRatio             0x4E
> +// Unused ID 0x4F to 0x50
>  #define PPSMC_MSG_AllowGfxOff                    0x51
>  #define PPSMC_MSG_DisallowGfxOff                 0x52
>  #define PPSMC_MSG_GetPptLimit                    0x53
> --
> 2.19.1
>
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