* [PATCH 1/6] drm/amdgpu: skip CG for VCN when late_init/fini @ 2018-05-16 12:52 Rex Zhu [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 12+ messages in thread From: Rex Zhu @ 2018-05-16 12:52 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fcd4bb2..25bee46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1718,6 +1718,7 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) /* skip CG for VCE/UVD, it's handled specially */ if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && adev->ip_blocks[i].version->funcs->set_clockgating_state) { /* enable clockgating to save power */ r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, @@ -1817,6 +1818,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && adev->ip_blocks[i].version->funcs->set_clockgating_state) { /* ungate blocks before hw fini so that we can shutdown the blocks safely */ r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
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* [PATCH 2/6] drm/amd/pp: Add smu support for vcn cg/pg on RV [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-05-16 12:52 ` Rex Zhu [not found] ` <1526475182-32156-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:52 ` [PATCH 3/6] drm/amdgpu: Add CG/PG flags for VCN Rex Zhu ` (4 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Rex Zhu @ 2018-05-16 12:52 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 25 ++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c index 32b1524..436326b 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c @@ -1146,6 +1146,29 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr) return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub); } +static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) +{ + if (bgate) { + amdgpu_device_ip_set_powergating_state(hwmgr->adev, + AMD_IP_BLOCK_TYPE_VCN, + AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state(hwmgr->adev, + AMD_IP_BLOCK_TYPE_VCN, + AMD_CG_STATE_GATE); + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_PowerDownVcn, 0); + } else { + smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_PowerUpVcn, 0); + amdgpu_device_ip_set_clockgating_state(hwmgr->adev, + AMD_IP_BLOCK_TYPE_VCN, + AMD_CG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(hwmgr->adev, + AMD_IP_BLOCK_TYPE_VCN, + AMD_PG_STATE_UNGATE); + } +} + static const struct pp_hwmgr_func smu10_hwmgr_funcs = { .backend_init = smu10_hwmgr_backend_init, .backend_fini = smu10_hwmgr_backend_fini, @@ -1154,7 +1177,7 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr) .force_dpm_level = smu10_dpm_force_dpm_level, .get_power_state_size = smu10_get_power_state_size, .powerdown_uvd = NULL, - .powergate_uvd = NULL, + .powergate_uvd = smu10_powergate_vcn, .powergate_vce = NULL, .get_mclk = smu10_dpm_get_mclk, .get_sclk = smu10_dpm_get_sclk, -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
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* Re: [PATCH 2/6] drm/amd/pp: Add smu support for vcn cg/pg on RV [not found] ` <1526475182-32156-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-05-16 15:55 ` Alex Deucher 0 siblings, 0 replies; 12+ messages in thread From: Alex Deucher @ 2018-05-16 15:55 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Wed, May 16, 2018 at 8:52 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 25 ++++++++++++++++++++++- > 1 file changed, 24 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c > index 32b1524..436326b 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c > @@ -1146,6 +1146,29 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr) > return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub); > } > > +static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) > +{ > + if (bgate) { > + amdgpu_device_ip_set_powergating_state(hwmgr->adev, > + AMD_IP_BLOCK_TYPE_VCN, > + AMD_PG_STATE_GATE); > + amdgpu_device_ip_set_clockgating_state(hwmgr->adev, > + AMD_IP_BLOCK_TYPE_VCN, > + AMD_CG_STATE_GATE); > + smum_send_msg_to_smc_with_parameter(hwmgr, > + PPSMC_MSG_PowerDownVcn, 0); > + } else { > + smum_send_msg_to_smc_with_parameter(hwmgr, > + PPSMC_MSG_PowerUpVcn, 0); > + amdgpu_device_ip_set_clockgating_state(hwmgr->adev, > + AMD_IP_BLOCK_TYPE_VCN, > + AMD_CG_STATE_UNGATE); > + amdgpu_device_ip_set_powergating_state(hwmgr->adev, > + AMD_IP_BLOCK_TYPE_VCN, > + AMD_PG_STATE_UNGATE); > + } > +} > + > static const struct pp_hwmgr_func smu10_hwmgr_funcs = { > .backend_init = smu10_hwmgr_backend_init, > .backend_fini = smu10_hwmgr_backend_fini, > @@ -1154,7 +1177,7 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr) > .force_dpm_level = smu10_dpm_force_dpm_level, > .get_power_state_size = smu10_get_power_state_size, > .powerdown_uvd = NULL, > - .powergate_uvd = NULL, > + .powergate_uvd = smu10_powergate_vcn, > .powergate_vce = NULL, > .get_mclk = smu10_dpm_get_mclk, > .get_sclk = smu10_dpm_get_sclk, > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/6] drm/amdgpu: Add CG/PG flags for VCN [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:52 ` [PATCH 2/6] drm/amd/pp: Add smu support for vcn cg/pg on RV Rex Zhu @ 2018-05-16 12:52 ` Rex Zhu [not found] ` <1526475182-32156-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:53 ` [PATCH 4/6] drm/amdgpu: Add runtime vcn cg/pg enablement Rex Zhu ` (3 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Rex Zhu @ 2018-05-16 12:52 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/include/amd_shared.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 33de330..b178176 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -92,7 +92,7 @@ enum amd_powergating_state { #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) - +#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) /* PG flags */ #define AMD_PG_SUPPORT_GFX_PG (1 << 0) #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) @@ -108,6 +108,7 @@ enum amd_powergating_state { #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) #define AMD_PG_SUPPORT_MMHUB (1 << 13) +#define AMD_PG_SUPPORT_VCN (1 << 14) enum PP_FEATURE_MASK { PP_SCLK_DPM_MASK = 0x1, -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
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* Re: [PATCH 3/6] drm/amdgpu: Add CG/PG flags for VCN [not found] ` <1526475182-32156-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-05-16 15:55 ` Alex Deucher 0 siblings, 0 replies; 12+ messages in thread From: Alex Deucher @ 2018-05-16 15:55 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Wed, May 16, 2018 at 8:52 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/include/amd_shared.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h > index 33de330..b178176 100644 > --- a/drivers/gpu/drm/amd/include/amd_shared.h > +++ b/drivers/gpu/drm/amd/include/amd_shared.h > @@ -92,7 +92,7 @@ enum amd_powergating_state { > #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) > #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) > #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) > - > +#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) > /* PG flags */ > #define AMD_PG_SUPPORT_GFX_PG (1 << 0) > #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) > @@ -108,6 +108,7 @@ enum amd_powergating_state { > #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) > #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) > #define AMD_PG_SUPPORT_MMHUB (1 << 13) > +#define AMD_PG_SUPPORT_VCN (1 << 14) > > enum PP_FEATURE_MASK { > PP_SCLK_DPM_MASK = 0x1, > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/6] drm/amdgpu: Add runtime vcn cg/pg enablement [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:52 ` [PATCH 2/6] drm/amd/pp: Add smu support for vcn cg/pg on RV Rex Zhu 2018-05-16 12:52 ` [PATCH 3/6] drm/amdgpu: Add CG/PG flags for VCN Rex Zhu @ 2018-05-16 12:53 ` Rex Zhu [not found] ` <1526475182-32156-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:53 ` [PATCH 5/6] drm/amdgpu: Enable static cg for vcn on RV Rex Zhu ` (2 subsequent siblings) 5 siblings, 1 reply; 12+ messages in thread From: Rex Zhu @ 2018-05-16 12:53 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 58e4953..8b0d491 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -208,9 +208,13 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) if (fences == 0) { if (adev->pm.dpm_enabled) { - /* might be used when with pg/cg amdgpu_dpm_enable_uvd(adev, false); - */ + } else { + /* shutdown the UVD block */ + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, + AMD_PG_STATE_GATE); + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCN, + AMD_CG_STATE_GATE); } } else { schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); @@ -223,9 +227,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); if (set_clocks && adev->pm.dpm_enabled) { - /* might be used when with pg/cg - amdgpu_dpm_enable_uvd(adev, true); - */ + if (adev->pm.dpm_enabled) { + amdgpu_dpm_enable_uvd(adev, true); + } else { + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCN, + AMD_CG_STATE_UNGATE); + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, + AMD_PG_STATE_UNGATE); + } } } -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <1526475182-32156-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 4/6] drm/amdgpu: Add runtime vcn cg/pg enablement [not found] ` <1526475182-32156-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-05-16 15:53 ` Alex Deucher 0 siblings, 0 replies; 12+ messages in thread From: Alex Deucher @ 2018-05-16 15:53 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Wed, May 16, 2018 at 8:53 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Please add a better patch description. E.g., drm/amdgpu: Add runtime vcn cg/pg enablement Enable support for dynamically powering up/down VCN on demand. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> With that fixed: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 19 ++++++++++++++----- > 1 file changed, 14 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 58e4953..8b0d491 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -208,9 +208,13 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work) > > if (fences == 0) { > if (adev->pm.dpm_enabled) { > - /* might be used when with pg/cg > amdgpu_dpm_enable_uvd(adev, false); > - */ > + } else { > + /* shutdown the UVD block */ > + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, > + AMD_PG_STATE_GATE); > + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCN, > + AMD_CG_STATE_GATE); > } > } else { > schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); > @@ -223,9 +227,14 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring) > bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); > > if (set_clocks && adev->pm.dpm_enabled) { > - /* might be used when with pg/cg > - amdgpu_dpm_enable_uvd(adev, true); > - */ > + if (adev->pm.dpm_enabled) { > + amdgpu_dpm_enable_uvd(adev, true); > + } else { > + amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCN, > + AMD_CG_STATE_UNGATE); > + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, > + AMD_PG_STATE_UNGATE); > + } > } > } > > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 5/6] drm/amdgpu: Enable static cg for vcn on RV [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> ` (2 preceding siblings ...) 2018-05-16 12:53 ` [PATCH 4/6] drm/amdgpu: Add runtime vcn cg/pg enablement Rex Zhu @ 2018-05-16 12:53 ` Rex Zhu [not found] ` <1526475182-32156-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:53 ` [PATCH 6/6] drm/amdgpu: Enable static pg feature " Rex Zhu 2018-05-16 15:54 ` [PATCH 1/6] drm/amdgpu: skip CG for VCN when late_init/fini Alex Deucher 5 siblings, 1 reply; 12+ messages in thread From: Rex Zhu @ 2018-05-16 12:53 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 16 ++++++++-------- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 8ccbcf9..485cb43 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -711,7 +711,8 @@ static int soc15_common_early_init(void *handle) AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_SDMA_MGCG | - AMD_CG_SUPPORT_SDMA_LS; + AMD_CG_SUPPORT_SDMA_LS | + AMD_CG_SUPPORT_VCN_MGCG; adev->pg_flags = AMD_PG_SUPPORT_SDMA; if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 0501746b..9e0a2b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -288,14 +288,14 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) * * Disable clock gating for VCN block */ -static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) +static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) { uint32_t data; /* JPEG disable CGC */ data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); - if (sw) + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; else data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; @@ -310,7 +310,7 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) /* UVD disable CGC */ data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); - if (sw) + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; else data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; @@ -415,13 +415,13 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) * * Enable clock gating for VCN block */ -static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) +static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) { uint32_t data = 0; /* enable JPEG CGC */ data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); - if (sw) + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; else data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; @@ -435,7 +435,7 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) /* enable UVD CGC */ data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); - if (sw) + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; else data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; @@ -500,7 +500,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) vcn_v1_0_mc_resume(adev); /* disable clock gating */ - vcn_v1_0_disable_clock_gating(adev, true); + vcn_v1_0_disable_clock_gating(adev); /* disable interupt */ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, @@ -681,7 +681,7 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); /* enable clock gating */ - vcn_v1_0_enable_clock_gating(adev, true); + vcn_v1_0_enable_clock_gating(adev); return 0; } -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <1526475182-32156-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 5/6] drm/amdgpu: Enable static cg for vcn on RV [not found] ` <1526475182-32156-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-05-16 15:45 ` Alex Deucher 0 siblings, 0 replies; 12+ messages in thread From: Alex Deucher @ 2018-05-16 15:45 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Wed, May 16, 2018 at 8:53 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 16 ++++++++-------- > 2 files changed, 10 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c > index 8ccbcf9..485cb43 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > @@ -711,7 +711,8 @@ static int soc15_common_early_init(void *handle) > AMD_CG_SUPPORT_MC_MGCG | > AMD_CG_SUPPORT_MC_LS | > AMD_CG_SUPPORT_SDMA_MGCG | > - AMD_CG_SUPPORT_SDMA_LS; > + AMD_CG_SUPPORT_SDMA_LS | > + AMD_CG_SUPPORT_VCN_MGCG; Split out the setting of the flag to enable this from the implementation. With that fixed: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > adev->pg_flags = AMD_PG_SUPPORT_SDMA; > > if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index 0501746b..9e0a2b1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -288,14 +288,14 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) > * > * Disable clock gating for VCN block > */ > -static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) > +static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) > { > uint32_t data; > > /* JPEG disable CGC */ > data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); > > - if (sw) > + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) > data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > else > data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; > @@ -310,7 +310,7 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) > > /* UVD disable CGC */ > data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); > - if (sw) > + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) > data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > else > data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; > @@ -415,13 +415,13 @@ static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev, bool sw) > * > * Enable clock gating for VCN block > */ > -static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) > +static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) > { > uint32_t data = 0; > > /* enable JPEG CGC */ > data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); > - if (sw) > + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) > data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > else > data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > @@ -435,7 +435,7 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev, bool sw) > > /* enable UVD CGC */ > data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); > - if (sw) > + if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) > data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > else > data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; > @@ -500,7 +500,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > vcn_v1_0_mc_resume(adev); > > /* disable clock gating */ > - vcn_v1_0_disable_clock_gating(adev, true); > + vcn_v1_0_disable_clock_gating(adev); > > /* disable interupt */ > WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, > @@ -681,7 +681,7 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) > ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); > > /* enable clock gating */ > - vcn_v1_0_enable_clock_gating(adev, true); > + vcn_v1_0_enable_clock_gating(adev); > > return 0; > } > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 6/6] drm/amdgpu: Enable static pg feature on RV [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> ` (3 preceding siblings ...) 2018-05-16 12:53 ` [PATCH 5/6] drm/amdgpu: Enable static cg for vcn on RV Rex Zhu @ 2018-05-16 12:53 ` Rex Zhu [not found] ` <1526475182-32156-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 15:54 ` [PATCH 1/6] drm/amdgpu: skip CG for VCN when late_init/fini Alex Deucher 5 siblings, 1 reply; 12+ messages in thread From: Rex Zhu @ 2018-05-16 12:53 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 11 ++ drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 183 ++++++++++++++++++++++++++++++-- 3 files changed, 187 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 2fd7db8..181e6af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -45,6 +45,17 @@ #define VCN_ENC_CMD_REG_WRITE 0x0000000b #define VCN_ENC_CMD_REG_WAIT 0x0000000c +enum engine_status_constants { + UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, + UVD_STATUS__UVD_BUSY = 0x00000004, + GB_ADDR_CONFIG_DEFAULT = 0x26010011, + UVD_STATUS__IDLE = 0x2, + UVD_STATUS__BUSY = 0x5, + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, + UVD_STATUS__RBC_BUSY = 0x1, +}; + struct amdgpu_vcn { struct amdgpu_bo *vcpu_bo; void *cpu_addr; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 485cb43..9a7a85d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -713,7 +713,8 @@ static int soc15_common_early_init(void *handle) AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_VCN_MGCG; - adev->pg_flags = AMD_PG_SUPPORT_SDMA; + + adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 9e0a2b1..89a9477 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -146,10 +146,6 @@ static int vcn_v1_0_hw_init(void *handle) struct amdgpu_ring *ring = &adev->vcn.ring_dec; int i, r; - r = vcn_v1_0_start(adev); - if (r) - goto done; - ring->ready = true; r = amdgpu_ring_test_ring(ring); if (r) { @@ -480,6 +476,117 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); } +static int vcn_wait_on_reg_read(struct amdgpu_device *adev, uint32_t segment_index, + uint32_t reg, uint32_t expected_value, + uint32_t mask) +{ + uint32_t loop, data; + + data = RREG32(adev->reg_offset[VCN_HWIP][0][segment_index] + reg); + + loop = 1000; + + while ((data & mask) != expected_value) { + udelay(10); + data = RREG32(adev->reg_offset[VCN_HWIP][0][segment_index] + reg); + loop--; + if (!loop) + return -ETIMEDOUT; + } + + return 0; +} + +static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) +{ + uint32_t data = 0; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { + data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); + + WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); + vcn_wait_on_reg_read(adev, mmUVD_PGFSM_STATUS_BASE_IDX, mmUVD_PGFSM_STATUS, + UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); + } else { + data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT + | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); + WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); + vcn_wait_on_reg_read(adev, mmUVD_PGFSM_STATUS_BASE_IDX, mmUVD_PGFSM_STATUS, + 0, 0xFFFFFFFF); + } + + /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ + + data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); + data &= ~0x103; + if (adev->pg_flags & AMD_PG_SUPPORT_VCN) + data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; + + WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); +} + +static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) +{ + uint32_t data = 0; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { + /* Before power off, this indicator has to be turned on */ + data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); + data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; + data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; + WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); + + + data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT + | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); + + WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); + + + data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT + | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); + vcn_wait_on_reg_read(adev, mmUVD_PGFSM_STATUS_BASE_IDX, + mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); + } +} + /** * vcn_v1_0_start - start VCN block * @@ -499,6 +606,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) vcn_v1_0_mc_resume(adev); + vcn_1_0_disable_static_power_gating(adev); /* disable clock gating */ vcn_v1_0_disable_clock_gating(adev); @@ -681,15 +789,46 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); /* enable clock gating */ - vcn_v1_0_enable_clock_gating(adev); + vcn_v1_0_enable_clock_gating(adev); + vcn_1_0_enable_static_power_gating(adev); return 0; } + +bool vcn_v1_0_is_idle(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); +} + +int vcn_v1_0_wait_for_idle(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + vcn_wait_on_reg_read(adev, mmUVD_STATUS_BASE_IDX, mmUVD_STATUS, + 0x2, 0x2); + return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); +} + static int vcn_v1_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { - /* needed for driver unload*/ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + + if (enable) { + /* wait for STATUS to clear */ + if (vcn_v1_0_is_idle(handle)) + return -EBUSY; + vcn_v1_0_enable_clock_gating(adev); + /* enable HW gates because UVD is idle */ +/* uvd_v6_0_set_hw_clock_gating(adev); */ + } else { + /* disable HW gating and enable Sw gating */ + vcn_v1_0_disable_clock_gating(adev); + } return 0; } @@ -1058,6 +1197,32 @@ static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) } +static int vcn_v1_0_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + /* This doesn't actually powergate the VCN block. + * That's done in the dpm code via the SMC. This + * just re-inits the block as necessary. The actual + * gating still happens in the dpm code. We should + * revisit this when there is a cleaner line between + * the smc and the hw blocks + */ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret = 0; + + //WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); + + if (state == AMD_PG_STATE_GATE) { + vcn_v1_0_stop(adev); + } else { + ret = vcn_v1_0_start(adev); + if (ret) + goto out; + } + +out: + return ret; +} static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { .name = "vcn_v1_0", @@ -1069,14 +1234,14 @@ static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) .hw_fini = vcn_v1_0_hw_fini, .suspend = vcn_v1_0_suspend, .resume = vcn_v1_0_resume, - .is_idle = NULL /* vcn_v1_0_is_idle */, - .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */, + .is_idle = vcn_v1_0_is_idle, + .wait_for_idle = vcn_v1_0_wait_for_idle, .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, .soft_reset = NULL /* vcn_v1_0_soft_reset */, .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, .set_clockgating_state = vcn_v1_0_set_clockgating_state, - .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */, + .set_powergating_state = vcn_v1_0_set_powergating_state, }; static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <1526475182-32156-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 6/6] drm/amdgpu: Enable static pg feature on RV [not found] ` <1526475182-32156-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2018-05-16 15:51 ` Alex Deucher 0 siblings, 0 replies; 12+ messages in thread From: Alex Deucher @ 2018-05-16 15:51 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Wed, May 16, 2018 at 8:53 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 11 ++ > drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 183 ++++++++++++++++++++++++++++++-- > 3 files changed, 187 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h > index 2fd7db8..181e6af 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h > @@ -45,6 +45,17 @@ > #define VCN_ENC_CMD_REG_WRITE 0x0000000b > #define VCN_ENC_CMD_REG_WAIT 0x0000000c > > +enum engine_status_constants { > + UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, > + UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, > + UVD_STATUS__UVD_BUSY = 0x00000004, > + GB_ADDR_CONFIG_DEFAULT = 0x26010011, > + UVD_STATUS__IDLE = 0x2, > + UVD_STATUS__BUSY = 0x5, > + UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, > + UVD_STATUS__RBC_BUSY = 0x1, > +}; > + > struct amdgpu_vcn { > struct amdgpu_bo *vcpu_bo; > void *cpu_addr; > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c > index 485cb43..9a7a85d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > @@ -713,7 +713,8 @@ static int soc15_common_early_init(void *handle) > AMD_CG_SUPPORT_SDMA_MGCG | > AMD_CG_SUPPORT_SDMA_LS | > AMD_CG_SUPPORT_VCN_MGCG; > - adev->pg_flags = AMD_PG_SUPPORT_SDMA; > + > + adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; > Make this a separate patch. Split out the setting of the flag to enable this from the implementation. > if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) > adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index 9e0a2b1..89a9477 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -146,10 +146,6 @@ static int vcn_v1_0_hw_init(void *handle) > struct amdgpu_ring *ring = &adev->vcn.ring_dec; > int i, r; > > - r = vcn_v1_0_start(adev); > - if (r) > - goto done; > - > ring->ready = true; > r = amdgpu_ring_test_ring(ring); > if (r) { > @@ -480,6 +476,117 @@ static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) > WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); > } > > +static int vcn_wait_on_reg_read(struct amdgpu_device *adev, uint32_t segment_index, > + uint32_t reg, uint32_t expected_value, > + uint32_t mask) > +{ > + uint32_t loop, data; > + > + data = RREG32(adev->reg_offset[VCN_HWIP][0][segment_index] + reg); > + > + loop = 1000; > + > + while ((data & mask) != expected_value) { > + udelay(10); > + data = RREG32(adev->reg_offset[VCN_HWIP][0][segment_index] + reg); > + loop--; > + if (!loop) > + return -ETIMEDOUT; > + } > + > + return 0; > +} Might be nice to wrap this with a macro so we can do something like: WAIT_REG_SOC15((reg), (val), (mask)) rather than having to pass the segment_index directly. No big deal either way. > + > +static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) > +{ > + uint32_t data = 0; > + > + if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { > + data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); > + > + WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); > + vcn_wait_on_reg_read(adev, mmUVD_PGFSM_STATUS_BASE_IDX, mmUVD_PGFSM_STATUS, > + UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); > + } else { > + data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT > + | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); > + WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); > + vcn_wait_on_reg_read(adev, mmUVD_PGFSM_STATUS_BASE_IDX, mmUVD_PGFSM_STATUS, > + 0, 0xFFFFFFFF); > + } > + > + /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ > + > + data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); > + data &= ~0x103; > + if (adev->pg_flags & AMD_PG_SUPPORT_VCN) > + data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; > + > + WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); > +} > + > +static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) > +{ > + uint32_t data = 0; > + > + if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { > + /* Before power off, this indicator has to be turned on */ > + data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); > + data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; > + data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; > + WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); > + > + > + data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT > + | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); > + > + WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); > + > + > + data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT > + | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); > + vcn_wait_on_reg_read(adev, mmUVD_PGFSM_STATUS_BASE_IDX, > + mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); > + } > +} > + > /** > * vcn_v1_0_start - start VCN block > * > @@ -499,6 +606,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev) > > vcn_v1_0_mc_resume(adev); > > + vcn_1_0_disable_static_power_gating(adev); > /* disable clock gating */ > vcn_v1_0_disable_clock_gating(adev); > > @@ -681,15 +789,46 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev) > ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); > > /* enable clock gating */ > - vcn_v1_0_enable_clock_gating(adev); > > + vcn_v1_0_enable_clock_gating(adev); > + vcn_1_0_enable_static_power_gating(adev); > return 0; > } > > + > +bool vcn_v1_0_is_idle(void *handle) > +{ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + > + return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); > +} > + > +int vcn_v1_0_wait_for_idle(void *handle) > +{ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + > + vcn_wait_on_reg_read(adev, mmUVD_STATUS_BASE_IDX, mmUVD_STATUS, > + 0x2, 0x2); > + return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2); > +} > + > static int vcn_v1_0_set_clockgating_state(void *handle, > enum amd_clockgating_state state) > { > - /* needed for driver unload*/ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; > + > + if (enable) { > + /* wait for STATUS to clear */ > + if (vcn_v1_0_is_idle(handle)) > + return -EBUSY; > + vcn_v1_0_enable_clock_gating(adev); > + /* enable HW gates because UVD is idle */ > +/* uvd_v6_0_set_hw_clock_gating(adev); */ > + } else { > + /* disable HW gating and enable Sw gating */ > + vcn_v1_0_disable_clock_gating(adev); > + } > return 0; > } > > @@ -1058,6 +1197,32 @@ static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) > > } > > +static int vcn_v1_0_set_powergating_state(void *handle, > + enum amd_powergating_state state) > +{ > + /* This doesn't actually powergate the VCN block. > + * That's done in the dpm code via the SMC. This > + * just re-inits the block as necessary. The actual > + * gating still happens in the dpm code. We should > + * revisit this when there is a cleaner line between > + * the smc and the hw blocks > + */ > + struct amdgpu_device *adev = (struct amdgpu_device *)handle; > + int ret = 0; > + > + //WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); > + drop this debugging leftover? > + if (state == AMD_PG_STATE_GATE) { > + vcn_v1_0_stop(adev); > + } else { > + ret = vcn_v1_0_start(adev); > + if (ret) > + goto out; > + } > + > +out: > + return ret; > +} > > static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { > .name = "vcn_v1_0", > @@ -1069,14 +1234,14 @@ static void vcn_v1_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) > .hw_fini = vcn_v1_0_hw_fini, > .suspend = vcn_v1_0_suspend, > .resume = vcn_v1_0_resume, > - .is_idle = NULL /* vcn_v1_0_is_idle */, > - .wait_for_idle = NULL /* vcn_v1_0_wait_for_idle */, > + .is_idle = vcn_v1_0_is_idle, > + .wait_for_idle = vcn_v1_0_wait_for_idle, > .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, > .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, > .soft_reset = NULL /* vcn_v1_0_soft_reset */, > .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, > .set_clockgating_state = vcn_v1_0_set_clockgating_state, > - .set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */, > + .set_powergating_state = vcn_v1_0_set_powergating_state, > }; > > static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/6] drm/amdgpu: skip CG for VCN when late_init/fini [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> ` (4 preceding siblings ...) 2018-05-16 12:53 ` [PATCH 6/6] drm/amdgpu: Enable static pg feature " Rex Zhu @ 2018-05-16 15:54 ` Alex Deucher 5 siblings, 0 replies; 12+ messages in thread From: Alex Deucher @ 2018-05-16 15:54 UTC (permalink / raw) To: Rex Zhu; +Cc: amd-gfx list On Wed, May 16, 2018 at 8:52 AM, Rex Zhu <Rex.Zhu@amd.com> wrote: > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Please add a patch description. E.g., something like: VCN clockgating is handled manually like VCE and UVD. With that fixed: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index fcd4bb2..25bee46 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1718,6 +1718,7 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev) > /* skip CG for VCE/UVD, it's handled specially */ > if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && > adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && > + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && > adev->ip_blocks[i].version->funcs->set_clockgating_state) { > /* enable clockgating to save power */ > r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, > @@ -1817,6 +1818,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) > > if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && > adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && > + adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && > adev->ip_blocks[i].version->funcs->set_clockgating_state) { > /* ungate blocks before hw fini so that we can shutdown the blocks safely */ > r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev, > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-05-16 15:55 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-05-16 12:52 [PATCH 1/6] drm/amdgpu: skip CG for VCN when late_init/fini Rex Zhu [not found] ` <1526475182-32156-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 12:52 ` [PATCH 2/6] drm/amd/pp: Add smu support for vcn cg/pg on RV Rex Zhu [not found] ` <1526475182-32156-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 15:55 ` Alex Deucher 2018-05-16 12:52 ` [PATCH 3/6] drm/amdgpu: Add CG/PG flags for VCN Rex Zhu [not found] ` <1526475182-32156-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 15:55 ` Alex Deucher 2018-05-16 12:53 ` [PATCH 4/6] drm/amdgpu: Add runtime vcn cg/pg enablement Rex Zhu [not found] ` <1526475182-32156-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 15:53 ` Alex Deucher 2018-05-16 12:53 ` [PATCH 5/6] drm/amdgpu: Enable static cg for vcn on RV Rex Zhu [not found] ` <1526475182-32156-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 15:45 ` Alex Deucher 2018-05-16 12:53 ` [PATCH 6/6] drm/amdgpu: Enable static pg feature " Rex Zhu [not found] ` <1526475182-32156-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2018-05-16 15:51 ` Alex Deucher 2018-05-16 15:54 ` [PATCH 1/6] drm/amdgpu: skip CG for VCN when late_init/fini Alex Deucher
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