[PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Evan Quan]

Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ac46eabe3bcd..65cc30766658 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 		dst_ptr = adev->gfx.rlc.cs_ptr;
 		gfx_v9_0_get_csb_buffer(adev, dst_ptr);
 		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
 	}
 
@@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
 	return 0;
 }
 
+static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
+{
+	uint64_t gpu_addr;
+	int r;
+
+	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+	if (unlikely(r != 0))
+		return r;
+
+	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+			AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
+	if (!r)
+		adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
+
+	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+
+	return r;
+}
+
+static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
+{
+	int r;
+
+	if (!adev->gfx.rlc.clear_state_obj)
+		return;
+
+	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+	if (likely(r == 0)) {
+		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+	}
+}
+
 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 {
 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
 
 	gfx_v9_0_gpu_init(adev);
 
+	r = gfx_v9_0_csb_vram_pin(adev);
+	if (r)
+		return r;
+
 	r = gfx_v9_0_rlc_resume(adev);
 	if (r)
 		return r;
@@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
 	gfx_v9_0_cp_enable(adev, false);
 	gfx_v9_0_rlc_stop(adev);
 
+	gfx_v9_0_csb_vram_unpin(adev);
+
 	return 0;
 }
 
-- 
2.18.0

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[PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and pg status

[Evan Quan]

CSIB init has no relation with rlc version and pg status. It should be
needed regardless of them.

Change-Id: Iccd12e1015f41c7e2bc3fe02472dc979015514d4
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 65cc30766658..2f6ac255203f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2182,6 +2182,8 @@ static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
 
 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 {
+	gfx_v9_0_init_csb(adev);
+
 	if (!adev->gfx.rlc.is_rlc_v2_1)
 		return;
 
@@ -2191,7 +2193,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 			      AMD_PG_SUPPORT_CP |
 			      AMD_PG_SUPPORT_GDS |
 			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
-		gfx_v9_0_init_csb(adev);
 		gfx_v9_1_init_rlc_save_restore_list(adev);
 		gfx_v9_0_enable_save_restore_machine(adev);
 
-- 
2.18.0

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RE: [PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and pg status

[Quan, Evan]

Ping..

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Thursday, July 05, 2018 5:09 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and
> pg status
> 
> CSIB init has no relation with rlc version and pg status. It should be needed
> regardless of them.
> 
> Change-Id: Iccd12e1015f41c7e2bc3fe02472dc979015514d4
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 65cc30766658..2f6ac255203f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2182,6 +2182,8 @@ static void
> gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device
> *ad
> 
>  static void gfx_v9_0_init_pg(struct amdgpu_device *adev)  {
> +	gfx_v9_0_init_csb(adev);
> +
>  	if (!adev->gfx.rlc.is_rlc_v2_1)
>  		return;
> 
> @@ -2191,7 +2193,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device
> *adev)
>  			      AMD_PG_SUPPORT_CP |
>  			      AMD_PG_SUPPORT_GDS |
>  			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
> -		gfx_v9_0_init_csb(adev);
>  		gfx_v9_1_init_rlc_save_restore_list(adev);
>  		gfx_v9_0_enable_save_restore_machine(adev);
> 
> --
> 2.18.0

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Re: [PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and pg status

[Alex Deucher]

On Sun, Jul 8, 2018 at 11:56 PM, Quan, Evan <Evan.Quan@amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan@amd.com]
>> Sent: Thursday, July 05, 2018 5:09 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan@amd.com>
>> Subject: [PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and
>> pg status
>>
>> CSIB init has no relation with rlc version and pg status. It should be needed
>> regardless of them.
>>
>> Change-Id: Iccd12e1015f41c7e2bc3fe02472dc979015514d4
>> Signed-off-by: Evan Quan <evan.quan@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 65cc30766658..2f6ac255203f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -2182,6 +2182,8 @@ static void
>> gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device
>> *ad
>>
>>  static void gfx_v9_0_init_pg(struct amdgpu_device *adev)  {
>> +     gfx_v9_0_init_csb(adev);
>> +
>>       if (!adev->gfx.rlc.is_rlc_v2_1)
>>               return;
>>
>> @@ -2191,7 +2193,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device
>> *adev)
>>                             AMD_PG_SUPPORT_CP |
>>                             AMD_PG_SUPPORT_GDS |
>>                             AMD_PG_SUPPORT_RLC_SMU_HS)) {
>> -             gfx_v9_0_init_csb(adev);
>>               gfx_v9_1_init_rlc_save_restore_list(adev);
>>               gfx_v9_0_enable_save_restore_machine(adev);
>>
>> --
>> 2.18.0
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Evan Quan]

It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc
save restore is also needed. And pg support is definitely not a
must for rlc save restore.

Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2f6ac255203f..8d895afa6c69 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 {
 	gfx_v9_0_init_csb(adev);
 
-	if (!adev->gfx.rlc.is_rlc_v2_1)
-		return;
+	/* init rlc save restore as long as the lists exist */
+	if (adev->gfx.rlc.reg_list_format_size_bytes &&
+	    adev->gfx.rlc.reg_list_size_bytes &&
+	    adev->gfx.rlc.reg_restore_list_size) {
+		gfx_v9_1_init_rlc_save_restore_list(adev);
+		gfx_v9_0_enable_save_restore_machine(adev);
+	}
 
 	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
 			      AMD_PG_SUPPORT_GFX_SMG |
@@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 			      AMD_PG_SUPPORT_CP |
 			      AMD_PG_SUPPORT_GDS |
 			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
-		gfx_v9_1_init_rlc_save_restore_list(adev);
-		gfx_v9_0_enable_save_restore_machine(adev);
-
 		WREG32(mmRLC_JUMP_TABLE_RESTORE,
 		       adev->gfx.rlc.cp_table_gpu_addr >> 8);
 		gfx_v9_0_init_gfx_power_gating(adev);
-- 
2.18.0

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Re: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:28PM +0800, Evan Quan wrote:
> It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc
> save restore is also needed. And pg support is definitely not a
> must for rlc save restore.
> 
> Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2f6ac255203f..8d895afa6c69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
>  {
>  	gfx_v9_0_init_csb(adev);
>  
> -	if (!adev->gfx.rlc.is_rlc_v2_1)
> -		return;
> +	/* init rlc save restore as long as the lists exist */

Is there any case if the save restore list not exist?
As far as I know, it should be always existed.

Thanks,
Ray

> +	if (adev->gfx.rlc.reg_list_format_size_bytes &&
> +	    adev->gfx.rlc.reg_list_size_bytes &&
> +	    adev->gfx.rlc.reg_restore_list_size) {
> +		gfx_v9_1_init_rlc_save_restore_list(adev);
> +		gfx_v9_0_enable_save_restore_machine(adev);
> +	}
>  
>  	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
>  			      AMD_PG_SUPPORT_GFX_SMG |
> @@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
>  			      AMD_PG_SUPPORT_CP |
>  			      AMD_PG_SUPPORT_GDS |
>  			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
> -		gfx_v9_1_init_rlc_save_restore_list(adev);
> -		gfx_v9_0_enable_save_restore_machine(adev);
> -
>  		WREG32(mmRLC_JUMP_TABLE_RESTORE,
>  		       adev->gfx.rlc.cp_table_gpu_addr >> 8);
>  		gfx_v9_0_init_gfx_power_gating(adev);
> -- 
> 2.18.0
> 
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RE: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Quan, Evan]

For vega10, the rlc save & restore list is still not imported yet.

Regards,
Evan
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Huang Rui
> Sent: Thursday, July 05, 2018 11:19 PM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the
> lists exist
> 
> On Thu, Jul 05, 2018 at 05:09:28PM +0800, Evan Quan wrote:
> > It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc save
> > restore is also needed. And pg support is definitely not a must for
> > rlc save restore.
> >
> > Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++-----
> >  1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 2f6ac255203f..8d895afa6c69 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct
> > amdgpu_device *adev)  {
> >  	gfx_v9_0_init_csb(adev);
> >
> > -	if (!adev->gfx.rlc.is_rlc_v2_1)
> > -		return;
> > +	/* init rlc save restore as long as the lists exist */
> 
> Is there any case if the save restore list not exist?
> As far as I know, it should be always existed.
> 
> Thanks,
> Ray
> 
> > +	if (adev->gfx.rlc.reg_list_format_size_bytes &&
> > +	    adev->gfx.rlc.reg_list_size_bytes &&
> > +	    adev->gfx.rlc.reg_restore_list_size) {
> > +		gfx_v9_1_init_rlc_save_restore_list(adev);
> > +		gfx_v9_0_enable_save_restore_machine(adev);
> > +	}
> >
> >  	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
> >  			      AMD_PG_SUPPORT_GFX_SMG |
> > @@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct
> amdgpu_device *adev)
> >  			      AMD_PG_SUPPORT_CP |
> >  			      AMD_PG_SUPPORT_GDS |
> >  			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
> > -		gfx_v9_1_init_rlc_save_restore_list(adev);
> > -		gfx_v9_0_enable_save_restore_machine(adev);
> > -
> >  		WREG32(mmRLC_JUMP_TABLE_RESTORE,
> >  		       adev->gfx.rlc.cp_table_gpu_addr >> 8);
> >  		gfx_v9_0_init_gfx_power_gating(adev);
> > --
> > 2.18.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:28PM +0800, Evan Quan wrote:
> It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc
> save restore is also needed. And pg support is definitely not a
> must for rlc save restore.
> 
> Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++-----
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2f6ac255203f..8d895afa6c69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
>  {
>  	gfx_v9_0_init_csb(adev);
>  
> -	if (!adev->gfx.rlc.is_rlc_v2_1)
> -		return;

Furthermore, as talked with you, we can continue using
"adev->gfx.rlc.is_rlc_v2_1" rlc firmware header version to check if the
current asic and ucode supported gfxoff, you know, we have to support
legacy ucode even the driver codes are updated.

Thanks,
Ray

> +	/* init rlc save restore as long as the lists exist */
> +	if (adev->gfx.rlc.reg_list_format_size_bytes &&
> +	    adev->gfx.rlc.reg_list_size_bytes &&
> +	    adev->gfx.rlc.reg_restore_list_size) {
> +		gfx_v9_1_init_rlc_save_restore_list(adev);
> +		gfx_v9_0_enable_save_restore_machine(adev);
> +	}
>  
>  	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
>  			      AMD_PG_SUPPORT_GFX_SMG |
> @@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
>  			      AMD_PG_SUPPORT_CP |
>  			      AMD_PG_SUPPORT_GDS |
>  			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
> -		gfx_v9_1_init_rlc_save_restore_list(adev);
> -		gfx_v9_0_enable_save_restore_machine(adev);
> -
>  		WREG32(mmRLC_JUMP_TABLE_RESTORE,
>  		       adev->gfx.rlc.cp_table_gpu_addr >> 8);
>  		gfx_v9_0_init_gfx_power_gating(adev);
> -- 
> 2.18.0
> 
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RE: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Quan, Evan]

Hi Ray,

After reconsideration, I think for the rlc save restore related, there are the following issues:
1. To use adev->gfx.rlc.reg_list_format_direct_reg_list_length or GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH?
->  "reg_list_format_direct_reg_list_length" is new introduced by rlc v2_1. 
To back compatible with asics(vega12,vega20 and vega10) with rlc v2_0,  i will suggest to use GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH directly.

2. Do we need to consider the gfxoff enable/disable message + old rlc fw case?
Per my observatrion and tests, there will be no harms for such case.
Since gfxoff will actually not take effect if the rlc fw is not ready. So, we do not need to consider back compatibility here.

Conclude all, I do not think we need to update vega12 rlc from v2_0 to v2_1. The below comparations can guard we do not break old vega12 rlc fws.
+	if (adev->gfx.rlc.reg_list_format_size_bytes &&
+	    adev->gfx.rlc.reg_list_size_bytes &&
+	    adev->gfx.rlc.reg_restore_list_size) {

Regards,
Evan
> -----Original Message-----
> From: Huang Rui [mailto:ray.huang@amd.com]
> Sent: Friday, July 06, 2018 6:15 PM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the
> lists exist
> 
> On Thu, Jul 05, 2018 at 05:09:28PM +0800, Evan Quan wrote:
> > It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc save
> > restore is also needed. And pg support is definitely not a must for
> > rlc save restore.
> >
> > Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++++++-----
> >  1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 2f6ac255203f..8d895afa6c69 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct
> > amdgpu_device *adev)  {
> >  	gfx_v9_0_init_csb(adev);
> >
> > -	if (!adev->gfx.rlc.is_rlc_v2_1)
> > -		return;
> 
> Furthermore, as talked with you, we can continue using "adev-
> >gfx.rlc.is_rlc_v2_1" rlc firmware header version to check if the current asic
> and ucode supported gfxoff, you know, we have to support legacy ucode
> even the driver codes are updated.
> 
> Thanks,
> Ray
> 
> > +	/* init rlc save restore as long as the lists exist */
> > +	if (adev->gfx.rlc.reg_list_format_size_bytes &&
> > +	    adev->gfx.rlc.reg_list_size_bytes &&
> > +	    adev->gfx.rlc.reg_restore_list_size) {
> > +		gfx_v9_1_init_rlc_save_restore_list(adev);
> > +		gfx_v9_0_enable_save_restore_machine(adev);
> > +	}
> >
> >  	if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
> >  			      AMD_PG_SUPPORT_GFX_SMG |
> > @@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct
> amdgpu_device *adev)
> >  			      AMD_PG_SUPPORT_CP |
> >  			      AMD_PG_SUPPORT_GDS |
> >  			      AMD_PG_SUPPORT_RLC_SMU_HS)) {
> > -		gfx_v9_1_init_rlc_save_restore_list(adev);
> > -		gfx_v9_0_enable_save_restore_machine(adev);
> > -
> >  		WREG32(mmRLC_JUMP_TABLE_RESTORE,
> >  		       adev->gfx.rlc.cp_table_gpu_addr >> 8);
> >  		gfx_v9_0_init_gfx_power_gating(adev);
> > --
> > 2.18.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

[Evan Quan]

For v2_0 rlc, rlc save restore list also needs to be initialized.
However, there is no reg_list_format_direct_reg_list_length
member(v2_1 spefic) for it.

Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8d895afa6c69..8d870d4f8414 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -42,6 +42,7 @@
 #define GFX9_MEC_HPD_SIZE 2048
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
+#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
 
 #define mmPWR_MISC_CNTL_STATUS					0x0183
 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0
@@ -1927,7 +1928,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
 	/* setup unique_indirect_regs array and indirect_start_offsets array */
 	unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
 	gfx_v9_1_parse_ind_reg_list(register_list_format,
-				    adev->gfx.rlc.reg_list_format_direct_reg_list_length,
+				    GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
 				    adev->gfx.rlc.reg_list_format_size_bytes >> 2,
 				    unique_indirect_regs,
 				    unique_indirect_reg_count,
@@ -1952,7 +1953,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
 		adev->gfx.rlc.reg_list_format_start);
 
 	/* direct register portion */
-	for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
+	for (i = 0; i < GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH; i++)
 		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
 			register_list_format[i]);
 
-- 
2.18.0

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Re: [PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:29PM +0800, Evan Quan wrote:
> For v2_0 rlc, rlc save restore list also needs to be initialized.
> However, there is no reg_list_format_direct_reg_list_length
> member(v2_1 spefic) for it.
> 
> Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d895afa6c69..8d870d4f8414 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -42,6 +42,7 @@
>  #define GFX9_MEC_HPD_SIZE 2048
>  #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
>  #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
> +#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
>  
>  #define mmPWR_MISC_CNTL_STATUS					0x0183
>  #define mmPWR_MISC_CNTL_STATUS_BASE_IDX				0
> @@ -1927,7 +1928,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
>  	/* setup unique_indirect_regs array and indirect_start_offsets array */
>  	unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
>  	gfx_v9_1_parse_ind_reg_list(register_list_format,
> -				    adev->gfx.rlc.reg_list_format_direct_reg_list_length,
> +				    GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
>  				    adev->gfx.rlc.reg_list_format_size_bytes >> 2,
>  				    unique_indirect_regs,
>  				    unique_indirect_reg_count,
> @@ -1952,7 +1953,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
>  		adev->gfx.rlc.reg_list_format_start);
>  
>  	/* direct register portion */
> -	for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
> +	for (i = 0; i < GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH; i++)

This definition is actually defined on register_list_format.h in the ucode.
So we would better to put it in firmware header.

Thanks,
Ray

>  		WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
>  			register_list_format[i]);
>  
> -- 
> 2.18.0
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

[Quan, Evan]

As discussed  for patch3, reg_list_format_direct_reg_list_length is newly introduced by rlc v2_1.
For ASICs(vega10/12/20) with rlc v2_0, it's not a good idea to use reg_list_format_direct_reg_list_length.

Regards,
Evan
> -----Original Message-----
> From: Huang Rui [mailto:ray.huang@amd.com]
> Sent: Thursday, July 05, 2018 11:07 PM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 04/10] drm/amdgpu: correct direct reg list length for
> v2_0 rlc
> 
> On Thu, Jul 05, 2018 at 05:09:29PM +0800, Evan Quan wrote:
> > For v2_0 rlc, rlc save restore list also needs to be initialized.
> > However, there is no reg_list_format_direct_reg_list_length
> > member(v2_1 spefic) for it.
> >
> > Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 8d895afa6c69..8d870d4f8414 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -42,6 +42,7 @@
> >  #define GFX9_MEC_HPD_SIZE 2048
> >  #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L  #define
> > RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
> > +#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
> >
> >  #define mmPWR_MISC_CNTL_STATUS
> 	0x0183
> >  #define mmPWR_MISC_CNTL_STATUS_BASE_IDX
> 	0
> > @@ -1927,7 +1928,7 @@ static int
> gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
> >  	/* setup unique_indirect_regs array and indirect_start_offsets array
> */
> >  	unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
> >  	gfx_v9_1_parse_ind_reg_list(register_list_format,
> > -				    adev-
> >gfx.rlc.reg_list_format_direct_reg_list_length,
> > +
> GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
> >  				    adev->gfx.rlc.reg_list_format_size_bytes >>
> 2,
> >  				    unique_indirect_regs,
> >  				    unique_indirect_reg_count,
> > @@ -1952,7 +1953,7 @@ static int
> gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
> >  		adev->gfx.rlc.reg_list_format_start);
> >
> >  	/* direct register portion */
> > -	for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
> > +	for (i = 0; i < GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH; i++)
> 
> This definition is actually defined on register_list_format.h in the ucode.
> So we would better to put it in firmware header.
> 
> Thanks,
> Ray
> 
> >  		WREG32(SOC15_REG_OFFSET(GC, 0,
> mmRLC_GPM_SCRATCH_DATA),
> >  			register_list_format[i]);
> >
> > --
> > 2.18.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Evan Quan]

This may break gfxoff support since this register will
be set by smc fw(for vega12, that's the case).

Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8d870d4f8414..3a75641a071d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
 	/* disable CG */
 	WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
 
-	/* disable PG */
-	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
-
 	gfx_v9_0_rlc_reset(adev);
 
 	gfx_v9_0_init_pg(adev);
-- 
2.18.0

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Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:30PM +0800, Evan Quan wrote:
> This may break gfxoff support since this register will
> be set by smc fw(for vega12, that's the case).
> 
> Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d870d4f8414..3a75641a071d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
>  	/* disable CG */
>  	WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
>  
> -	/* disable PG */
> -	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
> -
>  	gfx_v9_0_rlc_reset(adev);
>  
>  	gfx_v9_0_init_pg(adev);
> -- 
> 2.18.0
> 
> _______________________________________________
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Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Alex Deucher]

On Thu, Jul 5, 2018 at 5:09 AM, Evan Quan <evan.quan@amd.com> wrote:
> This may break gfxoff support since this register will
> be set by smc fw(for vega12, that's the case).
>

It took me a second to understand what you meant here.  Might be
worthwhile to clarify with something like:
SMU owns this register so the driver should not set it to avoid breaking gfxoff.

With that fixed up:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Alex

> Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d870d4f8414..3a75641a071d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
>         /* disable CG */
>         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
>
> -       /* disable PG */
> -       WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
> -
>         gfx_v9_0_rlc_reset(adev);
>
>         gfx_v9_0_init_pg(adev);
> --
> 2.18.0
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Huang Rui]

On Thu, Jul 05, 2018 at 11:33:52AM -0400, Alex Deucher wrote:
> On Thu, Jul 5, 2018 at 5:09 AM, Evan Quan <evan.quan@amd.com> wrote:
> > This may break gfxoff support since this register will
> > be set by smc fw(for vega12, that's the case).
> >
> 
> It took me a second to understand what you meant here.  Might be
> worthwhile to clarify with something like:
> SMU owns this register so the driver should not set it to avoid breaking gfxoff.
> 

Agree. Actually, it cleared Ultra_Low_Voltage_Enable bit of mmRLC_PG_CNTL,
that caused gfxoff break before. We should have explained clearly here. :-)

Thanks,
Ray

> With that fixed up:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> 
> Alex
> 
> > Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
> > Signed-off-by: Evan Quan <evan.quan@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
> >  1 file changed, 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 8d870d4f8414..3a75641a071d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
> >         /* disable CG */
> >         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
> >
> > -       /* disable PG */
> > -       WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
> > -
> >         gfx_v9_0_rlc_reset(adev);
> >
> >         gfx_v9_0_init_pg(adev);
> > --
> > 2.18.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
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[PATCH 06/10] drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

[Evan Quan]

On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.

Change-Id: I9042a8c89db16f220da5a589264937b51870c187
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3a75641a071d..ee537423af11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3551,8 +3551,11 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
-		data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
-			  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+
+		if (adev->asic_type != CHIP_VEGA12)
+			data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
+
+		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
 
@@ -3582,11 +3585,15 @@ static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
 	} else {
 		/* 1 - MGCG_OVERRIDE */
 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
-		data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
-			 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
+
+		if (adev->asic_type != CHIP_VEGA12)
+			data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
+
+		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
+
 		if (def != data)
 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 
-- 
2.18.0

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RE: [PATCH 06/10] drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

[Quan, Evan]

Ping..

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Thursday, July 05, 2018 5:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 06/10] drm/amdgpu: no touch for the reserved bit of
> RLC_CGTT_MGCG_OVERRIDE
> 
> On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.
> 
> Change-Id: I9042a8c89db16f220da5a589264937b51870c187
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++++++++----
>  1 file changed, 11 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 3a75641a071d..ee537423af11 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3551,8 +3551,11 @@ static void
> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>  	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
>  		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
>  		def = data = RREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE);
> -		data &=
> ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
> -
> RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
> +
> +		if (adev->asic_type != CHIP_VEGA12)
> +			data &=
> ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
> +
> +		data &=
> ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
> 
> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
> 
> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
> 
> @@ -3582,11 +3585,15 @@ static void
> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>  	} else {
>  		/* 1 - MGCG_OVERRIDE */
>  		def = data = RREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE);
> -		data |=
> (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
> -
> RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
> +
> +		if (adev->asic_type != CHIP_VEGA12)
> +			data |=
> RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
> +
> +		data |=
> (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
> 
> RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
> 
> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
> 
> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
> +
>  		if (def != data)
>  			WREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE, data);
> 
> --
> 2.18.0

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Re: [PATCH 06/10] drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

[Alex Deucher]

On Mon, Jul 9, 2018 at 12:06 AM, Quan, Evan <Evan.Quan@amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan@amd.com]
>> Sent: Thursday, July 05, 2018 5:10 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan@amd.com>
>> Subject: [PATCH 06/10] drm/amdgpu: no touch for the reserved bit of
>> RLC_CGTT_MGCG_OVERRIDE
>>
>> On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.
>>
>> Change-Id: I9042a8c89db16f220da5a589264937b51870c187
>> Signed-off-by: Evan Quan <evan.quan@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++++++++++----
>>  1 file changed, 11 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 3a75641a071d..ee537423af11 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3551,8 +3551,11 @@ static void
>> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>>       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
>>               /* 1 - RLC_CGTT_MGCG_OVERRIDE */
>>               def = data = RREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE);
>> -             data &=
>> ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
>> -
>> RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>> +
>> +             if (adev->asic_type != CHIP_VEGA12)
>> +                     data &=
>> ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>> +
>> +             data &=
>> ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
>>
>> @@ -3582,11 +3585,15 @@ static void
>> gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
>>       } else {
>>               /* 1 - MGCG_OVERRIDE */
>>               def = data = RREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE);
>> -             data |=
>> (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
>> -
>> RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
>> +
>> +             if (adev->asic_type != CHIP_VEGA12)
>> +                     data |=
>> RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
>> +
>> +             data |=
>> (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
>>
>> RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
>> +
>>               if (def != data)
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE, data);
>>
>> --
>> 2.18.0
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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[PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

[Evan Quan]

Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
change will help to enable gfxoff feature more frequently.

Change-Id: I021577e331b7beb19796bd6f5465b867f6038974
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ee537423af11..cb7f2efa9882 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3629,9 +3629,11 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
 		/* update CGCG and CGLS override bits */
 		if (def != data)
 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
-		/* enable 3Dcgcg FSM(0x0020003f) */
+
+		/* enable 3Dcgcg FSM(0x0000363f) */
 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
-		data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+
+		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
 			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
@@ -3678,9 +3680,10 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 		if (def != data)
 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 
-		/* enable cgcg FSM(0x0020003F) */
+		/* enable cgcg FSM(0x0000363F) */
 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
-		data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+
+		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
 			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
-- 
2.18.0

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RE: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

[Quan, Evan]

Ping..

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Thursday, July 05, 2018 5:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to
> wait before request CGCG
> 
> Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
> change will help to enable gfxoff feature more frequently.
> 
> Change-Id: I021577e331b7beb19796bd6f5465b867f6038974
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ee537423af11..cb7f2efa9882 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3629,9 +3629,11 @@ static void
> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
>  		/* update CGCG and CGLS override bits */
>  		if (def != data)
>  			WREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE, data);
> -		/* enable 3Dcgcg FSM(0x0020003f) */
> +
> +		/* enable 3Dcgcg FSM(0x0000363f) */
>  		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> -		data = (0x2000 <<
> RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +
> +		data = (0x36 <<
> +RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>  			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
>  			data |= (0x000F <<
> RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> @@ -3678,9 +3680,10 @@ static void
> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>  		if (def != data)
>  			WREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE, data);
> 
> -		/* enable cgcg FSM(0x0020003F) */
> +		/* enable cgcg FSM(0x0000363F) */
>  		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> -		data = (0x2000 <<
> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +
> +		data = (0x36 <<
> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>  			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>  			data |= (0x000F <<
> RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> --
> 2.18.0

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Re: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

[Alex Deucher]

On Mon, Jul 9, 2018 at 12:06 AM, Quan, Evan <Evan.Quan@amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan@amd.com]
>> Sent: Thursday, July 05, 2018 5:10 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan@amd.com>
>> Subject: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to
>> wait before request CGCG
>>
>> Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
>> change will help to enable gfxoff feature more frequently.


I assume this is ok for RV gfxoff as well?  if so:
Acked-by: Alex Deucher <alexander.deucher@amd.com>



>>
>> Change-Id: I021577e331b7beb19796bd6f5465b867f6038974
>> Signed-off-by: Evan Quan <evan.quan@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++----
>>  1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ee537423af11..cb7f2efa9882 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3629,9 +3629,11 @@ static void
>> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
>>               /* update CGCG and CGLS override bits */
>>               if (def != data)
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE, data);
>> -             /* enable 3Dcgcg FSM(0x0020003f) */
>> +
>> +             /* enable 3Dcgcg FSM(0x0000363f) */
>>               def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
>> -             data = (0x2000 <<
>> RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>> +
>> +             data = (0x36 <<
>> +RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>>                       RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
>>               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
>>                       data |= (0x000F <<
>> RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>> @@ -3678,9 +3680,10 @@ static void
>> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>>               if (def != data)
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE, data);
>>
>> -             /* enable cgcg FSM(0x0020003F) */
>> +             /* enable cgcg FSM(0x0000363F) */
>>               def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
>> -             data = (0x2000 <<
>> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>> +
>> +             data = (0x36 <<
>> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
>>                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>>               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>>                       data |= (0x000F <<
>> RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>> --
>> 2.18.0
>
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RE: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

[Quan, Evan]

Yes, Rv gfxoff is not affected.

Regards,
Evan
> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Wednesday, July 11, 2018 1:20 AM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has
> to wait before request CGCG
> 
> On Mon, Jul 9, 2018 at 12:06 AM, Quan, Evan <Evan.Quan@amd.com> wrote:
> > Ping..
> >
> >> -----Original Message-----
> >> From: Evan Quan [mailto:evan.quan@amd.com]
> >> Sent: Thursday, July 05, 2018 5:10 PM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: Quan, Evan <Evan.Quan@amd.com>
> >> Subject: [PATCH 07/10] drm/amdgpu: reduce the idle period that RLC
> >> has to wait before request CGCG
> >>
> >> Gfxoff feature may depends on the CGCG(on vega12, that's the case).
> >> This change will help to enable gfxoff feature more frequently.
> 
> 
> I assume this is ok for RV gfxoff as well?  if so:
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> 
> 
> 
> >>
> >> Change-Id: I021577e331b7beb19796bd6f5465b867f6038974
> >> Signed-off-by: Evan Quan <evan.quan@amd.com>
> >> ---
> >>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++----
> >>  1 file changed, 7 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> index ee537423af11..cb7f2efa9882 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> @@ -3629,9 +3629,11 @@ static void
> >> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> >>               /* update CGCG and CGLS override bits */
> >>               if (def != data)
> >>                       WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE,
> >> data);
> >> -             /* enable 3Dcgcg FSM(0x0020003f) */
> >> +
> >> +             /* enable 3Dcgcg FSM(0x0000363f) */
> >>               def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> >> -             data = (0x2000 <<
> >> RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> >> +
> >> +             data = (0x36 <<
> >> +RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> >>                       RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> >>               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
> >>                       data |= (0x000F <<
> >> RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> @@ -3678,9
> >> +3680,10 @@ static void
> >> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device
> *adev
> >>               if (def != data)
> >>                       WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE,
> >> data);
> >>
> >> -             /* enable cgcg FSM(0x0020003F) */
> >> +             /* enable cgcg FSM(0x0000363F) */
> >>               def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> >> -             data = (0x2000 <<
> >> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> >> +
> >> +             data = (0x36 <<
> >> RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> >>                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> >>               if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
> >>                       data |= (0x000F <<
> >> RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
> >> --
> >> 2.18.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode Apis directly

[Evan Quan]

No need to do double dereference to reach the Apis. They are
accessible directly.

Change-Id: I4b810c5e1981e0810df36a701b20edaf1f6af207
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index cb7f2efa9882..9679bdc0ea2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3618,7 +3618,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
 {
 	uint32_t data, def;
 
-	adev->gfx.rlc.funcs->enter_safe_mode(adev);
+	gfx_v9_0_enter_rlc_safe_mode(adev);
 
 	/* Enable 3D CGCG/CGLS */
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
@@ -3658,7 +3658,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
 	}
 
-	adev->gfx.rlc.funcs->exit_safe_mode(adev);
+	gfx_v9_0_exit_rlc_safe_mode(adev);
 }
 
 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
@@ -3666,7 +3666,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 {
 	uint32_t def, data;
 
-	adev->gfx.rlc.funcs->enter_safe_mode(adev);
+	gfx_v9_0_enter_rlc_safe_mode(adev);
 
 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
@@ -3706,7 +3706,7 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
 	}
 
-	adev->gfx.rlc.funcs->exit_safe_mode(adev);
+	gfx_v9_0_exit_rlc_safe_mode(adev);
 }
 
 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
-- 
2.18.0

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RE: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode Apis directly

[Quan, Evan]

Ping..

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Thursday, July 05, 2018 5:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode
> Apis directly
> 
> No need to do double dereference to reach the Apis. They are accessible
> directly.
> 
> Change-Id: I4b810c5e1981e0810df36a701b20edaf1f6af207
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index cb7f2efa9882..9679bdc0ea2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3618,7 +3618,7 @@ static void
> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,  {
>  	uint32_t data, def;
> 
> -	adev->gfx.rlc.funcs->enter_safe_mode(adev);
> +	gfx_v9_0_enter_rlc_safe_mode(adev);
> 
>  	/* Enable 3D CGCG/CGLS */
>  	if (enable && (adev->cg_flags &
> AMD_CG_SUPPORT_GFX_3D_CGCG)) { @@ -3658,7 +3658,7 @@ static void
> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
>  			WREG32_SOC15(GC, 0,
> mmRLC_CGCG_CGLS_CTRL_3D, data);
>  	}
> 
> -	adev->gfx.rlc.funcs->exit_safe_mode(adev);
> +	gfx_v9_0_exit_rlc_safe_mode(adev);
>  }
> 
>  static void gfx_v9_0_update_coarse_grain_clock_gating(struct
> amdgpu_device *adev, @@ -3666,7 +3666,7 @@ static void
> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev  {
>  	uint32_t def, data;
> 
> -	adev->gfx.rlc.funcs->enter_safe_mode(adev);
> +	gfx_v9_0_enter_rlc_safe_mode(adev);
> 
>  	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
>  		def = data = RREG32_SOC15(GC, 0,
> mmRLC_CGTT_MGCG_OVERRIDE); @@ -3706,7 +3706,7 @@ static void
> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>  			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL,
> data);
>  	}
> 
> -	adev->gfx.rlc.funcs->exit_safe_mode(adev);
> +	gfx_v9_0_exit_rlc_safe_mode(adev);
>  }
> 
>  static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
> --
> 2.18.0

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Re: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode Apis directly

[Alex Deucher]

On Mon, Jul 9, 2018 at 12:08 AM, Quan, Evan <Evan.Quan@amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan@amd.com]
>> Sent: Thursday, July 05, 2018 5:10 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan@amd.com>
>> Subject: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode
>> Apis directly
>>
>> No need to do double dereference to reach the Apis. They are accessible
>> directly.
>>

One advantage of using the callback is that you may end up having
different callbacks for different asics within the gfx9 family.  I
don't know if this will be the case or not.  IIRC, there were
differences between chips on older gfx versions.

Alex

>> Change-Id: I4b810c5e1981e0810df36a701b20edaf1f6af207
>> Signed-off-by: Evan Quan <evan.quan@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index cb7f2efa9882..9679bdc0ea2e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3618,7 +3618,7 @@ static void
>> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,  {
>>       uint32_t data, def;
>>
>> -     adev->gfx.rlc.funcs->enter_safe_mode(adev);
>> +     gfx_v9_0_enter_rlc_safe_mode(adev);
>>
>>       /* Enable 3D CGCG/CGLS */
>>       if (enable && (adev->cg_flags &
>> AMD_CG_SUPPORT_GFX_3D_CGCG)) { @@ -3658,7 +3658,7 @@ static void
>> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
>>                       WREG32_SOC15(GC, 0,
>> mmRLC_CGCG_CGLS_CTRL_3D, data);
>>       }
>>
>> -     adev->gfx.rlc.funcs->exit_safe_mode(adev);
>> +     gfx_v9_0_exit_rlc_safe_mode(adev);
>>  }
>>
>>  static void gfx_v9_0_update_coarse_grain_clock_gating(struct
>> amdgpu_device *adev, @@ -3666,7 +3666,7 @@ static void
>> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev  {
>>       uint32_t def, data;
>>
>> -     adev->gfx.rlc.funcs->enter_safe_mode(adev);
>> +     gfx_v9_0_enter_rlc_safe_mode(adev);
>>
>>       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
>>               def = data = RREG32_SOC15(GC, 0,
>> mmRLC_CGTT_MGCG_OVERRIDE); @@ -3706,7 +3706,7 @@ static void
>> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>>                       WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL,
>> data);
>>       }
>>
>> -     adev->gfx.rlc.funcs->exit_safe_mode(adev);
>> +     gfx_v9_0_exit_rlc_safe_mode(adev);
>>  }
>>
>>  static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
>> --
>> 2.18.0
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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RE: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode Apis directly

[Quan, Evan]

Ok, I will drop this patch.

Regards,
Evan
> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Wednesday, July 11, 2018 1:24 AM
> To: Quan, Evan <Evan.Quan@amd.com>
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe
> mode Apis directly
> 
> On Mon, Jul 9, 2018 at 12:08 AM, Quan, Evan <Evan.Quan@amd.com> wrote:
> > Ping..
> >
> >> -----Original Message-----
> >> From: Evan Quan [mailto:evan.quan@amd.com]
> >> Sent: Thursday, July 05, 2018 5:10 PM
> >> To: amd-gfx@lists.freedesktop.org
> >> Cc: Quan, Evan <Evan.Quan@amd.com>
> >> Subject: [PATCH 08/10] drm/amdgpu: use the accessible target rlc safe
> >> mode Apis directly
> >>
> >> No need to do double dereference to reach the Apis. They are
> >> accessible directly.
> >>
> 
> One advantage of using the callback is that you may end up having different
> callbacks for different asics within the gfx9 family.  I don't know if this will be
> the case or not.  IIRC, there were differences between chips on older gfx
> versions.
> 
> Alex
> 
> >> Change-Id: I4b810c5e1981e0810df36a701b20edaf1f6af207
> >> Signed-off-by: Evan Quan <evan.quan@amd.com>
> >> ---
> >>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----
> >>  1 file changed, 4 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> index cb7f2efa9882..9679bdc0ea2e 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> @@ -3618,7 +3618,7 @@ static void
> >> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,  {
> >>       uint32_t data, def;
> >>
> >> -     adev->gfx.rlc.funcs->enter_safe_mode(adev);
> >> +     gfx_v9_0_enter_rlc_safe_mode(adev);
> >>
> >>       /* Enable 3D CGCG/CGLS */
> >>       if (enable && (adev->cg_flags &
> >> AMD_CG_SUPPORT_GFX_3D_CGCG)) { @@ -3658,7 +3658,7 @@ static
> void
> >> gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
> >>                       WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D,
> >> data);
> >>       }
> >>
> >> -     adev->gfx.rlc.funcs->exit_safe_mode(adev);
> >> +     gfx_v9_0_exit_rlc_safe_mode(adev);
> >>  }
> >>
> >>  static void gfx_v9_0_update_coarse_grain_clock_gating(struct
> >> amdgpu_device *adev, @@ -3666,7 +3666,7 @@ static void
> >> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device
> *adev  {
> >>       uint32_t def, data;
> >>
> >> -     adev->gfx.rlc.funcs->enter_safe_mode(adev);
> >> +     gfx_v9_0_enter_rlc_safe_mode(adev);
> >>
> >>       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> >>               def = data = RREG32_SOC15(GC, 0,
> >> mmRLC_CGTT_MGCG_OVERRIDE); @@ -3706,7 +3706,7 @@ static void
> >> gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device
> *adev
> >>                       WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL,
> >> data);
> >>       }
> >>
> >> -     adev->gfx.rlc.funcs->exit_safe_mode(adev);
> >> +     gfx_v9_0_exit_rlc_safe_mode(adev);
> >>  }
> >>
> >>  static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device
> >> *adev,
> >> --
> >> 2.18.0
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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[PATCH 09/10] drm/amd/powerplay: add vega12 SMU gfxoff support

[Evan Quan]

Export apis for enabling/disabling SMU gfxoff support.

Change-Id: Idcea1db9f3dbe15edda1b76e1ff05435865af2a1
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c    | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 57492878874f..8efa983c41de 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2329,6 +2329,24 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
+{
+	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
+}
+
+static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
+{
+	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
+}
+
+static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+	if (enable)
+		return vega12_enable_gfx_off(hwmgr);
+	else
+		return vega12_disable_gfx_off(hwmgr);
+}
+
 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
 	.backend_init = vega12_hwmgr_backend_init,
 	.backend_fini = vega12_hwmgr_backend_fini,
@@ -2378,6 +2396,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
 	.get_thermal_temperature_range = vega12_get_thermal_temperature_range,
 	.register_irq_handlers = smu9_register_irq_handlers,
 	.start_thermal_controller = vega12_start_thermal_controller,
+	.gfx_off_control = vega12_gfx_off_control,
 };
 
 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
-- 
2.18.0

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Re: [PATCH 09/10] drm/amd/powerplay: add vega12 SMU gfxoff support

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:34PM +0800, Evan Quan wrote:
> Export apis for enabling/disabling SMU gfxoff support.
> 
> Change-Id: Idcea1db9f3dbe15edda1b76e1ff05435865af2a1
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c    | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 57492878874f..8efa983c41de 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -2329,6 +2329,24 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
>  	return 0;
>  }
>  
> +static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
> +{
> +	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
> +}
> +
> +static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
> +{
> +	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
> +}
> +
> +static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
> +{
> +	if (enable)
> +		return vega12_enable_gfx_off(hwmgr);
> +	else
> +		return vega12_disable_gfx_off(hwmgr);
> +}
> +
>  static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
>  	.backend_init = vega12_hwmgr_backend_init,
>  	.backend_fini = vega12_hwmgr_backend_fini,
> @@ -2378,6 +2396,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
>  	.get_thermal_temperature_range = vega12_get_thermal_temperature_range,
>  	.register_irq_handlers = smu9_register_irq_handlers,
>  	.start_thermal_controller = vega12_start_thermal_controller,
> +	.gfx_off_control = vega12_gfx_off_control,
>  };
>  
>  int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
> -- 
> 2.18.0
> 
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[PATCH 10/10] drm/amd/powerplay: no need to mask workable gfxoff feature for vega12

[Evan Quan]

Gfxoff feature for vega12 is workable. So, there is no need to
mask it any more.

Change-Id: I7e4d05c5c0acc2aa2b077eaaaf6f13589c87114b
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 9b675d9bd162..8994aa5c8cf8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -147,10 +147,10 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 		smu7_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_AI:
-		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		switch (hwmgr->chip_id) {
 		case CHIP_VEGA10:
 		case CHIP_VEGA20:
+			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
 			vega10_hwmgr_init(hwmgr);
 			break;
-- 
2.18.0

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RE: [PATCH 10/10] drm/amd/powerplay: no need to mask workable gfxoff feature for vega12

[Quan, Evan]

Ping..

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Thursday, July 05, 2018 5:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan@amd.com>
> Subject: [PATCH 10/10] drm/amd/powerplay: no need to mask workable
> gfxoff feature for vega12
> 
> Gfxoff feature for vega12 is workable. So, there is no need to mask it any
> more.
> 
> Change-Id: I7e4d05c5c0acc2aa2b077eaaaf6f13589c87114b
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 9b675d9bd162..8994aa5c8cf8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -147,10 +147,10 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  		smu7_init_function_pointers(hwmgr);
>  		break;
>  	case AMDGPU_FAMILY_AI:
> -		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  		switch (hwmgr->chip_id) {
>  		case CHIP_VEGA10:
>  		case CHIP_VEGA20:
> +			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  			hwmgr->smumgr_funcs = &vega10_smu_funcs;
>  			vega10_hwmgr_init(hwmgr);
>  			break;
> --
> 2.18.0

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Re: [PATCH 10/10] drm/amd/powerplay: no need to mask workable gfxoff feature for vega12

[Alex Deucher]

On Mon, Jul 9, 2018 at 12:36 AM, Quan, Evan <Evan.Quan@amd.com> wrote:
> Ping..
>
>> -----Original Message-----
>> From: Evan Quan [mailto:evan.quan@amd.com]
>> Sent: Thursday, July 05, 2018 5:10 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Quan, Evan <Evan.Quan@amd.com>
>> Subject: [PATCH 10/10] drm/amd/powerplay: no need to mask workable
>> gfxoff feature for vega12
>>
>> Gfxoff feature for vega12 is workable. So, there is no need to mask it any
>> more.
>>
>> Change-Id: I7e4d05c5c0acc2aa2b077eaaaf6f13589c87114b
>> Signed-off-by: Evan Quan <evan.quan@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index 9b675d9bd162..8994aa5c8cf8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -147,10 +147,10 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>>               smu7_init_function_pointers(hwmgr);
>>               break;
>>       case AMDGPU_FAMILY_AI:
>> -             hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>>               switch (hwmgr->chip_id) {
>>               case CHIP_VEGA10:
>>               case CHIP_VEGA20:
>> +                     hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>>                       hwmgr->smumgr_funcs = &vega10_smu_funcs;
>>                       vega10_hwmgr_init(hwmgr);
>>                       break;
>> --
>> 2.18.0
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote:
> Without this pin, the csb buffer will be filled with inconsistent
> data after S3 resume. And that will causes gfx hang on gfxoff
> exit since this csb will be executed then.
> 
> Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
> Signed-off-by: Evan Quan <evan.quan@amd.com>

It is nice to have the comments behind of csb_vram_pin function to explain
why we need "pin" here during resume phase.

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ac46eabe3bcd..65cc30766658 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>  		dst_ptr = adev->gfx.rlc.cs_ptr;
>  		gfx_v9_0_get_csb_buffer(adev, dst_ptr);
>  		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> +		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>  		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>  	}
>  
> @@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>  	return 0;
>  }
>  
> +static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
> +{
> +	uint64_t gpu_addr;
> +	int r;
> +
> +	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> +	if (unlikely(r != 0))
> +		return r;
> +
> +	r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> +			AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
> +	if (!r)
> +		adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
> +
> +	amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> +
> +	return r;
> +}
> +
> +static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
> +{
> +	int r;
> +
> +	if (!adev->gfx.rlc.clear_state_obj)
> +		return;
> +
> +	r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> +	if (likely(r == 0)) {
> +		amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> +		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> +	}
> +}
> +
>  static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
>  {
>  	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
> @@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
>  
>  	gfx_v9_0_gpu_init(adev);
>  
> +	r = gfx_v9_0_csb_vram_pin(adev);
> +	if (r)
> +		return r;
> +
>  	r = gfx_v9_0_rlc_resume(adev);
>  	if (r)
>  		return r;
> @@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
>  	gfx_v9_0_cp_enable(adev, false);
>  	gfx_v9_0_rlc_stop(adev);
>  
> +	gfx_v9_0_csb_vram_unpin(adev);
> +
>  	return 0;
>  }
>  
> -- 
> 2.18.0
> 
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Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Alex Deucher]

On Thu, Jul 5, 2018 at 11:25 AM, Huang Rui <ray.huang@amd.com> wrote:
> On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote:
>> Without this pin, the csb buffer will be filled with inconsistent
>> data after S3 resume. And that will causes gfx hang on gfxoff
>> exit since this csb will be executed then.
>>
>> Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
>> Signed-off-by: Evan Quan <evan.quan@amd.com>
>
> It is nice to have the comments behind of csb_vram_pin function to explain
> why we need "pin" here during resume phase.
>
> Reviewed-by: Huang Rui <ray.huang@amd.com>

Do the save restore buffers in gfx7 and 8 need a similar fix?

Alex

>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++++++++++++++++++++++++++
>>  1 file changed, 40 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ac46eabe3bcd..65cc30766658 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>>               dst_ptr = adev->gfx.rlc.cs_ptr;
>>               gfx_v9_0_get_csb_buffer(adev, dst_ptr);
>>               amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
>> +             amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>>               amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>>       }
>>
>> @@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>>       return 0;
>>  }
>>
>> +static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
>> +{
>> +     uint64_t gpu_addr;
>> +     int r;
>> +
>> +     r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
>> +     if (unlikely(r != 0))
>> +             return r;
>> +
>> +     r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
>> +                     AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
>> +     if (!r)
>> +             adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
>> +
>> +     amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>> +
>> +     return r;
>> +}
>> +
>> +static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
>> +{
>> +     int r;
>> +
>> +     if (!adev->gfx.rlc.clear_state_obj)
>> +             return;
>> +
>> +     r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
>> +     if (likely(r == 0)) {
>> +             amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>> +             amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>> +     }
>> +}
>> +
>>  static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
>>  {
>>       amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
>> @@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
>>
>>       gfx_v9_0_gpu_init(adev);
>>
>> +     r = gfx_v9_0_csb_vram_pin(adev);
>> +     if (r)
>> +             return r;
>> +
>>       r = gfx_v9_0_rlc_resume(adev);
>>       if (r)
>>               return r;
>> @@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
>>       gfx_v9_0_cp_enable(adev, false);
>>       gfx_v9_0_rlc_stop(adev);
>>
>> +     gfx_v9_0_csb_vram_unpin(adev);
>> +
>>       return 0;
>>  }
>>
>> --
>> 2.18.0
>>
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>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Quan, Evan]

Comment inline

> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Thursday, July 05, 2018 11:25 PM
> To: Huang, Ray <Ray.Huang@amd.com>
> Cc: Quan, Evan <Evan.Quan@amd.com>; amd-gfx list <amd-
> gfx@lists.freedesktop.org>
> Subject: Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init
> 
> On Thu, Jul 5, 2018 at 11:25 AM, Huang Rui <ray.huang@amd.com> wrote:
> > On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote:
> >> Without this pin, the csb buffer will be filled with inconsistent
> >> data after S3 resume. And that will causes gfx hang on gfxoff exit
> >> since this csb will be executed then.
> >>
> >> Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
> >> Signed-off-by: Evan Quan <evan.quan@amd.com>
> >
> > It is nice to have the comments behind of csb_vram_pin function to
> > explain why we need "pin" here during resume phase.
> >
> > Reviewed-by: Huang Rui <ray.huang@amd.com>
> 
> Do the save restore buffers in gfx7 and 8 need a similar fix?
> 
> Alex
It seems so. Test on polaris11, the csb is corrupt after resume from S3.
I will send another patch to fix them.
> >
> >> ---
> >>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40
> >> +++++++++++++++++++++++++++
> >>  1 file changed, 40 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> index ac46eabe3bcd..65cc30766658 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> @@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device
> *adev)
> >>               dst_ptr = adev->gfx.rlc.cs_ptr;
> >>               gfx_v9_0_get_csb_buffer(adev, dst_ptr);
> >>               amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> >> +             amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> >>               amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> >>       }
> >>
> >> @@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device
> *adev)
> >>       return 0;
> >>  }
> >>
> >> +static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev) {
> >> +     uint64_t gpu_addr;
> >> +     int r;
> >> +
> >> +     r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> >> +     if (unlikely(r != 0))
> >> +             return r;
> >> +
> >> +     r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> >> +                     AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
> >> +     if (!r)
> >> +             adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
> >> +
> >> +     amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> >> +
> >> +     return r;
> >> +}
> >> +
> >> +static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev) {
> >> +     int r;
> >> +
> >> +     if (!adev->gfx.rlc.clear_state_obj)
> >> +             return;
> >> +
> >> +     r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> >> +     if (likely(r == 0)) {
> >> +             amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> >> +             amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> >> +     }
> >> +}
> >> +
> >>  static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)  {
> >>       amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
> >> @@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
> >>
> >>       gfx_v9_0_gpu_init(adev);
> >>
> >> +     r = gfx_v9_0_csb_vram_pin(adev);
> >> +     if (r)
> >> +             return r;
> >> +
> >>       r = gfx_v9_0_rlc_resume(adev);
> >>       if (r)
> >>               return r;
> >> @@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
> >>       gfx_v9_0_cp_enable(adev, false);
> >>       gfx_v9_0_rlc_stop(adev);
> >>
> >> +     gfx_v9_0_csb_vram_unpin(adev);
> >> +
> >>       return 0;
> >>  }
> >>
> >> --
> >> 2.18.0
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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