* [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency @ 2018-05-23 17:51 Harry Wentland [not found] ` <20180523175157.22210-1-harry.wentland-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 5+ messages in thread From: Harry Wentland @ 2018-05-23 17:51 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mikita.lipski-5C7GfCeVMHo, rex.zhu-5C7GfCeVMHo, hersen.wu-5C7GfCeVMHo, tony.cheng-5C7GfCeVMHo Cc: Harry Wentland This is required so we use the correct minimum clocks for Vega. Without this pplib will never be able to enter the lowest clock states. Signed-off-by: Harry Wentland <harry.wentland@amd.com> --- .../display/amdgpu_dm/amdgpu_dm_services.c | 46 ++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 0229c7edb8ad..30ddd329104d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels( } } +static void pp_to_dc_clock_levels_with_latency( + const struct pp_clock_levels_with_latency *pp_clks, + struct dm_pp_clock_levels_with_latency *clk_level_info, + enum dm_pp_clock_type dc_clk_type) +{ + uint32_t i; + + if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { + DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), + pp_clks->num_levels, + DM_PP_MAX_CLOCK_LEVELS); + + clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; + } else + clk_level_info->num_levels = pp_clks->num_levels; + + DRM_INFO("DM_PPLIB: values for %s clock\n", + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); + + for (i = 0; i < clk_level_info->num_levels; i++) { + DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); + /* translate 10kHz to kHz */ + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; + } +} + bool dm_pp_get_clock_levels_by_type( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, @@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency( enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_latency *clk_level_info) { - /* TODO: to be implemented */ - return false; + struct amdgpu_device *adev = ctx->driver_context; + void *pp_handle = adev->powerplay.pp_handle; + struct pp_clock_levels_with_latency pp_clks = { 0 }; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + + if (!pp_funcs->get_clock_by_type_with_latency) + return false; + + if (pp_funcs->get_clock_by_type_with_latency(pp_handle, + dc_to_pp_clock_type(clk_type), + &pp_clks)) + return false; + + pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); + + return true; } bool dm_pp_get_clock_levels_by_type_with_voltage( -- 2.17.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
[parent not found: <20180523175157.22210-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency [not found] ` <20180523175157.22210-1-harry.wentland-5C7GfCeVMHo@public.gmane.org> @ 2018-05-24 4:35 ` Alex Deucher [not found] ` <CADnq5_P1gntWz1+x0tePmnsF0oA5AdsHPbYNvn9mzyA+ad4bKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2018-05-24 14:51 ` [PATCH v2] " Harry Wentland 1 sibling, 1 reply; 5+ messages in thread From: Alex Deucher @ 2018-05-24 4:35 UTC (permalink / raw) To: Harry Wentland Cc: Cheng, Tony, Lipski, Mikita, Rex Zhu, hersen.wu-5C7GfCeVMHo, amd-gfx list On Wed, May 23, 2018 at 1:51 PM, Harry Wentland <harry.wentland@amd.com> wrote: > This is required so we use the correct minimum clocks for Vega. Without > this pplib will never be able to enter the lowest clock states. > > Signed-off-by: Harry Wentland <harry.wentland@amd.com> > --- > .../display/amdgpu_dm/amdgpu_dm_services.c | 46 ++++++++++++++++++- > 1 file changed, 44 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > index 0229c7edb8ad..30ddd329104d 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > @@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels( > } > } > > +static void pp_to_dc_clock_levels_with_latency( > + const struct pp_clock_levels_with_latency *pp_clks, > + struct dm_pp_clock_levels_with_latency *clk_level_info, > + enum dm_pp_clock_type dc_clk_type) > +{ > + uint32_t i; > + > + if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { > + DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", > + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), > + pp_clks->num_levels, > + DM_PP_MAX_CLOCK_LEVELS); > + > + clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; > + } else > + clk_level_info->num_levels = pp_clks->num_levels; > + > + DRM_INFO("DM_PPLIB: values for %s clock\n", > + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); > + > + for (i = 0; i < clk_level_info->num_levels; i++) { > + DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); leftover debugging output? Maybe make that DRM_DEBUG? With that addressed: Acked-by: Alex Deucher <alexander.deucher@amd.com> Alex > + /* translate 10kHz to kHz */ > + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; > + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; > + } > +} > + > bool dm_pp_get_clock_levels_by_type( > const struct dc_context *ctx, > enum dm_pp_clock_type clk_type, > @@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency( > enum dm_pp_clock_type clk_type, > struct dm_pp_clock_levels_with_latency *clk_level_info) > { > - /* TODO: to be implemented */ > - return false; > + struct amdgpu_device *adev = ctx->driver_context; > + void *pp_handle = adev->powerplay.pp_handle; > + struct pp_clock_levels_with_latency pp_clks = { 0 }; > + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > + > + if (!pp_funcs->get_clock_by_type_with_latency) > + return false; > + > + if (pp_funcs->get_clock_by_type_with_latency(pp_handle, > + dc_to_pp_clock_type(clk_type), > + &pp_clks)) > + return false; > + > + pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); > + > + return true; > } > > bool dm_pp_get_clock_levels_by_type_with_voltage( > -- > 2.17.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <CADnq5_P1gntWz1+x0tePmnsF0oA5AdsHPbYNvn9mzyA+ad4bKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency [not found] ` <CADnq5_P1gntWz1+x0tePmnsF0oA5AdsHPbYNvn9mzyA+ad4bKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2018-05-28 1:46 ` Quan, Evan [not found] ` <DM5PR1201MB2489A23BE7366B2C86681C16E46E0-grEf7a3NxMAAZHT/xKzwlGrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org> 0 siblings, 1 reply; 5+ messages in thread From: Quan, Evan @ 2018-05-28 1:46 UTC (permalink / raw) To: Alex Deucher, Wentland, Harry Cc: Wu, Hersen, Zhu, Rex, Lipski, Mikita, Cheng, Tony, amd-gfx list [-- Attachment #1.1: Type: text/plain, Size: 4788 bytes --] > + /* translate 10kHz to kHz */ > + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; > + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; This seems a typo(latency_in_us = clocks_in_khz ?). And the comment does not meet the code. If it translates 10kHz to kHz, why there is no "*10"? > + } Regards, Evan ________________________________ From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sent: Thursday, May 24, 2018 12:35:52 PM To: Wentland, Harry Cc: Cheng, Tony; Lipski, Mikita; Zhu, Rex; Wu, Hersen; amd-gfx list Subject: Re: [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency On Wed, May 23, 2018 at 1:51 PM, Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org> wrote: > This is required so we use the correct minimum clocks for Vega. Without > this pplib will never be able to enter the lowest clock states. > > Signed-off-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org> > --- > .../display/amdgpu_dm/amdgpu_dm_services.c | 46 ++++++++++++++++++- > 1 file changed, 44 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > index 0229c7edb8ad..30ddd329104d 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c > @@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels( > } > } > > +static void pp_to_dc_clock_levels_with_latency( > + const struct pp_clock_levels_with_latency *pp_clks, > + struct dm_pp_clock_levels_with_latency *clk_level_info, > + enum dm_pp_clock_type dc_clk_type) > +{ > + uint32_t i; > + > + if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { > + DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", > + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), > + pp_clks->num_levels, > + DM_PP_MAX_CLOCK_LEVELS); > + > + clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; > + } else > + clk_level_info->num_levels = pp_clks->num_levels; > + > + DRM_INFO("DM_PPLIB: values for %s clock\n", > + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); > + > + for (i = 0; i < clk_level_info->num_levels; i++) { > + DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); leftover debugging output? Maybe make that DRM_DEBUG? With that addressed: Acked-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org> Alex > + /* translate 10kHz to kHz */ > + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; > + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; > + } > +} > + > bool dm_pp_get_clock_levels_by_type( > const struct dc_context *ctx, > enum dm_pp_clock_type clk_type, > @@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency( > enum dm_pp_clock_type clk_type, > struct dm_pp_clock_levels_with_latency *clk_level_info) > { > - /* TODO: to be implemented */ > - return false; > + struct amdgpu_device *adev = ctx->driver_context; > + void *pp_handle = adev->powerplay.pp_handle; > + struct pp_clock_levels_with_latency pp_clks = { 0 }; > + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; > + > + if (!pp_funcs->get_clock_by_type_with_latency) > + return false; > + > + if (pp_funcs->get_clock_by_type_with_latency(pp_handle, > + dc_to_pp_clock_type(clk_type), > + &pp_clks)) > + return false; > + > + pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); > + > + return true; > } > > bool dm_pp_get_clock_levels_by_type_with_voltage( > -- > 2.17.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 11938 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <DM5PR1201MB2489A23BE7366B2C86681C16E46E0-grEf7a3NxMAAZHT/xKzwlGrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>]
* Re: [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency [not found] ` <DM5PR1201MB2489A23BE7366B2C86681C16E46E0-grEf7a3NxMAAZHT/xKzwlGrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org> @ 2018-05-28 20:03 ` Harry Wentland 0 siblings, 0 replies; 5+ messages in thread From: Harry Wentland @ 2018-05-28 20:03 UTC (permalink / raw) To: Quan, Evan, Alex Deucher Cc: Wu, Hersen, Zhu, Rex, Lipski, Mikita, Cheng, Tony, amd-gfx list On 2018-05-27 09:46 PM, Quan, Evan wrote: >> + /* translate 10kHz to kHz */ >> + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; >> + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; > > This seems a typo(latency_in_us = clocks_in_khz ?). > Definitely a typo. Thanks for spotting this. > And the comment does not meet the code. If it translates 10kHz to kHz, why there is no "*10"? >> + } > I'll send a patch with fixes for both. No need for the comment here, just left-over from copy-paste. Harry > > Regards, > > Evan > > ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ > *From:* amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher@gmail.com> > *Sent:* Thursday, May 24, 2018 12:35:52 PM > *To:* Wentland, Harry > *Cc:* Cheng, Tony; Lipski, Mikita; Zhu, Rex; Wu, Hersen; amd-gfx list > *Subject:* Re: [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency > > On Wed, May 23, 2018 at 1:51 PM, Harry Wentland <harry.wentland@amd.com> wrote: >> This is required so we use the correct minimum clocks for Vega. Without >> this pplib will never be able to enter the lowest clock states. >> >> Signed-off-by: Harry Wentland <harry.wentland@amd.com> >> --- >> .../display/amdgpu_dm/amdgpu_dm_services.c | 46 ++++++++++++++++++- >> 1 file changed, 44 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c >> index 0229c7edb8ad..30ddd329104d 100644 >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c >> @@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels( >> } >> } >> >> +static void pp_to_dc_clock_levels_with_latency( >> + const struct pp_clock_levels_with_latency *pp_clks, >> + struct dm_pp_clock_levels_with_latency *clk_level_info, >> + enum dm_pp_clock_type dc_clk_type) >> +{ >> + uint32_t i; >> + >> + if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { >> + DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", >> + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), >> + pp_clks->num_levels, >> + DM_PP_MAX_CLOCK_LEVELS); >> + >> + clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; >> + } else >> + clk_level_info->num_levels = pp_clks->num_levels; >> + >> + DRM_INFO("DM_PPLIB: values for %s clock\n", >> + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); >> + >> + for (i = 0; i < clk_level_info->num_levels; i++) { >> + DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); > > leftover debugging output? Maybe make that DRM_DEBUG? With that addressed: > Acked-by: Alex Deucher <alexander.deucher@amd.com> > > Alex > >> + /* translate 10kHz to kHz */ >> + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; >> + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; >> + } >> +} >> + >> bool dm_pp_get_clock_levels_by_type( >> const struct dc_context *ctx, >> enum dm_pp_clock_type clk_type, >> @@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency( >> enum dm_pp_clock_type clk_type, >> struct dm_pp_clock_levels_with_latency *clk_level_info) >> { >> - /* TODO: to be implemented */ >> - return false; >> + struct amdgpu_device *adev = ctx->driver_context; >> + void *pp_handle = adev->powerplay.pp_handle; >> + struct pp_clock_levels_with_latency pp_clks = { 0 }; >> + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; >> + >> + if (!pp_funcs->get_clock_by_type_with_latency) >> + return false; >> + >> + if (pp_funcs->get_clock_by_type_with_latency(pp_handle, >> + dc_to_pp_clock_type(clk_type), >> + &pp_clks)) >> + return false; >> + >> + pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); >> + >> + return true; >> } >> >> bool dm_pp_get_clock_levels_by_type_with_voltage( >> -- >> 2.17.0 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency [not found] ` <20180523175157.22210-1-harry.wentland-5C7GfCeVMHo@public.gmane.org> 2018-05-24 4:35 ` Alex Deucher @ 2018-05-24 14:51 ` Harry Wentland 1 sibling, 0 replies; 5+ messages in thread From: Harry Wentland @ 2018-05-24 14:51 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mikita.lipski-5C7GfCeVMHo, rex.zhu-5C7GfCeVMHo, hersen.wu-5C7GfCeVMHo, tony.cheng-5C7GfCeVMHo, alexdeucher-Re5JQEeQqe8AvxtiuMwx3w Cc: Harry Wentland This is required so we use the correct minimum clocks for Vega. Without this pplib will never be able to enter the lowest clock states. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> --- .../display/amdgpu_dm/amdgpu_dm_services.c | 46 ++++++++++++++++++- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 0229c7edb8ad..ead3d21545b1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels( } } +static void pp_to_dc_clock_levels_with_latency( + const struct pp_clock_levels_with_latency *pp_clks, + struct dm_pp_clock_levels_with_latency *clk_level_info, + enum dm_pp_clock_type dc_clk_type) +{ + uint32_t i; + + if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { + DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n", + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type), + pp_clks->num_levels, + DM_PP_MAX_CLOCK_LEVELS); + + clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS; + } else + clk_level_info->num_levels = pp_clks->num_levels; + + DRM_DEBUG("DM_PPLIB: values for %s clock\n", + DC_DECODE_PP_CLOCK_TYPE(dc_clk_type)); + + for (i = 0; i < clk_level_info->num_levels; i++) { + DRM_DEBUG("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz); + /* translate 10kHz to kHz */ + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz; + clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz; + } +} + bool dm_pp_get_clock_levels_by_type( const struct dc_context *ctx, enum dm_pp_clock_type clk_type, @@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency( enum dm_pp_clock_type clk_type, struct dm_pp_clock_levels_with_latency *clk_level_info) { - /* TODO: to be implemented */ - return false; + struct amdgpu_device *adev = ctx->driver_context; + void *pp_handle = adev->powerplay.pp_handle; + struct pp_clock_levels_with_latency pp_clks = { 0 }; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + + if (!pp_funcs->get_clock_by_type_with_latency) + return false; + + if (pp_funcs->get_clock_by_type_with_latency(pp_handle, + dc_to_pp_clock_type(clk_type), + &pp_clks)) + return false; + + pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type); + + return true; } bool dm_pp_get_clock_levels_by_type_with_voltage( -- 2.17.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-05-28 20:03 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-05-23 17:51 [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency Harry Wentland [not found] ` <20180523175157.22210-1-harry.wentland-5C7GfCeVMHo@public.gmane.org> 2018-05-24 4:35 ` Alex Deucher [not found] ` <CADnq5_P1gntWz1+x0tePmnsF0oA5AdsHPbYNvn9mzyA+ad4bKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2018-05-28 1:46 ` Quan, Evan [not found] ` <DM5PR1201MB2489A23BE7366B2C86681C16E46E0-grEf7a3NxMAAZHT/xKzwlGrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org> 2018-05-28 20:03 ` Harry Wentland 2018-05-24 14:51 ` [PATCH v2] " Harry Wentland
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