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* [PATCH] drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folder
@ 2022-07-16 19:51 ` Melissa Wen
  0 siblings, 0 replies; 5+ messages in thread
From: Melissa Wen @ 2022-07-16 19:51 UTC (permalink / raw)
  To: harry.wentland, sunpeng.li, Rodrigo.Siqueira, alexander.deucher,
	christian.koenig, Xinhui.Pan, airlied, daniel
  Cc: Melissa Wen, dri-devel, amd-gfx, kernel-dev, linux-kernel

Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by
dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in
dcn31_resource that is not FPU protected. Move this function to dcn31_fpu
file as part of the work to isolate FPU code.

Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 9 ---------
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 9 +++++++++
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  | 2 ++
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 16bbccc69fdc..17c776e88514 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1716,15 +1716,6 @@ int dcn31_populate_dml_pipes_from_context(
 	return pipe_cnt;
 }
 
-void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
-{
-	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
-		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
-		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
-		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
-	}
-}
-
 void dcn31_calculate_wm_and_dlg(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
index 393458015d6a..41f8ec99da6b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
@@ -59,7 +59,6 @@ dcn31_set_mcif_arb_params(struct dc *dc,
 			  struct dc_state *context,
 			  display_e2e_pipe_params_st *pipes,
 			  int pipe_cnt);
-void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
 
 struct resource_pool *dcn31_create_resource_pool(
 		const struct dc_init_data *init_data,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 7be3476989ce..facac3daeaca 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -435,6 +435,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 };
 
+void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+{
+	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
+	}
+}
+
 void dcn31_calculate_wm_and_dlg_fp(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
index 24ac19c83687..0a10de80c1a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
@@ -31,6 +31,8 @@
 #define DCN3_15_MIN_COMPBUF_SIZE_KB 128
 #define DCN3_16_DEFAULT_DET_SIZE 192
 
+void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
+
 void dcn31_calculate_wm_and_dlg_fp(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH] drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folder
@ 2022-07-16 19:51 ` Melissa Wen
  0 siblings, 0 replies; 5+ messages in thread
From: Melissa Wen @ 2022-07-16 19:51 UTC (permalink / raw)
  To: harry.wentland, sunpeng.li, Rodrigo.Siqueira, alexander.deucher,
	christian.koenig, Xinhui.Pan, airlied, daniel
  Cc: kernel-dev, Melissa Wen, amd-gfx, dri-devel, linux-kernel

Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by
dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in
dcn31_resource that is not FPU protected. Move this function to dcn31_fpu
file as part of the work to isolate FPU code.

Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 9 ---------
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 9 +++++++++
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  | 2 ++
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 16bbccc69fdc..17c776e88514 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1716,15 +1716,6 @@ int dcn31_populate_dml_pipes_from_context(
 	return pipe_cnt;
 }
 
-void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
-{
-	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
-		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
-		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
-		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
-	}
-}
-
 void dcn31_calculate_wm_and_dlg(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
index 393458015d6a..41f8ec99da6b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
@@ -59,7 +59,6 @@ dcn31_set_mcif_arb_params(struct dc *dc,
 			  struct dc_state *context,
 			  display_e2e_pipe_params_st *pipes,
 			  int pipe_cnt);
-void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
 
 struct resource_pool *dcn31_create_resource_pool(
 		const struct dc_init_data *init_data,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 7be3476989ce..facac3daeaca 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -435,6 +435,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
 	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 };
 
+void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
+{
+	if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
+		context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
+		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
+		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
+	}
+}
+
 void dcn31_calculate_wm_and_dlg_fp(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
index 24ac19c83687..0a10de80c1a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
@@ -31,6 +31,8 @@
 #define DCN3_15_MIN_COMPBUF_SIZE_KB 128
 #define DCN3_16_DEFAULT_DET_SIZE 192
 
+void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
+
 void dcn31_calculate_wm_and_dlg_fp(
 		struct dc *dc, struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folder
  2022-07-16 19:51 ` Melissa Wen
  (?)
@ 2022-07-18 19:19   ` Alex Deucher
  -1 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2022-07-18 19:19 UTC (permalink / raw)
  To: Melissa Wen
  Cc: Wentland, Harry, Leo (Sunpeng) Li, Siqueira, Rodrigo, Deucher,
	Alexander, Christian Koenig, xinhui pan, Dave Airlie,
	Daniel Vetter, Maling list - DRI developers, amd-gfx list,
	kernel-dev, LKML

Applied with a trivial fix for dcn314_resource.c.

Thanks!

Alex

On Sat, Jul 16, 2022 at 3:52 PM Melissa Wen <mwen@igalia.com> wrote:
>
> Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by
> dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in
> dcn31_resource that is not FPU protected. Move this function to dcn31_fpu
> file as part of the work to isolate FPU code.
>
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 9 ---------
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 1 -
>  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 9 +++++++++
>  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  | 2 ++
>  4 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index 16bbccc69fdc..17c776e88514 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -1716,15 +1716,6 @@ int dcn31_populate_dml_pipes_from_context(
>         return pipe_cnt;
>  }
>
> -void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
> -{
> -       if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
> -               context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
> -               context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
> -               context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
> -       }
> -}
> -
>  void dcn31_calculate_wm_and_dlg(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> index 393458015d6a..41f8ec99da6b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> @@ -59,7 +59,6 @@ dcn31_set_mcif_arb_params(struct dc *dc,
>                           struct dc_state *context,
>                           display_e2e_pipe_params_st *pipes,
>                           int pipe_cnt);
> -void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
>
>  struct resource_pool *dcn31_create_resource_pool(
>                 const struct dc_init_data *init_data,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> index 7be3476989ce..facac3daeaca 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> @@ -435,6 +435,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
>         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
>  };
>
> +void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
> +{
> +       if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
> +               context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
> +               context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
> +               context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
> +       }
> +}
> +
>  void dcn31_calculate_wm_and_dlg_fp(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> index 24ac19c83687..0a10de80c1a4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> @@ -31,6 +31,8 @@
>  #define DCN3_15_MIN_COMPBUF_SIZE_KB 128
>  #define DCN3_16_DEFAULT_DET_SIZE 192
>
> +void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
> +
>  void dcn31_calculate_wm_and_dlg_fp(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> --
> 2.35.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folder
@ 2022-07-18 19:19   ` Alex Deucher
  0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2022-07-18 19:19 UTC (permalink / raw)
  To: Melissa Wen
  Cc: kernel-dev, Leo (Sunpeng) Li, xinhui pan, Siqueira, Rodrigo,
	LKML, Maling list - DRI developers, Dave Airlie, amd-gfx list,
	Deucher, Alexander, Christian Koenig

Applied with a trivial fix for dcn314_resource.c.

Thanks!

Alex

On Sat, Jul 16, 2022 at 3:52 PM Melissa Wen <mwen@igalia.com> wrote:
>
> Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by
> dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in
> dcn31_resource that is not FPU protected. Move this function to dcn31_fpu
> file as part of the work to isolate FPU code.
>
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 9 ---------
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 1 -
>  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 9 +++++++++
>  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  | 2 ++
>  4 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index 16bbccc69fdc..17c776e88514 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -1716,15 +1716,6 @@ int dcn31_populate_dml_pipes_from_context(
>         return pipe_cnt;
>  }
>
> -void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
> -{
> -       if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
> -               context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
> -               context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
> -               context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
> -       }
> -}
> -
>  void dcn31_calculate_wm_and_dlg(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> index 393458015d6a..41f8ec99da6b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> @@ -59,7 +59,6 @@ dcn31_set_mcif_arb_params(struct dc *dc,
>                           struct dc_state *context,
>                           display_e2e_pipe_params_st *pipes,
>                           int pipe_cnt);
> -void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
>
>  struct resource_pool *dcn31_create_resource_pool(
>                 const struct dc_init_data *init_data,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> index 7be3476989ce..facac3daeaca 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> @@ -435,6 +435,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
>         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
>  };
>
> +void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
> +{
> +       if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
> +               context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
> +               context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
> +               context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
> +       }
> +}
> +
>  void dcn31_calculate_wm_and_dlg_fp(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> index 24ac19c83687..0a10de80c1a4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> @@ -31,6 +31,8 @@
>  #define DCN3_15_MIN_COMPBUF_SIZE_KB 128
>  #define DCN3_16_DEFAULT_DET_SIZE 192
>
> +void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
> +
>  void dcn31_calculate_wm_and_dlg_fp(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> --
> 2.35.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folder
@ 2022-07-18 19:19   ` Alex Deucher
  0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2022-07-18 19:19 UTC (permalink / raw)
  To: Melissa Wen
  Cc: kernel-dev, Leo (Sunpeng) Li, xinhui pan, Siqueira, Rodrigo,
	LKML, Maling list - DRI developers, Dave Airlie, amd-gfx list,
	Daniel Vetter, Deucher, Alexander, Wentland, Harry,
	Christian Koenig

Applied with a trivial fix for dcn314_resource.c.

Thanks!

Alex

On Sat, Jul 16, 2022 at 3:52 PM Melissa Wen <mwen@igalia.com> wrote:
>
> Although dcn31_update_soc_for_wm_a() is only called in dml/dcn31/dcn31_fpu by
> dc->res_pool->funcs->update_soc_for_wm_a(dc, context), it's declared in
> dcn31_resource that is not FPU protected. Move this function to dcn31_fpu
> file as part of the work to isolate FPU code.
>
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 9 ---------
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h | 1 -
>  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c  | 9 +++++++++
>  drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h  | 2 ++
>  4 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index 16bbccc69fdc..17c776e88514 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -1716,15 +1716,6 @@ int dcn31_populate_dml_pipes_from_context(
>         return pipe_cnt;
>  }
>
> -void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
> -{
> -       if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
> -               context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
> -               context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
> -               context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
> -       }
> -}
> -
>  void dcn31_calculate_wm_and_dlg(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> index 393458015d6a..41f8ec99da6b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.h
> @@ -59,7 +59,6 @@ dcn31_set_mcif_arb_params(struct dc *dc,
>                           struct dc_state *context,
>                           display_e2e_pipe_params_st *pipes,
>                           int pipe_cnt);
> -void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
>
>  struct resource_pool *dcn31_create_resource_pool(
>                 const struct dc_init_data *init_data,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> index 7be3476989ce..facac3daeaca 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> @@ -435,6 +435,15 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_16_soc = {
>         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
>  };
>
> +void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
> +{
> +       if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
> +               context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
> +               context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
> +               context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
> +       }
> +}
> +
>  void dcn31_calculate_wm_and_dlg_fp(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> index 24ac19c83687..0a10de80c1a4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
> @@ -31,6 +31,8 @@
>  #define DCN3_15_MIN_COMPBUF_SIZE_KB 128
>  #define DCN3_16_DEFAULT_DET_SIZE 192
>
> +void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context);
> +
>  void dcn31_calculate_wm_and_dlg_fp(
>                 struct dc *dc, struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
> --
> 2.35.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-07-18 19:20 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-16 19:51 [PATCH] drm/amd/display: move dcn31_update_soc_for_wm_a func to dml fpu folder Melissa Wen
2022-07-16 19:51 ` Melissa Wen
2022-07-18 19:19 ` Alex Deucher
2022-07-18 19:19   ` Alex Deucher
2022-07-18 19:19   ` Alex Deucher

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