* [PATCH 1/2] drm/amd/powerplay: refine code in vega10_smumgr.c
@ 2017-05-02 8:56 Rex Zhu
[not found] ` <1493715386-8098-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Rex Zhu @ 2017-05-02 8:56 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
1. return error code instand of -1.
2. print msg info if send msg failed
Change-Id: I40529e4002f4f1fef7aca93e05bf1bd5f285d068
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
.../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 78 +++++++++++-----------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
index 5980f02f..05669cb 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
@@ -85,7 +85,7 @@ static uint32_t vega10_wait_for_response(struct pp_smumgr *smumgr)
uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr))
- return -1;
+ return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_90_BASE_IDX, mmMP1_SMN_C2PMSG_90);
@@ -109,7 +109,7 @@ int vega10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr,
uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr))
- return -1;
+ return -EINVAL;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_66_BASE_IDX, mmMP1_SMN_C2PMSG_66);
@@ -130,7 +130,7 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr))
- return -1;
+ return -EINVAL;
vega10_wait_for_response(smumgr);
@@ -140,9 +140,8 @@ int vega10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
vega10_send_msg_to_smc_without_waiting(smumgr, msg);
- PP_ASSERT_WITH_CODE(vega10_wait_for_response(smumgr) == 1,
- "Failed to send Message.",
- return -1);
+ if (vega10_wait_for_response(smumgr) != 1)
+ pr_err("Failed to send Message: 0x%x\n.", msg);
return 0;
}
@@ -160,7 +159,7 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
uint32_t reg;
if (!vega10_is_smc_ram_running(smumgr))
- return -1;
+ return -EINVAL;
vega10_wait_for_response(smumgr);
@@ -174,9 +173,8 @@ int vega10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
vega10_send_msg_to_smc_without_waiting(smumgr, msg);
- PP_ASSERT_WITH_CODE(vega10_wait_for_response(smumgr) == 1,
- "Failed to send Message.",
- return -1);
+ if (vega10_wait_for_response(smumgr) != 1)
+ pr_err("Failed to send Message: 0x%x\n.", msg);
return 0;
}
@@ -233,25 +231,25 @@ int vega10_copy_table_from_smc(struct pp_smumgr *smumgr,
(struct vega10_smumgr *)(smumgr->backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
- "Invalid SMU Table ID!", return -1;);
+ "Invalid SMU Table ID!", return -EINVAL);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
- "Invalid SMU Table version!", return -1;);
+ "Invalid SMU Table version!", return -EINVAL);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
- "Invalid SMU Table Length!", return -1;);
+ "Invalid SMU Table Length!", return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0,
- "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -1;);
+ "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!",
- return -1;);
+ return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_TransferTableSmu2Dram,
priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!",
- return -1;);
+ return -EINVAL);
memcpy(table, priv->smu_tables.entry[table_id].table,
priv->smu_tables.entry[table_id].size);
@@ -271,11 +269,11 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
(struct vega10_smumgr *)(smumgr->backend);
PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
- "Invalid SMU Table ID!", return -1;);
+ "Invalid SMU Table ID!", return -EINVAL);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
- "Invalid SMU Table version!", return -1;);
+ "Invalid SMU Table version!", return -EINVAL);
PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
- "Invalid SMU Table Length!", return -1;);
+ "Invalid SMU Table Length!", return -EINVAL);
memcpy(priv->smu_tables.entry[table_id].table, table,
priv->smu_tables.entry[table_id].size);
@@ -284,17 +282,17 @@ int vega10_copy_table_to_smc(struct pp_smumgr *smumgr,
PPSMC_MSG_SetDriverDramAddrHigh,
priv->smu_tables.entry[table_id].table_addr_high) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr High Failed!",
- return -1;);
+ return -EINVAL;);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_SetDriverDramAddrLow,
priv->smu_tables.entry[table_id].table_addr_low) == 0,
"[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!",
- return -1;);
+ return -EINVAL);
PP_ASSERT_WITH_CODE(vega10_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_TransferTableDram2Smu,
priv->smu_tables.entry[table_id].table_id) == 0,
"[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!",
- return -1;);
+ return -EINVAL);
return 0;
}
@@ -303,7 +301,7 @@ int vega10_save_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
{
PP_ASSERT_WITH_CODE(avfs_table,
"No access to SMC AVFS Table",
- return -1);
+ return -EINVAL);
return vega10_copy_table_from_smc(smumgr, avfs_table, AVFSTABLE);
}
@@ -312,7 +310,7 @@ int vega10_restore_vft_table(struct pp_smumgr *smumgr, uint8_t *avfs_table)
{
PP_ASSERT_WITH_CODE(avfs_table,
"No access to SMC AVFS Table",
- return -1);
+ return -EINVAL);
return vega10_copy_table_to_smc(smumgr, avfs_table, AVFSTABLE);
}
@@ -330,13 +328,16 @@ int vega10_enable_smc_features(struct pp_smumgr *smumgr,
int vega10_get_smc_features(struct pp_smumgr *smumgr,
uint32_t *features_enabled)
{
+ if (features_enabled == NULL)
+ return -EINVAL;
+
if (!vega10_send_msg_to_smc(smumgr,
PPSMC_MSG_GetEnabledSmuFeatures)) {
- if (!vega10_read_arg_from_smc(smumgr, features_enabled))
- return 0;
+ vega10_read_arg_from_smc(smumgr, features_enabled);
+ return 0;
}
- return -1;
+ return -EINVAL;
}
int vega10_set_tools_address(struct pp_smumgr *smumgr)
@@ -363,15 +364,14 @@ static int vega10_verify_smc_interface(struct pp_smumgr *smumgr)
PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(smumgr,
PPSMC_MSG_GetDriverIfVersion),
"Attempt to get SMC IF Version Number Failed!",
- return -1);
- PP_ASSERT_WITH_CODE(!vega10_read_arg_from_smc(smumgr,
- &smc_driver_if_version),
- "Attempt to read SMC IF Version Number Failed!",
- return -1);
+ return -EINVAL);
+ vega10_read_arg_from_smc(smumgr, &smc_driver_if_version);
if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
- pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
- smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
+ pr_err("Your firmware(0x%x) doesn't match \
+ SMU9_DRIVER_IF_VERSION(0x%x). \
+ Please update your firmware!\n",
+ smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
return -EINVAL;
}
@@ -421,7 +421,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
kfree(smumgr->backend);
cgs_free_gpu_mem(smumgr->device,
(cgs_handle_t)handle);
- return -1);
+ return -EINVAL);
priv->smu_tables.entry[PPTABLE].version = 0x01;
priv->smu_tables.entry[PPTABLE].size = sizeof(PPTable_t);
@@ -449,7 +449,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
(cgs_handle_t)priv->smu_tables.entry[PPTABLE].handle);
cgs_free_gpu_mem(smumgr->device,
(cgs_handle_t)handle);
- return -1);
+ return -EINVAL);
priv->smu_tables.entry[WMTABLE].version = 0x01;
priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
@@ -479,7 +479,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
(cgs_handle_t)priv->smu_tables.entry[WMTABLE].handle);
cgs_free_gpu_mem(smumgr->device,
(cgs_handle_t)handle);
- return -1);
+ return -EINVAL);
priv->smu_tables.entry[AVFSTABLE].version = 0x01;
priv->smu_tables.entry[AVFSTABLE].size = sizeof(AvfsTable_t);
@@ -537,7 +537,7 @@ static int vega10_smu_init(struct pp_smumgr *smumgr)
(cgs_handle_t)priv->smu_tables.entry[TOOLSTABLE].handle);
cgs_free_gpu_mem(smumgr->device,
(cgs_handle_t)handle);
- return -1);
+ return -EINVAL);
priv->smu_tables.entry[AVFSFUSETABLE].version = 0x01;
priv->smu_tables.entry[AVFSFUSETABLE].size = sizeof(AvfsFuseOverride_t);
@@ -579,7 +579,7 @@ static int vega10_start_smu(struct pp_smumgr *smumgr)
{
PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(smumgr),
"Failed to verify SMC interface!",
- return -1);
+ return -EINVAL);
return 0;
}
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] drm/amd/powerplay: set soc floor voltage on boot on vega10.
[not found] ` <1493715386-8098-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-05-02 8:56 ` Rex Zhu
[not found] ` <1493715386-8098-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 3+ messages in thread
From: Rex Zhu @ 2017-05-02 8:56 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Send the VBIOS bootup VDDC as a SOC floor voltage to SMU
before populating the PPTABLE. After DPM is enabled, This
floor voltage will be removed. This will prevent SMC from
going to Vmin upon receiving PPTable causing a violation.
Change-Id: Ieff3c7ffe58b8ec83127d90ca2bb1761a5c71462
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 28 ++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 15 ++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 25 +++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 3 +++
4 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index de3d8f3..5602311 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -387,3 +387,31 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
return 0;
}
+
+int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
+ struct pp_atomfwctrl_bios_boot_up_values *boot_values)
+{
+ struct atom_firmware_info_v3_1 *info = NULL;
+ uint16_t ix;
+
+ ix = GetIndexIntoMasterDataTable(firmwareinfo);
+ info = (struct atom_firmware_info_v3_1 *)
+ cgs_atom_get_data_table(hwmgr->device,
+ ix, NULL, NULL, NULL);
+
+ if (!info) {
+ pr_info("Error retrieving BIOS firmwareinfo!");
+ return -EINVAL;
+ }
+
+ boot_values->ulRevision = info->firmware_revision;
+ boot_values->ulGfxClk = info->bootup_sclk_in10khz;
+ boot_values->ulUClk = info->bootup_mclk_in10khz;
+ boot_values->ulSocClk = 0;
+ boot_values->usVddc = info->bootup_vddc_mv;
+ boot_values->usVddci = info->bootup_vddci_mv;
+ boot_values->usMvddc = info->bootup_mvddc_mv;
+ boot_values->usVddGfx = info->bootup_vddgfx_mv;
+
+ return 0;
+}
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
index be1579e..43a6711 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
@@ -119,6 +119,18 @@ struct pp_atomfwctrl_gpio_parameters {
uint8_t ucFwCtfGpio;
uint8_t ucFwCtfPolarity;
};
+
+struct pp_atomfwctrl_bios_boot_up_values {
+ uint32_t ulRevision;
+ uint32_t ulGfxClk;
+ uint32_t ulUClk;
+ uint32_t ulSocClk;
+ uint16_t usVddc;
+ uint16_t usVddci;
+ uint16_t usMvddc;
+ uint16_t usVddGfx;
+};
+
int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
uint32_t clock_type, uint32_t clock_value,
struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
@@ -136,5 +148,8 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
struct pp_atomfwctrl_gpio_parameters *param);
+int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
+ struct pp_atomfwctrl_bios_boot_up_values *boot_values);
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 68eae52..dbc1c03 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2298,6 +2298,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
(struct phm_ppt_v2_information *)(hwmgr->pptable);
PPTable_t *pp_table = &(data->smc_state_table.pp_table);
struct pp_atomfwctrl_voltage_table voltage_table;
+ struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
result = vega10_setup_default_dpm_tables(hwmgr);
PP_ASSERT_WITH_CODE(!result,
@@ -2369,6 +2370,24 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
return result);
}
+ result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
+ if (!result) {
+ data->vbios_boot_state.vddc = boot_up_values.usVddc;
+ data->vbios_boot_state.vddci = boot_up_values.usVddci;
+ data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
+ data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
+ data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
+ data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
+ if (0 != boot_up_values.usVddc) {
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_SetFloorSocVoltage,
+ (boot_up_values.usVddc * 4));
+ data->vbios_boot_state.bsoc_vddc_lock = true;
+ } else {
+ data->vbios_boot_state.bsoc_vddc_lock = false;
+ }
+ }
+
result = vega10_populate_avfs_parameters(hwmgr);
PP_ASSERT_WITH_CODE(!result,
"Failed to initialize AVFS Parameters!",
@@ -2590,6 +2609,12 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
data->smu_features[GNLD_LED_DISPLAY].enabled = true;
}
+ if (data->vbios_boot_state.bsoc_vddc_lock) {
+ smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+ PPSMC_MSG_SetFloorSocVoltage, 0);
+ data->vbios_boot_state.bsoc_vddc_lock = false;
+ }
+
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_Falcon_QuickTransition)) {
if (data->smu_features[GNLD_ACDC].supported) {
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 83c67b9..1912e08 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -177,8 +177,11 @@ struct vega10_dpmlevel_enable_mask {
};
struct vega10_vbios_boot_state {
+ bool bsoc_vddc_lock;
uint16_t vddc;
uint16_t vddci;
+ uint16_t mvddc;
+ uint16_t vdd_gfx;
uint32_t gfx_clock;
uint32_t mem_clock;
uint32_t soc_clock;
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 2/2] drm/amd/powerplay: set soc floor voltage on boot on vega10.
[not found] ` <1493715386-8098-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-05-02 14:02 ` Alex Deucher
0 siblings, 0 replies; 3+ messages in thread
From: Alex Deucher @ 2017-05-02 14:02 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, May 2, 2017 at 4:56 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Send the VBIOS bootup VDDC as a SOC floor voltage to SMU
> before populating the PPTABLE. After DPM is enabled, This
> floor voltage will be removed. This will prevent SMC from
> going to Vmin upon receiving PPTable causing a violation.
>
> Change-Id: Ieff3c7ffe58b8ec83127d90ca2bb1761a5c71462
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 28 ++++++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 15 ++++++++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 25 +++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 3 +++
> 4 files changed, 71 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> index de3d8f3..5602311 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> @@ -387,3 +387,31 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
>
> return 0;
> }
> +
> +int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
> + struct pp_atomfwctrl_bios_boot_up_values *boot_values)
> +{
> + struct atom_firmware_info_v3_1 *info = NULL;
> + uint16_t ix;
> +
> + ix = GetIndexIntoMasterDataTable(firmwareinfo);
> + info = (struct atom_firmware_info_v3_1 *)
> + cgs_atom_get_data_table(hwmgr->device,
> + ix, NULL, NULL, NULL);
> +
> + if (!info) {
> + pr_info("Error retrieving BIOS firmwareinfo!");
> + return -EINVAL;
> + }
> +
> + boot_values->ulRevision = info->firmware_revision;
> + boot_values->ulGfxClk = info->bootup_sclk_in10khz;
> + boot_values->ulUClk = info->bootup_mclk_in10khz;
> + boot_values->ulSocClk = 0;
> + boot_values->usVddc = info->bootup_vddc_mv;
> + boot_values->usVddci = info->bootup_vddci_mv;
> + boot_values->usMvddc = info->bootup_mvddc_mv;
> + boot_values->usVddGfx = info->bootup_vddgfx_mv;
> +
> + return 0;
> +}
> \ No newline at end of file
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> index be1579e..43a6711 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> @@ -119,6 +119,18 @@ struct pp_atomfwctrl_gpio_parameters {
> uint8_t ucFwCtfGpio;
> uint8_t ucFwCtfPolarity;
> };
> +
> +struct pp_atomfwctrl_bios_boot_up_values {
> + uint32_t ulRevision;
> + uint32_t ulGfxClk;
> + uint32_t ulUClk;
> + uint32_t ulSocClk;
> + uint16_t usVddc;
> + uint16_t usVddci;
> + uint16_t usMvddc;
> + uint16_t usVddGfx;
> +};
> +
> int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
> uint32_t clock_type, uint32_t clock_value,
> struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
> @@ -136,5 +148,8 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
> int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
> struct pp_atomfwctrl_gpio_parameters *param);
>
> +int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
> + struct pp_atomfwctrl_bios_boot_up_values *boot_values);
> +
> #endif
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 68eae52..dbc1c03 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2298,6 +2298,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
> (struct phm_ppt_v2_information *)(hwmgr->pptable);
> PPTable_t *pp_table = &(data->smc_state_table.pp_table);
> struct pp_atomfwctrl_voltage_table voltage_table;
> + struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
>
> result = vega10_setup_default_dpm_tables(hwmgr);
> PP_ASSERT_WITH_CODE(!result,
> @@ -2369,6 +2370,24 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
> return result);
> }
>
> + result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
> + if (!result) {
> + data->vbios_boot_state.vddc = boot_up_values.usVddc;
> + data->vbios_boot_state.vddci = boot_up_values.usVddci;
> + data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
> + data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
> + data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
> + data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
> + if (0 != boot_up_values.usVddc) {
> + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> + PPSMC_MSG_SetFloorSocVoltage,
> + (boot_up_values.usVddc * 4));
> + data->vbios_boot_state.bsoc_vddc_lock = true;
> + } else {
> + data->vbios_boot_state.bsoc_vddc_lock = false;
> + }
> + }
> +
> result = vega10_populate_avfs_parameters(hwmgr);
> PP_ASSERT_WITH_CODE(!result,
> "Failed to initialize AVFS Parameters!",
> @@ -2590,6 +2609,12 @@ static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
> data->smu_features[GNLD_LED_DISPLAY].enabled = true;
> }
>
> + if (data->vbios_boot_state.bsoc_vddc_lock) {
> + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> + PPSMC_MSG_SetFloorSocVoltage, 0);
> + data->vbios_boot_state.bsoc_vddc_lock = false;
> + }
> +
> if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_Falcon_QuickTransition)) {
> if (data->smu_features[GNLD_ACDC].supported) {
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 83c67b9..1912e08 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -177,8 +177,11 @@ struct vega10_dpmlevel_enable_mask {
> };
>
> struct vega10_vbios_boot_state {
> + bool bsoc_vddc_lock;
> uint16_t vddc;
> uint16_t vddci;
> + uint16_t mvddc;
> + uint16_t vdd_gfx;
> uint32_t gfx_clock;
> uint32_t mem_clock;
> uint32_t soc_clock;
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-05-02 14:02 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-02 8:56 [PATCH 1/2] drm/amd/powerplay: refine code in vega10_smumgr.c Rex Zhu
[not found] ` <1493715386-8098-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-05-02 8:56 ` [PATCH 2/2] drm/amd/powerplay: set soc floor voltage on boot on vega10 Rex Zhu
[not found] ` <1493715386-8098-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-05-02 14:02 ` Alex Deucher
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