* [PATCH 1/3] drm/amdgpu/pm: update MP v13_0_4 smu message register marco
@ 2022-05-26 18:00 Alex Deucher
2022-05-26 18:00 ` [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context Alex Deucher
2022-05-26 18:00 ` [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c Alex Deucher
0 siblings, 2 replies; 7+ messages in thread
From: Alex Deucher @ 2022-05-26 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tim Huang, Huang Rui
From: Huang Rui <ray.huang@amd.com>
Update MP v13_0_4 register macro for SMU message
v2: squash in missed case (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 5de7da75d14a..5215ead4978f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -51,6 +51,15 @@
#define mmMP1_SMN_C2PMSG_90 0x029a
#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282
+#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1
+
+#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292
+#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1
+
+#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a
+#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1
+
/* SMU 13.0.5 has its specific mailbox messaging registers */
#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
@@ -92,6 +101,8 @@ static void smu_cmn_read_arg(struct smu_context *smu,
if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
*arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
+ else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
+ *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
else
*arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
}
@@ -141,6 +152,8 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu)
for ( ; timeout > 0; timeout--) {
if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
+ else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
+ reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4);
else
reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
@@ -167,6 +180,9 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
+ } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
+ msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4);
+ prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
} else {
msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
@@ -268,6 +284,10 @@ static void __smu_cmn_send_msg(struct smu_context *smu,
WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
+ } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0);
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param);
+ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg);
} else {
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
--
2.35.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
2022-05-26 18:00 [PATCH 1/3] drm/amdgpu/pm: update MP v13_0_4 smu message register marco Alex Deucher
@ 2022-05-26 18:00 ` Alex Deucher
2022-05-31 21:15 ` Alex Deucher
2022-06-01 0:49 ` Wang, Yang(Kevin)
2022-05-26 18:00 ` [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c Alex Deucher
1 sibling, 2 replies; 7+ messages in thread
From: Alex Deucher @ 2022-05-26 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 ++++
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 9 +++++++++
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 14 ++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 18 ++++++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 14 ++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 14 ++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 1 +
17 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index a6a7b6c33683..36af1f417dcd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -563,6 +563,10 @@ struct smu_context
struct stb_context stb_context;
struct firmware pptable_firmware;
+
+ u32 param_reg;
+ u32 msg_reg;
+ u32 resp_reg;
};
struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
index acb3be292096..a9215494dcdd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
@@ -316,5 +316,7 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 036fd2810ecc..f60dcc4f7e75 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -298,5 +298,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
uint32_t size);
int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
+
+void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 201563072189..bfabcd3c45aa 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2509,4 +2509,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
smu->table_map = arcturus_table_map;
smu->pwr_src_map = arcturus_pwr_src_map;
smu->workload_map = arcturus_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index f1a4a720d426..ca4d97b7f576 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -591,4 +591,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
smu->message_map = cyan_skillfish_message_map;
smu->table_map = cyan_skillfish_table_map;
smu->is_apu = true;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 5f22fc3430f4..0bcd4fe0ef17 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -3580,4 +3580,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
smu->table_map = navi10_table_map;
smu->pwr_src_map = navi10_pwr_src_map;
smu->workload_map = navi10_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 6b452e3f5ee3..f6f21b516fd6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -4357,4 +4357,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
smu->table_map = sienna_cichlid_table_map;
smu->pwr_src_map = sienna_cichlid_pwr_src_map;
smu->workload_map = sienna_cichlid_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b87f550af26b..974b8fe1dbb6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -2197,3 +2197,12 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
return ret;
}
+
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 5551e1426ef5..e2d8ac90cf36 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -2213,4 +2213,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
smu->table_map = vangogh_table_map;
smu->workload_map = vangogh_workload_map;
smu->is_apu = true;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 012e3bd99cc2..85e22210963f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -41,6 +41,15 @@
#undef pr_info
#undef pr_debug
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+
static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
@@ -1447,6 +1456,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
void renoir_set_ppt_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->ppt_funcs = &renoir_ppt_funcs;
smu->message_map = renoir_message_map;
smu->clock_map = renoir_clk_map;
@@ -1454,4 +1465,7 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
smu->workload_map = renoir_workload_map;
smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
smu->is_apu = true;
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index fb130409309c..2e6a93869be8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -2117,4 +2117,5 @@ void aldebaran_set_ppt_funcs(struct smu_context *smu)
smu->clock_map = aldebaran_clk_map;
smu->feature_map = aldebaran_feature_mask_map;
smu->table_map = aldebaran_table_map;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 7be4f6875a7b..6fd3216b91d0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -60,6 +60,15 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+
#define SMU13_VOLTAGE_SCALE 4
#define LINK_WIDTH_MAX 6
@@ -2386,3 +2395,12 @@ int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
+
+void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 5c74a72577c6..418480e0c077 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1651,4 +1651,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
smu->table_map = smu_v13_0_0_table_map;
smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
smu->workload_map = smu_v13_0_0_workload_map;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 5a17b51aa0f9..8ccda593fc50 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -43,6 +43,15 @@
#undef pr_info
#undef pr_debug
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 1
+
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 1
+
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
@@ -1034,9 +1043,14 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
smu->message_map = smu_v13_0_4_message_map;
smu->feature_map = smu_v13_0_4_feature_mask_map;
smu->table_map = smu_v13_0_4_table_map;
smu->is_apu = true;
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index b81711c4ff33..47360ef5c175 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -42,6 +42,15 @@
#undef pr_info
#undef pr_debug
+#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_2_BASE_IDX 0
+
+#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_34_BASE_IDX 0
+
+#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_33_BASE_IDX 0
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -1049,9 +1058,14 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
smu->message_map = smu_v13_0_5_message_map;
smu->feature_map = smu_v13_0_5_feature_mask_map;
smu->table_map = smu_v13_0_5_table_map;
smu->is_apu = true;
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 4e1861fb2c6a..bdea7bca3805 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1594,4 +1594,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
smu->table_map = smu_v13_0_7_table_map;
smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
smu->workload_map = smu_v13_0_7_workload_map;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index feff4f8c927c..70cbc46341a3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -1203,4 +1203,5 @@ void yellow_carp_set_ppt_funcs(struct smu_context *smu)
smu->feature_map = yellow_carp_feature_mask_map;
smu->table_map = yellow_carp_table_map;
smu->is_apu = true;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
--
2.35.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c
2022-05-26 18:00 [PATCH 1/3] drm/amdgpu/pm: update MP v13_0_4 smu message register marco Alex Deucher
2022-05-26 18:00 ` [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context Alex Deucher
@ 2022-05-26 18:00 ` Alex Deucher
2022-05-31 21:15 ` Alex Deucher
2022-06-01 14:57 ` Luben Tuikov
1 sibling, 2 replies; 7+ messages in thread
From: Alex Deucher @ 2022-05-26 18:00 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Use the per asic offsets so the we don't have to have
asic specific logic in the common code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 77 +++-----------------------
1 file changed, 7 insertions(+), 70 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 5215ead4978f..53cd62ccab5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -37,40 +37,6 @@
#undef pr_info
#undef pr_debug
-/*
- * Although these are defined in each ASIC's specific header file.
- * They share the same definitions and values. That makes common
- * APIs for SMC messages issuing for all ASICs possible.
- */
-#define mmMP1_SMN_C2PMSG_66 0x0282
-#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
-
-#define mmMP1_SMN_C2PMSG_82 0x0292
-#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
-
-#define mmMP1_SMN_C2PMSG_90 0x029a
-#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
-
-#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282
-#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1
-
-#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292
-#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1
-
-#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a
-#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1
-
-/* SMU 13.0.5 has its specific mailbox messaging registers */
-
-#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
-#define mmMP1_C2PMSG_2_BASE_IDX 0
-
-#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
-#define mmMP1_C2PMSG_34_BASE_IDX 0
-
-#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
-#define mmMP1_C2PMSG_33_BASE_IDX 0
-
#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
#undef __SMU_DUMMY_MAP
@@ -99,12 +65,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
{
struct amdgpu_device *adev = smu->adev;
- if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
- *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
- else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
- *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
- else
- *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ *arg = RREG32(smu->param_reg);
}
/* Redefine the SMU error codes here.
@@ -150,12 +111,7 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu)
u32 reg;
for ( ; timeout > 0; timeout--) {
- if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
- reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
- else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
- reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4);
- else
- reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
+ reg = RREG32(smu->resp_reg);
if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
break;
@@ -177,16 +133,8 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
switch (reg_c2pmsg_90) {
case SMU_RESP_NONE: {
- if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
- msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
- prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
- } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
- msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4);
- prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
- } else {
- msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
- prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
- }
+ msg_idx = RREG32(smu->msg_reg);
+ prm = RREG32(smu->param_reg);
dev_err_ratelimited(adev->dev,
"SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
msg_idx, prm);
@@ -280,20 +228,9 @@ static void __smu_cmn_send_msg(struct smu_context *smu,
{
struct amdgpu_device *adev = smu->adev;
- if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
- WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
- WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
- WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
- } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0);
- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param);
- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg);
- } else {
- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
- }
-
+ WREG32(smu->resp_reg, 0);
+ WREG32(smu->param_reg, param);
+ WREG32(smu->msg_reg, msg);
}
/**
--
2.35.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
2022-05-26 18:00 ` [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context Alex Deucher
@ 2022-05-31 21:15 ` Alex Deucher
2022-06-01 0:49 ` Wang, Yang(Kevin)
1 sibling, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2022-05-31 21:15 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
Ping?
On Thu, May 26, 2022 at 2:00 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> So we can eventaully use them in the common smu code for
> accessing the SMU mailboxes without needing a lot of
> per asic logic in the common code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 ++++
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h | 2 ++
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++
> .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
> .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 1 +
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
> drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 9 +++++++++
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 14 ++++++++++++++
> .../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 1 +
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 18 ++++++++++++++++++
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 14 ++++++++++++++
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 14 ++++++++++++++
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 1 +
> 17 files changed, 86 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index a6a7b6c33683..36af1f417dcd 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -563,6 +563,10 @@ struct smu_context
> struct stb_context stb_context;
>
> struct firmware pptable_firmware;
> +
> + u32 param_reg;
> + u32 msg_reg;
> + u32 resp_reg;
> };
>
> struct i2c_adapter;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
> index acb3be292096..a9215494dcdd 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
> @@ -316,5 +316,7 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
>
> int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
>
> +void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
> +
> #endif
> #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> index 036fd2810ecc..f60dcc4f7e75 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
> @@ -298,5 +298,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
> uint32_t size);
>
> int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
> +
> +void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
> #endif
> #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> index 201563072189..bfabcd3c45aa 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
> @@ -2509,4 +2509,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
> smu->table_map = arcturus_table_map;
> smu->pwr_src_map = arcturus_pwr_src_map;
> smu->workload_map = arcturus_workload_map;
> + smu_v11_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> index f1a4a720d426..ca4d97b7f576 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
> @@ -591,4 +591,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
> smu->message_map = cyan_skillfish_message_map;
> smu->table_map = cyan_skillfish_table_map;
> smu->is_apu = true;
> + smu_v11_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 5f22fc3430f4..0bcd4fe0ef17 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -3580,4 +3580,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
> smu->table_map = navi10_table_map;
> smu->pwr_src_map = navi10_pwr_src_map;
> smu->workload_map = navi10_workload_map;
> + smu_v11_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 6b452e3f5ee3..f6f21b516fd6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -4357,4 +4357,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
> smu->table_map = sienna_cichlid_table_map;
> smu->pwr_src_map = sienna_cichlid_pwr_src_map;
> smu->workload_map = sienna_cichlid_workload_map;
> + smu_v11_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> index b87f550af26b..974b8fe1dbb6 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
> @@ -2197,3 +2197,12 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
>
> return ret;
> }
> +
> +void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
> +{
> + struct amdgpu_device *adev = smu->adev;
> +
> + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
> + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
> + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
> +}
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 5551e1426ef5..e2d8ac90cf36 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -2213,4 +2213,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
> smu->table_map = vangogh_table_map;
> smu->workload_map = vangogh_workload_map;
> smu->is_apu = true;
> + smu_v11_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> index 012e3bd99cc2..85e22210963f 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
> @@ -41,6 +41,15 @@
> #undef pr_info
> #undef pr_debug
>
> +#define mmMP1_SMN_C2PMSG_66 0x0282
> +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
> +
> +#define mmMP1_SMN_C2PMSG_82 0x0292
> +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
> +
> +#define mmMP1_SMN_C2PMSG_90 0x029a
> +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
> +
> static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
> MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
> @@ -1447,6 +1456,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
>
> void renoir_set_ppt_funcs(struct smu_context *smu)
> {
> + struct amdgpu_device *adev = smu->adev;
> +
> smu->ppt_funcs = &renoir_ppt_funcs;
> smu->message_map = renoir_message_map;
> smu->clock_map = renoir_clk_map;
> @@ -1454,4 +1465,7 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
> smu->workload_map = renoir_workload_map;
> smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
> smu->is_apu = true;
> + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
> + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
> + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> index fb130409309c..2e6a93869be8 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
> @@ -2117,4 +2117,5 @@ void aldebaran_set_ppt_funcs(struct smu_context *smu)
> smu->clock_map = aldebaran_clk_map;
> smu->feature_map = aldebaran_feature_mask_map;
> smu->table_map = aldebaran_table_map;
> + smu_v13_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 7be4f6875a7b..6fd3216b91d0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -60,6 +60,15 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
> MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
> MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
>
> +#define mmMP1_SMN_C2PMSG_66 0x0282
> +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
> +
> +#define mmMP1_SMN_C2PMSG_82 0x0292
> +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
> +
> +#define mmMP1_SMN_C2PMSG_90 0x029a
> +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
> +
> #define SMU13_VOLTAGE_SCALE 4
>
> #define LINK_WIDTH_MAX 6
> @@ -2386,3 +2395,12 @@ int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
> return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
> smu_table->clocks_table, false);
> }
> +
> +void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
> +{
> + struct amdgpu_device *adev = smu->adev;
> +
> + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
> + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
> + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
> +}
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index 5c74a72577c6..418480e0c077 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -1651,4 +1651,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
> smu->table_map = smu_v13_0_0_table_map;
> smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
> smu->workload_map = smu_v13_0_0_workload_map;
> + smu_v13_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> index 5a17b51aa0f9..8ccda593fc50 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
> @@ -43,6 +43,15 @@
> #undef pr_info
> #undef pr_debug
>
> +#define mmMP1_SMN_C2PMSG_66 0x0282
> +#define mmMP1_SMN_C2PMSG_66_BASE_IDX 1
> +
> +#define mmMP1_SMN_C2PMSG_82 0x0292
> +#define mmMP1_SMN_C2PMSG_82_BASE_IDX 1
> +
> +#define mmMP1_SMN_C2PMSG_90 0x029a
> +#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1
> +
> #define FEATURE_MASK(feature) (1ULL << feature)
>
> #define SMC_DPM_FEATURE ( \
> @@ -1034,9 +1043,14 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
>
> void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
> {
> + struct amdgpu_device *adev = smu->adev;
> +
> smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
> smu->message_map = smu_v13_0_4_message_map;
> smu->feature_map = smu_v13_0_4_feature_mask_map;
> smu->table_map = smu_v13_0_4_table_map;
> smu->is_apu = true;
> + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
> + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
> + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
> index b81711c4ff33..47360ef5c175 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
> @@ -42,6 +42,15 @@
> #undef pr_info
> #undef pr_debug
>
> +#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
> +#define mmMP1_C2PMSG_2_BASE_IDX 0
> +
> +#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
> +#define mmMP1_C2PMSG_34_BASE_IDX 0
> +
> +#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
> +#define mmMP1_C2PMSG_33_BASE_IDX 0
> +
> #define FEATURE_MASK(feature) (1ULL << feature)
> #define SMC_DPM_FEATURE ( \
> FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
> @@ -1049,9 +1058,14 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
>
> void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
> {
> + struct amdgpu_device *adev = smu->adev;
> +
> smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
> smu->message_map = smu_v13_0_5_message_map;
> smu->feature_map = smu_v13_0_5_feature_mask_map;
> smu->table_map = smu_v13_0_5_table_map;
> smu->is_apu = true;
> + smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
> + smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
> + smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 4e1861fb2c6a..bdea7bca3805 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -1594,4 +1594,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
> smu->table_map = smu_v13_0_7_table_map;
> smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
> smu->workload_map = smu_v13_0_7_workload_map;
> + smu_v13_0_set_smu_mailbox_registers(smu);
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> index feff4f8c927c..70cbc46341a3 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
> @@ -1203,4 +1203,5 @@ void yellow_carp_set_ppt_funcs(struct smu_context *smu)
> smu->feature_map = yellow_carp_feature_mask_map;
> smu->table_map = yellow_carp_table_map;
> smu->is_apu = true;
> + smu_v13_0_set_smu_mailbox_registers(smu);
> }
> --
> 2.35.3
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c
2022-05-26 18:00 ` [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c Alex Deucher
@ 2022-05-31 21:15 ` Alex Deucher
2022-06-01 14:57 ` Luben Tuikov
1 sibling, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2022-05-31 21:15 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
Ping?
On Thu, May 26, 2022 at 2:01 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> Use the per asic offsets so the we don't have to have
> asic specific logic in the common code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 77 +++-----------------------
> 1 file changed, 7 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index 5215ead4978f..53cd62ccab5d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -37,40 +37,6 @@
> #undef pr_info
> #undef pr_debug
>
> -/*
> - * Although these are defined in each ASIC's specific header file.
> - * They share the same definitions and values. That makes common
> - * APIs for SMC messages issuing for all ASICs possible.
> - */
> -#define mmMP1_SMN_C2PMSG_66 0x0282
> -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
> -
> -#define mmMP1_SMN_C2PMSG_82 0x0292
> -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
> -
> -#define mmMP1_SMN_C2PMSG_90 0x029a
> -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
> -
> -#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282
> -#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1
> -
> -#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292
> -#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1
> -
> -#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a
> -#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1
> -
> -/* SMU 13.0.5 has its specific mailbox messaging registers */
> -
> -#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
> -#define mmMP1_C2PMSG_2_BASE_IDX 0
> -
> -#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
> -#define mmMP1_C2PMSG_34_BASE_IDX 0
> -
> -#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
> -#define mmMP1_C2PMSG_33_BASE_IDX 0
> -
> #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
>
> #undef __SMU_DUMMY_MAP
> @@ -99,12 +65,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
> {
> struct amdgpu_device *adev = smu->adev;
>
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
> - *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
> - else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
> - *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
> - else
> - *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
> + *arg = RREG32(smu->param_reg);
> }
>
> /* Redefine the SMU error codes here.
> @@ -150,12 +111,7 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu)
> u32 reg;
>
> for ( ; timeout > 0; timeout--) {
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
> - reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
> - else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
> - reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4);
> - else
> - reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
> + reg = RREG32(smu->resp_reg);
> if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
> break;
>
> @@ -177,16 +133,8 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
>
> switch (reg_c2pmsg_90) {
> case SMU_RESP_NONE: {
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
> - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
> - prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
> - } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
> - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4);
> - prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
> - } else {
> - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
> - prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
> - }
> + msg_idx = RREG32(smu->msg_reg);
> + prm = RREG32(smu->param_reg);
> dev_err_ratelimited(adev->dev,
> "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
> msg_idx, prm);
> @@ -280,20 +228,9 @@ static void __smu_cmn_send_msg(struct smu_context *smu,
> {
> struct amdgpu_device *adev = smu->adev;
>
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
> - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
> - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
> - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
> - } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg);
> - } else {
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
> - }
> -
> + WREG32(smu->resp_reg, 0);
> + WREG32(smu->param_reg, param);
> + WREG32(smu->msg_reg, msg);
> }
>
> /**
> --
> 2.35.3
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
2022-05-26 18:00 ` [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context Alex Deucher
2022-05-31 21:15 ` Alex Deucher
@ 2022-06-01 0:49 ` Wang, Yang(Kevin)
1 sibling, 0 replies; 7+ messages in thread
From: Wang, Yang(Kevin) @ 2022-06-01 0:49 UTC (permalink / raw)
To: Deucher, Alexander, amd-gfx
[-- Attachment #1: Type: text/plain, Size: 16092 bytes --]
[AMD Official Use Only - General]
Series is
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexander.deucher@amd.com>
Sent: Friday, May 27, 2022 2:00 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for
accessing the SMU mailboxes without needing a lot of
per asic logic in the common code.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 ++++
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 +
.../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 1 +
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 9 +++++++++
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 1 +
.../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 14 ++++++++++++++
.../gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c | 1 +
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 18 ++++++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 14 ++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 14 ++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 1 +
.../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 1 +
17 files changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index a6a7b6c33683..36af1f417dcd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -563,6 +563,10 @@ struct smu_context
struct stb_context stb_context;
struct firmware pptable_firmware;
+
+ u32 param_reg;
+ u32 msg_reg;
+ u32 resp_reg;
};
struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
index acb3be292096..a9215494dcdd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0.h
@@ -316,5 +316,7 @@ int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 036fd2810ecc..f60dcc4f7e75 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -298,5 +298,7 @@ int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
uint32_t size);
int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
+
+void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 201563072189..bfabcd3c45aa 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -2509,4 +2509,5 @@ void arcturus_set_ppt_funcs(struct smu_context *smu)
smu->table_map = arcturus_table_map;
smu->pwr_src_map = arcturus_pwr_src_map;
smu->workload_map = arcturus_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
index f1a4a720d426..ca4d97b7f576 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c
@@ -591,4 +591,5 @@ void cyan_skillfish_set_ppt_funcs(struct smu_context *smu)
smu->message_map = cyan_skillfish_message_map;
smu->table_map = cyan_skillfish_table_map;
smu->is_apu = true;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 5f22fc3430f4..0bcd4fe0ef17 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -3580,4 +3580,5 @@ void navi10_set_ppt_funcs(struct smu_context *smu)
smu->table_map = navi10_table_map;
smu->pwr_src_map = navi10_pwr_src_map;
smu->workload_map = navi10_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 6b452e3f5ee3..f6f21b516fd6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -4357,4 +4357,5 @@ void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
smu->table_map = sienna_cichlid_table_map;
smu->pwr_src_map = sienna_cichlid_pwr_src_map;
smu->workload_map = sienna_cichlid_workload_map;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index b87f550af26b..974b8fe1dbb6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -2197,3 +2197,12 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
return ret;
}
+
+void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 5551e1426ef5..e2d8ac90cf36 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -2213,4 +2213,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
smu->table_map = vangogh_table_map;
smu->workload_map = vangogh_workload_map;
smu->is_apu = true;
+ smu_v11_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index 012e3bd99cc2..85e22210963f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -41,6 +41,15 @@
#undef pr_info
#undef pr_debug
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+
static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
@@ -1447,6 +1456,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
void renoir_set_ppt_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->ppt_funcs = &renoir_ppt_funcs;
smu->message_map = renoir_message_map;
smu->clock_map = renoir_clk_map;
@@ -1454,4 +1465,7 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
smu->workload_map = renoir_workload_map;
smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
smu->is_apu = true;
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index fb130409309c..2e6a93869be8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -2117,4 +2117,5 @@ void aldebaran_set_ppt_funcs(struct smu_context *smu)
smu->clock_map = aldebaran_clk_map;
smu->feature_map = aldebaran_feature_mask_map;
smu->table_map = aldebaran_table_map;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 7be4f6875a7b..6fd3216b91d0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -60,6 +60,15 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
MODULE_FIRMWARE("amdgpu/smu_13_0_0.bin");
MODULE_FIRMWARE("amdgpu/smu_13_0_7.bin");
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
+
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
+
#define SMU13_VOLTAGE_SCALE 4
#define LINK_WIDTH_MAX 6
@@ -2386,3 +2395,12 @@ int smu_v13_0_set_default_dpm_tables(struct smu_context *smu)
return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0,
smu_table->clocks_table, false);
}
+
+void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+ struct amdgpu_device *adev = smu->adev;
+
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 5c74a72577c6..418480e0c077 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1651,4 +1651,5 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
smu->table_map = smu_v13_0_0_table_map;
smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
smu->workload_map = smu_v13_0_0_workload_map;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index 5a17b51aa0f9..8ccda593fc50 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -43,6 +43,15 @@
#undef pr_info
#undef pr_debug
+#define mmMP1_SMN_C2PMSG_66 0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX 1
+
+#define mmMP1_SMN_C2PMSG_82 0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX 1
+
+#define mmMP1_SMN_C2PMSG_90 0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX 1
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
@@ -1034,9 +1043,14 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
smu->message_map = smu_v13_0_4_message_map;
smu->feature_map = smu_v13_0_4_feature_mask_map;
smu->table_map = smu_v13_0_4_table_map;
smu->is_apu = true;
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
index b81711c4ff33..47360ef5c175 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c
@@ -42,6 +42,15 @@
#undef pr_info
#undef pr_debug
+#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_2_BASE_IDX 0
+
+#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_34_BASE_IDX 0
+
+#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
+#define mmMP1_C2PMSG_33_BASE_IDX 0
+
#define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
@@ -1049,9 +1058,14 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = {
void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu)
{
+ struct amdgpu_device *adev = smu->adev;
+
smu->ppt_funcs = &smu_v13_0_5_ppt_funcs;
smu->message_map = smu_v13_0_5_message_map;
smu->feature_map = smu_v13_0_5_feature_mask_map;
smu->table_map = smu_v13_0_5_table_map;
smu->is_apu = true;
+ smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34);
+ smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2);
+ smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 4e1861fb2c6a..bdea7bca3805 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1594,4 +1594,5 @@ void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
smu->table_map = smu_v13_0_7_table_map;
smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
smu->workload_map = smu_v13_0_7_workload_map;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
index feff4f8c927c..70cbc46341a3 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
@@ -1203,4 +1203,5 @@ void yellow_carp_set_ppt_funcs(struct smu_context *smu)
smu->feature_map = yellow_carp_feature_mask_map;
smu->table_map = yellow_carp_table_map;
smu->is_apu = true;
+ smu_v13_0_set_smu_mailbox_registers(smu);
}
--
2.35.3
[-- Attachment #2: Type: text/html, Size: 30166 bytes --]
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c
2022-05-26 18:00 ` [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c Alex Deucher
2022-05-31 21:15 ` Alex Deucher
@ 2022-06-01 14:57 ` Luben Tuikov
1 sibling, 0 replies; 7+ messages in thread
From: Luben Tuikov @ 2022-06-01 14:57 UTC (permalink / raw)
To: Alex Deucher, amd-gfx
Yes, this is a good change--abstracting the SMU messaging registers for ASICs.
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
On 2022-05-26 14:00, Alex Deucher wrote:
> Use the per asic offsets so the we don't have to have
> asic specific logic in the common code.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 77 +++-----------------------
> 1 file changed, 7 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> index 5215ead4978f..53cd62ccab5d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
> @@ -37,40 +37,6 @@
> #undef pr_info
> #undef pr_debug
>
> -/*
> - * Although these are defined in each ASIC's specific header file.
> - * They share the same definitions and values. That makes common
> - * APIs for SMC messages issuing for all ASICs possible.
> - */
> -#define mmMP1_SMN_C2PMSG_66 0x0282
> -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
> -
> -#define mmMP1_SMN_C2PMSG_82 0x0292
> -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
> -
> -#define mmMP1_SMN_C2PMSG_90 0x029a
> -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
> -
> -#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282
> -#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1
> -
> -#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292
> -#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1
> -
> -#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a
> -#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1
> -
> -/* SMU 13.0.5 has its specific mailbox messaging registers */
> -
> -#define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4)
> -#define mmMP1_C2PMSG_2_BASE_IDX 0
> -
> -#define mmMP1_C2PMSG_34 (0xbee262 + 0xb00000 / 4)
> -#define mmMP1_C2PMSG_34_BASE_IDX 0
> -
> -#define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4)
> -#define mmMP1_C2PMSG_33_BASE_IDX 0
> -
> #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
>
> #undef __SMU_DUMMY_MAP
> @@ -99,12 +65,7 @@ static void smu_cmn_read_arg(struct smu_context *smu,
> {
> struct amdgpu_device *adev = smu->adev;
>
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
> - *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
> - else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
> - *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
> - else
> - *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
> + *arg = RREG32(smu->param_reg);
> }
>
> /* Redefine the SMU error codes here.
> @@ -150,12 +111,7 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu)
> u32 reg;
>
> for ( ; timeout > 0; timeout--) {
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5))
> - reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33);
> - else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
> - reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4);
> - else
> - reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
> + reg = RREG32(smu->resp_reg);
> if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
> break;
>
> @@ -177,16 +133,8 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu,
>
> switch (reg_c2pmsg_90) {
> case SMU_RESP_NONE: {
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
> - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2);
> - prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34);
> - } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
> - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4);
> - prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4);
> - } else {
> - msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66);
> - prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
> - }
> + msg_idx = RREG32(smu->msg_reg);
> + prm = RREG32(smu->param_reg);
> dev_err_ratelimited(adev->dev,
> "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
> msg_idx, prm);
> @@ -280,20 +228,9 @@ static void __smu_cmn_send_msg(struct smu_context *smu,
> {
> struct amdgpu_device *adev = smu->adev;
>
> - if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) {
> - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0);
> - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param);
> - WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg);
> - } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) {
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg);
> - } else {
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
> - WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
> - }
> -
> + WREG32(smu->resp_reg, 0);
> + WREG32(smu->param_reg, param);
> + WREG32(smu->msg_reg, msg);
> }
>
> /**
Regards,
--
Luben
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-06-01 14:57 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-26 18:00 [PATCH 1/3] drm/amdgpu/pm: update MP v13_0_4 smu message register marco Alex Deucher
2022-05-26 18:00 ` [PATCH 2/3] drm/amdgpu/swsmu: add SMU mailbox registers in SMU context Alex Deucher
2022-05-31 21:15 ` Alex Deucher
2022-06-01 0:49 ` Wang, Yang(Kevin)
2022-05-26 18:00 ` [PATCH 3/3] drm/amdgpu/swsmu: use new register offsets for smu_cmn.c Alex Deucher
2022-05-31 21:15 ` Alex Deucher
2022-06-01 14:57 ` Luben Tuikov
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