* [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
@ 2022-05-26 17:57 Alex Deucher
2022-05-31 21:14 ` Alex Deucher
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-26 17:57 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Tim Huang
Set the default reset method to mode2 for SMU IP v13.0.4
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 9e18a2b22607..a400f5273343 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -310,6 +310,7 @@ static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device *adev)
{
if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
+ amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
amdgpu_reset_method == AMD_RESET_METHOD_BACO)
return amdgpu_reset_method;
@@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
return AMD_RESET_METHOD_MODE1;
+ case IP_VERSION(13, 0, 4):
+ return AMD_RESET_METHOD_MODE2;
default:
if (amdgpu_dpm_is_baco_supported(adev))
return AMD_RESET_METHOD_BACO;
@@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device *adev)
dev_info(adev->dev, "BACO reset\n");
ret = amdgpu_dpm_baco_reset(adev);
break;
+ case AMD_RESET_METHOD_MODE2:
+ dev_info(adev->dev, "MODE2 reset\n");
+ ret = amdgpu_dpm_mode2_reset(adev);
+ break;
default:
dev_info(adev->dev, "MODE1 reset\n");
ret = amdgpu_device_mode1_reset(adev);
--
2.35.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
2022-05-26 17:57 [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4 Alex Deucher
@ 2022-05-31 21:14 ` Alex Deucher
2022-06-02 7:53 ` Quan, Evan
2022-06-06 9:23 ` Huang, Tim
2 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-31 21:14 UTC (permalink / raw)
To: Alex Deucher; +Cc: Tim Huang, amd-gfx list
Ping?
On Thu, May 26, 2022 at 1:58 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>
> Set the default reset method to mode2 for SMU IP v13.0.4
>
> Signed-off-by: Tim Huang <tim.huang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 9e18a2b22607..a400f5273343 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -310,6 +310,7 @@ static enum amd_reset_method
> soc21_asic_reset_method(struct amdgpu_device *adev)
> {
> if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
> + amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
> amdgpu_reset_method == AMD_RESET_METHOD_BACO)
> return amdgpu_reset_method;
>
> @@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
> switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 0):
> return AMD_RESET_METHOD_MODE1;
> + case IP_VERSION(13, 0, 4):
> + return AMD_RESET_METHOD_MODE2;
> default:
> if (amdgpu_dpm_is_baco_supported(adev))
> return AMD_RESET_METHOD_BACO;
> @@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device *adev)
> dev_info(adev->dev, "BACO reset\n");
> ret = amdgpu_dpm_baco_reset(adev);
> break;
> + case AMD_RESET_METHOD_MODE2:
> + dev_info(adev->dev, "MODE2 reset\n");
> + ret = amdgpu_dpm_mode2_reset(adev);
> + break;
> default:
> dev_info(adev->dev, "MODE1 reset\n");
> ret = amdgpu_device_mode1_reset(adev);
> --
> 2.35.3
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
2022-05-26 17:57 [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4 Alex Deucher
2022-05-31 21:14 ` Alex Deucher
@ 2022-06-02 7:53 ` Quan, Evan
2022-06-06 9:23 ` Huang, Tim
2 siblings, 0 replies; 4+ messages in thread
From: Quan, Evan @ 2022-06-02 7:53 UTC (permalink / raw)
To: Deucher, Alexander, amd-gfx; +Cc: Deucher, Alexander, Huang, Tim
[AMD Official Use Only - General]
Acked-by: Evan Quan <evan.quan@amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Friday, May 27, 2022 1:58 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Tim
> <Tim.Huang@amd.com>
> Subject: [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP
> v13.0.4
>
> Set the default reset method to mode2 for SMU IP v13.0.4
>
> Signed-off-by: Tim Huang <tim.huang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
> b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 9e18a2b22607..a400f5273343 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -310,6 +310,7 @@ static enum amd_reset_method
> soc21_asic_reset_method(struct amdgpu_device *adev) {
> if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
> + amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
> amdgpu_reset_method == AMD_RESET_METHOD_BACO)
> return amdgpu_reset_method;
>
> @@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device
> *adev)
> switch (adev->ip_versions[MP1_HWIP][0]) {
> case IP_VERSION(13, 0, 0):
> return AMD_RESET_METHOD_MODE1;
> + case IP_VERSION(13, 0, 4):
> + return AMD_RESET_METHOD_MODE2;
> default:
> if (amdgpu_dpm_is_baco_supported(adev))
> return AMD_RESET_METHOD_BACO;
> @@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device
> *adev)
> dev_info(adev->dev, "BACO reset\n");
> ret = amdgpu_dpm_baco_reset(adev);
> break;
> + case AMD_RESET_METHOD_MODE2:
> + dev_info(adev->dev, "MODE2 reset\n");
> + ret = amdgpu_dpm_mode2_reset(adev);
> + break;
> default:
> dev_info(adev->dev, "MODE1 reset\n");
> ret = amdgpu_device_mode1_reset(adev);
> --
> 2.35.3
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
2022-05-26 17:57 [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4 Alex Deucher
2022-05-31 21:14 ` Alex Deucher
2022-06-02 7:53 ` Quan, Evan
@ 2022-06-06 9:23 ` Huang, Tim
2 siblings, 0 replies; 4+ messages in thread
From: Huang, Tim @ 2022-06-06 9:23 UTC (permalink / raw)
To: Deucher, Alexander, amd-gfx; +Cc: Quan, Evan
[AMD Official Use Only - General]
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
-----Original Message-----
From: Deucher, Alexander <Alexander.Deucher@amd.com>
Sent: Friday, May 27, 2022 1:58 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Tim <Tim.Huang@amd.com>
Subject: [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4
Set the default reset method to mode2 for SMU IP v13.0.4
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 9e18a2b22607..a400f5273343 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -310,6 +310,7 @@ static enum amd_reset_method soc21_asic_reset_method(struct amdgpu_device *adev) {
if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
+ amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
amdgpu_reset_method == AMD_RESET_METHOD_BACO)
return amdgpu_reset_method;
@@ -320,6 +321,8 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
return AMD_RESET_METHOD_MODE1;
+ case IP_VERSION(13, 0, 4):
+ return AMD_RESET_METHOD_MODE2;
default:
if (amdgpu_dpm_is_baco_supported(adev))
return AMD_RESET_METHOD_BACO;
@@ -341,6 +344,10 @@ static int soc21_asic_reset(struct amdgpu_device *adev)
dev_info(adev->dev, "BACO reset\n");
ret = amdgpu_dpm_baco_reset(adev);
break;
+ case AMD_RESET_METHOD_MODE2:
+ dev_info(adev->dev, "MODE2 reset\n");
+ ret = amdgpu_dpm_mode2_reset(adev);
+ break;
default:
dev_info(adev->dev, "MODE1 reset\n");
ret = amdgpu_device_mode1_reset(adev);
--
2.35.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-06-06 9:23 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-05-26 17:57 [PATCH] drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.4 Alex Deucher
2022-05-31 21:14 ` Alex Deucher
2022-06-02 7:53 ` Quan, Evan
2022-06-06 9:23 ` Huang, Tim
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