* [PATCH v2 0/7] ARM: sunxi: Switch to clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
Hi,
We currently have in our clock driver a logic very similar to the one
that clock-indices is supposed to cover.
Using this property, we can create a new driver generic for all gates
that will get the valid indices directly from the device tree, instead
of storing that in the driver itself.
While we're at it, we also move to using CLK_OF_DECLARE for that new
driver, which should ease the orphan clocks breakage we saw.
Let me know what you think,
Maxime
Changes from v1:
- Remove unused headers in the driver
- Fix the wrong commit log for the A80
Maxime Ripard (7):
ARM: sun4i: Add clock indices
ARM: sun5i: Add clock indices
ARM: sun6i: Add clock indices
ARM: sun7i: Add clock indices
ARM: sun8i: Add clock indices
ARM: sun9i: Wrap the clock-indices
clk: sunxi: Add a simple gates driver
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++----
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 ++++-
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 24 +++++
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++
arch/arm/boot/dts/sun9i-a80.dtsi | 32 +++++--
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
11 files changed, 333 insertions(+), 207 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 0/7] ARM: sunxi: Switch to clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
We currently have in our clock driver a logic very similar to the one
that clock-indices is supposed to cover.
Using this property, we can create a new driver generic for all gates
that will get the valid indices directly from the device tree, instead
of storing that in the driver itself.
While we're at it, we also move to using CLK_OF_DECLARE for that new
driver, which should ease the orphan clocks breakage we saw.
Let me know what you think,
Maxime
Changes from v1:
- Remove unused headers in the driver
- Fix the wrong commit log for the A80
Maxime Ripard (7):
ARM: sun4i: Add clock indices
ARM: sun5i: Add clock indices
ARM: sun6i: Add clock indices
ARM: sun7i: Add clock indices
ARM: sun8i: Add clock indices
ARM: sun9i: Wrap the clock-indices
clk: sunxi: Add a simple gates driver
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++----
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 ++++-
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 24 +++++
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++
arch/arm/boot/dts/sun9i-a80.dtsi | 32 +++++--
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
11 files changed, 333 insertions(+), 207 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
--
2.4.6
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 1/7] ARM: sun4i: Add clock indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: linux-clk, Chen-Yu Tsai, linux-arm-kernel, Maxime Ripard
The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++++++++++++++++++++++----------
1 file changed, 52 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 61c03d1fe530..ab0e131587bb 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -241,6 +241,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
@@ -257,17 +258,36 @@
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>,
+ <21>, <22>, <23>,
+ <24>, <25>, <26>,
+ <32>, <33>, <34>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <45>,
+ <46>, <47>,
+ <50>, <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ "ahb_ohci0", "ahb_ehci1",
+ "ahb_ohci1", "ahb_ss", "ahb_dma",
+ "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0",
+ "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps",
+ "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
+ "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1",
+ "ahb_de_fe0", "ahb_de_fe1",
+ "ahb_mp", "ahb_mali400";
};
apb0: apb0@01c20054 {
@@ -283,9 +303,14 @@
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <5>, <6>,
+ <7>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ "apb0_ac97", "apb0_iis",
+ "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
};
apb1: clk@01c20058 {
@@ -301,12 +326,22 @@
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <4>,
+ <5>, <6>,
+ <7>, <16>,
+ <17>, <18>,
+ <19>, <20>,
+ <21>, <22>,
+ <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_can",
+ "apb1_scr", "apb1_ps20",
+ "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
};
nand_clk: clk@01c20080 {
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 1/7] ARM: sun4i: Add clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++++++++++++++++++++++----------
1 file changed, 52 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 61c03d1fe530..ab0e131587bb 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -241,6 +241,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
@@ -257,17 +258,36 @@
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>,
+ <21>, <22>, <23>,
+ <24>, <25>, <26>,
+ <32>, <33>, <34>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <45>,
+ <46>, <47>,
+ <50>, <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ "ahb_ohci0", "ahb_ehci1",
+ "ahb_ohci1", "ahb_ss", "ahb_dma",
+ "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0",
+ "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps",
+ "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
+ "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1",
+ "ahb_de_fe0", "ahb_de_fe1",
+ "ahb_mp", "ahb_mali400";
};
apb0: apb0 at 01c20054 {
@@ -283,9 +303,14 @@
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <5>, <6>,
+ <7>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ "apb0_ac97", "apb0_iis",
+ "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
};
apb1: clk at 01c20058 {
@@ -301,12 +326,22 @@
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <4>,
+ <5>, <6>,
+ <7>, <16>,
+ <17>, <18>,
+ <19>, <20>,
+ <21>, <22>,
+ <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_can",
+ "apb1_scr", "apb1_ps20",
+ "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
};
nand_clk: clk at 01c20080 {
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/7] ARM: sun5i: Add clock indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 +++++++++++++++++++++--
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++++++++++++++++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index f11efb722bbb..a513b416a807 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -85,6 +85,17 @@
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <17>, <18>,
+ <20>, <21>, <22>,
+ <26>, <28>, <32>,
+ <34>, <36>, <40>,
+ <43>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -103,6 +114,9 @@
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <3>,
+ <5>, <6>,
+ <10>;
clock-output-names = "apb0_codec", "apb0_iis",
"apb0_pio", "apb0_ir",
"apb0_keypad";
@@ -113,9 +127,14 @@
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3";
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 976d4faa2179..f3631c9c6fa2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -104,6 +104,16 @@
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <20>,
+ <21>, <22>,
+ <28>, <32>, <36>,
+ <40>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -121,6 +131,8 @@
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <5>,
+ <6>;
clock-output-names = "apb0_codec", "apb0_pio",
"apb0_ir";
};
@@ -130,8 +142,12 @@
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <17>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart1",
+ "apb1_uart3";
};
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 54b097830434..427c0e7289fa 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -178,6 +178,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/7] ARM: sun5i: Add clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 +++++++++++++++++++++--
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++++++++++++++++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index f11efb722bbb..a513b416a807 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -85,6 +85,17 @@
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <17>, <18>,
+ <20>, <21>, <22>,
+ <26>, <28>, <32>,
+ <34>, <36>, <40>,
+ <43>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -103,6 +114,9 @@
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <3>,
+ <5>, <6>,
+ <10>;
clock-output-names = "apb0_codec", "apb0_iis",
"apb0_pio", "apb0_ir",
"apb0_keypad";
@@ -113,9 +127,14 @@
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3";
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 976d4faa2179..f3631c9c6fa2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -104,6 +104,16 @@
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <20>,
+ <21>, <22>,
+ <28>, <32>, <36>,
+ <40>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -121,6 +131,8 @@
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <5>,
+ <6>;
clock-output-names = "apb0_codec", "apb0_pio",
"apb0_ir";
};
@@ -130,8 +142,12 @@
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <17>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart1",
+ "apb1_uart3";
};
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 54b097830434..427c0e7289fa 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -178,6 +178,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/7] ARM: sun6i: Add clock indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a018cf..3ec456fa03a4 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -252,6 +252,20 @@
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>,
+ <17>, <18>, <19>,
+ <20>, <21>, <22>,
+ <23>, <24>, <26>,
+ <27>, <29>,
+ <30>, <31>, <32>,
+ <36>, <37>, <40>,
+ <43>, <44>, <45>,
+ <46>, <47>, <50>,
+ <52>, <55>, <56>,
+ <57>, <58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
@@ -281,6 +295,9 @@
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <4>,
+ <5>, <12>,
+ <13>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
@@ -299,6 +316,10 @@
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <16>,
+ <17>, <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3",
"apb2_uart0", "apb2_uart1",
@@ -384,6 +405,9 @@
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
+ clock-indices = <8>, <9>, <10>,
+ <16>, <17>,
+ <18>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/7] ARM: sun6i: Add clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a018cf..3ec456fa03a4 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -252,6 +252,20 @@
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>,
+ <17>, <18>, <19>,
+ <20>, <21>, <22>,
+ <23>, <24>, <26>,
+ <27>, <29>,
+ <30>, <31>, <32>,
+ <36>, <37>, <40>,
+ <43>, <44>, <45>,
+ <46>, <47>, <50>,
+ <52>, <55>, <56>,
+ <57>, <58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
@@ -281,6 +295,9 @@
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <4>,
+ <5>, <12>,
+ <13>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
@@ -299,6 +316,10 @@
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <16>,
+ <17>, <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3",
"apb2_uart0", "apb2_uart1",
@@ -384,6 +405,9 @@
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
+ clock-indices = <8>, <9>, <10>,
+ <16>, <17>,
+ <18>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 4/7] ARM: sun7i: Add clock indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6a63f30c9a69..ca0b01a96c52 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -267,6 +267,19 @@
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>, <21>,
+ <22>, <23>, <25>,
+ <28>, <32>, <33>, <34>,
+ <35>, <36>, <37>, <40>,
+ <41>, <42>, <43>,
+ <44>, <45>, <46>,
+ <47>, <49>, <50>,
+ <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
@@ -295,6 +308,10 @@
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <8>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis0", "apb0_iis1",
"apb0_pio", "apb0_ir0", "apb0_ir1",
@@ -314,6 +331,12 @@
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <15>, <16>, <17>,
+ <18>, <19>, <20>,
+ <21>, <22>, <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_can",
"apb1_scr", "apb1_ps20", "apb1_ps21",
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 4/7] ARM: sun7i: Add clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6a63f30c9a69..ca0b01a96c52 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -267,6 +267,19 @@
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>, <21>,
+ <22>, <23>, <25>,
+ <28>, <32>, <33>, <34>,
+ <35>, <36>, <37>, <40>,
+ <41>, <42>, <43>,
+ <44>, <45>, <46>,
+ <47>, <49>, <50>,
+ <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
@@ -295,6 +308,10 @@
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <8>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis0", "apb0_iis1",
"apb0_pio", "apb0_ir0", "apb0_ir1",
@@ -314,6 +331,12 @@
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <15>, <16>, <17>,
+ <18>, <19>, <20>,
+ <21>, <22>, <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_can",
"apb1_scr", "apb1_ps20", "apb1_ps21",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7abd0ae3143d..c318c770b6c1 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -180,6 +180,15 @@
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <6>,
+ <8>, <9>, <10>,
+ <13>, <14>,
+ <19>, <20>,
+ <21>, <24>, <26>,
+ <29>, <32>, <36>,
+ <40>, <44>, <46>,
+ <52>, <54>,
+ <57>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
@@ -196,6 +205,8 @@
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <5>,
+ <12>, <13>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
@@ -213,6 +224,10 @@
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>, <20>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7abd0ae3143d..c318c770b6c1 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -180,6 +180,15 @@
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <6>,
+ <8>, <9>, <10>,
+ <13>, <14>,
+ <19>, <20>,
+ <21>, <24>, <26>,
+ <29>, <32>, <36>,
+ <40>, <44>, <46>,
+ <52>, <54>,
+ <57>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
@@ -196,6 +205,8 @@
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <5>,
+ <12>, <13>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
@@ -213,6 +224,10 @@
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>, <20>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 6/7] ARM: sun9i: Wrap the clock-indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
Wrap the clock-indices to match the wrapping of the clock-output-names in
order to make it easier to match indices to names.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a43ad779ee2f..5908e3dcf965 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -277,9 +277,12 @@
compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
reg = <0x06000580 0x4>;
clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
- <14>, <15>, <16>, <18>, <20>, <21>,
- <22>, <23>;
+ clock-indices = <0>, <1>, <3>,
+ <5>, <8>, <12>,
+ <13>, <14>,
+ <15>, <16>, <18>,
+ <20>, <21>, <22>,
+ <23>;
clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
"ahb0_ss", "ahb0_sd", "ahb0_nand1",
"ahb0_nand0", "ahb0_sdram",
@@ -293,7 +296,10 @@
compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
reg = <0x06000584 0x4>;
clocks = <&ahb1>;
- clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+ clock-indices = <0>, <1>,
+ <17>, <21>,
+ <22>, <23>,
+ <24>;
clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
"ahb1_gmac", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_hstimer",
@@ -305,8 +311,9 @@
compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
reg = <0x06000588 0x4>;
clocks = <&ahb2>;
- clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
- <11>;
+ clock-indices = <0>, <1>,
+ <2>, <4>, <5>,
+ <7>, <8>, <11>;
clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
@@ -317,8 +324,10 @@
compatible = "allwinner,sun9i-a80-apb0-gates-clk";
reg = <0x06000590 0x4>;
clocks = <&apb0>;
- clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
- <17>, <18>, <19>;
+ clock-indices = <1>, <5>,
+ <11>, <12>, <13>,
+ <15>, <17>, <18>,
+ <19>;
clock-output-names = "apb0_spdif", "apb0_pio",
"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
"apb0_lradc", "apb0_gpadc", "apb0_twd",
@@ -330,8 +339,11 @@
compatible = "allwinner,sun9i-a80-apb1-gates-clk";
reg = <0x06000594 0x4>;
clocks = <&apb1>;
- clock-indices = <0>, <1>, <2>, <3>, <4>,
- <16>, <17>, <18>, <19>, <20>, <21>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <16>, <17>,
+ <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
"apb1_uart0", "apb1_uart1",
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 6/7] ARM: sun9i: Wrap the clock-indices
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
Wrap the clock-indices to match the wrapping of the clock-output-names in
order to make it easier to match indices to names.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a43ad779ee2f..5908e3dcf965 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -277,9 +277,12 @@
compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
reg = <0x06000580 0x4>;
clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
- <14>, <15>, <16>, <18>, <20>, <21>,
- <22>, <23>;
+ clock-indices = <0>, <1>, <3>,
+ <5>, <8>, <12>,
+ <13>, <14>,
+ <15>, <16>, <18>,
+ <20>, <21>, <22>,
+ <23>;
clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
"ahb0_ss", "ahb0_sd", "ahb0_nand1",
"ahb0_nand0", "ahb0_sdram",
@@ -293,7 +296,10 @@
compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
reg = <0x06000584 0x4>;
clocks = <&ahb1>;
- clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+ clock-indices = <0>, <1>,
+ <17>, <21>,
+ <22>, <23>,
+ <24>;
clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
"ahb1_gmac", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_hstimer",
@@ -305,8 +311,9 @@
compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
reg = <0x06000588 0x4>;
clocks = <&ahb2>;
- clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
- <11>;
+ clock-indices = <0>, <1>,
+ <2>, <4>, <5>,
+ <7>, <8>, <11>;
clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
@@ -317,8 +324,10 @@
compatible = "allwinner,sun9i-a80-apb0-gates-clk";
reg = <0x06000590 0x4>;
clocks = <&apb0>;
- clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
- <17>, <18>, <19>;
+ clock-indices = <1>, <5>,
+ <11>, <12>, <13>,
+ <15>, <17>, <18>,
+ <19>;
clock-output-names = "apb0_spdif", "apb0_pio",
"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
"apb0_lradc", "apb0_gpadc", "apb0_twd",
@@ -330,8 +339,11 @@
compatible = "allwinner,sun9i-a80-apb1-gates-clk";
reg = <0x06000594 0x4>;
clocks = <&apb1>;
- clock-indices = <0>, <1>, <2>, <3>, <4>,
- <16>, <17>, <18>, <19>, <20>, <21>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <16>, <17>,
+ <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
"apb1_uart0", "apb1_uart1",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 7/7] clk: sunxi: Add a simple gates driver
2015-07-31 17:46 ` Maxime Ripard
@ 2015-07-31 17:46 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: linux-clk, Chen-Yu Tsai, linux-arm-kernel, Maxime Ripard
The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.
Move this code in a new driver that handles all the gates array and solves
both these issues.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
3 files changed, 158 insertions(+), 177 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 058f273d6154..f5a35b82cc1a 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-hosc.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
+obj-y += clk-simple-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
new file mode 100644
index 000000000000..39e57e3d745c
--- /dev/null
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_simple_gates_setup(struct device_node *node,
+ const int protected[],
+ int nprotected)
+{
+ struct clk_onecell_data *clk_data;
+ const char *clk_parent, *clk_name;
+ struct property *prop;
+ struct resource res;
+ void __iomem *clk_reg;
+ void __iomem *reg;
+ const __be32 *p;
+ int number, i = 0, j;
+ u8 clk_bit;
+ u32 index;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg))
+ return;
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err_unmap;
+
+ number = of_property_count_u32_elems(node, "clock-indices");
+ of_property_read_u32_index(node, "clock-indices", number - 1, &number);
+
+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err_free_data;
+
+ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+ of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+
+ clk_reg = reg + 4 * (index / 32);
+ clk_bit = index % 32;
+
+ clk_data->clks[index] = clk_register_gate(NULL, clk_name,
+ clk_parent, 0,
+ clk_reg,
+ clk_bit,
+ 0, &gates_lock);
+ i++;
+
+ if (IS_ERR(clk_data->clks[index])) {
+ WARN_ON(true);
+ continue;
+ }
+
+ for (j = 0; j < nprotected; j++)
+ if (protected[j] == index)
+ clk_prepare_enable(clk_data->clks[index]);
+
+ }
+
+ clk_data->clk_num = number + 1;
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err_free_data:
+ kfree(clk_data);
+err_unmap:
+ iounmap(reg);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+}
+
+static void __init sunxi_simple_gates_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, NULL, 0);
+}
+
+CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
+ sunxi_simple_gates_init);
+
+static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
+ 14, /* ahb_sdram */
+};
+
+static void __init sun4i_a10_ahb_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
+ ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
+}
+CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
+ sun4i_a10_ahb_init);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abf7b37faf73..1fec91093fcd 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -900,150 +900,6 @@ struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
};
-static const struct gates_data sun4i_axi_gates_data __initconst = {
- .mask = {1},
-};
-
-static const struct gates_data sun4i_ahb_gates_data __initconst = {
- .mask = {0x7F77FFF, 0x14FB3F},
-};
-
-static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
- .mask = {0x147667e7, 0x185915},
-};
-
-static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
- .mask = {0x107067e7, 0x185111},
-};
-
-static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
- .mask = {0xEDFE7F62, 0x794F931},
-};
-
-static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
- .mask = { 0x12f77fff, 0x16ff3f },
-};
-
-static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
- .mask = {0x25386742, 0x2505111},
-};
-
-static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
- .mask = {0xF5F12B},
-};
-
-static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
- .mask = {0x1E20003},
-};
-
-static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
- .mask = {0x9B7},
-};
-
-static const struct gates_data sun4i_apb0_gates_data __initconst = {
- .mask = {0x4EF},
-};
-
-static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
- .mask = {0x469},
-};
-
-static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
- .mask = {0x61},
-};
-
-static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
- .mask = { 0x4ff },
-};
-
-static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
- .mask = {0xEB822},
-};
-
-static const struct gates_data sun4i_apb1_gates_data __initconst = {
- .mask = {0xFF00F7},
-};
-
-static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
- .mask = {0xf0007},
-};
-
-static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
- .mask = {0xa0007},
-};
-
-static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
- .mask = {0x3031},
-};
-
-static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
- .mask = {0x3021},
-};
-
-static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
- .mask = {0x3F000F},
-};
-
-static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
- .mask = { 0xff80ff },
-};
-
-static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
- .mask = {0x3F001F},
-};
-
-static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
- .mask = {0x1F0007},
-};
-
-static void __init sunxi_gates_clk_setup(struct device_node *node,
- struct gates_data *data)
-{
- struct clk_onecell_data *clk_data;
- const char *clk_parent;
- const char *clk_name;
- void __iomem *reg;
- int qty;
- int i = 0;
- int j = 0;
-
- reg = of_iomap(node, 0);
-
- clk_parent = of_clk_get_parent_name(node, 0);
-
- /* Worst-case size approximation and memory allocation */
- qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- return;
- clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
- for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
- of_property_read_string_index(node, "clock-output-names",
- j, &clk_name);
-
- clk_data->clks[i] = clk_register_gate(NULL, clk_name,
- clk_parent, 0,
- reg + 4 * (i/32), i % 32,
- 0, &clk_lock);
- WARN_ON(IS_ERR(clk_data->clks[i]));
- clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
-
- j++;
- }
-
- /* Adjust to the real max */
- clk_data->clk_num = i;
-
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
-
-
-
/**
* sunxi_divs_clk_setup() helper data
*/
@@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
{}
};
-/* Matches for gate clocks */
-static const struct of_device_id clk_gates_match[] __initconst = {
- {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
- {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
- {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
- {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
- {}
-};
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
void *function)
@@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
/* Register mux clocks */
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
- /* Register gate clocks */
- of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-
/* Protect the clocks that needs to stay on */
for (i = 0; i < nclocks; i++) {
struct clk *clk = clk_get(NULL, clocks[i]);
@@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
static const char *sun4i_a10_critical_clocks[] __initdata = {
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun4i_a10_init_clocks(struct device_node *node)
@@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
static const char *sun5i_critical_clocks[] __initdata = {
"cpu",
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun5i_init_clocks(struct device_node *node)
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 7/7] clk: sunxi: Add a simple gates driver
@ 2015-07-31 17:46 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-31 17:46 UTC (permalink / raw)
To: linux-arm-kernel
The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.
Move this code in a new driver that handles all the gates array and solves
both these issues.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
3 files changed, 158 insertions(+), 177 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 058f273d6154..f5a35b82cc1a 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-hosc.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
+obj-y += clk-simple-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
new file mode 100644
index 000000000000..39e57e3d745c
--- /dev/null
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_simple_gates_setup(struct device_node *node,
+ const int protected[],
+ int nprotected)
+{
+ struct clk_onecell_data *clk_data;
+ const char *clk_parent, *clk_name;
+ struct property *prop;
+ struct resource res;
+ void __iomem *clk_reg;
+ void __iomem *reg;
+ const __be32 *p;
+ int number, i = 0, j;
+ u8 clk_bit;
+ u32 index;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg))
+ return;
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err_unmap;
+
+ number = of_property_count_u32_elems(node, "clock-indices");
+ of_property_read_u32_index(node, "clock-indices", number - 1, &number);
+
+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err_free_data;
+
+ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+ of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+
+ clk_reg = reg + 4 * (index / 32);
+ clk_bit = index % 32;
+
+ clk_data->clks[index] = clk_register_gate(NULL, clk_name,
+ clk_parent, 0,
+ clk_reg,
+ clk_bit,
+ 0, &gates_lock);
+ i++;
+
+ if (IS_ERR(clk_data->clks[index])) {
+ WARN_ON(true);
+ continue;
+ }
+
+ for (j = 0; j < nprotected; j++)
+ if (protected[j] == index)
+ clk_prepare_enable(clk_data->clks[index]);
+
+ }
+
+ clk_data->clk_num = number + 1;
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err_free_data:
+ kfree(clk_data);
+err_unmap:
+ iounmap(reg);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+}
+
+static void __init sunxi_simple_gates_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, NULL, 0);
+}
+
+CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
+ sunxi_simple_gates_init);
+
+static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
+ 14, /* ahb_sdram */
+};
+
+static void __init sun4i_a10_ahb_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
+ ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
+}
+CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
+ sun4i_a10_ahb_init);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abf7b37faf73..1fec91093fcd 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -900,150 +900,6 @@ struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
};
-static const struct gates_data sun4i_axi_gates_data __initconst = {
- .mask = {1},
-};
-
-static const struct gates_data sun4i_ahb_gates_data __initconst = {
- .mask = {0x7F77FFF, 0x14FB3F},
-};
-
-static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
- .mask = {0x147667e7, 0x185915},
-};
-
-static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
- .mask = {0x107067e7, 0x185111},
-};
-
-static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
- .mask = {0xEDFE7F62, 0x794F931},
-};
-
-static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
- .mask = { 0x12f77fff, 0x16ff3f },
-};
-
-static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
- .mask = {0x25386742, 0x2505111},
-};
-
-static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
- .mask = {0xF5F12B},
-};
-
-static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
- .mask = {0x1E20003},
-};
-
-static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
- .mask = {0x9B7},
-};
-
-static const struct gates_data sun4i_apb0_gates_data __initconst = {
- .mask = {0x4EF},
-};
-
-static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
- .mask = {0x469},
-};
-
-static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
- .mask = {0x61},
-};
-
-static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
- .mask = { 0x4ff },
-};
-
-static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
- .mask = {0xEB822},
-};
-
-static const struct gates_data sun4i_apb1_gates_data __initconst = {
- .mask = {0xFF00F7},
-};
-
-static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
- .mask = {0xf0007},
-};
-
-static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
- .mask = {0xa0007},
-};
-
-static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
- .mask = {0x3031},
-};
-
-static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
- .mask = {0x3021},
-};
-
-static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
- .mask = {0x3F000F},
-};
-
-static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
- .mask = { 0xff80ff },
-};
-
-static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
- .mask = {0x3F001F},
-};
-
-static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
- .mask = {0x1F0007},
-};
-
-static void __init sunxi_gates_clk_setup(struct device_node *node,
- struct gates_data *data)
-{
- struct clk_onecell_data *clk_data;
- const char *clk_parent;
- const char *clk_name;
- void __iomem *reg;
- int qty;
- int i = 0;
- int j = 0;
-
- reg = of_iomap(node, 0);
-
- clk_parent = of_clk_get_parent_name(node, 0);
-
- /* Worst-case size approximation and memory allocation */
- qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- return;
- clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
- for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
- of_property_read_string_index(node, "clock-output-names",
- j, &clk_name);
-
- clk_data->clks[i] = clk_register_gate(NULL, clk_name,
- clk_parent, 0,
- reg + 4 * (i/32), i % 32,
- 0, &clk_lock);
- WARN_ON(IS_ERR(clk_data->clks[i]));
- clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
-
- j++;
- }
-
- /* Adjust to the real max */
- clk_data->clk_num = i;
-
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
-
-
-
/**
* sunxi_divs_clk_setup() helper data
*/
@@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
{}
};
-/* Matches for gate clocks */
-static const struct of_device_id clk_gates_match[] __initconst = {
- {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
- {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
- {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
- {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
- {}
-};
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
void *function)
@@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
/* Register mux clocks */
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
- /* Register gate clocks */
- of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-
/* Protect the clocks that needs to stay on */
for (i = 0; i < nclocks; i++) {
struct clk *clk = clk_get(NULL, clocks[i]);
@@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
static const char *sun4i_a10_critical_clocks[] __initdata = {
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun4i_a10_init_clocks(struct device_node *node)
@@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
static const char *sun5i_critical_clocks[] __initdata = {
"cpu",
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun5i_init_clocks(struct device_node *node)
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/7] ARM: sun8i: Add clock indices
2015-07-31 17:46 ` Maxime Ripard
@ 2015-08-07 16:21 ` Chen-Yu Tsai
-1 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-08-07 16:21 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mike Turquette, Stephen Boyd, linux-clk, Chen-Yu Tsai, linux-arm-kernel
On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The A23 and A33 gates have a non continuous set of clock IDs that are
> valid. Add the clock-indices property to the DT to express this.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 7abd0ae3143d..c318c770b6c1 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -180,6 +180,15 @@
> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> reg = <0x01c20060 0x8>;
> clocks = <&ahb1>;
> + clock-indices = <1>, <6>,
Turns out the A33 (and I assume the same with the A23) has
an ahb1 clock gate for the Security System at clock-index <5>.
This is found in the updated A33 user manual.
> + <8>, <9>, <10>,
> + <13>, <14>,
> + <19>, <20>,
> + <21>, <24>, <26>,
> + <29>, <32>, <36>,
> + <40>, <44>, <46>,
> + <52>, <54>,
<53> is ahb1 clock gate for msgbox, again found in A33 manual.
> + <57>;
<58> is ahb1 clock gate for SAT, which seems to be part of the
display pipeline.
> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> "ahb1_nand", "ahb1_sdram",
> @@ -196,6 +205,8 @@
> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> reg = <0x01c20068 0x4>;
> clocks = <&apb1>;
> + clock-indices = <0>, <5>,
> + <12>, <13>;
> clock-output-names = "apb1_codec", "apb1_pio",
> "apb1_daudio0", "apb1_daudio1";
> };
> @@ -213,6 +224,10 @@
> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> reg = <0x01c2006c 0x4>;
> clocks = <&apb2>;
> + clock-indices = <0>, <1>,
> + <2>, <16>,
> + <17>, <18>,
> + <19>, <20>;
> clock-output-names = "apb2_i2c0", "apb2_i2c1",
> "apb2_i2c2", "apb2_uart0",
> "apb2_uart1", "apb2_uart2",
> --
> 2.4.6
>
Not sure if you want to add the clocks I mentioned together
in this patch, or do a separate patch.
The rest look good.
ChenYu
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
@ 2015-08-07 16:21 ` Chen-Yu Tsai
0 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-08-07 16:21 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The A23 and A33 gates have a non continuous set of clock IDs that are
> valid. Add the clock-indices property to the DT to express this.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> index 7abd0ae3143d..c318c770b6c1 100644
> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> @@ -180,6 +180,15 @@
> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> reg = <0x01c20060 0x8>;
> clocks = <&ahb1>;
> + clock-indices = <1>, <6>,
Turns out the A33 (and I assume the same with the A23) has
an ahb1 clock gate for the Security System at clock-index <5>.
This is found in the updated A33 user manual.
> + <8>, <9>, <10>,
> + <13>, <14>,
> + <19>, <20>,
> + <21>, <24>, <26>,
> + <29>, <32>, <36>,
> + <40>, <44>, <46>,
> + <52>, <54>,
<53> is ahb1 clock gate for msgbox, again found in A33 manual.
> + <57>;
<58> is ahb1 clock gate for SAT, which seems to be part of the
display pipeline.
> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> "ahb1_nand", "ahb1_sdram",
> @@ -196,6 +205,8 @@
> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> reg = <0x01c20068 0x4>;
> clocks = <&apb1>;
> + clock-indices = <0>, <5>,
> + <12>, <13>;
> clock-output-names = "apb1_codec", "apb1_pio",
> "apb1_daudio0", "apb1_daudio1";
> };
> @@ -213,6 +224,10 @@
> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> reg = <0x01c2006c 0x4>;
> clocks = <&apb2>;
> + clock-indices = <0>, <1>,
> + <2>, <16>,
> + <17>, <18>,
> + <19>, <20>;
> clock-output-names = "apb2_i2c0", "apb2_i2c1",
> "apb2_i2c2", "apb2_uart0",
> "apb2_uart1", "apb2_uart2",
> --
> 2.4.6
>
Not sure if you want to add the clocks I mentioned together
in this patch, or do a separate patch.
The rest look good.
ChenYu
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/7] ARM: sun8i: Add clock indices
2015-08-07 16:21 ` Chen-Yu Tsai
@ 2015-08-11 4:49 ` Chen-Yu Tsai
-1 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-08-11 4:49 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Maxime Ripard, Stephen Boyd, Mike Turquette, linux-arm-kernel, linux-clk
On Sat, Aug 8, 2015 at 12:21 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>> The A23 and A33 gates have a non continuous set of clock IDs that are
>> valid. Add the clock-indices property to the DT to express this.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> index 7abd0ae3143d..c318c770b6c1 100644
>> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> @@ -180,6 +180,15 @@
>> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>> reg = <0x01c20060 0x8>;
>> clocks = <&ahb1>;
>> + clock-indices = <1>, <6>,
>
> Turns out the A33 (and I assume the same with the A23) has
> an ahb1 clock gate for the Security System at clock-index <5>.
Looks like the A23 does not have this one, nor the SS mod clock.
> This is found in the updated A33 user manual.
>
>> + <8>, <9>, <10>,
>> + <13>, <14>,
>> + <19>, <20>,
>> + <21>, <24>, <26>,
>> + <29>, <32>, <36>,
>> + <40>, <44>, <46>,
>> + <52>, <54>,
>
> <53> is ahb1 clock gate for msgbox, again found in A33 manual.
A23 has this one. Found in Allwinner kernel sources.
>> + <57>;
>
> <58> is ahb1 clock gate for SAT, which seems to be part of the
> display pipeline.
This one is A33 only.
I guess we should do a separate compatible for A33 AHB1 clock gates.
ChenYu
>> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
>> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
>> "ahb1_nand", "ahb1_sdram",
>> @@ -196,6 +205,8 @@
>> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
>> reg = <0x01c20068 0x4>;
>> clocks = <&apb1>;
>> + clock-indices = <0>, <5>,
>> + <12>, <13>;
>> clock-output-names = "apb1_codec", "apb1_pio",
>> "apb1_daudio0", "apb1_daudio1";
>> };
>> @@ -213,6 +224,10 @@
>> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
>> reg = <0x01c2006c 0x4>;
>> clocks = <&apb2>;
>> + clock-indices = <0>, <1>,
>> + <2>, <16>,
>> + <17>, <18>,
>> + <19>, <20>;
>> clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> "apb2_i2c2", "apb2_uart0",
>> "apb2_uart1", "apb2_uart2",
>> --
>> 2.4.6
>>
>
> Not sure if you want to add the clocks I mentioned together
> in this patch, or do a separate patch.
>
> The rest look good.
>
> ChenYu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
@ 2015-08-11 4:49 ` Chen-Yu Tsai
0 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-08-11 4:49 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Aug 8, 2015 at 12:21 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>> The A23 and A33 gates have a non continuous set of clock IDs that are
>> valid. Add the clock-indices property to the DT to express this.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> ---
>> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
>> 1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> index 7abd0ae3143d..c318c770b6c1 100644
>> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> @@ -180,6 +180,15 @@
>> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>> reg = <0x01c20060 0x8>;
>> clocks = <&ahb1>;
>> + clock-indices = <1>, <6>,
>
> Turns out the A33 (and I assume the same with the A23) has
> an ahb1 clock gate for the Security System at clock-index <5>.
Looks like the A23 does not have this one, nor the SS mod clock.
> This is found in the updated A33 user manual.
>
>> + <8>, <9>, <10>,
>> + <13>, <14>,
>> + <19>, <20>,
>> + <21>, <24>, <26>,
>> + <29>, <32>, <36>,
>> + <40>, <44>, <46>,
>> + <52>, <54>,
>
> <53> is ahb1 clock gate for msgbox, again found in A33 manual.
A23 has this one. Found in Allwinner kernel sources.
>> + <57>;
>
> <58> is ahb1 clock gate for SAT, which seems to be part of the
> display pipeline.
This one is A33 only.
I guess we should do a separate compatible for A33 AHB1 clock gates.
ChenYu
>> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
>> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
>> "ahb1_nand", "ahb1_sdram",
>> @@ -196,6 +205,8 @@
>> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
>> reg = <0x01c20068 0x4>;
>> clocks = <&apb1>;
>> + clock-indices = <0>, <5>,
>> + <12>, <13>;
>> clock-output-names = "apb1_codec", "apb1_pio",
>> "apb1_daudio0", "apb1_daudio1";
>> };
>> @@ -213,6 +224,10 @@
>> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
>> reg = <0x01c2006c 0x4>;
>> clocks = <&apb2>;
>> + clock-indices = <0>, <1>,
>> + <2>, <16>,
>> + <17>, <18>,
>> + <19>, <20>;
>> clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> "apb2_i2c2", "apb2_uart0",
>> "apb2_uart1", "apb2_uart2",
>> --
>> 2.4.6
>>
>
> Not sure if you want to add the clocks I mentioned together
> in this patch, or do a separate patch.
>
> The rest look good.
>
> ChenYu
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/7] ARM: sun8i: Add clock indices
2015-08-11 4:49 ` Chen-Yu Tsai
@ 2015-08-11 17:50 ` Michael Turquette
-1 siblings, 0 replies; 28+ messages in thread
From: Michael Turquette @ 2015-08-11 17:50 UTC (permalink / raw)
To: Chen-Yu Tsai, Chen-Yu Tsai
Cc: Maxime Ripard, Stephen Boyd, linux-arm-kernel, linux-clk
Quoting Chen-Yu Tsai (2015-08-10 21:49:54)
> On Sat, Aug 8, 2015 at 12:21 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> > On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
> > <maxime.ripard@free-electrons.com> wrote:
> >> The A23 and A33 gates have a non continuous set of clock IDs that are
> >> valid. Add the clock-indices property to the DT to express this.
> >>
> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
> >> 1 file changed, 15 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/=
sun8i-a23-a33.dtsi
> >> index 7abd0ae3143d..c318c770b6c1 100644
> >> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> >> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> >> @@ -180,6 +180,15 @@
> >> compatible =3D "allwinner,sun8i-a23-ahb1-gates=
-clk";
> >> reg =3D <0x01c20060 0x8>;
> >> clocks =3D <&ahb1>;
> >> + clock-indices =3D <1>, <6>,
> >
> > Turns out the A33 (and I assume the same with the A23) has
> > an ahb1 clock gate for the Security System at clock-index <5>.
> =
> Looks like the A23 does not have this one, nor the SS mod clock.
> =
> > This is found in the updated A33 user manual.
> >
> >> + <8>, <9>, <10>,
> >> + <13>, <14>,
> >> + <19>, <20>,
> >> + <21>, <24>, <26>,
> >> + <29>, <32>, <36>,
> >> + <40>, <44>, <46>,
> >> + <52>, <54>,
> >
> > <53> is ahb1 clock gate for msgbox, again found in A33 manual.
> =
> A23 has this one. Found in Allwinner kernel sources.
> =
> >> + <57>;
> >
> > <58> is ahb1 clock gate for SAT, which seems to be part of the
> > display pipeline.
> =
> This one is A33 only.
> =
> I guess we should do a separate compatible for A33 AHB1 clock gates.
ChenYu,
I believe Maxime is on vacation. I told him that I would pick these
patches directly. It looks like your comments can be fixed up in
follow-up patches at a later date, correct?
If so then I will apply them to clk-next.
Regards,
Mike
> =
> ChenYu
> =
> >> clock-output-names =3D "ahb1_mipidsi", "ahb1_d=
ma",
> >> "ahb1_mmc0", "ahb1_mmc1", "ahb=
1_mmc2",
> >> "ahb1_nand", "ahb1_sdram",
> >> @@ -196,6 +205,8 @@
> >> compatible =3D "allwinner,sun8i-a23-apb1-gates=
-clk";
> >> reg =3D <0x01c20068 0x4>;
> >> clocks =3D <&apb1>;
> >> + clock-indices =3D <0>, <5>,
> >> + <12>, <13>;
> >> clock-output-names =3D "apb1_codec", "apb1_pio=
",
> >> "apb1_daudio0", "apb1_daudio1";
> >> };
> >> @@ -213,6 +224,10 @@
> >> compatible =3D "allwinner,sun8i-a23-apb2-gates=
-clk";
> >> reg =3D <0x01c2006c 0x4>;
> >> clocks =3D <&apb2>;
> >> + clock-indices =3D <0>, <1>,
> >> + <2>, <16>,
> >> + <17>, <18>,
> >> + <19>, <20>;
> >> clock-output-names =3D "apb2_i2c0", "apb2_i2c1=
",
> >> "apb2_i2c2", "apb2_uart0",
> >> "apb2_uart1", "apb2_uart2",
> >> --
> >> 2.4.6
> >>
> >
> > Not sure if you want to add the clocks I mentioned together
> > in this patch, or do a separate patch.
> >
> > The rest look good.
> >
> > ChenYu
> =
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
@ 2015-08-11 17:50 ` Michael Turquette
0 siblings, 0 replies; 28+ messages in thread
From: Michael Turquette @ 2015-08-11 17:50 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Chen-Yu Tsai (2015-08-10 21:49:54)
> On Sat, Aug 8, 2015 at 12:21 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> > On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
> > <maxime.ripard@free-electrons.com> wrote:
> >> The A23 and A33 gates have a non continuous set of clock IDs that are
> >> valid. Add the clock-indices property to the DT to express this.
> >>
> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
> >> 1 file changed, 15 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> >> index 7abd0ae3143d..c318c770b6c1 100644
> >> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> >> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> >> @@ -180,6 +180,15 @@
> >> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> >> reg = <0x01c20060 0x8>;
> >> clocks = <&ahb1>;
> >> + clock-indices = <1>, <6>,
> >
> > Turns out the A33 (and I assume the same with the A23) has
> > an ahb1 clock gate for the Security System at clock-index <5>.
>
> Looks like the A23 does not have this one, nor the SS mod clock.
>
> > This is found in the updated A33 user manual.
> >
> >> + <8>, <9>, <10>,
> >> + <13>, <14>,
> >> + <19>, <20>,
> >> + <21>, <24>, <26>,
> >> + <29>, <32>, <36>,
> >> + <40>, <44>, <46>,
> >> + <52>, <54>,
> >
> > <53> is ahb1 clock gate for msgbox, again found in A33 manual.
>
> A23 has this one. Found in Allwinner kernel sources.
>
> >> + <57>;
> >
> > <58> is ahb1 clock gate for SAT, which seems to be part of the
> > display pipeline.
>
> This one is A33 only.
>
> I guess we should do a separate compatible for A33 AHB1 clock gates.
ChenYu,
I believe Maxime is on vacation. I told him that I would pick these
patches directly. It looks like your comments can be fixed up in
follow-up patches at a later date, correct?
If so then I will apply them to clk-next.
Regards,
Mike
>
> ChenYu
>
> >> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> >> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> >> "ahb1_nand", "ahb1_sdram",
> >> @@ -196,6 +205,8 @@
> >> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> >> reg = <0x01c20068 0x4>;
> >> clocks = <&apb1>;
> >> + clock-indices = <0>, <5>,
> >> + <12>, <13>;
> >> clock-output-names = "apb1_codec", "apb1_pio",
> >> "apb1_daudio0", "apb1_daudio1";
> >> };
> >> @@ -213,6 +224,10 @@
> >> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> >> reg = <0x01c2006c 0x4>;
> >> clocks = <&apb2>;
> >> + clock-indices = <0>, <1>,
> >> + <2>, <16>,
> >> + <17>, <18>,
> >> + <19>, <20>;
> >> clock-output-names = "apb2_i2c0", "apb2_i2c1",
> >> "apb2_i2c2", "apb2_uart0",
> >> "apb2_uart1", "apb2_uart2",
> >> --
> >> 2.4.6
> >>
> >
> > Not sure if you want to add the clocks I mentioned together
> > in this patch, or do a separate patch.
> >
> > The rest look good.
> >
> > ChenYu
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 7/7] clk: sunxi: Add a simple gates driver
2015-07-31 17:46 ` Maxime Ripard
@ 2015-08-11 23:19 ` Michael Turquette
-1 siblings, 0 replies; 28+ messages in thread
From: Michael Turquette @ 2015-08-11 23:19 UTC (permalink / raw)
To: Maxime Ripard
Cc: Stephen Boyd, linux-clk, Chen-Yu Tsai,
Stephen Boyd <sboyd@codeaurora.org>,
Emilio Lopez <emilio@elopez.com.ar>,
Hans de Goede <hdegoede@redhat.com>,
linux-clk <linux-clk@vger.kernel.org>,
linux-arm-kernel
On Fri, Jul 31, 2015 at 10:46 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The gates were handled with a common piece of framework that was
> registering all gates array, that was not using the CLK_OF_DECLARE logic,
> and was not using clock-indices but some private masks that were pretty
> much equivalent.
>
> Move this code in a new driver that handles all the gates array and solves
> both these issues.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
FYI a small fix was rolled into this patch. It was missing clk.h since
we removed that from clk-provider.h.
Regards,
Mike
> ---
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
> drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
> 3 files changed, 158 insertions(+), 177 deletions(-)
> create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 058f273d6154..f5a35b82cc1a 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
> obj-y += clk-a10-hosc.o
> obj-y += clk-a20-gmac.o
> obj-y += clk-mod0.o
> +obj-y += clk-simple-gates.o
> obj-y += clk-sun8i-mbus.o
> obj-y += clk-sun9i-core.o
> obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> new file mode 100644
> index 000000000000..39e57e3d745c
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +static DEFINE_SPINLOCK(gates_lock);
> +
> +static void __init sunxi_simple_gates_setup(struct device_node *node,
> + const int protected[],
> + int nprotected)
> +{
> + struct clk_onecell_data *clk_data;
> + const char *clk_parent, *clk_name;
> + struct property *prop;
> + struct resource res;
> + void __iomem *clk_reg;
> + void __iomem *reg;
> + const __be32 *p;
> + int number, i = 0, j;
> + u8 clk_bit;
> + u32 index;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg))
> + return;
> +
> + clk_parent = of_clk_get_parent_name(node, 0);
> +
> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> + if (!clk_data)
> + goto err_unmap;
> +
> + number = of_property_count_u32_elems(node, "clock-indices");
> + of_property_read_u32_index(node, "clock-indices", number - 1, &number);
> +
> + clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
> + if (!clk_data->clks)
> + goto err_free_data;
> +
> + of_property_for_each_u32(node, "clock-indices", prop, p, index) {
> + of_property_read_string_index(node, "clock-output-names",
> + i, &clk_name);
> +
> + clk_reg = reg + 4 * (index / 32);
> + clk_bit = index % 32;
> +
> + clk_data->clks[index] = clk_register_gate(NULL, clk_name,
> + clk_parent, 0,
> + clk_reg,
> + clk_bit,
> + 0, &gates_lock);
> + i++;
> +
> + if (IS_ERR(clk_data->clks[index])) {
> + WARN_ON(true);
> + continue;
> + }
> +
> + for (j = 0; j < nprotected; j++)
> + if (protected[j] == index)
> + clk_prepare_enable(clk_data->clks[index]);
> +
> + }
> +
> + clk_data->clk_num = number + 1;
> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return;
> +
> +err_free_data:
> + kfree(clk_data);
> +err_unmap:
> + iounmap(reg);
> + of_address_to_resource(node, 0, &res);
> + release_mem_region(res.start, resource_size(&res));
> +}
> +
> +static void __init sunxi_simple_gates_init(struct device_node *node)
> +{
> + sunxi_simple_gates_setup(node, NULL, 0);
> +}
> +
> +CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +
> +static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
> + 14, /* ahb_sdram */
> +};
> +
> +static void __init sun4i_a10_ahb_init(struct device_node *node)
> +{
> + sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
> + ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
> +}
> +CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index abf7b37faf73..1fec91093fcd 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -900,150 +900,6 @@ struct gates_data {
> DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> };
>
> -static const struct gates_data sun4i_axi_gates_data __initconst = {
> - .mask = {1},
> -};
> -
> -static const struct gates_data sun4i_ahb_gates_data __initconst = {
> - .mask = {0x7F77FFF, 0x14FB3F},
> -};
> -
> -static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
> - .mask = {0x147667e7, 0x185915},
> -};
> -
> -static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
> - .mask = {0x107067e7, 0x185111},
> -};
> -
> -static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
> - .mask = {0xEDFE7F62, 0x794F931},
> -};
> -
> -static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
> - .mask = { 0x12f77fff, 0x16ff3f },
> -};
> -
> -static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
> - .mask = {0x25386742, 0x2505111},
> -};
> -
> -static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
> - .mask = {0xF5F12B},
> -};
> -
> -static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
> - .mask = {0x1E20003},
> -};
> -
> -static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
> - .mask = {0x9B7},
> -};
> -
> -static const struct gates_data sun4i_apb0_gates_data __initconst = {
> - .mask = {0x4EF},
> -};
> -
> -static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
> - .mask = {0x469},
> -};
> -
> -static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
> - .mask = {0x61},
> -};
> -
> -static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
> - .mask = { 0x4ff },
> -};
> -
> -static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
> - .mask = {0xEB822},
> -};
> -
> -static const struct gates_data sun4i_apb1_gates_data __initconst = {
> - .mask = {0xFF00F7},
> -};
> -
> -static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
> - .mask = {0xf0007},
> -};
> -
> -static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
> - .mask = {0xa0007},
> -};
> -
> -static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
> - .mask = {0x3031},
> -};
> -
> -static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
> - .mask = {0x3021},
> -};
> -
> -static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
> - .mask = {0x3F000F},
> -};
> -
> -static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
> - .mask = { 0xff80ff },
> -};
> -
> -static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
> - .mask = {0x3F001F},
> -};
> -
> -static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
> - .mask = {0x1F0007},
> -};
> -
> -static void __init sunxi_gates_clk_setup(struct device_node *node,
> - struct gates_data *data)
> -{
> - struct clk_onecell_data *clk_data;
> - const char *clk_parent;
> - const char *clk_name;
> - void __iomem *reg;
> - int qty;
> - int i = 0;
> - int j = 0;
> -
> - reg = of_iomap(node, 0);
> -
> - clk_parent = of_clk_get_parent_name(node, 0);
> -
> - /* Worst-case size approximation and memory allocation */
> - qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
> - clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> - if (!clk_data)
> - return;
> - clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
> - if (!clk_data->clks) {
> - kfree(clk_data);
> - return;
> - }
> -
> - for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
> - of_property_read_string_index(node, "clock-output-names",
> - j, &clk_name);
> -
> - clk_data->clks[i] = clk_register_gate(NULL, clk_name,
> - clk_parent, 0,
> - reg + 4 * (i/32), i % 32,
> - 0, &clk_lock);
> - WARN_ON(IS_ERR(clk_data->clks[i]));
> - clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
> -
> - j++;
> - }
> -
> - /* Adjust to the real max */
> - clk_data->clk_num = i;
> -
> - of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> -}
> -
> -
> -
> /**
> * sunxi_divs_clk_setup() helper data
> */
> @@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
> {}
> };
>
> -/* Matches for gate clocks */
> -static const struct of_device_id clk_gates_match[] __initconst = {
> - {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
> - {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
> - {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
> - {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
> - {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
> - {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
> - {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
> - {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
> - {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
> - {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
> - {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
> - {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
> - {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
> - {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
> - {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
> - {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
> - {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
> - {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
> - {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
> - {}
> -};
>
> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
> void *function)
> @@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
> /* Register mux clocks */
> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
>
> - /* Register gate clocks */
> - of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
> -
> /* Protect the clocks that needs to stay on */
> for (i = 0; i < nclocks; i++) {
> struct clk *clk = clk_get(NULL, clocks[i]);
> @@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
>
> static const char *sun4i_a10_critical_clocks[] __initdata = {
> "pll5_ddr",
> - "ahb_sdram",
> };
>
> static void __init sun4i_a10_init_clocks(struct device_node *node)
> @@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
> static const char *sun5i_critical_clocks[] __initdata = {
> "cpu",
> "pll5_ddr",
> - "ahb_sdram",
> };
>
> static void __init sun5i_init_clocks(struct device_node *node)
> --
> 2.4.6
>
--
Michael Turquette
CEO
BayLibre - At the Heart of Embedded Linux
http://baylibre.com/
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 7/7] clk: sunxi: Add a simple gates driver
@ 2015-08-11 23:19 ` Michael Turquette
0 siblings, 0 replies; 28+ messages in thread
From: Michael Turquette @ 2015-08-11 23:19 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 31, 2015 at 10:46 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The gates were handled with a common piece of framework that was
> registering all gates array, that was not using the CLK_OF_DECLARE logic,
> and was not using clock-indices but some private masks that were pretty
> much equivalent.
>
> Move this code in a new driver that handles all the gates array and solves
> both these issues.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
FYI a small fix was rolled into this patch. It was missing clk.h since
we removed that from clk-provider.h.
Regards,
Mike
> ---
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk-simple-gates.c | 157 +++++++++++++++++++++++++++++++
> drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
> 3 files changed, 158 insertions(+), 177 deletions(-)
> create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 058f273d6154..f5a35b82cc1a 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
> obj-y += clk-a10-hosc.o
> obj-y += clk-a20-gmac.o
> obj-y += clk-mod0.o
> +obj-y += clk-simple-gates.o
> obj-y += clk-sun8i-mbus.o
> obj-y += clk-sun9i-core.o
> obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> new file mode 100644
> index 000000000000..39e57e3d745c
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -0,0 +1,157 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +static DEFINE_SPINLOCK(gates_lock);
> +
> +static void __init sunxi_simple_gates_setup(struct device_node *node,
> + const int protected[],
> + int nprotected)
> +{
> + struct clk_onecell_data *clk_data;
> + const char *clk_parent, *clk_name;
> + struct property *prop;
> + struct resource res;
> + void __iomem *clk_reg;
> + void __iomem *reg;
> + const __be32 *p;
> + int number, i = 0, j;
> + u8 clk_bit;
> + u32 index;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg))
> + return;
> +
> + clk_parent = of_clk_get_parent_name(node, 0);
> +
> + clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> + if (!clk_data)
> + goto err_unmap;
> +
> + number = of_property_count_u32_elems(node, "clock-indices");
> + of_property_read_u32_index(node, "clock-indices", number - 1, &number);
> +
> + clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
> + if (!clk_data->clks)
> + goto err_free_data;
> +
> + of_property_for_each_u32(node, "clock-indices", prop, p, index) {
> + of_property_read_string_index(node, "clock-output-names",
> + i, &clk_name);
> +
> + clk_reg = reg + 4 * (index / 32);
> + clk_bit = index % 32;
> +
> + clk_data->clks[index] = clk_register_gate(NULL, clk_name,
> + clk_parent, 0,
> + clk_reg,
> + clk_bit,
> + 0, &gates_lock);
> + i++;
> +
> + if (IS_ERR(clk_data->clks[index])) {
> + WARN_ON(true);
> + continue;
> + }
> +
> + for (j = 0; j < nprotected; j++)
> + if (protected[j] == index)
> + clk_prepare_enable(clk_data->clks[index]);
> +
> + }
> +
> + clk_data->clk_num = number + 1;
> + of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +
> + return;
> +
> +err_free_data:
> + kfree(clk_data);
> +err_unmap:
> + iounmap(reg);
> + of_address_to_resource(node, 0, &res);
> + release_mem_region(res.start, resource_size(&res));
> +}
> +
> +static void __init sunxi_simple_gates_init(struct device_node *node)
> +{
> + sunxi_simple_gates_setup(node, NULL, 0);
> +}
> +
> +CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
> + sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
> + sunxi_simple_gates_init);
> +
> +static const int sun4i_a10_ahb_critical_clocks[] __initconst = {
> + 14, /* ahb_sdram */
> +};
> +
> +static void __init sun4i_a10_ahb_init(struct device_node *node)
> +{
> + sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
> + ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
> +}
> +CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> +CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
> + sun4i_a10_ahb_init);
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index abf7b37faf73..1fec91093fcd 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -900,150 +900,6 @@ struct gates_data {
> DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
> };
>
> -static const struct gates_data sun4i_axi_gates_data __initconst = {
> - .mask = {1},
> -};
> -
> -static const struct gates_data sun4i_ahb_gates_data __initconst = {
> - .mask = {0x7F77FFF, 0x14FB3F},
> -};
> -
> -static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
> - .mask = {0x147667e7, 0x185915},
> -};
> -
> -static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
> - .mask = {0x107067e7, 0x185111},
> -};
> -
> -static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
> - .mask = {0xEDFE7F62, 0x794F931},
> -};
> -
> -static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
> - .mask = { 0x12f77fff, 0x16ff3f },
> -};
> -
> -static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
> - .mask = {0x25386742, 0x2505111},
> -};
> -
> -static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
> - .mask = {0xF5F12B},
> -};
> -
> -static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
> - .mask = {0x1E20003},
> -};
> -
> -static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
> - .mask = {0x9B7},
> -};
> -
> -static const struct gates_data sun4i_apb0_gates_data __initconst = {
> - .mask = {0x4EF},
> -};
> -
> -static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
> - .mask = {0x469},
> -};
> -
> -static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
> - .mask = {0x61},
> -};
> -
> -static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
> - .mask = { 0x4ff },
> -};
> -
> -static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
> - .mask = {0xEB822},
> -};
> -
> -static const struct gates_data sun4i_apb1_gates_data __initconst = {
> - .mask = {0xFF00F7},
> -};
> -
> -static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
> - .mask = {0xf0007},
> -};
> -
> -static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
> - .mask = {0xa0007},
> -};
> -
> -static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
> - .mask = {0x3031},
> -};
> -
> -static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
> - .mask = {0x3021},
> -};
> -
> -static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
> - .mask = {0x3F000F},
> -};
> -
> -static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
> - .mask = { 0xff80ff },
> -};
> -
> -static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
> - .mask = {0x3F001F},
> -};
> -
> -static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
> - .mask = {0x1F0007},
> -};
> -
> -static void __init sunxi_gates_clk_setup(struct device_node *node,
> - struct gates_data *data)
> -{
> - struct clk_onecell_data *clk_data;
> - const char *clk_parent;
> - const char *clk_name;
> - void __iomem *reg;
> - int qty;
> - int i = 0;
> - int j = 0;
> -
> - reg = of_iomap(node, 0);
> -
> - clk_parent = of_clk_get_parent_name(node, 0);
> -
> - /* Worst-case size approximation and memory allocation */
> - qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
> - clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
> - if (!clk_data)
> - return;
> - clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
> - if (!clk_data->clks) {
> - kfree(clk_data);
> - return;
> - }
> -
> - for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
> - of_property_read_string_index(node, "clock-output-names",
> - j, &clk_name);
> -
> - clk_data->clks[i] = clk_register_gate(NULL, clk_name,
> - clk_parent, 0,
> - reg + 4 * (i/32), i % 32,
> - 0, &clk_lock);
> - WARN_ON(IS_ERR(clk_data->clks[i]));
> - clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
> -
> - j++;
> - }
> -
> - /* Adjust to the real max */
> - clk_data->clk_num = i;
> -
> - of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> -}
> -
> -
> -
> /**
> * sunxi_divs_clk_setup() helper data
> */
> @@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
> {}
> };
>
> -/* Matches for gate clocks */
> -static const struct of_device_id clk_gates_match[] __initconst = {
> - {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
> - {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
> - {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
> - {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
> - {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
> - {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
> - {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
> - {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
> - {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
> - {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
> - {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
> - {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
> - {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
> - {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
> - {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
> - {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
> - {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
> - {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
> - {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
> - {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
> - {}
> -};
>
> static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
> void *function)
> @@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
> /* Register mux clocks */
> of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
>
> - /* Register gate clocks */
> - of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
> -
> /* Protect the clocks that needs to stay on */
> for (i = 0; i < nclocks; i++) {
> struct clk *clk = clk_get(NULL, clocks[i]);
> @@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
>
> static const char *sun4i_a10_critical_clocks[] __initdata = {
> "pll5_ddr",
> - "ahb_sdram",
> };
>
> static void __init sun4i_a10_init_clocks(struct device_node *node)
> @@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
> static const char *sun5i_critical_clocks[] __initdata = {
> "cpu",
> "pll5_ddr",
> - "ahb_sdram",
> };
>
> static void __init sun5i_init_clocks(struct device_node *node)
> --
> 2.4.6
>
--
Michael Turquette
CEO
BayLibre - At the Heart of Embedded Linux
http://baylibre.com/
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/7] ARM: sun8i: Add clock indices
2015-08-11 17:50 ` Michael Turquette
@ 2015-08-12 3:17 ` Chen-Yu Tsai
-1 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-08-12 3:17 UTC (permalink / raw)
To: Michael Turquette
Cc: Chen-Yu Tsai, Stephen Boyd, Maxime Ripard, linux-arm-kernel, linux-clk
On Wed, Aug 12, 2015 at 1:50 AM, Michael Turquette
<mturquette@baylibre.com> wrote:
> Quoting Chen-Yu Tsai (2015-08-10 21:49:54)
>> On Sat, Aug 8, 2015 at 12:21 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>> > On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
>> > <maxime.ripard@free-electrons.com> wrote:
>> >> The A23 and A33 gates have a non continuous set of clock IDs that are
>> >> valid. Add the clock-indices property to the DT to express this.
>> >>
>> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> >> ---
>> >> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
>> >> 1 file changed, 15 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> >> index 7abd0ae3143d..c318c770b6c1 100644
>> >> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> >> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> >> @@ -180,6 +180,15 @@
>> >> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>> >> reg = <0x01c20060 0x8>;
>> >> clocks = <&ahb1>;
>> >> + clock-indices = <1>, <6>,
>> >
>> > Turns out the A33 (and I assume the same with the A23) has
>> > an ahb1 clock gate for the Security System at clock-index <5>.
>>
>> Looks like the A23 does not have this one, nor the SS mod clock.
>>
>> > This is found in the updated A33 user manual.
>> >
>> >> + <8>, <9>, <10>,
>> >> + <13>, <14>,
>> >> + <19>, <20>,
>> >> + <21>, <24>, <26>,
>> >> + <29>, <32>, <36>,
>> >> + <40>, <44>, <46>,
>> >> + <52>, <54>,
>> >
>> > <53> is ahb1 clock gate for msgbox, again found in A33 manual.
>>
>> A23 has this one. Found in Allwinner kernel sources.
>>
>> >> + <57>;
>> >
>> > <58> is ahb1 clock gate for SAT, which seems to be part of the
>> > display pipeline.
>>
>> This one is A33 only.
>>
>> I guess we should do a separate compatible for A33 AHB1 clock gates.
>
> ChenYu,
>
> I believe Maxime is on vacation. I told him that I would pick these
> patches directly. It looks like your comments can be fixed up in
> follow-up patches at a later date, correct?
That's right. I was mostly asking how to proceed with adding them.
> If so then I will apply them to clk-next.
Please do. (I see they are already in.)
Thanks
ChenYu
> Regards,
> Mike
>
>>
>> ChenYu
>>
>> >> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
>> >> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
>> >> "ahb1_nand", "ahb1_sdram",
>> >> @@ -196,6 +205,8 @@
>> >> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
>> >> reg = <0x01c20068 0x4>;
>> >> clocks = <&apb1>;
>> >> + clock-indices = <0>, <5>,
>> >> + <12>, <13>;
>> >> clock-output-names = "apb1_codec", "apb1_pio",
>> >> "apb1_daudio0", "apb1_daudio1";
>> >> };
>> >> @@ -213,6 +224,10 @@
>> >> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
>> >> reg = <0x01c2006c 0x4>;
>> >> clocks = <&apb2>;
>> >> + clock-indices = <0>, <1>,
>> >> + <2>, <16>,
>> >> + <17>, <18>,
>> >> + <19>, <20>;
>> >> clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> >> "apb2_i2c2", "apb2_uart0",
>> >> "apb2_uart1", "apb2_uart2",
>> >> --
>> >> 2.4.6
>> >>
>> >
>> > Not sure if you want to add the clocks I mentioned together
>> > in this patch, or do a separate patch.
>> >
>> > The rest look good.
>> >
>> > ChenYu
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
@ 2015-08-12 3:17 ` Chen-Yu Tsai
0 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-08-12 3:17 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 12, 2015 at 1:50 AM, Michael Turquette
<mturquette@baylibre.com> wrote:
> Quoting Chen-Yu Tsai (2015-08-10 21:49:54)
>> On Sat, Aug 8, 2015 at 12:21 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>> > On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
>> > <maxime.ripard@free-electrons.com> wrote:
>> >> The A23 and A33 gates have a non continuous set of clock IDs that are
>> >> valid. Add the clock-indices property to the DT to express this.
>> >>
>> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>> >> ---
>> >> arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
>> >> 1 file changed, 15 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> >> index 7abd0ae3143d..c318c770b6c1 100644
>> >> --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> >> +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
>> >> @@ -180,6 +180,15 @@
>> >> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>> >> reg = <0x01c20060 0x8>;
>> >> clocks = <&ahb1>;
>> >> + clock-indices = <1>, <6>,
>> >
>> > Turns out the A33 (and I assume the same with the A23) has
>> > an ahb1 clock gate for the Security System at clock-index <5>.
>>
>> Looks like the A23 does not have this one, nor the SS mod clock.
>>
>> > This is found in the updated A33 user manual.
>> >
>> >> + <8>, <9>, <10>,
>> >> + <13>, <14>,
>> >> + <19>, <20>,
>> >> + <21>, <24>, <26>,
>> >> + <29>, <32>, <36>,
>> >> + <40>, <44>, <46>,
>> >> + <52>, <54>,
>> >
>> > <53> is ahb1 clock gate for msgbox, again found in A33 manual.
>>
>> A23 has this one. Found in Allwinner kernel sources.
>>
>> >> + <57>;
>> >
>> > <58> is ahb1 clock gate for SAT, which seems to be part of the
>> > display pipeline.
>>
>> This one is A33 only.
>>
>> I guess we should do a separate compatible for A33 AHB1 clock gates.
>
> ChenYu,
>
> I believe Maxime is on vacation. I told him that I would pick these
> patches directly. It looks like your comments can be fixed up in
> follow-up patches at a later date, correct?
That's right. I was mostly asking how to proceed with adding them.
> If so then I will apply them to clk-next.
Please do. (I see they are already in.)
Thanks
ChenYu
> Regards,
> Mike
>
>>
>> ChenYu
>>
>> >> clock-output-names = "ahb1_mipidsi", "ahb1_dma",
>> >> "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
>> >> "ahb1_nand", "ahb1_sdram",
>> >> @@ -196,6 +205,8 @@
>> >> compatible = "allwinner,sun8i-a23-apb1-gates-clk";
>> >> reg = <0x01c20068 0x4>;
>> >> clocks = <&apb1>;
>> >> + clock-indices = <0>, <5>,
>> >> + <12>, <13>;
>> >> clock-output-names = "apb1_codec", "apb1_pio",
>> >> "apb1_daudio0", "apb1_daudio1";
>> >> };
>> >> @@ -213,6 +224,10 @@
>> >> compatible = "allwinner,sun8i-a23-apb2-gates-clk";
>> >> reg = <0x01c2006c 0x4>;
>> >> clocks = <&apb2>;
>> >> + clock-indices = <0>, <1>,
>> >> + <2>, <16>,
>> >> + <17>, <18>,
>> >> + <19>, <20>;
>> >> clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> >> "apb2_i2c2", "apb2_uart0",
>> >> "apb2_uart1", "apb2_uart2",
>> >> --
>> >> 2.4.6
>> >>
>> >
>> > Not sure if you want to add the clocks I mentioned together
>> > in this patch, or do a separate patch.
>> >
>> > The rest look good.
>> >
>> > ChenYu
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/7] ARM: sun8i: Add clock indices
2015-08-07 16:21 ` Chen-Yu Tsai
@ 2015-08-19 9:15 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-08-19 9:15 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: Mike Turquette, Stephen Boyd, linux-clk, linux-arm-kernel
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Hi Chen-Yu,
On Sat, Aug 08, 2015 at 12:21:17AM +0800, Chen-Yu Tsai wrote:
> On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The A23 and A33 gates have a non continuous set of clock IDs that are
> > valid. Add the clock-indices property to the DT to express this.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> > index 7abd0ae3143d..c318c770b6c1 100644
> > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> > @@ -180,6 +180,15 @@
> > compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> > reg = <0x01c20060 0x8>;
> > clocks = <&ahb1>;
> > + clock-indices = <1>, <6>,
>
> Turns out the A33 (and I assume the same with the A23) has
> an ahb1 clock gate for the Security System at clock-index <5>.
>
> This is found in the updated A33 user manual.
>
> > + <8>, <9>, <10>,
> > + <13>, <14>,
> > + <19>, <20>,
> > + <21>, <24>, <26>,
> > + <29>, <32>, <36>,
> > + <40>, <44>, <46>,
> > + <52>, <54>,
>
> <53> is ahb1 clock gate for msgbox, again found in A33 manual.
>
> > + <57>;
>
> <58> is ahb1 clock gate for SAT, which seems to be part of the
> display pipeline.
>
> > clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> > "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> > "ahb1_nand", "ahb1_sdram",
> > @@ -196,6 +205,8 @@
> > compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> > reg = <0x01c20068 0x4>;
> > clocks = <&apb1>;
> > + clock-indices = <0>, <5>,
> > + <12>, <13>;
> > clock-output-names = "apb1_codec", "apb1_pio",
> > "apb1_daudio0", "apb1_daudio1";
> > };
> > @@ -213,6 +224,10 @@
> > compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> > reg = <0x01c2006c 0x4>;
> > clocks = <&apb2>;
> > + clock-indices = <0>, <1>,
> > + <2>, <16>,
> > + <17>, <18>,
> > + <19>, <20>;
> > clock-output-names = "apb2_i2c0", "apb2_i2c1",
> > "apb2_i2c2", "apb2_uart0",
> > "apb2_uart1", "apb2_uart2",
> > --
> > 2.4.6
> >
>
> Not sure if you want to add the clocks I mentioned together
> in this patch, or do a separate patch.
>
> The rest look good.
Thanks for your input, I'll send some new patches to deal with this.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: sun8i: Add clock indices
@ 2015-08-19 9:15 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-08-19 9:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi Chen-Yu,
On Sat, Aug 08, 2015 at 12:21:17AM +0800, Chen-Yu Tsai wrote:
> On Sat, Aug 1, 2015 at 1:46 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The A23 and A33 gates have a non continuous set of clock IDs that are
> > valid. Add the clock-indices property to the DT to express this.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> > index 7abd0ae3143d..c318c770b6c1 100644
> > --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
> > @@ -180,6 +180,15 @@
> > compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> > reg = <0x01c20060 0x8>;
> > clocks = <&ahb1>;
> > + clock-indices = <1>, <6>,
>
> Turns out the A33 (and I assume the same with the A23) has
> an ahb1 clock gate for the Security System at clock-index <5>.
>
> This is found in the updated A33 user manual.
>
> > + <8>, <9>, <10>,
> > + <13>, <14>,
> > + <19>, <20>,
> > + <21>, <24>, <26>,
> > + <29>, <32>, <36>,
> > + <40>, <44>, <46>,
> > + <52>, <54>,
>
> <53> is ahb1 clock gate for msgbox, again found in A33 manual.
>
> > + <57>;
>
> <58> is ahb1 clock gate for SAT, which seems to be part of the
> display pipeline.
>
> > clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> > "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> > "ahb1_nand", "ahb1_sdram",
> > @@ -196,6 +205,8 @@
> > compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> > reg = <0x01c20068 0x4>;
> > clocks = <&apb1>;
> > + clock-indices = <0>, <5>,
> > + <12>, <13>;
> > clock-output-names = "apb1_codec", "apb1_pio",
> > "apb1_daudio0", "apb1_daudio1";
> > };
> > @@ -213,6 +224,10 @@
> > compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> > reg = <0x01c2006c 0x4>;
> > clocks = <&apb2>;
> > + clock-indices = <0>, <1>,
> > + <2>, <16>,
> > + <17>, <18>,
> > + <19>, <20>;
> > clock-output-names = "apb2_i2c0", "apb2_i2c1",
> > "apb2_i2c2", "apb2_uart0",
> > "apb2_uart1", "apb2_uart2",
> > --
> > 2.4.6
> >
>
> Not sure if you want to add the clocks I mentioned together
> in this patch, or do a separate patch.
>
> The rest look good.
Thanks for your input, I'll send some new patches to deal with this.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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end of thread, other threads:[~2015-08-19 9:15 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-31 17:46 [PATCH v2 0/7] ARM: sunxi: Switch to clock indices Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 1/7] ARM: sun4i: Add " Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 2/7] ARM: sun5i: " Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 3/7] ARM: sun6i: " Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 4/7] ARM: sun7i: " Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 5/7] ARM: sun8i: " Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-08-07 16:21 ` Chen-Yu Tsai
2015-08-07 16:21 ` Chen-Yu Tsai
2015-08-11 4:49 ` Chen-Yu Tsai
2015-08-11 4:49 ` Chen-Yu Tsai
2015-08-11 17:50 ` Michael Turquette
2015-08-11 17:50 ` Michael Turquette
2015-08-12 3:17 ` Chen-Yu Tsai
2015-08-12 3:17 ` Chen-Yu Tsai
2015-08-19 9:15 ` Maxime Ripard
2015-08-19 9:15 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 6/7] ARM: sun9i: Wrap the clock-indices Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-07-31 17:46 ` [PATCH v2 7/7] clk: sunxi: Add a simple gates driver Maxime Ripard
2015-07-31 17:46 ` Maxime Ripard
2015-08-11 23:19 ` Michael Turquette
2015-08-11 23:19 ` Michael Turquette
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