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From: Bin Meng <bmeng.cn@gmail.com>
To: Rick Chen <rick@andestech.com>, Leo Liang <ycliang@andestech.com>,
	 U-Boot Mailing List <u-boot@lists.denx.de>
Subject: Re: [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask
Date: Mon, 14 Jun 2021 11:47:41 +0800	[thread overview]
Message-ID: <CAEUhbmUFDqe0kkAVLQAnsrzqnJrBm+1WnRQhx6hue37zLawGAw@mail.gmail.com> (raw)
In-Reply-To: <20210609075602.157709-1-bmeng.cn@gmail.com>

On Wed, Jun 9, 2021 at 3:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Current logic in riscv_get_ipi() for Andes PLICSW does not look good
> to me. The mask to test IPI pending bits for a hart should be left
> shifted by (8 * gd->arch.boot_hart), just the same as what is done in
> riscv_send_ipi().
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
> It looks there is no datasheet released from Andes that describes how
> PLICSW works, and its register fields. I can only get an understanding
> from current U-Boot and OpenSBI PLICSW driver.
>
> This requires testing on Andes hardware, which I don't have access to.
>
>  arch/riscv/lib/andes_plic.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

Ping?

  reply	other threads:[~2021-06-14  3:48 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-09  7:56 [RFT PATCH] riscv: andes_plic: Fix riscv_get_ipi() mask Bin Meng
2021-06-14  3:47 ` Bin Meng [this message]
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FE5EA99D2@ATCPCS12.andestech.com>
2021-06-15  3:08     ` Rick Chen

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