[U-Boot] [PATCH v2 00/51] x86: Add support for samus

[U-Boot] [PATCH v2 00/51] x86: Add support for samus

[Simon Glass]

This series adds support for samus, the Chromebook Pixel 2015. Since it is
only the second board added that does not use an FSP, there is quite a bit
of refactoring involved to avoid code duplication.

Samus uses roughly the same binary blobs as link, except now there is one
more called the reference code binary. The only available binary for this
is a coreboot 'rmodule' extracted from flash. This is a simplified ELF
format so it fairly easy to load and use.

It is also possible to boot U-Boot from coreboot on samus. This works well
but for a delay for non-existent IDE on start-up. The standard build does
not work with binaries taken from flash, so it isn't easy to replicate
this - you'll just have to take my word for it. I am working on getting that
figured out - coreboot recently gained upstream support for loading U-Boot
as a payload, so it should be possible to get this working nicely before
long.

In any case much of the code comes from coreboot - individual files are
credited with their source.

Perhaps the main value of this series is the improved non-FSP support and
additions for broadwell, which samus uses. It should make it easier to add
support for future non-FSP platforms.

Changes in v2:
- Use a #define for the output flush command
- Adjust the code order slightly
- Simplify the code in serial_initialize()
- Use gd->arch.x86_mask to get the stepping value
- Rename microcode_intel.c to microcode.c
- Use capitals for header guard
- Use capitals for header guard
- Move cougarcanyon lpc_common.h include to this patch
- Use capitals for header guard
- Use capitals for header guard
- Rename sdram_common.c to mrc.c
- Rename sdram to mrc
- Use setio_32() instead of setio_le32(), etc.
- Add Kconfig help for the moved options
- Fix tab indentation
- Don't try to read microcode version on quark
- Use gd->arch.x86_device instead of reading the device ID again
- Rename subject to 'core' instead of 'code'
- Fix micrcode typo
- Don't try to update microcode on FSP platforms
- Add GPIO output definition for a1 and a6
- Use setio_32() instead of setio_le32(), etc.
- Fix 'PCB' typo (should be 'PCH')
- Use setio_32() instead of setio_le32(), etc.
- Use capitals for header guard
- Use capitals for header guard
- Use capitals for header guard
- Fix comment style
- Use capitals for header guard
- Rename sdram to mrc
- Use setio_32() instead of setio_le32(), etc.
- Fix 'configure' typo
- Correct naming of Intel platforms

Simon Glass (51):
  dm: timer: Correct timer init ordering after relocation
  arm: Add a 64-bit division routine to the private library
  dhry: Correct dhrystone calculation for fast machines
  syscon: Avoid returning a device on failure
  input: i8042: Make sure the keyboard is enabled
  x86: Allow use of serial soon after relocation
  x86: cpu: Add functions to return the family and stepping
  x86: Move cache-as-RAM code into a common location
  x86: Move microcode code to a common location
  x86: Create a common header for Intel register access
  x86: Add the root-complex block to common intel registers
  x86: Move common LPC code to its own place
  x86: Move common CPU code to its own place
  x86: Rename PORT_RESET to IO_PORT_RESET
  x86: Move Intel Management Engine code to a common place
  x86: ivybridge: Drop sandybridge_early_init()
  x86: Move common PCH code into a common place
  x86: Add common SDRAM-init code
  x86: ivybridge: Convert to use the common SDRAM code
  x86: dts: Drop memory SPD compatible string
  x86: Add macros to clear and set I/O bits
  x86: Allow I/O functions to use pointers
  x86: Move common MRC Kconfig options to the common file
  x86: Record the CPU details when starting each core
  x86: ivybridge: Show microcode version for each core
  x86: Update microcode for secondary CPUs
  x86: link: Add pin configuration to the device tree
  x86: Add an ICH6 pin configuration driver
  x86: gpio: Allow the pinctrl driver to set up the pin config
  x86: Drop all the old pin configuration code
  x86: Add support for running Intel reference code
  x86: dts: Update the pinctrl binding a little
  x86: Add basic support for broadwell
  x86: broadwell: Add a PCH driver
  x86: broadwell: Add a pinctrl driver
  x86: broadwell: Add a SATA driver
  x86: broadwell: Add a northbridge driver
  x86: broadwell: Add an LPC driver
  x86: broadwell: Add reference code support
  x86: broadwell: Add power-control support
  x86: broadwell: Add support for SDRAM setup
  x86: broadwell: Add a GPIO driver
  x86: broadwell: Add support for high-speed I/O lane with ME
  x86: Support a chained-boot development flow
  x86: broadwell: Add video support
  x86: Add a default address for reference code
  x86: Use white on black for the console on chromebooks
  x86: Update README for new developments
  x86: Add a function to set the IOAPIC ID
  x86: Fix a header nit in x86-chromebook.h
  x86: Add support for the samus chromebook

 Makefile                                           |  14 +-
 arch/arm/lib/Makefile                              |   3 +-
 arch/arm/lib/_uldivmod.S                           | 245 +++++++
 arch/x86/Kconfig                                   |  73 ++
 arch/x86/cpu/Makefile                              |   2 +
 arch/x86/cpu/broadwell/Kconfig                     |  30 +
 arch/x86/cpu/broadwell/Makefile                    |  17 +
 arch/x86/cpu/broadwell/cpu.c                       | 761 ++++++++++++++++++++
 arch/x86/cpu/broadwell/iobp.c                      | 144 ++++
 arch/x86/cpu/broadwell/lpc.c                       |  77 ++
 arch/x86/cpu/broadwell/me.c                        |  57 ++
 arch/x86/cpu/broadwell/northbridge.c               |  59 ++
 arch/x86/cpu/broadwell/pch.c                       | 540 ++++++++++++++
 arch/x86/cpu/broadwell/pinctrl_broadwell.c         | 278 +++++++
 arch/x86/cpu/broadwell/power_state.c               |  89 +++
 arch/x86/cpu/broadwell/refcode.c                   | 113 +++
 arch/x86/cpu/broadwell/sata.c                      | 269 +++++++
 arch/x86/cpu/broadwell/sdram.c                     | 307 ++++++++
 arch/x86/cpu/cpu.c                                 |  15 +-
 arch/x86/cpu/intel_common/Makefile                 |  16 +
 arch/x86/cpu/{ivybridge => intel_common}/car.S     |   4 +-
 arch/x86/cpu/intel_common/cpu.c                    | 111 +++
 arch/x86/cpu/intel_common/lpc.c                    | 100 +++
 .../cpu/{ivybridge => intel_common}/me_status.c    |  20 +-
 .../microcode_intel.c => intel_common/microcode.c} |  11 +-
 arch/x86/cpu/intel_common/mrc.c                    | 271 +++++++
 arch/x86/cpu/intel_common/pch_common.c             |  25 +
 .../{ivybridge => intel_common}/report_platform.c  |   2 +-
 arch/x86/cpu/ioapic.c                              |  16 +
 arch/x86/cpu/ivybridge/Kconfig                     |  27 +-
 arch/x86/cpu/ivybridge/Makefile                    |   4 -
 arch/x86/cpu/ivybridge/bd82x6x.c                   |  17 +-
 arch/x86/cpu/ivybridge/cpu.c                       |  86 +--
 arch/x86/cpu/ivybridge/early_me.c                  |  31 +-
 arch/x86/cpu/ivybridge/gma.c                       |   1 +
 arch/x86/cpu/ivybridge/lpc.c                       |  77 +-
 arch/x86/cpu/ivybridge/model_206ax.c               |   3 +-
 arch/x86/cpu/ivybridge/northbridge.c               |   5 +-
 arch/x86/cpu/ivybridge/sata.c                      |  47 +-
 arch/x86/cpu/ivybridge/sdram.c                     | 400 +++--------
 arch/x86/cpu/mp_init.c                             |  11 +-
 arch/x86/cpu/start.S                               |  79 ++
 arch/x86/dts/Makefile                              |   1 +
 arch/x86/dts/chromebook_link.dts                   | 156 +++-
 arch/x86/dts/chromebook_samus.dts                  | 628 ++++++++++++++++
 arch/x86/include/asm/arch-broadwell/cpu.h          |  48 ++
 arch/x86/include/asm/arch-broadwell/gpio.h         |  91 +++
 arch/x86/include/asm/arch-broadwell/iomap.h        |  53 ++
 arch/x86/include/asm/arch-broadwell/lpc.h          |  32 +
 arch/x86/include/asm/arch-broadwell/me.h           | 200 ++++++
 arch/x86/include/asm/arch-broadwell/pch.h          | 153 ++++
 arch/x86/include/asm/arch-broadwell/pei_data.h     | 177 +++++
 arch/x86/include/asm/arch-broadwell/pm.h           | 129 ++++
 arch/x86/include/asm/arch-broadwell/rcb.h          |  58 ++
 arch/x86/include/asm/arch-broadwell/spi.h          |  87 +++
 arch/x86/include/asm/arch-ivybridge/me.h           | 333 +--------
 arch/x86/include/asm/arch-ivybridge/pch.h          |  62 --
 arch/x86/include/asm/arch-ivybridge/sandybridge.h  |   7 -
 arch/x86/include/asm/cpu.h                         |  27 +
 arch/x86/include/asm/cpu_common.h                  |  35 +
 arch/x86/include/asm/global_data.h                 |  24 +
 arch/x86/include/asm/gpio.h                        | 141 ----
 arch/x86/include/asm/intel_regs.h                  |  28 +
 arch/x86/include/asm/io.h                          |  34 +-
 arch/x86/include/asm/ioapic.h                      |   2 +
 arch/x86/include/asm/lpc_common.h                  |  59 ++
 arch/x86/include/asm/me_common.h                   | 372 ++++++++++
 .../include/asm/{arch-ivybridge => }/microcode.h   |  12 +
 arch/x86/include/asm/mrc_common.h                  |  55 ++
 arch/x86/include/asm/pch_common.h                  |  56 ++
 arch/x86/include/asm/processor.h                   |   2 +-
 arch/x86/include/asm/report_platform.h             |  19 +
 arch/x86/lib/Makefile                              |   1 +
 arch/x86/lib/fsp/fsp_car.S                         |   2 +
 arch/x86/lib/pinctrl_ich6.c                        | 216 ++++++
 board/coreboot/coreboot/coreboot.c                 |   5 -
 board/efi/efi-x86/efi.c                            |   5 -
 board/google/Kconfig                               |  13 +
 board/google/chromebook_link/link.c                | 138 ----
 board/google/chromebook_samus/Kconfig              |  40 ++
 board/google/chromebook_samus/MAINTAINERS          |   6 +
 board/google/chromebook_samus/Makefile             |   7 +
 board/google/chromebook_samus/samus.c              |  18 +
 board/google/chromebox_panther/panther.c           |   4 -
 board/intel/bayleybay/bayleybay.c                  |   5 -
 board/intel/cougarcanyon2/cougarcanyon2.c          |   6 +-
 board/intel/crownbay/crownbay.c                    |   5 -
 board/intel/galileo/galileo.c                      |   5 -
 board/intel/minnowmax/minnowmax.c                  |   8 -
 common/board_f.c                                   |   7 +
 common/board_r.c                                   |   4 +-
 configs/bayleybay_defconfig                        |   2 +
 configs/chromebook_samus_defconfig                 |  51 ++
 configs/cougarcanyon2_defconfig                    |   2 +
 configs/crownbay_defconfig                         |   2 +
 configs/galileo_defconfig                          |   2 +
 configs/minnowmax_defconfig                        |   6 +-
 doc/README.x86                                     |  97 ++-
 .../gpio/intel,x86-broadwell-pinctrl.txt           | 208 ++++++
 .../gpio/intel,x86-pinctrl.txt                     |  22 +-
 drivers/core/syscon-uclass.c                       |   1 +
 drivers/gpio/Kconfig                               |   9 +
 drivers/gpio/Makefile                              |   1 +
 drivers/gpio/intel_broadwell_gpio.c                | 198 +++++
 drivers/gpio/intel_ich6_gpio.c                     | 191 +----
 drivers/input/i8042.c                              |   4 +
 drivers/serial/serial-uclass.c                     |   2 +-
 drivers/video/Kconfig                              |  14 +-
 drivers/video/Makefile                             |   2 +
 drivers/video/broadwell_igd.c                      | 797 +++++++++++++++++++++
 drivers/video/i915_reg.h                           | 362 ++++++++++
 include/configs/chromebook_samus.h                 |  29 +
 include/configs/x86-chromebook.h                   |   8 +-
 include/dt-bindings/gpio/x86-gpio.h                |  12 +
 include/fdtdec.h                                   |   2 -
 include/i8042.h                                    |   1 +
 lib/dhry/cmd_dhry.c                                |   8 +-
 lib/fdtdec.c                                       |   2 -
 118 files changed, 8550 insertions(+), 1518 deletions(-)
 create mode 100644 arch/arm/lib/_uldivmod.S
 create mode 100644 arch/x86/cpu/broadwell/Kconfig
 create mode 100644 arch/x86/cpu/broadwell/Makefile
 create mode 100644 arch/x86/cpu/broadwell/cpu.c
 create mode 100644 arch/x86/cpu/broadwell/iobp.c
 create mode 100644 arch/x86/cpu/broadwell/lpc.c
 create mode 100644 arch/x86/cpu/broadwell/me.c
 create mode 100644 arch/x86/cpu/broadwell/northbridge.c
 create mode 100644 arch/x86/cpu/broadwell/pch.c
 create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c
 create mode 100644 arch/x86/cpu/broadwell/power_state.c
 create mode 100644 arch/x86/cpu/broadwell/refcode.c
 create mode 100644 arch/x86/cpu/broadwell/sata.c
 create mode 100644 arch/x86/cpu/broadwell/sdram.c
 create mode 100644 arch/x86/cpu/intel_common/Makefile
 rename arch/x86/cpu/{ivybridge => intel_common}/car.S (98%)
 create mode 100644 arch/x86/cpu/intel_common/cpu.c
 create mode 100644 arch/x86/cpu/intel_common/lpc.c
 rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%)
 rename arch/x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} (96%)
 create mode 100644 arch/x86/cpu/intel_common/mrc.c
 create mode 100644 arch/x86/cpu/intel_common/pch_common.c
 rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%)
 create mode 100644 arch/x86/dts/chromebook_samus.dts
 create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/me.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h
 create mode 100644 arch/x86/include/asm/cpu_common.h
 create mode 100644 arch/x86/include/asm/intel_regs.h
 create mode 100644 arch/x86/include/asm/lpc_common.h
 create mode 100644 arch/x86/include/asm/me_common.h
 rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (63%)
 create mode 100644 arch/x86/include/asm/mrc_common.h
 create mode 100644 arch/x86/include/asm/pch_common.h
 create mode 100644 arch/x86/include/asm/report_platform.h
 create mode 100644 arch/x86/lib/pinctrl_ich6.c
 create mode 100644 board/google/chromebook_samus/Kconfig
 create mode 100644 board/google/chromebook_samus/MAINTAINERS
 create mode 100644 board/google/chromebook_samus/Makefile
 create mode 100644 board/google/chromebook_samus/samus.c
 create mode 100644 configs/chromebook_samus_defconfig
 create mode 100644 doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
 create mode 100644 drivers/gpio/intel_broadwell_gpio.c
 create mode 100644 drivers/video/broadwell_igd.c
 create mode 100644 drivers/video/i915_reg.h
 create mode 100644 include/configs/chromebook_samus.h

-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 01/51] dm: timer: Correct timer init ordering after relocation

[Simon Glass]

Commit 1057e6c broke use of the timer with driver model. If the timer is used
before relocation, then it becomes broken after relocation. This prevents
some x86 boards from booting. Fix it.

Fixes: 1057e6c (timer: Set up the real timer after driver model is available)

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 common/board_r.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/common/board_r.c b/common/board_r.c
index 52a9b26..0f068bf 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -318,11 +318,13 @@ static int initr_dm(void)
 	/* Save the pre-reloc driver model and start a new one */
 	gd->dm_root_f = gd->dm_root;
 	gd->dm_root = NULL;
+#ifdef CONFIG_TIMER
+	gd->timer = NULL;
+#endif
 	ret = dm_init_and_scan(false);
 	if (ret)
 		return ret;
 #ifdef CONFIG_TIMER_EARLY
-	gd->timer = NULL;
 	ret = dm_timer_init();
 	if (ret)
 		return ret;
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 02/51] arm: Add a 64-bit division routine to the private library

[Simon Glass]

This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.

Code is available for using the CLZ instruction but it is not enabled at
present.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/arm/lib/Makefile    |   3 +-
 arch/arm/lib/_uldivmod.S | 245 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 247 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/lib/_uldivmod.S

diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f3db7b5..7a0fb58 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,7 +6,8 @@
 #
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
-			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
+			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
+			_uldivmod.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/_uldivmod.S
new file mode 100644
index 0000000..426c2f2
--- /dev/null
+++ b/arch/arm/lib/_uldivmod.S
@@ -0,0 +1,245 @@
+/*
+ * Copyright 2010, Google Inc.
+ *
+ * Brought in from coreboot uldivmod.S
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/* We don't use Thumb instructions for now */
+#define ARM(x...)	x
+#define THUMB(x...)
+
+/*
+ * A, Q = r0 + (r1 << 32)
+ * B, R = r2 + (r3 << 32)
+ * A / B = Q ... R
+ */
+
+A_0	.req	r0
+A_1	.req	r1
+B_0	.req	r2
+B_1	.req	r3
+C_0	.req	r4
+C_1	.req	r5
+D_0	.req	r6
+D_1	.req	r7
+
+Q_0	.req	r0
+Q_1	.req	r1
+R_0	.req	r2
+R_1	.req	r3
+
+THUMB(
+TMP	.req	r8
+)
+
+ENTRY(__aeabi_uldivmod)
+	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
+	@ Test if B == 0
+	orrs	ip, B_0, B_1		@ Z set -> B == 0
+	beq	L_div_by_0
+	@ Test if B is power of 2: (B & (B - 1)) == 0
+	subs	C_0, B_0, #1
+	sbc	C_1, B_1, #0
+	tst	C_0, B_0
+	tsteq	B_1, C_1
+	beq	L_pow2
+	@ Test if A_1 == B_1 == 0
+	orrs	ip, A_1, B_1
+	beq	L_div_32_32
+
+L_div_64_64:
+/* CLZ only exists in ARM architecture version 5 and above. */
+#ifdef HAVE_CLZ
+	mov	C_0, #1
+	mov	C_1, #0
+	@ D_0 = clz A
+	teq	A_1, #0
+	clz	D_0, A_1
+	clzeq	ip, A_0
+	addeq	D_0, D_0, ip
+	@ D_1 = clz B
+	teq	B_1, #0
+	clz	D_1, B_1
+	clzeq	ip, B_0
+	addeq	D_1, D_1, ip
+	@ if clz B - clz A > 0
+	subs	D_0, D_1, D_0
+	bls	L_done_shift
+	@ B <<= (clz B - clz A)
+	subs	D_1, D_0, #32
+	rsb	ip, D_0, #32
+	movmi	B_1, B_1, lsl D_0
+ARM(	orrmi	B_1, B_1, B_0, lsr ip	)
+THUMB(	lsrmi	TMP, B_0, ip		)
+THUMB(	orrmi	B_1, B_1, TMP		)
+	movpl	B_1, B_0, lsl D_1
+	mov	B_0, B_0, lsl D_0
+	@ C = 1 << (clz B - clz A)
+	movmi	C_1, C_1, lsl D_0
+ARM(	orrmi	C_1, C_1, C_0, lsr ip	)
+THUMB(	lsrmi	TMP, C_0, ip		)
+THUMB(	orrmi	C_1, C_1, TMP		)
+	movpl	C_1, C_0, lsl D_1
+	mov	C_0, C_0, lsl D_0
+L_done_shift:
+	mov	D_0, #0
+	mov	D_1, #0
+	@ C: current bit; D: result
+#else
+	@ C: current bit; D: result
+	mov	C_0, #1
+	mov	C_1, #0
+	mov	D_0, #0
+	mov	D_1, #0
+L_lsl_4:
+	cmp	B_1, #0x10000000
+	cmpcc	B_1, A_1
+	cmpeq	B_0, A_0
+	bcs	L_lsl_1
+	@ B <<= 4
+	mov	B_1, B_1, lsl #4
+	orr	B_1, B_1, B_0, lsr #28
+	mov	B_0, B_0, lsl #4
+	@ C <<= 4
+	mov	C_1, C_1, lsl #4
+	orr	C_1, C_1, C_0, lsr #28
+	mov	C_0, C_0, lsl #4
+	b	L_lsl_4
+L_lsl_1:
+	cmp	B_1, #0x80000000
+	cmpcc	B_1, A_1
+	cmpeq	B_0, A_0
+	bcs	L_subtract
+	@ B <<= 1
+	mov	B_1, B_1, lsl #1
+	orr	B_1, B_1, B_0, lsr #31
+	mov	B_0, B_0, lsl #1
+	@ C <<= 1
+	mov	C_1, C_1, lsl #1
+	orr	C_1, C_1, C_0, lsr #31
+	mov	C_0, C_0, lsl #1
+	b	L_lsl_1
+#endif
+L_subtract:
+	@ if A >= B
+	cmp	A_1, B_1
+	cmpeq	A_0, B_0
+	bcc	L_update
+	@ A -= B
+	subs	A_0, A_0, B_0
+	sbc	A_1, A_1, B_1
+	@ D |= C
+	orr	D_0, D_0, C_0
+	orr	D_1, D_1, C_1
+L_update:
+	@ if A == 0: break
+	orrs	ip, A_1, A_0
+	beq	L_exit
+	@ C >>= 1
+	movs	C_1, C_1, lsr #1
+	movs	C_0, C_0, rrx
+	@ if C == 0: break
+	orrs	ip, C_1, C_0
+	beq	L_exit
+	@ B >>= 1
+	movs	B_1, B_1, lsr #1
+	mov	B_0, B_0, rrx
+	b	L_subtract
+L_exit:
+	@ Note: A, B & Q, R are aliases
+	mov	R_0, A_0
+	mov	R_1, A_1
+	mov	Q_0, D_0
+	mov	Q_1, D_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_div_32_32:
+	@ Note:	A_0 &	r0 are aliases
+	@	Q_1	r1
+	mov	r1, B_0
+	bl	__aeabi_uidivmod
+	mov	R_0, r1
+	mov	R_1, #0
+	mov	Q_1, #0
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+
+L_pow2:
+#ifdef HAVE_CLZ
+	@ Note: A, B and Q, R are aliases
+	@ R = A & (B - 1)
+	and	C_0, A_0, C_0
+	and	C_1, A_1, C_1
+	@ Q = A >> log2(B)
+	@ Note: B must not be 0 here!
+	clz	D_0, B_0
+	add	D_1, D_0, #1
+	rsbs	D_0, D_0, #31
+	bpl	L_1
+	clz	D_0, B_1
+	rsb	D_0, D_0, #31
+	mov	A_0, A_1, lsr D_0
+	add	D_0, D_0, #32
+L_1:
+	movpl	A_0, A_0, lsr D_0
+ARM(	orrpl	A_0, A_0, A_1, lsl D_1	)
+THUMB(	lslpl	TMP, A_1, D_1		)
+THUMB(	orrpl	A_0, A_0, TMP		)
+	mov	A_1, A_1, lsr D_0
+	@ Mov back C to R
+	mov	R_0, C_0
+	mov	R_1, C_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#else
+	@ Note: A, B and Q, R are aliases
+	@ R = A & (B - 1)
+	and	C_0, A_0, C_0
+	and	C_1, A_1, C_1
+	@ Q = A >> log2(B)
+	@ Note: B must not be 0 here!
+	@ Count the leading zeroes in B.
+	mov	D_0, #0
+	orrs	B_0, B_0, B_0
+	@ If B is greater than 1 << 31, divide A and B by 1 << 32.
+	moveq	A_0, A_1
+	moveq	A_1, #0
+	moveq	B_0, B_1
+	@ Count the remaining leading zeroes in B.
+	movs	B_1, B_0, lsl #16
+	addeq	D_0, #16
+	moveq	B_0, B_0, lsr #16
+	tst	B_0, #0xff
+	addeq	D_0, #8
+	moveq	B_0, B_0, lsr #8
+	tst	B_0, #0xf
+	addeq	D_0, #4
+	moveq	B_0, B_0, lsr #4
+	tst	B_0, #0x3
+	addeq	D_0, #2
+	moveq	B_0, B_0, lsr #2
+	tst	B_0, #0x1
+	addeq	D_0, #1
+	@ Shift A to the right by the appropriate amount.
+	rsb	D_1, D_0, #32
+	mov	Q_0, A_0, lsr D_0
+	orr	Q_0, A_1, lsl D_1
+	mov	Q_1, A_1, lsr D_0
+	@ Move C to R
+	mov	R_0, C_0
+	mov	R_1, C_1
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+#endif
+
+L_div_by_0:
+	bl	__div0
+	@ As wrong as it could be
+	mov	Q_0, #0
+	mov	Q_1, #0
+	mov	R_0, #0
+	mov	R_1, #0
+	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
+ENDPROC(__aeabi_uldivmod)
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 03/51] dhry: Correct dhrystone calculation for fast machines

[Simon Glass]

At present samus reports about 5600 DMIPS. With the default iteration count
this is OK, but if 10 million runs are performed it overflows. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 lib/dhry/cmd_dhry.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/lib/dhry/cmd_dhry.c b/lib/dhry/cmd_dhry.c
index 5dc191e..d7e1e6a 100644
--- a/lib/dhry/cmd_dhry.c
+++ b/lib/dhry/cmd_dhry.c
@@ -6,11 +6,13 @@
 
 #include <common.h>
 #include <command.h>
+#include <div64.h>
 #include "dhry.h"
 
 static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	ulong start, duration, dhry_per_sec, vax_mips;
+	ulong start, duration, vax_mips;
+	u64 dhry_per_sec;
 	int iterations = 1000000;
 
 	if (argc > 1)
@@ -19,10 +21,10 @@ static int do_dhry(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	start = get_timer(0);
 	dhry(iterations);
 	duration = get_timer(start);
-	dhry_per_sec = iterations * 1000 / duration;
+	dhry_per_sec = lldiv(iterations * 1000ULL, duration);
 	vax_mips = dhry_per_sec / 1757;
 	printf("%d iterations in %lu ms: %lu/s, %lu DMIPS\n", iterations,
-	       duration, dhry_per_sec, vax_mips);
+	       duration, (ulong)dhry_per_sec, vax_mips);
 
 	return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 04/51] syscon: Avoid returning a device on failure

[Simon Glass]

If the device cannot be probed, syscon_get_by_driver_data() will still
return a useful value in its devp parameter. Ensure that it returns NULL
instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 drivers/core/syscon-uclass.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c
index a0666d0..e03f46a 100644
--- a/drivers/core/syscon-uclass.c
+++ b/drivers/core/syscon-uclass.c
@@ -38,6 +38,7 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
 	struct uclass *uc;
 	int ret;
 
+	*devp = NULL;
 	ret = uclass_get(UCLASS_SYSCON, &uc);
 	if (ret)
 		return ret;
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 05/51] input: i8042: Make sure the keyboard is enabled

[Simon Glass]

Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Use a #define for the output flush command
- Adjust the code order slightly

 drivers/input/i8042.c | 4 ++++
 include/i8042.h       | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c
index 661d7fd..03d4840 100644
--- a/drivers/input/i8042.c
+++ b/drivers/input/i8042.c
@@ -134,6 +134,10 @@ static int kbd_reset(int quirk)
 	    kbd_read(I8042_DATA_REG) != KBD_POR)
 		goto err;
 
+	if (kbd_write(I8042_DATA_REG, CMD_DRAIN_OUTPUT) ||
+	    kbd_read(I8042_DATA_REG) != KBD_ACK)
+		goto err;
+
 	/* set AT translation and disable irq */
 	config = kbd_cmd_read(CMD_RD_CONFIG);
 	if (config == -1)
diff --git a/include/i8042.h b/include/i8042.h
index 9723b6a..0766488 100644
--- a/include/i8042.h
+++ b/include/i8042.h
@@ -35,6 +35,7 @@
 #define CMD_KBD_DIS	0xad	/* keyboard disable */
 #define CMD_KBD_EN	0xae	/* keyboard enable */
 #define CMD_SET_KBD_LED	0xed	/* set keyboard led */
+#define CMD_DRAIN_OUTPUT 0xf4   /* drain output buffer */
 #define CMD_RESET_KBD	0xff	/* reset keyboard */
 
 /* i8042 command result */
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 06/51] x86: Allow use of serial soon after relocation

[Simon Glass]

At present on x86 machines with use cache-as-RAM, the memory goes away just
before board_init_r() is called. This means that serial drivers are
no-longer unavailable, until initr_dm() it called, etc.

Any attempt to use printf() within this period will cause a hang.

To fix this, mark the serial devices as 'unavailable' when it is no-longer
available. Bring it back when serial_initialize() is called. This means that
the debug UART will be used instead for this period.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Simplify the code in serial_initialize()

 common/board_f.c               | 7 +++++++
 drivers/serial/serial-uclass.c | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c
index 622093a..109025a 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1096,6 +1096,13 @@ void board_init_f_r(void)
 		hang();
 
 	/*
+	 * The pre-relocation drivers may be using memory that has now gone
+	 * away. Mark serial as unavailable - this will fall back to the debug
+	 * UART if available.
+	 */
+	gd->flags &= ~GD_FLG_SERIAL_READY;
+
+	/*
 	 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
 	 * Transfer execution from Flash to RAM by calculating the address
 	 * of the in-RAM copy of board_init_r() and calling it
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 1c447ff..3588fad 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -115,7 +115,7 @@ int serial_init(void)
 /* Called after relocation */
 void serial_initialize(void)
 {
-	serial_find_console_or_panic();
+	serial_init();
 }
 
 static void _serial_putc(struct udevice *dev, char ch)
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 07/51] x86: cpu: Add functions to return the family and stepping

[Simon Glass]

These two identifiers can be useful for drivers which need to adjust their
behaviour depending on the CPU family or stepping (revision).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Use gd->arch.x86_mask to get the stepping value

 arch/x86/cpu/cpu.c         | 10 ++++++++++
 arch/x86/include/asm/cpu.h | 14 ++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8800e09..afc3ecd 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -333,6 +333,16 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
 }
 
+u32 cpu_get_family_model(void)
+{
+	return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+	return gd->arch.x86_mask;
+}
+
 int x86_cpu_init_f(void)
 {
 	const u32 em_rst = ~X86_CR0_EM;
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 18b0345..987dc65 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -260,4 +260,18 @@ void cpu_call32(ulong code_seg32, ulong target, ulong table);
  */
 int cpu_jump_to_64bit(ulong setup_base, ulong target);
 
+/**
+ * cpu_get_family_model() - Get the family and model for the CPU
+ *
+ * @return the CPU ID masked with 0x0fff0ff0
+ */
+u32 cpu_get_family_model(void);
+
+/**
+ * cpu_get_stepping() - Get the stepping value for the CPU
+ *
+ * @return the CPU ID masked with 0xf
+ */
+u32 cpu_get_stepping(void);
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 08/51] x86: Move cache-as-RAM code into a common location

[Simon Glass]

This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/Makefile                          | 1 +
 arch/x86/cpu/intel_common/Makefile             | 7 +++++++
 arch/x86/cpu/{ivybridge => intel_common}/car.S | 0
 arch/x86/cpu/ivybridge/Makefile                | 1 -
 4 files changed, 8 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/intel_common/Makefile
 rename arch/x86/cpu/{ivybridge => intel_common}/car.S (100%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2ff2377..2583809 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -18,6 +18,7 @@ AFLAGS_call32.o := -fpic -fshort-wchar
 
 extra-y += call32.o
 
+obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
new file mode 100644
index 0000000..5dd9573
--- /dev/null
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_HAVE_MRC) += car.o
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/intel_common/car.S
similarity index 100%
rename from arch/x86/cpu/ivybridge/car.S
rename to arch/x86/cpu/intel_common/car.S
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 9203219..b117f0d 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,7 +7,6 @@
 ifdef CONFIG_HAVE_FSP
 obj-y += fsp_configs.o ivybridge.o
 else
-obj-y += car.o
 obj-y += cpu.o
 obj-y += early_me.o
 obj-y += gma.o
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 09/51] x86: Move microcode code to a common location

[Simon Glass]

This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Rename microcode_intel.c to microcode.c

 arch/x86/cpu/intel_common/Makefile                                    | 3 +++
 arch/x86/cpu/intel_common/car.S                                       | 2 +-
 .../x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} | 4 +++-
 arch/x86/cpu/ivybridge/Makefile                                       | 1 -
 arch/x86/cpu/ivybridge/cpu.c                                          | 2 +-
 arch/x86/include/asm/{arch-ivybridge => }/microcode.h                 | 0
 6 files changed, 8 insertions(+), 4 deletions(-)
 rename arch/x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} (98%)
 rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (100%)

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 5dd9573..ca4e171 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -5,3 +5,6 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+ifndef CONFIG_TARGET_EFI
+obj-y += microcode.o
+endif
diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S
index 1defabf..81ac976 100644
--- a/arch/x86/cpu/intel_common/car.S
+++ b/arch/x86/cpu/intel_common/car.S
@@ -12,12 +12,12 @@
  */
 
 #include <common.h>
+#include <asm/microcode.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
-#include <asm/arch/microcode.h>
 
 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/intel_common/microcode.c
similarity index 98%
rename from arch/x86/cpu/ivybridge/microcode_intel.c
rename to arch/x86/cpu/intel_common/microcode.c
index 2440a97..3054fab 100644
--- a/arch/x86/cpu/ivybridge/microcode_intel.c
+++ b/arch/x86/cpu/intel_common/microcode.c
@@ -12,10 +12,12 @@
 #include <fdtdec.h>
 #include <libfdt.h>
 #include <asm/cpu.h>
+#include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/processor.h>
-#include <asm/arch/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /**
  * struct microcode_update - standard microcode header from Intel
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index b117f0d..78006f1 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -13,7 +13,6 @@ obj-y += gma.o
 obj-y += lpc.o
 obj-y += me_status.o
 obj-y += model_206ax.o
-obj-y += microcode_intel.o
 obj-y += northbridge.o
 obj-y += report_platform.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 948833c..c54e800 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -19,13 +19,13 @@
 #include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/model_206ax.h>
-#include <asm/arch/microcode.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/microcode.h
similarity index 100%
rename from arch/x86/include/asm/arch-ivybridge/microcode.h
rename to arch/x86/include/asm/microcode.h
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 10/51] x86: Create a common header for Intel register access

[Simon Glass]

There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Use capitals for header guard

 arch/x86/cpu/ivybridge/cpu.c                      |  1 +
 arch/x86/cpu/ivybridge/gma.c                      |  1 +
 arch/x86/cpu/ivybridge/northbridge.c              |  5 +++--
 arch/x86/cpu/ivybridge/sdram.c                    |  3 ++-
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
 arch/x86/include/asm/intel_regs.h                 | 15 +++++++++++++++
 6 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 arch/x86/include/asm/intel_regs.h

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index c54e800..f847a2f 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -17,6 +17,7 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 3b6291e..87e06e7 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -12,6 +12,7 @@
 #include <errno.h>
 #include <fdtdec.h>
 #include <pci_rom.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index a066607..f7e0bc3 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -12,6 +12,7 @@
 #include <asm/msr.h>
 #include <asm/acpi.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/processor.h>
@@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
 	debug("Setting up static registers\n");
 	dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
 	dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
-	dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
-	dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+	dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+	dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
 	/* 64MB - busses 0-63 */
 	dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
 	dm_pci_write_config32(dev, PCIEXBAR + 4,
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e23c422..6f45071 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -23,6 +23,7 @@
 #include <asm/processor.h>
 #include <asm/gpio.h>
 #include <asm/global_data.h>
+#include <asm/intel_regs.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -682,7 +683,7 @@ int dram_init(void)
 {
 	struct pei_data pei_data __aligned(8) = {
 		.pei_version = PEI_VERSION,
-		.mchbar = DEFAULT_MCHBAR,
+		.mchbar = MCH_BASE_ADDRESS,
 		.dmibar = DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_PCIE_ECAM_BASE,
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index d137d67..59b05cc 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -38,7 +38,6 @@
 #define IED_SIZE	0x400000
 
 /* Northbridge BARs */
-#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
 #define DEFAULT_RCBABASE	0xfed1c000
@@ -97,8 +96,6 @@
 /*
  * MCHBAR
  */
-#define MCHBAR_REG(reg)		(DEFAULT_MCHBAR + (reg))
-
 #define SSKPD		0x5d14	/* 16bit (scratchpad) */
 #define BIOS_RESET_CPL	0x5da8	/* 8bit */
 
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
new file mode 100644
index 0000000..9725738
--- /dev/null
+++ b/arch/x86/include/asm/intel_regs.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_INTEL_REGS_H
+#define __ASM_INTEL_REGS_H
+
+/* Access the memory-controller hub */
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+#define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 11/51] x86: Add the root-complex block to common intel registers

[Simon Glass]

This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/ivybridge/bd82x6x.c          | 1 +
 arch/x86/cpu/ivybridge/lpc.c              | 6 ++++--
 arch/x86/include/asm/arch-ivybridge/pch.h | 5 -----
 arch/x86/include/asm/intel_regs.h         | 4 ++++
 4 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 9972b0a..55057e0 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -11,6 +11,7 @@
 #include <pch.h>
 #include <syscon.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/pci.h>
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 9ab5ed3..26ffaa0 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -13,6 +13,7 @@
 #include <rtc.h>
 #include <pci.h>
 #include <asm/acpi.h>
+#include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
 #include <asm/ioapic.h>
@@ -420,7 +421,7 @@ static void enable_spi_prefetch(struct udevice *pch)
 static void enable_port80_on_lpc(struct udevice *pch)
 {
 	/* Enable port 80 POST on LPC */
-	dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+	dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
 	clrbits_le32(RCB_REG(GCS), 4);
 }
 
@@ -552,7 +553,8 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
 {
 	/* Setting up Southbridge. In the northbridge code. */
 	debug("Setting up static southbridge registers\n");
-	dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+	dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
+			      RCB_BASE_ADDRESS | 1);
 	dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1);
 
 	/* Enable ACPI BAR */
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index af3e8e7..628b517 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -211,11 +211,6 @@
 
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
 
-
-/* Root Complex Register Block */
-#define DEFAULT_RCBA		0xfed1c000
-#define RCB_REG(reg)		(DEFAULT_RCBA + (reg))
-
 #define PCH_RCBA_BASE		0xf0
 
 #define VCH		0x0000	/* 32bit */
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
index 9725738..961d2bd 100644
--- a/arch/x86/include/asm/intel_regs.h
+++ b/arch/x86/include/asm/intel_regs.h
@@ -12,4 +12,8 @@
 #define MCH_BASE_SIZE		0x8000
 #define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
 
+/* Access the Root Complex Register Block */
+#define RCB_BASE_ADDRESS	0xfed1c000
+#define RCB_REG(reg)		(RCB_BASE_ADDRESS + (reg))
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 12/51] x86: Move common LPC code to its own place

[Simon Glass]

Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use capitals for header guard
- Move cougarcanyon lpc_common.h include to this patch

 arch/x86/cpu/intel_common/Makefile        |   1 +
 arch/x86/cpu/intel_common/lpc.c           | 100 ++++++++++++++++++++++++++++++
 arch/x86/cpu/ivybridge/bd82x6x.c          |  16 +----
 arch/x86/cpu/ivybridge/lpc.c              |  73 ++--------------------
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/lpc_common.h         |  59 ++++++++++++++++++
 board/intel/cougarcanyon2/cougarcanyon2.c |   1 +
 7 files changed, 167 insertions(+), 85 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/lpc.c
 create mode 100644 arch/x86/include/asm/lpc_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index ca4e171..74b005a 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+obj-y += lpc.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode.o
 endif
diff --git a/arch/x86/cpu/intel_common/lpc.c b/arch/x86/cpu/intel_common/lpc.c
new file mode 100644
index 0000000..03cb45b
--- /dev/null
+++ b/arch/x86/cpu/intel_common/lpc.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Enable Prefetching and Caching */
+static void enable_spi_prefetch(struct udevice *pch)
+{
+	u8 reg8;
+
+	dm_pci_read_config8(pch, 0xdc, &reg8);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+	/* Enable port 80 POST on LPC */
+	dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
+	clrbits_le32(RCB_REG(GCS), 4);
+}
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev:	LPC device
+ * @return 0 if OK, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev)
+{
+	struct udevice *pch = dev->parent;
+	struct reg_info {
+		u32 base;
+		u32 size;
+	} values[4], *ptr;
+	int count;
+	int i;
+
+	count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+			"intel,gen-dec", (u32 *)values,
+			sizeof(values) / sizeof(u32));
+	if (count < 0)
+		return -EINVAL;
+
+	/* Set COM1/COM2 decode range */
+	dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010);
+
+	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+	dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+			      GAMEL_LPC_EN | COMA_LPC_EN);
+
+	/* Write all registers but use 0 if we run out of data */
+	count = count * sizeof(u32) / sizeof(values[0]);
+	for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
+		u32 reg = 0;
+
+		if (i < count)
+			reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
+		dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
+	}
+
+	enable_spi_prefetch(pch);
+
+	/* This is already done in start.S, but let's do it in C */
+	enable_port80_on_lpc(pch);
+
+	return 0;
+}
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect)
+{
+	uint8_t bios_cntl;
+
+	/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+	dm_pci_read_config8(dev, bios_ctrl, &bios_cntl);
+	if (protect) {
+		bios_cntl &= ~BIOS_CTRL_BIOSWE;
+		bios_cntl |= BIT(5);
+	} else {
+		bios_cntl |= BIOS_CTRL_BIOSWE;
+		bios_cntl &= ~BIT(5);
+	}
+	dm_pci_write_config8(dev, bios_ctrl, bios_cntl);
+
+	return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 55057e0..4c039ac 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -14,6 +14,7 @@
 #include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
@@ -188,20 +189,7 @@ static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 
 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 {
-	uint8_t bios_cntl;
-
-	/* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
-	dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
-	if (protect) {
-		bios_cntl &= ~BIOS_CTRL_BIOSWE;
-		bios_cntl |= BIT(5);
-	} else {
-		bios_cntl |= BIOS_CTRL_BIOSWE;
-		bios_cntl &= ~BIT(5);
-	}
-	dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
-
-	return 0;
+	return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
 }
 
 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 26ffaa0..88ab797 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -17,6 +17,7 @@
 #include <asm/interrupt.h>
 #include <asm/io.h>
 #include <asm/ioapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 
@@ -405,26 +406,6 @@ static void pch_fixups(struct udevice *pch)
 	setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(struct udevice *pch)
-{
-	u8 reg8;
-
-	dm_pci_read_config8(pch, 0xdc, &reg8);
-	reg8 &= ~(3 << 2);
-	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-	dm_pci_write_config8(pch, 0xdc, reg8);
-}
-
-static void enable_port80_on_lpc(struct udevice *pch)
-{
-	/* Enable port 80 POST on LPC */
-	dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
-	clrbits_le32(RCB_REG(GCS), 4);
-}
-
 static void set_spi_speed(void)
 {
 	u32 fdod;
@@ -441,54 +422,6 @@ static void set_spi_speed(void)
 	clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
 }
 
-/**
- * lpc_early_init() - set up LPC serial ports and other early things
- *
- * @dev:	LPC device
- * @return 0 if OK, -ve on error
- */
-static int lpc_early_init(struct udevice *dev)
-{
-	struct reg_info {
-		u32 base;
-		u32 size;
-	} values[4], *ptr;
-	int count;
-	int i;
-
-	count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
-			"intel,gen-dec", (u32 *)values,
-			sizeof(values) / sizeof(u32));
-	if (count < 0)
-		return -EINVAL;
-
-	/* Set COM1/COM2 decode range */
-	dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
-
-	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
-	dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
-			      GAMEL_LPC_EN | COMA_LPC_EN);
-
-	/* Write all registers but use 0 if we run out of data */
-	count = count * sizeof(u32) / sizeof(values[0]);
-	for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
-		u32 reg = 0;
-
-		if (i < count)
-			reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
-		dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
-	}
-
-	enable_spi_prefetch(dev->parent);
-
-	/* This is already done in start.S, but let's do it in C */
-	enable_port80_on_lpc(dev->parent);
-
-	set_spi_speed();
-
-	return 0;
-}
-
 static int lpc_init_extra(struct udevice *dev)
 {
 	struct udevice *pch = dev->parent;
@@ -551,6 +484,8 @@ static int lpc_init_extra(struct udevice *dev)
 
 static int bd82x6x_lpc_early_init(struct udevice *dev)
 {
+	set_spi_speed();
+
 	/* Setting up Southbridge. In the northbridge code. */
 	debug("Setting up static southbridge registers\n");
 	dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,
@@ -575,7 +510,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev)
 	int ret;
 
 	if (!(gd->flags & GD_FLG_RELOC)) {
-		ret = lpc_early_init(dev);
+		ret = lpc_common_early_init(dev);
 		if (ret) {
 			debug("%s: lpc_early_init() failed\n", __func__);
 			return ret;
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 628b517..f96dc2b 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -211,8 +211,6 @@
 
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
 
-#define PCH_RCBA_BASE		0xf0
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/arch/x86/include/asm/lpc_common.h b/arch/x86/include/asm/lpc_common.h
new file mode 100644
index 0000000..a90a22d
--- /dev/null
+++ b/arch/x86/include/asm/lpc_common.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_LPC_COMMON_H
+#define __ASM_LPC_COMMON_H
+
+#define PCH_RCBA_BASE		0xf0
+
+#define RC		0x3400	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+
+#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
+#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
+#define LPC_EN			0x82 /* LPC IF Enables Register */
+#define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
+#define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
+#define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
+#define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
+#define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
+#define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
+#define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
+#define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
+#define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
+#define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
+#define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
+#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
+#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
+#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
+#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
+#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
+#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
+#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
+#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
+
+/**
+ * lpc_common_early_init() - Set up common LPC init
+ *
+ * This sets up the legacy decode areas, GEN_DEC, SPI prefetch and Port80. It
+ * also puts the RCB in the correct place so that RCB_REG() works.
+ *
+ * @dev:	LPC device (a child of the PCH)
+ * @return 0 on success, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev);
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect);
+
+#endif
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c
index 31a480a..c03247c 100644
--- a/board/intel/cougarcanyon2/cougarcanyon2.c
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -10,6 +10,7 @@
 #include <pci.h>
 #include <smsc_sio1007.h>
 #include <asm/ibmpc.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 13/51] x86: Move common CPU code to its own place

[Simon Glass]

Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use capitals for header guard

 arch/x86/cpu/intel_common/Makefile        |   1 +
 arch/x86/cpu/intel_common/cpu.c           | 111 ++++++++++++++++++++++++++++++
 arch/x86/cpu/ivybridge/cpu.c              |  82 ++--------------------
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/cpu_common.h         |  35 ++++++++++
 arch/x86/include/asm/intel_regs.h         |   9 +++
 6 files changed, 162 insertions(+), 78 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/cpu.c
 create mode 100644 arch/x86/include/asm/cpu_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 74b005a..06de964 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+obj-y += cpu.o
 obj-y += lpc.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode.o
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
new file mode 100644
index 0000000..1210943
--- /dev/null
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/lapic.h>
+#include <asm/lpc_common.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/post.h>
+#include <asm/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int report_bist_failure(void)
+{
+	if (gd->arch.bist != 0) {
+		post_code(POST_BIST_FAILURE);
+		printf("BIST failed: %08x\n", gd->arch.bist);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+int cpu_common_init(void)
+{
+	struct udevice *dev, *lpc;
+	int ret;
+
+	/* Halt if there was a built in self test failure */
+	ret = report_bist_failure();
+	if (ret)
+		return ret;
+
+	enable_lapic();
+
+	ret = microcode_update_intel();
+	if (ret && ret != -EEXIST)
+		return ret;
+
+	/* Enable upper 128bytes of CMOS */
+	writel(1 << 2, RCB_REG(RC));
+
+	/* Early chipset init required before RAM init can work */
+	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+
+	ret = uclass_first_device(UCLASS_LPC, &lpc);
+	if (ret)
+		return ret;
+	if (!lpc)
+		return -ENODEV;
+
+	/* Cause the SATA device to do its early init */
+	uclass_first_device(UCLASS_DISK, &dev);
+
+	return 0;
+}
+
+int cpu_set_flex_ratio_to_tdp_nominal(void)
+{
+	msr_t flex_ratio, msr;
+	u8 nominal_ratio;
+
+	/* Check for Flex Ratio support */
+	flex_ratio = msr_read(MSR_FLEX_RATIO);
+	if (!(flex_ratio.lo & FLEX_RATIO_EN))
+		return -EINVAL;
+
+	/* Check for >0 configurable TDPs */
+	msr = msr_read(MSR_PLATFORM_INFO);
+	if (((msr.hi >> 1) & 3) == 0)
+		return -EINVAL;
+
+	/* Use nominal TDP ratio for flex ratio */
+	msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+	nominal_ratio = msr.lo & 0xff;
+
+	/* See if flex ratio is already set to nominal TDP ratio */
+	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+		return 0;
+
+	/* Set flex ratio to nominal TDP ratio */
+	flex_ratio.lo &= ~0xff00;
+	flex_ratio.lo |= nominal_ratio << 8;
+	flex_ratio.lo |= FLEX_RATIO_LOCK;
+	msr_write(MSR_FLEX_RATIO, flex_ratio);
+
+	/* Set flex ratio in soft reset data register bits 11:6 */
+	clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
+			(nominal_ratio & 0x3f) << 6);
+
+	debug("CPU: Soft reset to set up flex ratio\n");
+
+	/* Set soft reset control to use register value */
+	setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
+
+	/* Issue warm reset, will be "CPU only" due to soft reset data */
+	outb(0x0, PORT_RESET);
+	outb(SYS_RST | RST_CPU, PORT_RESET);
+	cpu_hlt();
+
+	/* Not reached */
+	return -EINVAL;
+}
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index f847a2f..b8234ae 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -17,6 +17,7 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <asm/cpu.h>
+#include <asm/cpu_common.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
@@ -34,51 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int set_flex_ratio_to_tdp_nominal(void)
 {
-	msr_t flex_ratio, msr;
-	u8 nominal_ratio;
-
 	/* Minimum CPU revision for configurable TDP support */
 	if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
 		return -EINVAL;
 
-	/* Check for Flex Ratio support */
-	flex_ratio = msr_read(MSR_FLEX_RATIO);
-	if (!(flex_ratio.lo & FLEX_RATIO_EN))
-		return -EINVAL;
-
-	/* Check for >0 configurable TDPs */
-	msr = msr_read(MSR_PLATFORM_INFO);
-	if (((msr.hi >> 1) & 3) == 0)
-		return -EINVAL;
-
-	/* Use nominal TDP ratio for flex ratio */
-	msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
-	nominal_ratio = msr.lo & 0xff;
-
-	/* See if flex ratio is already set to nominal TDP ratio */
-	if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
-		return 0;
-
-	/* Set flex ratio to nominal TDP ratio */
-	flex_ratio.lo &= ~0xff00;
-	flex_ratio.lo |= nominal_ratio << 8;
-	flex_ratio.lo |= FLEX_RATIO_LOCK;
-	msr_write(MSR_FLEX_RATIO, flex_ratio);
-
-	/* Set flex ratio in soft reset data register bits 11:6 */
-	clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
-			(nominal_ratio & 0x3f) << 6);
-
-	/* Set soft reset control to use register value */
-	setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
-
-	/* Issue warm reset, will be "CPU only" due to soft reset data */
-	outb(0x0, PORT_RESET);
-	outb(SYS_RST | RST_CPU, PORT_RESET);
-	cpu_hlt();
-
-	/* Not reached */
-	return -EINVAL;
+	return cpu_set_flex_ratio_to_tdp_nominal();
 }
 
 int arch_cpu_init(void)
@@ -163,17 +124,6 @@ static void enable_usb_bar(struct udevice *bus)
 	pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
 }
 
-static int report_bist_failure(void)
-{
-	if (gd->arch.bist != 0) {
-		post_code(POST_BIST_FAILURE);
-		printf("BIST failed: %08x\n", gd->arch.bist);
-		return -EFAULT;
-	}
-
-	return 0;
-}
-
 int print_cpuinfo(void)
 {
 	enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
@@ -184,20 +134,6 @@ int print_cpuinfo(void)
 	uint16_t pm1_sts;
 	int ret;
 
-	/* Halt if there was a built in self test failure */
-	ret = report_bist_failure();
-	if (ret)
-		return ret;
-
-	enable_lapic();
-
-	ret = microcode_update_intel();
-	if (ret)
-		return ret;
-
-	/* Enable upper 128bytes of CMOS */
-	writel(1 << 2, RCB_REG(RC));
-
 	/* TODO: cmos_post_init() */
 	if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
 		debug("soft reset detected\n");
@@ -208,17 +144,9 @@ int print_cpuinfo(void)
 		reset_cpu(0);
 	}
 
-	/* Early chipset init required before RAM init can work */
-	uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
-
-	ret = uclass_first_device(UCLASS_LPC, &lpc);
+	ret = cpu_common_init();
 	if (ret)
 		return ret;
-	if (!dev)
-		return -ENODEV;
-
-	/* Cause the SATA device to do its early init */
-	uclass_first_device(UCLASS_DISK, &dev);
 
 	/* Check PM1_STS[15] to see if we are waking from Sx */
 	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
@@ -244,8 +172,10 @@ int print_cpuinfo(void)
 		return -ENODEV;
 
 	/* Prepare USB controller early in S3 resume */
-	if (boot_mode == PEI_BOOT_RESUME)
+	if (boot_mode == PEI_BOOT_RESUME) {
+		uclass_first_device(UCLASS_LPC, &lpc);
 		enable_usb_bar(pci_get_controller(lpc->parent));
+	}
 
 	gd->arch.pei_boot_mode = boot_mode;
 
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index f96dc2b..e72ff2a 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -332,8 +332,6 @@
 #define SPI_FREQ_SWSEQ	0x3893
 #define SPI_DESC_COMP0	0x38b0
 #define SPI_FREQ_WR_ERA	0x38b4
-#define SOFT_RESET_CTRL 0x38f4
-#define SOFT_RESET_DATA 0x38f8
 
 #define DIR_ROUTE(a, b, c, d) \
 		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h
new file mode 100644
index 0000000..562de3e
--- /dev/null
+++ b/arch/x86/include/asm/cpu_common.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_CPU_COMMON_H
+#define __ASM_CPU_COMMON_H
+
+#define IA32_PERF_CTL			0x199
+
+/**
+ * cpu_common_init() - Set up common CPU init
+ *
+ * This reports BIST failure, enables the LAPIC, updates microcode, enables
+ * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_common_init(void);
+
+/**
+ * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
+ *
+ * If a change is needed, this function will do a soft reset so it takes
+ * effect.
+ *
+ * Some details are available here:
+ * http://forum.hwbot.org/showthread.php?t=76092
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_set_flex_ratio_to_tdp_nominal(void);
+
+#endif
diff --git a/arch/x86/include/asm/intel_regs.h b/arch/x86/include/asm/intel_regs.h
index 961d2bd..d2a6d26 100644
--- a/arch/x86/include/asm/intel_regs.h
+++ b/arch/x86/include/asm/intel_regs.h
@@ -12,8 +12,17 @@
 #define MCH_BASE_SIZE		0x8000
 #define MCHBAR_REG(reg)		(MCH_BASE_ADDRESS + (reg))
 
+#define MCHBAR_PEI_VERSION	0x5034
+#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define MCH_DDR_POWER_LIMIT_LO	0x58e0
+#define MCH_DDR_POWER_LIMIT_HI	0x58e4
+
 /* Access the Root Complex Register Block */
 #define RCB_BASE_ADDRESS	0xfed1c000
 #define RCB_REG(reg)		(RCB_BASE_ADDRESS + (reg))
 
+#define SOFT_RESET_CTRL		0x38f4
+#define SOFT_RESET_DATA		0x38f8
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 14/51] x86: Rename PORT_RESET to IO_PORT_RESET

[Simon Glass]

This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/cpu.c               | 4 ++--
 arch/x86/cpu/intel_common/cpu.c  | 4 ++--
 arch/x86/include/asm/processor.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index afc3ecd..7dfe071 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -469,14 +469,14 @@ void  flush_cache(unsigned long dummy1, unsigned long dummy2)
 __weak void reset_cpu(ulong addr)
 {
 	/* Do a hard reset through the chipset's reset control register */
-	outb(SYS_RST | RST_CPU, PORT_RESET);
+	outb(SYS_RST | RST_CPU, IO_PORT_RESET);
 	for (;;)
 		cpu_hlt();
 }
 
 void x86_full_reset(void)
 {
-	outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
+	outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
 }
 
 int dcache_status(void)
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 1210943..93e4505 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -102,8 +102,8 @@ int cpu_set_flex_ratio_to_tdp_nominal(void)
 	setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
 
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
-	outb(0x0, PORT_RESET);
-	outb(SYS_RST | RST_CPU, PORT_RESET);
+	outb(0x0, IO_PORT_RESET);
+	outb(SYS_RST | RST_CPU, IO_PORT_RESET);
 	cpu_hlt();
 
 	/* Not reached */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 7c77b90..cefc633 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -36,7 +36,7 @@
  *
  * The naming follows Intel's naming.
  */
-#define PORT_RESET		0xcf9
+#define IO_PORT_RESET		0xcf9
 
 enum {
 	SYS_RST		= 1 << 1,	/* 0 for soft reset, 1 for hard reset */
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 15/51] x86: Move Intel Management Engine code to a common place

[Simon Glass]

Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use capitals for header guard

 arch/x86/cpu/intel_common/Makefile                 |   2 +
 .../cpu/{ivybridge => intel_common}/me_status.c    |  20 +-
 .../{ivybridge => intel_common}/report_platform.c  |   2 +-
 arch/x86/cpu/ivybridge/Makefile                    |   2 -
 arch/x86/cpu/ivybridge/early_me.c                  |  31 +-
 arch/x86/cpu/ivybridge/sdram.c                     |   3 +-
 arch/x86/include/asm/arch-ivybridge/me.h           | 333 +-----------------
 arch/x86/include/asm/arch-ivybridge/sandybridge.h  |   2 -
 arch/x86/include/asm/me_common.h                   | 372 +++++++++++++++++++++
 arch/x86/include/asm/report_platform.h             |  19 ++
 10 files changed, 417 insertions(+), 369 deletions(-)
 rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%)
 rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%)
 create mode 100644 arch/x86/include/asm/me_common.h
 create mode 100644 arch/x86/include/asm/report_platform.h

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 06de964..1918ca3 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -7,6 +7,8 @@
 obj-$(CONFIG_HAVE_MRC) += car.o
 obj-y += cpu.o
 obj-y += lpc.o
+obj-$(CONFIG_HAVE_MRC) += me_status.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode.o
 endif
+obj-$(CONFIG_HAVE_MRC) += report_platform.o
diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/intel_common/me_status.c
similarity index 93%
rename from arch/x86/cpu/ivybridge/me_status.c
rename to arch/x86/cpu/intel_common/me_status.c
index 15cf69f..130d219 100644
--- a/arch/x86/cpu/ivybridge/me_status.c
+++ b/arch/x86/cpu/intel_common/me_status.c
@@ -128,7 +128,14 @@ static const char *const me_progress_policy_values[] = {
 	[0x10] = "Required VSCC values for flash parts do not match",
 };
 
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+
+/**
+ * _intel_me_status() - Check Intel Management Engine status
+ *
+ * struct hfs:	Firmware status
+ * struct gmes:	Management engine status
+ */
+static void _intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
 {
 	/* Check Current States */
 	debug("ME: FW Partition Table      : %s\n",
@@ -193,3 +200,14 @@ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
 	}
 	debug("\n");
 }
+
+void intel_me_status(struct udevice *me_dev)
+{
+	struct me_hfs hfs;
+	struct me_gmes gmes;
+
+	pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
+	pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
+
+	_intel_me_status(&hfs, &gmes);
+}
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/intel_common/report_platform.c
similarity index 98%
rename from arch/x86/cpu/ivybridge/report_platform.c
rename to arch/x86/cpu/intel_common/report_platform.c
index c78322a..05e1cf9 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/intel_common/report_platform.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <asm/cpu.h>
 #include <asm/pci.h>
+#include <asm/report_platform.h>
 #include <asm/arch/pch.h>
-#include <asm/arch/sandybridge.h>
 
 static void report_cpu_info(void)
 {
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 78006f1..9cdb07b 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -11,10 +11,8 @@ obj-y += cpu.o
 obj-y += early_me.o
 obj-y += gma.o
 obj-y += lpc.o
-obj-y += me_status.o
 obj-y += model_206ax.o
 obj-y += northbridge.o
-obj-y += report_platform.o
 obj-y += sata.o
 obj-y += sdram.o
 endif
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index b1df77d..cda96ab 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -27,35 +27,6 @@ static const char *const me_ack_values[] = {
 	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
 };
 
-static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
-				      int offset)
-{
-	u32 dword;
-
-	dm_pci_read_config32(me_dev, offset, &dword);
-	memcpy(ptr, &dword, sizeof(dword));
-}
-
-static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
-				       int offset)
-{
-	u32 dword = 0;
-
-	memcpy(&dword, ptr, sizeof(dword));
-	dm_pci_write_config32(me_dev, offset, dword);
-}
-
-void intel_early_me_status(struct udevice *me_dev)
-{
-	struct me_hfs hfs;
-	struct me_gmes gmes;
-
-	pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS);
-	pci_read_dword_ptr(me_dev, &gmes, PCI_ME_GMES);
-
-	intel_me_status(&hfs, &gmes);
-}
-
 int intel_early_me_init(struct udevice *me_dev)
 {
 	int count;
@@ -159,7 +130,7 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
 	debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
 
 	/* Check status after acknowledgement */
-	intel_early_me_status(me_dev);
+	intel_me_status(me_dev);
 
 	switch (hfs.ack_data) {
 	case ME_HFS_ACK_CONTINUE:
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 6f45071..af76826 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -27,6 +27,7 @@
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
+#include <asm/report_platform.h>
 #include <asm/arch/me.h>
 #include <asm/arch/pei_data.h>
 #include <asm/arch/pch.h>
@@ -384,7 +385,7 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
 	if (BASE_REV_SNB == done)
 		intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
 	else
-		intel_early_me_status(me_dev);
+		intel_me_status(me_dev);
 
 	post_system_agent_init(pei_data);
 	report_memory_config();
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
index eb1b73f..bc1bc8e 100644
--- a/arch/x86/include/asm/arch-ivybridge/me.h
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -9,225 +9,7 @@
 #ifndef _ASM_INTEL_ME_H
 #define _ASM_INTEL_ME_H
 
-#include <linux/compiler.h>
-#include <linux/types.h>
-
-#define ME_RETRY		100000	/* 1 second */
-#define ME_DELAY		10	/* 10 us */
-
-/*
- * Management Engine PCI registers
- */
-
-#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
-#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
-
-#define PCI_ME_HFS		0x40
-#define  ME_HFS_CWS_RESET	0
-#define  ME_HFS_CWS_INIT	1
-#define  ME_HFS_CWS_REC		2
-#define  ME_HFS_CWS_NORMAL	5
-#define  ME_HFS_CWS_WAIT	6
-#define  ME_HFS_CWS_TRANS	7
-#define  ME_HFS_CWS_INVALID	8
-#define  ME_HFS_STATE_PREBOOT	0
-#define  ME_HFS_STATE_M0_UMA	1
-#define  ME_HFS_STATE_M3	4
-#define  ME_HFS_STATE_M0	5
-#define  ME_HFS_STATE_BRINGUP	6
-#define  ME_HFS_STATE_ERROR	7
-#define  ME_HFS_ERROR_NONE	0
-#define  ME_HFS_ERROR_UNCAT	1
-#define  ME_HFS_ERROR_IMAGE	3
-#define  ME_HFS_ERROR_DEBUG	4
-#define  ME_HFS_MODE_NORMAL	0
-#define  ME_HFS_MODE_DEBUG	2
-#define  ME_HFS_MODE_DIS	3
-#define  ME_HFS_MODE_OVER_JMPR	4
-#define  ME_HFS_MODE_OVER_MEI	5
-#define  ME_HFS_BIOS_DRAM_ACK	1
-#define  ME_HFS_ACK_NO_DID	0
-#define  ME_HFS_ACK_RESET	1
-#define  ME_HFS_ACK_PWR_CYCLE	2
-#define  ME_HFS_ACK_S3		3
-#define  ME_HFS_ACK_S4		4
-#define  ME_HFS_ACK_S5		5
-#define  ME_HFS_ACK_GBL_RESET	6
-#define  ME_HFS_ACK_CONTINUE	7
-
-struct me_hfs {
-	u32 working_state:4;
-	u32 mfg_mode:1;
-	u32 fpt_bad:1;
-	u32 operation_state:3;
-	u32 fw_init_complete:1;
-	u32 ft_bup_ld_flr:1;
-	u32 update_in_progress:1;
-	u32 error_code:4;
-	u32 operation_mode:4;
-	u32 reserved:4;
-	u32 boot_options_present:1;
-	u32 ack_data:3;
-	u32 bios_msg_ack:4;
-} __packed;
-
-#define PCI_ME_UMA		0x44
-
-struct me_uma {
-	u32 size:6;
-	u32 reserved_1:10;
-	u32 valid:1;
-	u32 reserved_0:14;
-	u32 set_to_one:1;
-} __packed;
-
-#define PCI_ME_H_GS		0x4c
-#define  ME_INIT_DONE		1
-#define  ME_INIT_STATUS_SUCCESS	0
-#define  ME_INIT_STATUS_NOMEM	1
-#define  ME_INIT_STATUS_ERROR	2
-
-struct me_did {
-	u32 uma_base:16;
-	u32 reserved:8;
-	u32 status:4;
-	u32 init_done:4;
-} __packed;
-
-#define PCI_ME_GMES		0x48
-#define  ME_GMES_PHASE_ROM	0
-#define  ME_GMES_PHASE_BUP	1
-#define  ME_GMES_PHASE_UKERNEL	2
-#define  ME_GMES_PHASE_POLICY	3
-#define  ME_GMES_PHASE_MODULE	4
-#define  ME_GMES_PHASE_UNKNOWN	5
-#define  ME_GMES_PHASE_HOST	6
-
-struct me_gmes {
-	u32 bist_in_prog:1;
-	u32 icc_prog_sts:2;
-	u32 invoke_mebx:1;
-	u32 cpu_replaced_sts:1;
-	u32 mbp_rdy:1;
-	u32 mfs_failure:1;
-	u32 warm_rst_req_for_df:1;
-	u32 cpu_replaced_valid:1;
-	u32 reserved_1:2;
-	u32 fw_upd_ipu:1;
-	u32 reserved_2:4;
-	u32 current_state:8;
-	u32 current_pmevent:4;
-	u32 progress_code:4;
-} __packed;
-
-#define PCI_ME_HERES		0xbc
-#define  PCI_ME_EXT_SHA1	0x00
-#define  PCI_ME_EXT_SHA256	0x02
-#define PCI_ME_HER(x)		(0xc0+(4*(x)))
-
-struct me_heres {
-	u32 extend_reg_algorithm:4;
-	u32 reserved:26;
-	u32 extend_feature_present:1;
-	u32 extend_reg_valid:1;
-} __packed;
-
-/*
- * Management Engine MEI registers
- */
-
-#define MEI_H_CB_WW		0x00
-#define MEI_H_CSR		0x04
-#define MEI_ME_CB_RW		0x08
-#define MEI_ME_CSR_HA		0x0c
-
-struct mei_csr {
-	u32 interrupt_enable:1;
-	u32 interrupt_status:1;
-	u32 interrupt_generate:1;
-	u32 ready:1;
-	u32 reset:1;
-	u32 reserved:3;
-	u32 buffer_read_ptr:8;
-	u32 buffer_write_ptr:8;
-	u32 buffer_depth:8;
-} __packed;
-
-#define MEI_ADDRESS_CORE	0x01
-#define MEI_ADDRESS_AMT		0x02
-#define MEI_ADDRESS_RESERVED	0x03
-#define MEI_ADDRESS_WDT		0x04
-#define MEI_ADDRESS_MKHI	0x07
-#define MEI_ADDRESS_ICC		0x08
-#define MEI_ADDRESS_THERMAL	0x09
-
-#define MEI_HOST_ADDRESS	0
-
-struct mei_header {
-	u32 client_address:8;
-	u32 host_address:8;
-	u32 length:9;
-	u32 reserved:6;
-	u32 is_complete:1;
-} __packed;
-
-#define MKHI_GROUP_ID_CBM	0x00
-#define MKHI_GROUP_ID_FWCAPS	0x03
-#define MKHI_GROUP_ID_MDES	0x08
-#define MKHI_GROUP_ID_GEN	0xff
-
-#define MKHI_GLOBAL_RESET	0x0b
-
-#define MKHI_FWCAPS_GET_RULE	0x02
-
-#define MKHI_MDES_ENABLE	0x09
-
-#define MKHI_GET_FW_VERSION	0x02
-#define MKHI_END_OF_POST	0x0c
-#define MKHI_FEATURE_OVERRIDE	0x14
-
-struct mkhi_header {
-	u32 group_id:8;
-	u32 command:7;
-	u32 is_response:1;
-	u32 reserved:8;
-	u32 result:8;
-} __packed;
-
-struct me_fw_version {
-	u16 code_minor;
-	u16 code_major;
-	u16 code_build_number;
-	u16 code_hot_fix;
-	u16 recovery_minor;
-	u16 recovery_major;
-	u16 recovery_build_number;
-	u16 recovery_hot_fix;
-} __packed;
-
-
-#define HECI_EOP_STATUS_SUCCESS       0x0
-#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
-
-#define CBM_RR_GLOBAL_RESET	0x01
-
-#define GLOBAL_RESET_BIOS_MRC	0x01
-#define GLOBAL_RESET_BIOS_POST	0x02
-#define GLOBAL_RESET_MEBX	0x03
-
-struct me_global_reset {
-	u8 request_origin;
-	u8 reset_type;
-} __packed;
-
-enum me_bios_path {
-	ME_NORMAL_BIOS_PATH,
-	ME_S3WAKE_BIOS_PATH,
-	ME_ERROR_BIOS_PATH,
-	ME_RECOVERY_BIOS_PATH,
-	ME_DISABLE_BIOS_PATH,
-	ME_FIRMWARE_UPDATE_BIOS_PATH,
-};
+#include <asm/me_common.h>
 
 struct __packed mbp_fw_version_name {
 	u32 major_version:16;
@@ -244,46 +26,6 @@ struct __packed mbp_icc_profile {
 	u32 register_lock_mask[3];
 };
 
-struct __packed mefwcaps_sku {
-	u32 full_net:1;
-	u32 std_net:1;
-	u32 manageability:1;
-	u32 small_business:1;
-	u32 l3manageability:1;
-	u32 intel_at:1;
-	u32 intel_cls:1;
-	u32 reserved:3;
-	u32 intel_mpc:1;
-	u32 icc_over_clocking:1;
-	u32 pavp:1;
-	u32 reserved_1:4;
-	u32 ipv6:1;
-	u32 kvm:1;
-	u32 och:1;
-	u32 vlan:1;
-	u32 tls:1;
-	u32 reserved_4:1;
-	u32 wlan:1;
-	u32 reserved_5:8;
-};
-
-struct __packed tdt_state_flag {
-	u16 lock_state:1;
-	u16 authenticate_module:1;
-	u16 s3authentication:1;
-	u16 flash_wear_out:1;
-	u16 flash_variable_security:1;
-	u16 wwan3gpresent:1;
-	u16 wwan3goob:1;
-	u16 reserved:9;
-};
-
-struct __packed tdt_state_info {
-	u8 state;
-	u8 last_theft_trigger;
-	struct tdt_state_flag flags;
-};
-
 struct __packed platform_type_rule_data {
 	u32 platform_target_usage_type:4;
 	u32 platform_target_market_type:2;
@@ -299,16 +41,6 @@ struct __packed mbp_fw_caps {
 	u8 available;
 };
 
-struct __packed mbp_rom_bist_data {
-	u16 device_id;
-	u16 fuse_test_flags;
-	u32 umchid[4];
-};
-
-struct __packed mbp_platform_key {
-	u32 key[8];
-};
-
 struct __packed mbp_plat_type {
 	struct platform_type_rule_data rule_data;
 	u8 available;
@@ -325,67 +57,4 @@ struct __packed me_bios_payload {
 	u32 mfsintegrity;
 };
 
-struct __packed mbp_header {
-	u32 mbp_size:8;
-	u32 num_entries:8;
-	u32 rsvd:16;
-};
-
-struct __packed mbp_item_header {
-	u32 app_id:8;
-	u32 item_id:8;
-	u32 length:8;
-	u32 rsvd:8;
-};
-
-struct __packed me_fwcaps {
-	u32 id;
-	u8 length;
-	struct mefwcaps_sku caps_sku;
-	u8 reserved[3];
-};
-
-/**
- * intel_me_status() - Check Intel Management Engine status
- *
- * struct hfs:	Firmware status
- * struct gmes:	Management engine status
- */
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
-
-/**
- * intel_early_me_status() - Check early Management Engine Status
- *
- * @me_dev:	Management engine PCI device
- */
-void intel_early_me_status(struct udevice *me_dev);
-
-/**
- * intel_early_me_init() - Early Intel Management Engine init
- *
- * @me_dev:	Management engine PCI device
- * @return 0 if OK, -ve on error
- */
-int intel_early_me_init(struct udevice *me_dev);
-
-/**
- * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
- *
- * @me_dev:	Management engine PCI device
- * @return UMA size if OK, -EINVAL on error
- */
-int intel_early_me_uma_size(struct udevice *me_dev);
-
-/**
- * intel_early_me_init_done() - Complete Intel Management Engine init
- *
- * @dev:	Northbridge device
- * @me_dev:	Management engine PCI device
- * @status:	Status result (ME_INIT_...)
- * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
- * if ME did not respond
- */
-int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
-			     uint status);
-
 #endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index 59b05cc..c395d53 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -113,8 +113,6 @@
  */
 int bridge_silicon_revision(struct udevice *dev);
 
-void report_platform_info(struct udevice *dev);
-
 void sandybridge_early_init(int chipset_type);
 
 #endif
diff --git a/arch/x86/include/asm/me_common.h b/arch/x86/include/asm/me_common.h
new file mode 100644
index 0000000..7089117
--- /dev/null
+++ b/arch/x86/include/asm/me_common.h
@@ -0,0 +1,372 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Coreboot copies lots of code around. Here we are trying to keep the common
+ * code in a separate file to reduce code duplication and hopefully make it
+ * easier to add new platform.
+ *
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ME_COMMON_H
+#define __ASM_ME_COMMON_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define MCHBAR_PEI_VERSION	0x5034
+
+#define ME_RETRY		100000	/* 1 second */
+#define ME_DELAY		10	/* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
+#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
+
+#define PCI_ME_HFS		0x40
+#define  ME_HFS_CWS_RESET	0
+#define  ME_HFS_CWS_INIT	1
+#define  ME_HFS_CWS_REC		2
+#define  ME_HFS_CWS_NORMAL	5
+#define  ME_HFS_CWS_WAIT	6
+#define  ME_HFS_CWS_TRANS	7
+#define  ME_HFS_CWS_INVALID	8
+#define  ME_HFS_STATE_PREBOOT	0
+#define  ME_HFS_STATE_M0_UMA	1
+#define  ME_HFS_STATE_M3	4
+#define  ME_HFS_STATE_M0	5
+#define  ME_HFS_STATE_BRINGUP	6
+#define  ME_HFS_STATE_ERROR	7
+#define  ME_HFS_ERROR_NONE	0
+#define  ME_HFS_ERROR_UNCAT	1
+#define  ME_HFS_ERROR_IMAGE	3
+#define  ME_HFS_ERROR_DEBUG	4
+#define  ME_HFS_MODE_NORMAL	0
+#define  ME_HFS_MODE_DEBUG	2
+#define  ME_HFS_MODE_DIS	3
+#define  ME_HFS_MODE_OVER_JMPR	4
+#define  ME_HFS_MODE_OVER_MEI	5
+#define  ME_HFS_BIOS_DRAM_ACK	1
+#define  ME_HFS_ACK_NO_DID	0
+#define  ME_HFS_ACK_RESET	1
+#define  ME_HFS_ACK_PWR_CYCLE	2
+#define  ME_HFS_ACK_S3		3
+#define  ME_HFS_ACK_S4		4
+#define  ME_HFS_ACK_S5		5
+#define  ME_HFS_ACK_GBL_RESET	6
+#define  ME_HFS_ACK_CONTINUE	7
+
+struct me_hfs {
+	u32 working_state:4;
+	u32 mfg_mode:1;
+	u32 fpt_bad:1;
+	u32 operation_state:3;
+	u32 fw_init_complete:1;
+	u32 ft_bup_ld_flr:1;
+	u32 update_in_progress:1;
+	u32 error_code:4;
+	u32 operation_mode:4;
+	u32 reserved:4;
+	u32 boot_options_present:1;
+	u32 ack_data:3;
+	u32 bios_msg_ack:4;
+} __packed;
+
+#define PCI_ME_UMA		0x44
+
+struct me_uma {
+	u32 size:6;
+	u32 reserved_1:10;
+	u32 valid:1;
+	u32 reserved_0:14;
+	u32 set_to_one:1;
+} __packed;
+
+#define PCI_ME_H_GS		0x4c
+#define  ME_INIT_DONE		1
+#define  ME_INIT_STATUS_SUCCESS	0
+#define  ME_INIT_STATUS_NOMEM	1
+#define  ME_INIT_STATUS_ERROR	2
+
+struct me_did {
+	u32 uma_base:16;
+	u32 reserved:7;
+	u32 rapid_start:1;	/* Broadwell only */
+	u32 status:4;
+	u32 init_done:4;
+} __packed;
+
+#define PCI_ME_GMES		0x48
+#define  ME_GMES_PHASE_ROM	0
+#define  ME_GMES_PHASE_BUP	1
+#define  ME_GMES_PHASE_UKERNEL	2
+#define  ME_GMES_PHASE_POLICY	3
+#define  ME_GMES_PHASE_MODULE	4
+#define  ME_GMES_PHASE_UNKNOWN	5
+#define  ME_GMES_PHASE_HOST	6
+
+struct me_gmes {
+	u32 bist_in_prog:1;
+	u32 icc_prog_sts:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_rst_req_for_df:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved_1:2;
+	u32 fw_upd_ipu:1;
+	u32 reserved_2:4;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HERES		0xbc
+#define  PCI_ME_EXT_SHA1	0x00
+#define  PCI_ME_EXT_SHA256	0x02
+#define PCI_ME_HER(x)		(0xc0+(4*(x)))
+
+struct me_heres {
+	u32 extend_reg_algorithm:4;
+	u32 reserved:26;
+	u32 extend_feature_present:1;
+	u32 extend_reg_valid:1;
+} __packed;
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW		0x00
+#define MEI_H_CSR		0x04
+#define MEI_ME_CB_RW		0x08
+#define MEI_ME_CSR_HA		0x0c
+
+struct mei_csr {
+	u32 interrupt_enable:1;
+	u32 interrupt_status:1;
+	u32 interrupt_generate:1;
+	u32 ready:1;
+	u32 reset:1;
+	u32 reserved:3;
+	u32 buffer_read_ptr:8;
+	u32 buffer_write_ptr:8;
+	u32 buffer_depth:8;
+} __packed;
+
+#define MEI_ADDRESS_CORE	0x01
+#define MEI_ADDRESS_AMT		0x02
+#define MEI_ADDRESS_RESERVED	0x03
+#define MEI_ADDRESS_WDT		0x04
+#define MEI_ADDRESS_MKHI	0x07
+#define MEI_ADDRESS_ICC		0x08
+#define MEI_ADDRESS_THERMAL	0x09
+
+#define MEI_HOST_ADDRESS	0
+
+struct mei_header {
+	u32 client_address:8;
+	u32 host_address:8;
+	u32 length:9;
+	u32 reserved:6;
+	u32 is_complete:1;
+} __packed;
+
+#define MKHI_GROUP_ID_CBM	0x00
+#define MKHI_GROUP_ID_FWCAPS	0x03
+#define MKHI_GROUP_ID_MDES	0x08
+#define MKHI_GROUP_ID_GEN	0xff
+
+#define MKHI_GET_FW_VERSION	0x02
+#define MKHI_END_OF_POST	0x0c
+#define MKHI_FEATURE_OVERRIDE	0x14
+
+/* Ivybridge only: */
+#define MKHI_GLOBAL_RESET	0x0b
+#define MKHI_FWCAPS_GET_RULE	0x02
+#define MKHI_MDES_ENABLE	0x09
+
+/* Broadwell only: */
+#define MKHI_GLOBAL_RESET	0x0b
+#define MKHI_FWCAPS_GET_RULE	0x02
+#define MKHI_GROUP_ID_HMRFPO	0x05
+#define MKHI_HMRFPO_LOCK	0x02
+#define MKHI_HMRFPO_LOCK_NOACK	0x05
+#define MKHI_MDES_ENABLE	0x09
+#define MKHI_END_OF_POST_NOACK	0x1a
+
+struct mkhi_header {
+	u32 group_id:8;
+	u32 command:7;
+	u32 is_response:1;
+	u32 reserved:8;
+	u32 result:8;
+} __packed;
+
+struct me_fw_version {
+	u16 code_minor;
+	u16 code_major;
+	u16 code_build_number;
+	u16 code_hot_fix;
+	u16 recovery_minor;
+	u16 recovery_major;
+	u16 recovery_build_number;
+	u16 recovery_hot_fix;
+} __packed;
+
+
+#define HECI_EOP_STATUS_SUCCESS       0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET	0x01
+
+#define GLOBAL_RESET_BIOS_MRC	0x01
+#define GLOBAL_RESET_BIOS_POST	0x02
+#define GLOBAL_RESET_MEBX	0x03
+
+struct me_global_reset {
+	u8 request_origin;
+	u8 reset_type;
+} __packed;
+
+enum me_bios_path {
+	ME_NORMAL_BIOS_PATH,
+	ME_S3WAKE_BIOS_PATH,
+	ME_ERROR_BIOS_PATH,
+	ME_RECOVERY_BIOS_PATH,
+	ME_DISABLE_BIOS_PATH,
+	ME_FIRMWARE_UPDATE_BIOS_PATH,
+};
+
+struct __packed mefwcaps_sku {
+	u32 full_net:1;
+	u32 std_net:1;
+	u32 manageability:1;
+	u32 small_business:1;
+	u32 l3manageability:1;
+	u32 intel_at:1;
+	u32 intel_cls:1;
+	u32 reserved:3;
+	u32 intel_mpc:1;
+	u32 icc_over_clocking:1;
+	u32 pavp:1;
+	u32 reserved_1:4;
+	u32 ipv6:1;
+	u32 kvm:1;
+	u32 och:1;
+	u32 vlan:1;
+	u32 tls:1;
+	u32 reserved_4:1;
+	u32 wlan:1;
+	u32 reserved_5:8;
+};
+
+struct __packed tdt_state_flag {
+	u16 lock_state:1;
+	u16 authenticate_module:1;
+	u16 s3authentication:1;
+	u16 flash_wear_out:1;
+	u16 flash_variable_security:1;
+	u16 wwan3gpresent:1;	/* ivybridge only */
+	u16 wwan3goob:1;	/* ivybridge only */
+	u16 reserved:9;
+};
+
+struct __packed tdt_state_info {
+	u8 state;
+	u8 last_theft_trigger;
+	struct tdt_state_flag flags;
+};
+
+struct __packed mbp_rom_bist_data {
+	u16 device_id;
+	u16 fuse_test_flags;
+	u32 umchid[4];
+};
+
+struct __packed mbp_platform_key {
+	u32 key[8];
+};
+
+struct __packed mbp_header {
+	u32 mbp_size:8;
+	u32 num_entries:8;
+	u32 rsvd:16;
+};
+
+struct __packed mbp_item_header {
+	u32 app_id:8;
+	u32 item_id:8;
+	u32 length:8;
+	u32 rsvd:8;
+};
+
+struct __packed me_fwcaps {
+	u32 id;
+	u8 length;
+	struct mefwcaps_sku caps_sku;
+	u8 reserved[3];
+};
+
+/**
+ * intel_me_status() - Check Intel Management Engine status
+ *
+ * @me_dev:	Management engine PCI device
+ */
+void intel_me_status(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init() - Early Intel Management Engine init
+ *
+ * @me_dev:	Management engine PCI device
+ * @return 0 if OK, -ve on error
+ */
+int intel_early_me_init(struct udevice *me_dev);
+
+/**
+ * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
+ *
+ * @me_dev:	Management engine PCI device
+ * @return UMA size if OK, -EINVAL on error
+ */
+int intel_early_me_uma_size(struct udevice *me_dev);
+
+/**
+ * intel_early_me_init_done() - Complete Intel Management Engine init
+ *
+ * @dev:	Northbridge device
+ * @me_dev:	Management engine PCI device
+ * @status:	Status result (ME_INIT_...)
+ * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
+ * if ME did not respond
+ */
+int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
+			     uint status);
+
+int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
+			  uint16_t *checksum);
+
+static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
+				      int offset)
+{
+	u32 dword;
+
+	dm_pci_read_config32(me_dev, offset, &dword);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
+				       int offset)
+{
+	u32 dword = 0;
+
+	memcpy(&dword, ptr, sizeof(dword));
+	dm_pci_write_config32(me_dev, offset, dword);
+}
+#endif
diff --git a/arch/x86/include/asm/report_platform.h b/arch/x86/include/asm/report_platform.h
new file mode 100644
index 0000000..4607dd3
--- /dev/null
+++ b/arch/x86/include/asm/report_platform.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ARCH_REPORT_PLATFORM_H
+#define __ARCH_REPORT_PLATFORM_H
+
+/**
+ * report_platform_info() - Report platform information
+ *
+ * This reports information about the CPU and chipset.
+ *
+ * @dev:	Northbridge device
+ */
+void report_platform_info(struct udevice *dev);
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 16/51] x86: ivybridge: Drop sandybridge_early_init()

[Simon Glass]

This function was removed in the previous clean-up. Drop it from the header
file also.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index c395d53..8e0f668 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -113,6 +113,4 @@
  */
 int bridge_silicon_revision(struct udevice *dev);
 
-void sandybridge_early_init(int chipset_type);
-
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 17/51] x86: Move common PCH code into a common place

[Simon Glass]

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/intel_common/Makefile        |  1 +
 arch/x86/cpu/intel_common/pch_common.c    | 25 ++++++++++++++
 arch/x86/cpu/ivybridge/cpu.c              |  1 +
 arch/x86/cpu/ivybridge/sata.c             | 47 +++++++++-----------------
 arch/x86/include/asm/arch-ivybridge/pch.h | 53 -----------------------------
 arch/x86/include/asm/pch_common.h         | 56 +++++++++++++++++++++++++++++++
 6 files changed, 99 insertions(+), 84 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/pch_common.c
 create mode 100644 arch/x86/include/asm/pch_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 1918ca3..e235526 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_HAVE_MRC) += me_status.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode.o
 endif
+obj-y += pch_common.o
 obj-$(CONFIG_HAVE_MRC) += report_platform.o
diff --git a/arch/x86/cpu/intel_common/pch_common.c b/arch/x86/cpu/intel_common/pch_common.c
new file mode 100644
index 0000000..1f05b44
--- /dev/null
+++ b/arch/x86/cpu/intel_common/pch_common.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/pch_common.h>
+
+u32 pch_common_sir_read(struct udevice *dev, int idx)
+{
+	u32 data;
+
+	dm_pci_write_config32(dev, SATA_SIRI, idx);
+	dm_pci_read_config32(dev, SATA_SIRD, &data);
+
+	return data;
+}
+
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value)
+{
+	dm_pci_write_config32(dev, SATA_SIRI, idx);
+	dm_pci_write_config32(dev, SATA_SIRD, value);
+}
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index b8234ae..78fa73a 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -21,6 +21,7 @@
 #include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
 #include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index a59d9ed..c2dbab8 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -9,28 +9,13 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <asm/io.h>
+#include <asm/pch_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/bd82x6x.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static inline u32 sir_read(struct udevice *dev, int idx)
-{
-	u32 data;
-
-	dm_pci_write_config32(dev, SATA_SIRI, idx);
-	dm_pci_read_config32(dev, SATA_SIRD, &data);
-
-	return data;
-}
-
-static inline void sir_write(struct udevice *dev, int idx, u32 value)
-{
-	dm_pci_write_config32(dev, SATA_SIRI, idx);
-	dm_pci_write_config32(dev, SATA_SIRD, value);
-}
-
 static void common_sata_init(struct udevice *dev, unsigned int port_map)
 {
 	u32 reg32;
@@ -177,27 +162,27 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 		pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
 
 	/* Additional Programming Requirements */
-	sir_write(dev, 0x04, 0x00001600);
-	sir_write(dev, 0x28, 0xa0000033);
-	reg32 = sir_read(dev, 0x54);
+	pch_common_sir_write(dev, 0x04, 0x00001600);
+	pch_common_sir_write(dev, 0x28, 0xa0000033);
+	reg32 = pch_common_sir_read(dev, 0x54);
 	reg32 &= 0xff000000;
 	reg32 |= 0x5555aa;
-	sir_write(dev, 0x54, reg32);
-	sir_write(dev, 0x64, 0xcccc8484);
-	reg32 = sir_read(dev, 0x68);
+	pch_common_sir_write(dev, 0x54, reg32);
+	pch_common_sir_write(dev, 0x64, 0xcccc8484);
+	reg32 = pch_common_sir_read(dev, 0x68);
 	reg32 &= 0xffff0000;
 	reg32 |= 0xcccc;
-	sir_write(dev, 0x68, reg32);
-	reg32 = sir_read(dev, 0x78);
+	pch_common_sir_write(dev, 0x68, reg32);
+	reg32 = pch_common_sir_read(dev, 0x78);
 	reg32 &= 0x0000ffff;
 	reg32 |= 0x88880000;
-	sir_write(dev, 0x78, reg32);
-	sir_write(dev, 0x84, 0x001c7000);
-	sir_write(dev, 0x88, 0x88338822);
-	sir_write(dev, 0xa0, 0x001c7000);
-	sir_write(dev, 0xc4, 0x0c0c0c0c);
-	sir_write(dev, 0xc8, 0x0c0c0c0c);
-	sir_write(dev, 0xd4, 0x10000000);
+	pch_common_sir_write(dev, 0x78, reg32);
+	pch_common_sir_write(dev, 0x84, 0x001c7000);
+	pch_common_sir_write(dev, 0x88, 0x88338822);
+	pch_common_sir_write(dev, 0xa0, 0x001c7000);
+	pch_common_sir_write(dev, 0xc4, 0x0c0c0c0c);
+	pch_common_sir_write(dev, 0xc8, 0x0c0c0c0c);
+	pch_common_sir_write(dev, 0xd4, 0x10000000);
 
 	pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
 	pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index e72ff2a..4725250 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -69,8 +69,6 @@
 #define RTC_POWER_FAILED	(1 << 1)
 #define SLEEP_AFTER_POWER_FAIL	(1 << 0)
 
-#define PMBASE			0x40
-#define ACPI_CNTL		0x44
 #define BIOS_CNTL		0xDC
 #define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
@@ -99,60 +97,11 @@
 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
 #define GPIO_ROUT		0xb8
 
-#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
-#define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
-#define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
-#define LPC_EN			0x82 /* LPC IF Enables Register */
-#define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
-#define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
-#define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
-#define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
-#define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
-#define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
-#define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
-#define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
-#define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
-#define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
-#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
-#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
-#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
-#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
-#define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
-#define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
-#define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
-#define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
-#define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
-#define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
-#define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
-#define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
-#define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
-
 /* PCI Configuration Space (D31:F1): IDE */
 #define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
 #define PCH_SATA_DEV		PCI_BDF(0, 0x1f, 2)
 #define PCH_SATA2_DEV		PCI_BDF(0, 0x1f, 5)
 
-#define INTR_LN			0x3c
-#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
-#define   IDE_DECODE_ENABLE	(1 << 15)
-#define   IDE_SITRE		(1 << 14)
-#define   IDE_ISP_5_CLOCKS	(0 << 12)
-#define   IDE_ISP_4_CLOCKS	(1 << 12)
-#define   IDE_ISP_3_CLOCKS	(2 << 12)
-#define   IDE_RCT_4_CLOCKS	(0 <<  8)
-#define   IDE_RCT_3_CLOCKS	(1 <<  8)
-#define   IDE_RCT_2_CLOCKS	(2 <<  8)
-#define   IDE_RCT_1_CLOCKS	(3 <<  8)
-#define   IDE_DTE1		(1 <<  7)
-#define   IDE_PPE1		(1 <<  6)
-#define   IDE_IE1		(1 <<  5)
-#define   IDE_TIME1		(1 <<  4)
-#define   IDE_DTE0		(1 <<  3)
-#define   IDE_PPE0		(1 <<  2)
-#define   IDE_IE0		(1 <<  1)
-#define   IDE_TIME0		(1 <<  0)
-#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
-
 #define IDE_SDMA_CNT		0x48	/* Synchronous DMA control */
 #define   IDE_SSDE1		(1 <<  3)
 #define   IDE_SSDE0		(1 <<  2)
@@ -337,9 +286,7 @@
 		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
 			((b) << DIR_IBR) | ((a) << DIR_IAR))
 
-#define RC		0x3400	/* 32bit */
 #define HPTC		0x3404	/* 32bit */
-#define GCS		0x3410	/* 32bit */
 #define BUC		0x3414	/* 32bit */
 #define PCH_DISABLE_GBE		(1 << 5)
 #define FD		0x3418	/* 32bit */
diff --git a/arch/x86/include/asm/pch_common.h b/arch/x86/include/asm/pch_common.h
new file mode 100644
index 0000000..924ccc4
--- /dev/null
+++ b/arch/x86/include/asm/pch_common.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __asm_pch_common_h
+#define __asm_pch_common_h
+
+/* Common Intel SATA registers */
+#define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
+#define SATA_SP			0xd0 /* Scratchpad */
+
+#define INTR_LN			0x3c
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define   IDE_DECODE_ENABLE	(1 << 15)
+#define   IDE_SITRE		(1 << 14)
+#define   IDE_ISP_5_CLOCKS	(0 << 12)
+#define   IDE_ISP_4_CLOCKS	(1 << 12)
+#define   IDE_ISP_3_CLOCKS	(2 << 12)
+#define   IDE_RCT_4_CLOCKS	(0 <<  8)
+#define   IDE_RCT_3_CLOCKS	(1 <<  8)
+#define   IDE_RCT_2_CLOCKS	(2 <<  8)
+#define   IDE_RCT_1_CLOCKS	(3 <<  8)
+#define   IDE_DTE1		(1 <<  7)
+#define   IDE_PPE1		(1 <<  6)
+#define   IDE_IE1		(1 <<  5)
+#define   IDE_TIME1		(1 <<  4)
+#define   IDE_DTE0		(1 <<  3)
+#define   IDE_PPE0		(1 <<  2)
+#define   IDE_IE0		(1 <<  1)
+#define   IDE_TIME0		(1 <<  0)
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+
+#define SERIRQ_CNTL		0x64
+
+/**
+ * pch_common_sir_read() - Read from a SATA indexed register
+ *
+ * @dev:	SATA device
+ * @idx:	Register index to read
+ * @return value read from register
+ */
+u32 pch_common_sir_read(struct udevice *dev, int idx);
+
+/**
+ * pch_common_sir_write() - Write to a SATA indexed register
+ *
+ * @dev:	SATA device
+ * @idx:	Register index to write
+ * @value:	Value to write
+ */
+void pch_common_sir_write(struct udevice *dev, int idx, u32 value);
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 18/51] x86: Add common SDRAM-init code

[Simon Glass]

The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Rename sdram_common.c to mrc.c

 arch/x86/cpu/intel_common/Makefile |   1 +
 arch/x86/cpu/intel_common/mrc.c    | 271 +++++++++++++++++++++++++++++++++++++
 arch/x86/include/asm/mrc_common.h  |  55 ++++++++
 3 files changed, 327 insertions(+)
 create mode 100644 arch/x86/cpu/intel_common/mrc.c
 create mode 100644 arch/x86/include/asm/mrc_common.h

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index e235526..bfdad76 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -13,3 +13,4 @@ obj-y += microcode.o
 endif
 obj-y += pch_common.o
 obj-$(CONFIG_HAVE_MRC) += report_platform.o
+obj-$(CONFIG_HAVE_MRC) += mrc.o
diff --git a/arch/x86/cpu/intel_common/mrc.c b/arch/x86/cpu/intel_common/mrc.c
new file mode 100644
index 0000000..01b6e86
--- /dev/null
+++ b/arch/x86/cpu/intel_common/mrc.c
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/intel_regs.h>
+#include <asm/mrc_common.h>
+#include <asm/pch_common.h>
+#include <asm/post.h>
+#include <asm/arch/me.h>
+#include <asm/report_platform.h>
+
+static const char *const ecc_decoder[] = {
+	"inactive",
+	"active on IO",
+	"disabled on IO",
+	"active"
+};
+
+ulong mrc_common_board_get_usable_ram_top(ulong total_size)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	uintptr_t dest_addr = 0;
+	struct memory_area *largest = NULL;
+	int i;
+
+	/* Find largest area of memory below 4GB */
+
+	for (i = 0; i < info->num_areas; i++) {
+		struct memory_area *area = &info->area[i];
+
+		if (area->start >= 1ULL << 32)
+			continue;
+		if (!largest || area->size > largest->size)
+			largest = area;
+	}
+
+	/* If no suitable area was found, return an error. */
+	assert(largest);
+	if (!largest || largest->size < (2 << 20))
+		panic("No available memory found for relocation");
+
+	dest_addr = largest->start + largest->size;
+
+	return (ulong)dest_addr;
+}
+
+void mrc_common_dram_init_banksize(void)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	int num_banks;
+	int i;
+
+	for (i = 0, num_banks = 0; i < info->num_areas; i++) {
+		struct memory_area *area = &info->area[i];
+
+		if (area->start >= 1ULL << 32)
+			continue;
+		gd->bd->bi_dram[num_banks].start = area->start;
+		gd->bd->bi_dram[num_banks].size = area->size;
+		num_banks++;
+	}
+}
+
+int mrc_add_memory_area(struct memory_info *info, uint64_t start,
+			  uint64_t end)
+{
+	struct memory_area *ptr;
+
+	if (info->num_areas == CONFIG_NR_DRAM_BANKS)
+		return -ENOSPC;
+
+	ptr = &info->area[info->num_areas];
+	ptr->start = start;
+	ptr->size = end - start;
+	info->total_memory += ptr->size;
+	if (ptr->start < (1ULL << 32))
+		info->total_32bit_memory += ptr->size;
+	debug("%d: memory %llx size %llx, total now %llx / %llx\n",
+	      info->num_areas, ptr->start, ptr->size,
+	      info->total_32bit_memory, info->total_memory);
+	info->num_areas++;
+
+	return 0;
+}
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+void report_memory_config(void)
+{
+	u32 addr_decoder_common, addr_decode_ch[2];
+	int i;
+
+	addr_decoder_common = readl(MCHBAR_REG(0x5000));
+	addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
+	addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
+
+	debug("memcfg DDR3 clock %d MHz\n",
+	      (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
+	debug("memcfg channel assignment: A: %d, B % d, C % d\n",
+	      addr_decoder_common & 3,
+	      (addr_decoder_common >> 2) & 3,
+	      (addr_decoder_common >> 4) & 3);
+
+	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+		u32 ch_conf = addr_decode_ch[i];
+		debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+		debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+		debug("   enhanced interleave mode %s\n",
+		      ((ch_conf >> 22) & 1) ? "on" : "off");
+		debug("   rank interleave %s\n",
+		      ((ch_conf >> 21) & 1) ? "on" : "off");
+		debug("   DIMMA %d MB width x%d %s rank%s\n",
+		      ((ch_conf >> 0) & 0xff) * 256,
+		      ((ch_conf >> 19) & 1) ? 16 : 8,
+		      ((ch_conf >> 17) & 1) ? "dual" : "single",
+		      ((ch_conf >> 16) & 1) ? "" : ", selected");
+		debug("   DIMMB %d MB width x%d %s rank%s\n",
+		      ((ch_conf >> 8) & 0xff) * 256,
+		      ((ch_conf >> 20) & 1) ? 16 : 8,
+		      ((ch_conf >> 18) & 1) ? "dual" : "single",
+		      ((ch_conf >> 16) & 1) ? ", selected" : "");
+	}
+}
+
+int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap)
+{
+	const void *blob = gd->fdt_blob;
+	int spd_index;
+	struct gpio_desc desc[4];
+	int spd_node;
+	int node;
+	int ret;
+
+	ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
+					ARRAY_SIZE(desc), GPIOD_IS_IN);
+	if (ret < 0) {
+		debug("%s: gpio ret=%d\n", __func__, ret);
+		return ret;
+	}
+	spd_index = dm_gpio_get_values_as_int(desc, ret);
+	debug("spd index %d\n", spd_index);
+
+	node = fdt_first_subnode(blob, dev->of_offset);
+	if (node < 0)
+		return -EINVAL;
+	for (spd_node = fdt_first_subnode(blob, node);
+	     spd_node > 0;
+	     spd_node = fdt_next_subnode(blob, spd_node)) {
+		int len;
+
+		if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
+			continue;
+		*spd_datap = fdt_getprop(blob, spd_node, "data", &len);
+		if (len < size) {
+			printf("Missing SPD data\n");
+			return -EINVAL;
+		}
+
+		debug("Using SDRAM SPD data for '%s'\n",
+		      fdt_get_name(blob, spd_node, NULL));
+		return 0;
+	}
+
+	printf("No SPD data found for index %d\n", spd_index);
+	return -ENOENT;
+}
+
+asmlinkage void sdram_console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+	putc(byte);
+#endif
+}
+
+/**
+ * Find the PEI executable in the ROM and execute it.
+ *
+ * @me_dev: Management Engine device
+ * @pei_data: configuration data for UEFI PEI reference code
+ */
+static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
+			    void *pei_data, bool use_asm_linkage)
+{
+	unsigned version;
+	const char *data;
+
+	report_platform_info(dev);
+	debug("Starting UEFI PEI System Agent\n");
+
+	debug("PEI data at %p:\n", pei_data);
+
+	data = (char *)CONFIG_X86_MRC_ADDR;
+	if (data) {
+		int rv;
+		ulong start;
+
+		debug("Calling MRC@%p\n", data);
+		post_code(POST_PRE_MRC);
+		start = get_timer(0);
+		if (use_asm_linkage) {
+			asmlinkage int (*func)(void *);
+
+			func = (asmlinkage int (*)(void *))data;
+			rv = func(pei_data);
+		} else {
+			int (*func)(void *);
+
+			func = (int (*)(void *))data;
+			rv = func(pei_data);
+		}
+		post_code(POST_MRC);
+		if (rv) {
+			switch (rv) {
+			case -1:
+				printf("PEI version mismatch.\n");
+				break;
+			case -2:
+				printf("Invalid memory frequency.\n");
+				break;
+			default:
+				printf("MRC returned %x.\n", rv);
+			}
+			printf("Nonzero MRC return value.\n");
+			return -EFAULT;
+		}
+		debug("MRC execution time %lu ms\n", get_timer(start));
+	} else {
+		printf("UEFI PEI System Agent not found.\n");
+		return -ENOSYS;
+	}
+
+	version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION));
+	debug("System Agent Version %d.%d.%d Build %d\n",
+	      version >> 24 , (version >> 16) & 0xff,
+	      (version >> 8) & 0xff, version & 0xff);
+
+#if CONFIG_USBDEBUG
+	/* mrc.bin reconfigures USB, so reinit it to have debug */
+	early_usbdebug_init();
+#endif
+
+	return 0;
+}
+
+int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
+{
+	struct udevice *me_dev;
+	int ret;
+
+	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
+	if (ret)
+		return ret;
+
+	ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
+	if (ret)
+		return ret;
+	quick_ram_check();
+	post_code(POST_DRAM);
+	report_memory_config();
+
+	return 0;
+}
diff --git a/arch/x86/include/asm/mrc_common.h b/arch/x86/include/asm/mrc_common.h
new file mode 100644
index 0000000..cad24f2
--- /dev/null
+++ b/arch/x86/include/asm/mrc_common.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_MRC_COMMON_H
+#define __ASM_MRC_COMMON_H
+
+#include <linux/linkage.h>
+
+/**
+ * mrc_common_init() - Set up SDRAM
+ *
+ * This calls the memory reference code (MRC) to set up SDRAM
+ *
+ * @dev:	Northbridge device
+ * @pei_data:	Platform-specific data required by the MRC
+ * @use_asm_linkage: true if the call to MRC requires asmlinkage, false if it
+ * uses normal U-Boot calling
+ * @return 0 if OK, -ve on error
+ */
+int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage);
+
+asmlinkage void sdram_console_tx_byte(unsigned char byte);
+
+int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap);
+
+void report_memory_config(void);
+
+/**
+ * mrc_add_memory_area() - Add a new usable memory area to our list
+ *
+ * Note: @start and @end must not span the first 4GB boundary
+ *
+ * @info:	Place to store memory info
+ * @start:	Start of this memory area
+ * @end:	End of this memory area + 1
+ */
+int mrc_add_memory_area(struct memory_info *info, uint64_t start,
+			  uint64_t end);
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong mrc_common_board_get_usable_ram_top(ulong total_size);
+
+void mrc_common_dram_init_banksize(void);
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 19/51] x86: ivybridge: Convert to use the common SDRAM code

[Simon Glass]

Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Rename sdram to mrc

 arch/x86/cpu/ivybridge/sdram.c | 394 +++++++++--------------------------------
 1 file changed, 83 insertions(+), 311 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index af76826..73c859f 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -25,6 +25,7 @@
 #include <asm/global_data.h>
 #include <asm/intel_regs.h>
 #include <asm/mrccache.h>
+#include <asm/mrc_common.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/report_platform.h>
@@ -40,57 +41,14 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CMOS_OFFSET_MRC_SEED_S3		156
 #define CMOS_OFFSET_MRC_SEED_CHK	160
 
-/*
- * This function looks for the highest region of memory lower than 4GB which
- * has enough space for U-Boot where U-Boot is aligned on a page boundary.
- * It overrides the default implementation found elsewhere which simply
- * picks the end of ram, wherever that may be. The location of the stack,
- * the relocation address, and how far U-Boot is moved by relocation are
- * set in the global data structure.
- */
 ulong board_get_usable_ram_top(ulong total_size)
 {
-	struct memory_info *info = &gd->arch.meminfo;
-	uintptr_t dest_addr = 0;
-	struct memory_area *largest = NULL;
-	int i;
-
-	/* Find largest area of memory below 4GB */
-
-	for (i = 0; i < info->num_areas; i++) {
-		struct memory_area *area = &info->area[i];
-
-		if (area->start >= 1ULL << 32)
-			continue;
-		if (!largest || area->size > largest->size)
-			largest = area;
-	}
-
-	/* If no suitable area was found, return an error. */
-	assert(largest);
-	if (!largest || largest->size < (2 << 20))
-		panic("No available memory found for relocation");
-
-	dest_addr = largest->start + largest->size;
-
-	return (ulong)dest_addr;
+	return mrc_common_board_get_usable_ram_top(total_size);
 }
 
 void dram_init_banksize(void)
 {
-	struct memory_info *info = &gd->arch.meminfo;
-	int num_banks;
-	int i;
-
-	for (i = 0, num_banks = 0; i < info->num_areas; i++) {
-		struct memory_area *area = &info->area[i];
-
-		if (area->start >= 1ULL << 32)
-			continue;
-		gd->bd->bi_dram[num_banks].start = area->start;
-		gd->bd->bi_dram[num_banks].size = area->size;
-		num_banks++;
-	}
+	mrc_common_dram_init_banksize();
 }
 
 static int read_seed_from_cmos(struct pei_data *pei_data)
@@ -217,164 +175,10 @@ int misc_init_r(void)
 	return 0;
 }
 
-static const char *const ecc_decoder[] = {
-	"inactive",
-	"active on IO",
-	"disabled on IO",
-	"active"
-};
-
-/*
- * Dump in the log memory controller configuration as read from the memory
- * controller registers.
- */
-static void report_memory_config(void)
+static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
+				   struct pei_data *pei_data)
 {
-	u32 addr_decoder_common, addr_decode_ch[2];
-	int i;
-
-	addr_decoder_common = readl(MCHBAR_REG(0x5000));
-	addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
-	addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
-
-	debug("memcfg DDR3 clock %d MHz\n",
-	      (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
-	debug("memcfg channel assignment: A: %d, B % d, C % d\n",
-	      addr_decoder_common & 3,
-	      (addr_decoder_common >> 2) & 3,
-	      (addr_decoder_common >> 4) & 3);
-
-	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
-		u32 ch_conf = addr_decode_ch[i];
-		debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
-		debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
-		debug("   enhanced interleave mode %s\n",
-		      ((ch_conf >> 22) & 1) ? "on" : "off");
-		debug("   rank interleave %s\n",
-		      ((ch_conf >> 21) & 1) ? "on" : "off");
-		debug("   DIMMA %d MB width x%d %s rank%s\n",
-		      ((ch_conf >> 0) & 0xff) * 256,
-		      ((ch_conf >> 19) & 1) ? 16 : 8,
-		      ((ch_conf >> 17) & 1) ? "dual" : "single",
-		      ((ch_conf >> 16) & 1) ? "" : ", selected");
-		debug("   DIMMB %d MB width x%d %s rank%s\n",
-		      ((ch_conf >> 8) & 0xff) * 256,
-		      ((ch_conf >> 20) & 1) ? 16 : 8,
-		      ((ch_conf >> 18) & 1) ? "dual" : "single",
-		      ((ch_conf >> 16) & 1) ? ", selected" : "");
-	}
-}
-
-static void post_system_agent_init(struct pei_data *pei_data)
-{
-	/* If PCIe init is skipped, set the PEG clock gating */
-	if (!pei_data->pcie_init)
-		setbits_le32(MCHBAR_REG(0x7010), 1);
-}
-
-static asmlinkage void console_tx_byte(unsigned char byte)
-{
-#ifdef DEBUG
-	putc(byte);
-#endif
-}
-
-static int recovery_mode_enabled(void)
-{
-	return false;
-}
-
-/**
- * Find the PEI executable in the ROM and execute it.
- *
- * @dev: Northbridge device
- * @pei_data: configuration data for UEFI PEI reference code
- */
-int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
-		     struct pei_data *pei_data)
-{
-	unsigned version;
-	const char *data;
 	uint16_t done;
-	int ret;
-
-	report_platform_info(dev);
-
-	/* Wait for ME to be ready */
-	ret = intel_early_me_init(me_dev);
-	if (ret)
-		return ret;
-	ret = intel_early_me_uma_size(me_dev);
-	if (ret < 0)
-		return ret;
-
-	debug("Starting UEFI PEI System Agent\n");
-
-	/*
-	 * Do not pass MRC data in for recovery mode boot,
-	 * Always pass it in for S3 resume.
-	 */
-	if (!recovery_mode_enabled() ||
-	    pei_data->boot_mode == PEI_BOOT_RESUME) {
-		ret = prepare_mrc_cache(pei_data);
-		if (ret)
-			debug("prepare_mrc_cache failed: %d\n", ret);
-	}
-
-	/* If MRC data is not found we cannot continue S3 resume. */
-	if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
-		debug("Giving up in sdram_initialize: No MRC data\n");
-		reset_cpu(0);
-	}
-
-	/* Pass console handler in pei_data */
-	pei_data->tx_byte = console_tx_byte;
-
-	debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
-
-	data = (char *)CONFIG_X86_MRC_ADDR;
-	if (data) {
-		int rv;
-		int (*func)(struct pei_data *);
-		ulong start;
-
-		debug("Calling MRC at %p\n", data);
-		post_code(POST_PRE_MRC);
-		start = get_timer(0);
-		func = (int (*)(struct pei_data *))data;
-		rv = func(pei_data);
-		post_code(POST_MRC);
-		if (rv) {
-			switch (rv) {
-			case -1:
-				printf("PEI version mismatch.\n");
-				break;
-			case -2:
-				printf("Invalid memory frequency.\n");
-				break;
-			default:
-				printf("MRC returned %x.\n", rv);
-			}
-			printf("Nonzero MRC return value.\n");
-			return -EFAULT;
-		}
-		debug("MRC execution time %lu ms\n", get_timer(start));
-	} else {
-		printf("UEFI PEI System Agent not found.\n");
-		return -ENOSYS;
-	}
-
-#if CONFIG_USBDEBUG
-	/* mrc.bin reconfigures USB, so reinit it to have debug */
-	early_usbdebug_init();
-#endif
-
-	version = readl(MCHBAR_REG(0x5034));
-	debug("System Agent Version %d.%d.%d Build %d\n",
-	      version >> 24 , (version >> 16) & 0xff,
-	      (version >> 8) & 0xff, version & 0xff);
-	debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
-	      pei_data->mrc_output);
 
 	/*
 	 * Send ME init done for SandyBridge here.  This is done inside the
@@ -387,23 +191,14 @@ int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
 	else
 		intel_me_status(me_dev);
 
-	post_system_agent_init(pei_data);
-	report_memory_config();
-
-	/* S3 resume: don't save scrambler seed or MRC data */
-	if (pei_data->boot_mode != PEI_BOOT_RESUME) {
-		/*
-		 * This will be copied to SDRAM in reserve_arch(), then written
-		 * to SPI flash in mrccache_save()
-		 */
-		gd->arch.mrc_output = (char *)pei_data->mrc_output;
-		gd->arch.mrc_output_len = pei_data->mrc_output_len;
-		ret = write_seeds_to_cmos(pei_data);
-		if (ret)
-			debug("Failed to write seeds to CMOS: %d\n", ret);
-	}
+	/* If PCIe init is skipped, set the PEG clock gating */
+	if (!pei_data->pcie_init)
+		setbits_le32(MCHBAR_REG(0x7010), 1);
+}
 
-	return 0;
+static int recovery_mode_enabled(void)
+{
+	return false;
 }
 
 int reserve_arch(void)
@@ -411,87 +206,16 @@ int reserve_arch(void)
 	return mrccache_reserve();
 }
 
-static int copy_spd(struct pei_data *peid)
+static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
-	const int gpio_vector[] = {41, 42, 43, 10, -1};
-	int spd_index;
-	const void *blob = gd->fdt_blob;
-	int node, spd_node;
-	int ret, i;
-
-	for (i = 0; ; i++) {
-		if (gpio_vector[i] == -1)
-			break;
-		ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
-		if (ret) {
-			debug("%s: Could not request gpio %d\n", __func__,
-			      gpio_vector[i]);
-			return ret;
-		}
-	}
-	spd_index = gpio_get_values_as_int(gpio_vector);
-	debug("spd index %d\n", spd_index);
-	node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
-	if (node < 0) {
-		printf("SPD data not found.\n");
-		return -ENOENT;
-	}
-
-	for (spd_node = fdt_first_subnode(blob, node);
-	     spd_node > 0;
-	     spd_node = fdt_next_subnode(blob, spd_node)) {
-		const char *data;
-		int len;
-
-		if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
-			continue;
-		data = fdt_getprop(blob, spd_node, "data", &len);
-		if (len < sizeof(peid->spd_data[0])) {
-			printf("Missing SPD data\n");
-			return -EINVAL;
-		}
-
-		debug("Using SDRAM SPD data for '%s'\n",
-		      fdt_get_name(blob, spd_node, NULL));
-		memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
-		break;
-	}
-
-	if (spd_node < 0) {
-		printf("No SPD data found for index %d\n", spd_index);
-		return -ENOENT;
-	}
+	const void *data;
+	int ret;
 
-	return 0;
-}
+	ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
+	if (ret)
+		return ret;
 
-/**
- * add_memory_area() - Add a new usable memory area to our list
- *
- * Note: @start and @end must not span the first 4GB boundary
- *
- * @info:	Place to store memory info
- * @start:	Start of this memory area
- * @end:	End of this memory area + 1
- */
-static int add_memory_area(struct memory_info *info,
-			   uint64_t start, uint64_t end)
-{
-	struct memory_area *ptr;
-
-	if (info->num_areas == CONFIG_NR_DRAM_BANKS)
-		return -ENOSPC;
-
-	ptr = &info->area[info->num_areas];
-	ptr->start = start;
-	ptr->size = end - start;
-	info->total_memory += ptr->size;
-	if (ptr->start < (1ULL << 32))
-		info->total_32bit_memory += ptr->size;
-	debug("%d: memory %llx size %llx, total now %llx / %llx\n",
-	      info->num_areas, ptr->start, ptr->size,
-	      info->total_32bit_memory, info->total_memory);
-	info->num_areas++;
+	memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
 
 	return 0;
 }
@@ -610,10 +334,10 @@ static int sdram_find(struct udevice *dev)
 	debug("Available memory below 4GB: %lluM\n", tomk >> 10);
 
 	/* Report the memory regions */
-	add_memory_area(info, 1 << 20, 2 << 28);
-	add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
-	add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
-	add_memory_area(info, 1ULL << 32, touud);
+	mrc_add_memory_area(info, 1 << 20, 2 << 28);
+	mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
+	mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
+	mrc_add_memory_area(info, 1ULL << 32, touud);
 
 	/* Add MTRRs for memory */
 	mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
@@ -682,7 +406,7 @@ static void rcba_config(void)
 
 int dram_init(void)
 {
-	struct pei_data pei_data __aligned(8) = {
+	struct pei_data _pei_data __aligned(8) = {
 		.pei_version = PEI_VERSION,
 		.mchbar = MCH_BASE_ADDRESS,
 		.dmibar = DEFAULT_DMIBAR,
@@ -735,6 +459,7 @@ int dram_init(void)
 			{ 0, 4, 0x0000 }, /* P13= Empty */
 		},
 	};
+	struct pei_data *pei_data = &_pei_data;
 	struct udevice *dev, *me_dev;
 	int ret;
 
@@ -746,27 +471,74 @@ int dram_init(void)
 	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
 	if (ret)
 		return ret;
-	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
-	debug("mrc_input %p\n", pei_data.mrc_input);
-	pei_data.boot_mode = gd->arch.pei_boot_mode;
-	ret = copy_spd(&pei_data);
-	if (!ret)
-		ret = sdram_initialise(dev, me_dev, &pei_data);
+	ret = copy_spd(dev, pei_data);
 	if (ret)
 		return ret;
+	pei_data->boot_mode = gd->arch.pei_boot_mode;
+	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
+	debug("mrc_input %p\n", pei_data->mrc_input);
 
-	rcba_config();
-	quick_ram_check();
+	/*
+	 * Do not pass MRC data in for recovery mode boot,
+	 * Always pass it in for S3 resume.
+	 */
+	if (!recovery_mode_enabled() ||
+	    pei_data->boot_mode == PEI_BOOT_RESUME) {
+		ret = prepare_mrc_cache(pei_data);
+		if (ret)
+			debug("prepare_mrc_cache failed: %d\n", ret);
+	}
 
-	writew(0xCAFE, MCHBAR_REG(SSKPD));
+	/* If MRC data is not found we cannot continue S3 resume. */
+	if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
+		debug("Giving up in sdram_initialize: No MRC data\n");
+		reset_cpu(0);
+	}
 
-	post_code(POST_DRAM);
+	/* Pass console handler in pei_data */
+	pei_data->tx_byte = sdram_console_tx_byte;
 
-	ret = sdram_find(dev);
+	/* Wait for ME to be ready */
+	ret = intel_early_me_init(me_dev);
 	if (ret)
 		return ret;
+	ret = intel_early_me_uma_size(me_dev);
+	if (ret < 0)
+		return ret;
 
+	ret = mrc_common_init(dev, pei_data, false);
+	if (ret)
+		return ret;
+
+	ret = sdram_find(dev);
+	if (ret)
+		return ret;
 	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
 
+	debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
+	      pei_data->mrc_output);
+
+	post_system_agent_init(dev, me_dev, pei_data);
+	report_memory_config();
+
+	/* S3 resume: don't save scrambler seed or MRC data */
+	if (pei_data->boot_mode != PEI_BOOT_RESUME) {
+		/*
+		 * This will be copied to SDRAM in reserve_arch(), then written
+		 * to SPI flash in mrccache_save()
+		 */
+		gd->arch.mrc_output = (char *)pei_data->mrc_output;
+		gd->arch.mrc_output_len = pei_data->mrc_output_len;
+		ret = write_seeds_to_cmos(pei_data);
+		if (ret)
+			debug("Failed to write seeds to CMOS: %d\n", ret);
+	}
+
+	writew(0xCAFE, MCHBAR_REG(SSKPD));
+	if (ret)
+		return ret;
+
+	rcba_config();
+
 	return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 20/51] x86: dts: Drop memory SPD compatible string

[Simon Glass]

This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/dts/chromebook_link.dts | 1 -
 include/fdtdec.h                 | 1 -
 lib/fdtdec.c                     | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index a702ea9..7ddbe43 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -78,7 +78,6 @@
 					<&gpio_b 11 0>, <&gpio_a 10 0>;
 			u-boot,dm-pre-reloc;
 			spd {
-				compatible = "memory-spd";
 				#address-cells = <1>;
 				#size-cells = <0>;
 				elpida_4Gb_1600_x16 {
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4caf3b6..eed01e0 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -152,7 +152,6 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS5_I2C,	/* Exynos5 High Speed I2C Controller */
 	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
 	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
-	COMPAT_MEMORY_SPD,		/* Memory SPD information */
 	COMPAT_INTEL_PANTHERPOINT_AHCI,	/* Intel Pantherpoint AHCI */
 	COMPAT_INTEL_MODEL_206AX,	/* Intel Model 206AX CPU */
 	COMPAT_INTEL_GMA,		/* Intel Graphics Media Accelerator */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b361a25..6e89e95 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -57,7 +57,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS5_I2C, "samsung,exynos5-hsi2c"),
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
-	COMPAT(MEMORY_SPD, "memory-spd"),
 	COMPAT(INTEL_PANTHERPOINT_AHCI, "intel,pantherpoint-ahci"),
 	COMPAT(INTEL_MODEL_206AX, "intel,model-206ax"),
 	COMPAT(INTEL_GMA, "intel,gma"),
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 21/51] x86: Add macros to clear and set I/O bits

[Simon Glass]

The clrsetbits_...() macros are useful for working with memory mapped I/O.
But they do not work with I/O space, as used on x86 machines.

Add some macros to provide similar features for I/O.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Use setio_32() instead of setio_le32(), etc.

 arch/x86/include/asm/io.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index e0b2561..b99e4d6 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -254,6 +254,28 @@ __OUTS(b)
 __OUTS(w)
 __OUTS(l)
 
+/* IO space accessors */
+#define clrio(type, addr, clear) \
+	out##type(in##type(addr) & ~(clear), (addr))
+
+#define setio(type, addr, set) \
+	out##type(in##type(addr) | (set), (addr))
+
+#define clrsetio(type, addr, clear, set) \
+	out##type((in##type(addr) & ~(clear)) | (set), (addr))
+
+#define clrio_32(addr, clear) clrio(l, addr, clear)
+#define clrio_16(addr, clear) clrio(w, addr, clear)
+#define clrio_8(addr, clear) clrio(b, addr, clear)
+
+#define setio_32(addr, set) setio(l, addr, set)
+#define setio_16(addr, set) setio(w, addr, set)
+#define setio_8(addr, set) setio(b, addr, set)
+
+#define clrsetio_32(addr, clear, set) clrsetio(l, addr, clear, set)
+#define clrsetio_16(addr, clear, set) clrsetio(w, addr, clear, set)
+#define clrsetio_8(addr, clear, set) clrsetio(b, addr, clear, set)
+
 static inline void sync(void)
 {
 }
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 22/51] x86: Allow I/O functions to use pointers

[Simon Glass]

It is common with memory-mapped I/O to use the address of a structure member
to access memory, as in:

   struct some_regs {
      u32 ctrl;
      u32 data;
   }

   struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;

   writel(1, &reg->ctrl);
   writel(2, &reg->data);

This does not currently work with inl(), outl(), etc. Add a cast to permit
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/include/asm/io.h | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index b99e4d6..3156781 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -202,7 +202,7 @@ out:
  * Talk about misusing macros..
  */
 #define __OUT1(s,x) \
-static inline void out##s(unsigned x value, unsigned short port) {
+static inline void _out##s(unsigned x value, unsigned short port) {
 
 #define __OUT2(s,s1,s2) \
 __asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
@@ -213,7 +213,7 @@ __OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
 __OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));}
 
 #define __IN1(s) \
-static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
+static inline RETURN_TYPE _in##s(unsigned short port) { RETURN_TYPE _v;
 
 #define __IN2(s,s1,s2) \
 __asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
@@ -242,10 +242,18 @@ __IN(w,"")
 __IN(l,"")
 #undef RETURN_TYPE
 
+#define inb(port)	_inb((uintptr_t)(port))
+#define inw(port)	_inw((uintptr_t)(port))
+#define inl(port)	_inl((uintptr_t)(port))
+
 __OUT(b,"b",char)
 __OUT(w,"w",short)
 __OUT(l,,int)
 
+#define outb(val, port)	_outb(val, (uintptr_t)(port))
+#define outw(val, port)	_outw(val, (uintptr_t)(port))
+#define outl(val, port)	_outl(val, (uintptr_t)(port))
+
 __INS(b)
 __INS(w)
 __INS(l)
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 23/51] x86: Move common MRC Kconfig options to the common file

[Simon Glass]

At present the MRC options are private to ivybridge. Other Intel CPUs also
use these settings. Move them to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Add Kconfig help for the moved options
- Fix tab indentation

 arch/x86/Kconfig               | 61 ++++++++++++++++++++++++++++++++++++++++++
 arch/x86/cpu/ivybridge/Kconfig | 27 +------------------
 2 files changed, 62 insertions(+), 26 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5fad794..64c824f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -266,6 +266,67 @@ config ENABLE_MRC_CACHE
 	  to be used for speeding up boot time on future reboots and/or
 	  power cycles.
 
+config HAVE_MRC
+	bool "Add a System Agent binary"
+	depends on !HAVE_FSP
+	help
+	  Select this option to add a System Agent binary to
+	  the resulting U-Boot image. MRC stands for Memory Reference Code.
+	  It is a binary blob which U-Boot uses to set up SDRAM.
+
+	  Note: Without this binary U-Boot will not be able to set up its
+	  SDRAM so will not boot.
+
+config CACHE_MRC_BIN
+	bool
+	depends on HAVE_MRC
+	default n
+	help
+	  Enable caching for the memory reference code binary. This uses an
+	  MTRR (memory type range register) to turn on caching for the section
+	  of SPI flash that contains the memory reference code. This makes
+	  SDRAM init run faster.
+
+config CACHE_MRC_SIZE_KB
+	int
+	depends on HAVE_MRC
+	default 512
+	help
+	  Sets the size of the cached area for the memory reference code.
+	  This ends at the end of SPI flash (address 0xffffffff) and is
+	  measured in KB. Typically this is set to 512, providing for 0.5MB
+	  of cached space.
+
+config DCACHE_RAM_BASE
+	hex
+	depends on HAVE_MRC
+	help
+	  Sets the base of the data cache area in memory space. This is the
+	  start address of the cache-as-RAM (CAR) area and the address varies
+	  depending on the CPU. Once CAR is set up, read/write memory becomes
+	  available at this address and can be used temporarily until SDRAM
+	  is working.
+
+config DCACHE_RAM_SIZE
+	hex
+	depends on HAVE_MRC
+	default 0x40000
+	help
+	  Sets the total size of the data cache area in memory space. This
+	  sets the size of the cache-as-RAM (CAR) area. Note that much of the
+	  CAR space is required by the MRC. The CAR space available to U-Boot
+	  is normally at the start and typically extends to 1/4 or 1/2 of the
+	  available size.
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	depends on HAVE_MRC
+	help
+	  This is the amount of CAR (Cache as RAM) reserved for use by the
+	  memory reference code. This depends on the implementation of the
+	  memory reference code and must be set correctly or the board will
+	  not boot.
+
 config SMP
 	bool "Enable Symmetric Multiprocessing"
 	default n
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 0819347..e23d01a 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -7,43 +7,18 @@
 
 config NORTHBRIDGE_INTEL_IVYBRIDGE
 	bool
-	select CACHE_MRC_BIN
+	select CACHE_MRC_BIN if HAVE_MRC
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
-config CACHE_MRC_BIN
-	bool
-	default n
-
-config CACHE_MRC_SIZE_KB
-	int
-	default 512
-
 config DCACHE_RAM_BASE
-	hex
 	default 0xff7e0000
 
 config DCACHE_RAM_SIZE
-	hex
 	default 0x20000
 
-config HAVE_MRC
-        bool "Add a System Agent binary"
-        help
-          Select this option to add a System Agent binary to
-          the resulting U-Boot image. MRC stands for Memory Reference Code.
-          It is a binary blob which U-Boot uses to set up SDRAM.
-
-          Note: Without this binary U-Boot will not be able to set up its
-          SDRAM so will not boot.
-
 config DCACHE_RAM_MRC_VAR_SIZE
-	hex
 	default 0x4000
-	help
-	  This is the amount of CAR (Cache as RAM) reserved for use by the
-	  memory reference code. This should be set to 16KB (0x4000 hex)
-	  so that MRC has enough space to run.
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 24/51] x86: Record the CPU details when starting each core

[Simon Glass]

As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Don't try to read microcode version on quark
- Use gd->arch.x86_device instead of reading the device ID again

 arch/x86/cpu/intel_common/microcode.c | 7 ++++++-
 arch/x86/cpu/mp_init.c                | 5 +++++
 arch/x86/include/asm/microcode.h      | 9 +++++++++
 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/intel_common/microcode.c b/arch/x86/cpu/intel_common/microcode.c
index 3054fab..daf0d69 100644
--- a/arch/x86/cpu/intel_common/microcode.c
+++ b/arch/x86/cpu/intel_common/microcode.c
@@ -64,8 +64,12 @@ static int microcode_decode_node(const void *blob, int node,
 	return 0;
 }
 
-static inline uint32_t microcode_read_rev(void)
+int microcode_read_rev(void)
 {
+	/* Quark does not have microcode MSRs */
+#ifdef CONFIG_INTEL_QUARK
+	return 0;
+#else
 	/*
 	 * Some Intel CPUs can be very finicky about the CPUID sequence used.
 	 * So this is implemented in assembly so that it works reliably.
@@ -90,6 +94,7 @@ static inline uint32_t microcode_read_rev(void)
 	);
 
 	return high;
+#endif
 }
 
 static void microcode_read_cpu(struct microcode_update *cpu)
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index ca47e9e..4cc6555 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -15,6 +15,7 @@
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
@@ -560,12 +561,16 @@ int mp_init(struct mp_params *p)
 
 int mp_init_cpu(struct udevice *cpu, void *unused)
 {
+	struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
+
 	/*
 	 * Multiple APs are brought up simultaneously and they may get the same
 	 * seq num in the uclass_resolve_seq() during device_probe(). To avoid
 	 * this, set req_seq to the reg number in the device tree in advance.
 	 */
 	cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
+	plat->ucode_version = microcode_read_rev();
+	plat->device_id = gd->arch.x86_device;
 
 	return device_probe(cpu);
 }
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 67f32cc..0478935 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -18,6 +18,15 @@
  * not updates were found, -EINVAL if an update was invalid
  */
 int microcode_update_intel(void);
+
+/**
+ * microcode_read_rev() - Read the microcode version
+ *
+ * This reads the microcode version of the currently running CPU
+ *
+ * @return microcode version number
+ */
+int microcode_read_rev(void);
 #endif /* __ASSEMBLY__ */
 
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 25/51] x86: ivybridge: Show microcode version for each core

[Simon Glass]

Enable the microcode feature so that the microcode version is shown with the
'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Rename subject to 'core' instead of 'code'

 arch/x86/cpu/ivybridge/model_206ax.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 950132a..cef4256 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -458,7 +458,8 @@ static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
 
 	msr = msr_read(MSR_IA32_PERF_CTL);
 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
-	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+		1 << CPU_FEAT_UCODE;
 
 	return 0;
 }
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 26/51] x86: Update microcode for secondary CPUs

[Simon Glass]

Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Fix micrcode typo
- Don't try to update microcode on FSP platforms

 arch/x86/cpu/cpu.c               | 1 +
 arch/x86/cpu/intel_common/car.S  | 2 ++
 arch/x86/cpu/mp_init.c           | 6 ++++--
 arch/x86/include/asm/microcode.h | 3 +++
 arch/x86/lib/fsp/fsp_car.S       | 2 ++
 5 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 7dfe071..233a6c8 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -27,6 +27,7 @@
 #include <asm/control_regs.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
diff --git a/arch/x86/cpu/intel_common/car.S b/arch/x86/cpu/intel_common/car.S
index 81ac976..6e0db96 100644
--- a/arch/x86/cpu/intel_common/car.S
+++ b/arch/x86/cpu/intel_common/car.S
@@ -237,5 +237,7 @@ mtrr_table_end:
 	.align 4
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:	/* Declared in microcode.h */
 	.long	0			/* microcode base */
 	.long	0			/* microcode size */
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 4cc6555..2604a68 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -248,8 +248,10 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
 	if (!stack)
 		return -ENOMEM;
 	params->stack_top = (u32)(stack + size);
-
-	params->microcode_ptr = 0;
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
+	params->microcode_ptr = ucode_base;
+	debug("Microcode at %x\n", params->microcode_ptr);
+#endif
 	params->msr_table_ptr = (u32)msr_save;
 	ret = save_bsp_msrs(msr_save, sizeof(msr_save));
 	if (ret < 0)
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 0478935..29bf060 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -9,6 +9,9 @@
 
 #ifndef __ASSEMBLY__
 
+/* This is a declaration for ucode_base in start.S */
+extern u32 ucode_base;
+
 /**
  * microcode_update_intel() - Apply microcode updates
  *
diff --git a/arch/x86/lib/fsp/fsp_car.S b/arch/x86/lib/fsp/fsp_car.S
index 15b3751..fbe8aef 100644
--- a/arch/x86/lib/fsp/fsp_car.S
+++ b/arch/x86/lib/fsp/fsp_car.S
@@ -102,6 +102,8 @@ temp_ram_init_romstack:
 temp_ram_init_params:
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:	/* Declared in micrcode.h */
 	.long	0			/* microcode base */
 	.long	0			/* microcode size */
 	.long	CONFIG_SYS_MONITOR_BASE	/* code region base */
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 27/51] x86: link: Add pin configuration to the device tree

[Simon Glass]

At present pin configuration on link does not use the standard mechanism,
but some rather ugly custom code. As a first step to resolving this, add the
pin configuration to the device tree.

Four of the GPIOs must be available before relocation (for SDRAM pin
strapping).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Add GPIO output definition for a1 and a6

 arch/x86/dts/chromebook_link.dts | 155 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 155 insertions(+)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 7ddbe43..fb1b31d 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -1,5 +1,7 @@
 /dts-v1/;
 
+#include <dt-bindings/gpio/x86-gpio.h>
+
 /include/ "skeleton.dtsi"
 /include/ "keyboard.dtsi"
 /include/ "serial.dtsi"
@@ -62,6 +64,159 @@
 		intel,duplicate-por;
 	};
 
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		u-boot,dm-pre-reloc;
+		reg = <0 0>;
+
+		gpio_a0 {
+			gpio-offset = <0 0>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a1 {
+			gpio-offset = <0>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+		gpio_a3 {
+			gpio-offset = <0 3>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a5 {
+			gpio-offset = <0 5>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a6 {
+			gpio-offset = <0 6>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+		gpio_a7 {
+			gpio-offset = <0 7>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a8 {
+			gpio-offset = <0 8>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a9 {
+			gpio-offset = <0 9>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a10 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0 10>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a11 {
+			gpio-offset = <0 11>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a12 {
+			gpio-offset = <0 12>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a14 {
+			gpio-offset = <0 14>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a15 {
+			gpio-offset = <0 15>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+		};
+
+		gpio_a21 {
+			gpio-offset = <0 21>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_a24 {
+			gpio-offset = <0 24>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
+		gpio_a28 {
+			gpio-offset = <0 28>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b4 {
+			gpio-offset = <0x30 4>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+		gpio_b9 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0x30 9>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b10 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0x30 10>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b11 {
+			u-boot,dm-pre-reloc;
+			gpio-offset = <0x30 11>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b25 {
+			gpio-offset = <0x30 25>;
+			mode-gpio;
+			direction = <PIN_INPUT>;
+		};
+
+		gpio_b28 {
+			gpio-offset = <0x30 28>;
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+		};
+
+	};
+
 	pci {
 		compatible = "pci-x86";
 		#address-cells = <3>;
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 28/51] x86: Add an ICH6 pin configuration driver

[Simon Glass]

Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Use setio_32() instead of setio_le32(), etc.

 arch/x86/include/asm/cpu.h                         |   1 +
 arch/x86/lib/Makefile                              |   1 +
 arch/x86/lib/pinctrl_ich6.c                        | 216 +++++++++++++++++++++
 .../gpio/intel,x86-pinctrl.txt                     |   1 +
 4 files changed, 219 insertions(+)
 create mode 100644 arch/x86/lib/pinctrl_ich6.c

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 987dc65..85386da 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -54,6 +54,7 @@ enum {
 	X86_NONE,
 	X86_SYSCON_ME,		/* Intel Management Engine */
 	X86_SYSCON_GMA,		/* Intel Graphics Media Accelerator */
+	X86_SYSCON_PINCONF,	/* Intel x86 pin configuration */
 };
 
 struct cpuid_result {
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 6e0234a..dc90df2 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -23,6 +23,7 @@ obj-y += cmd_mtrr.o
 obj-y	+= northbridge-uclass.o
 obj-$(CONFIG_I8259_PIC) += i8259.o
 obj-$(CONFIG_I8254_TIMER) += i8254.o
+obj-y	+= pinctrl_ich6.o
 obj-y	+= pirq_routing.o
 obj-y	+= relocate.o
 obj-y += physmem.o
diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c
new file mode 100644
index 0000000..3f94cdf
--- /dev/null
+++ b/arch/x86/lib/pinctrl_ich6.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_USESEL_OFFSET(x)	(x)
+#define GPIO_IOSEL_OFFSET(x)	(x + 4)
+#define GPIO_LVL_OFFSET(x)	((x) ? (x) + 8 : 0xc)
+#define GPI_INV			0x2c
+
+#define IOPAD_MODE_MASK			0x7
+#define IOPAD_PULL_ASSIGN_SHIFT		7
+#define IOPAD_PULL_ASSIGN_MASK		(0x3 << IOPAD_PULL_ASSIGN_SHIFT)
+#define IOPAD_PULL_STRENGTH_SHIFT	9
+#define IOPAD_PULL_STRENGTH_MASK	(0x3 << IOPAD_PULL_STRENGTH_SHIFT)
+
+static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value)
+{
+	if (value)
+		setio_32(base, 1UL << offset);
+	else
+		clrio_32(base, 1UL << offset);
+
+	return 0;
+}
+
+static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func)
+{
+	if (func)
+		setio_32(base, 1UL << offset);
+	else
+		clrio_32(base, 1UL << offset);
+
+	return 0;
+}
+
+static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir)
+{
+	if (!dir)
+		setio_32(base, 1UL << offset);
+	else
+		clrio_32(base, 1UL << offset);
+
+	return 0;
+}
+
+static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
+{
+	bool is_gpio, invert;
+	u32 gpio_offset[2];
+	int pad_offset;
+	int dir, val;
+	int ret;
+
+	/*
+	 * GPIO node is not mandatory, so we only do the pinmuxing if the
+	 * node exists.
+	 */
+	ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
+				   gpio_offset, 2);
+	if (!ret) {
+		/* Do we want to force the GPIO mode? */
+		is_gpio = fdtdec_get_bool(gd->fdt_blob, pin_node, "mode-gpio");
+		if (is_gpio)
+			ich6_pinctrl_set_function(GPIO_USESEL_OFFSET(gpiobase) +
+						gpio_offset[0], gpio_offset[1],
+						1);
+
+		dir = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
+		if (dir != -1)
+			ich6_pinctrl_set_direction(GPIO_IOSEL_OFFSET(gpiobase) +
+						 gpio_offset[0], gpio_offset[1],
+						 dir);
+
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "output-value",
+				     -1);
+		if (val != -1)
+			ich6_pinctrl_set_value(GPIO_LVL_OFFSET(gpiobase) +
+					     gpio_offset[0], gpio_offset[1],
+					     val);
+
+		invert = fdtdec_get_bool(gd->fdt_blob, pin_node, "invert");
+		if (invert)
+			setio_32(gpiobase + GPI_INV, 1 << gpio_offset[1]);
+		debug("gpio %#x bit %d, is_gpio %d, dir %d, val %d, invert %d\n",
+		      gpio_offset[0], gpio_offset[1], is_gpio, dir, val,
+		      invert);
+	}
+
+	/* if iobase is present, let's configure the pad */
+	if (iobase != -1) {
+		int iobase_addr;
+
+		/*
+		 * The offset for the same pin for the IOBASE and GPIOBASE are
+		 * different, so instead of maintaining a lookup table,
+		 * the device tree should provide directly the correct
+		 * value for both mapping.
+		 */
+		pad_offset = fdtdec_get_int(gd->fdt_blob, pin_node,
+					    "pad-offset", -1);
+		if (pad_offset == -1)
+			return 0;
+
+		/* compute the absolute pad address */
+		iobase_addr = iobase + pad_offset;
+
+		/*
+		 * Do we need to set a specific function mode?
+		 * If someone put also 'mode-gpio', this option will
+		 * be just ignored by the controller
+		 */
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
+		if (val != -1)
+			clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
+
+		/* Configure the pull-up/down if needed */
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
+		if (val != -1)
+			clrsetbits_le32(iobase_addr,
+					IOPAD_PULL_ASSIGN_MASK,
+					val << IOPAD_PULL_ASSIGN_SHIFT);
+
+		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength",
+				     -1);
+		if (val != -1)
+			clrsetbits_le32(iobase_addr,
+					IOPAD_PULL_STRENGTH_MASK,
+					val << IOPAD_PULL_STRENGTH_SHIFT);
+
+		debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
+		      readl(iobase_addr));
+	}
+
+	return 0;
+}
+
+static int ich6_pinctrl_probe(struct udevice *dev)
+{
+	struct udevice *pch;
+	int pin_node;
+	int ret;
+	u32 gpiobase;
+	u32 iobase = -1;
+
+	debug("%s: start\n", __func__);
+	ret = uclass_first_device(UCLASS_PCH, &pch);
+	if (ret)
+		return ret;
+	if (!pch)
+		return -ENODEV;
+
+	/*
+	 * Get the memory/io base address to configure every pins.
+	 * IOBASE is used to configure the mode/pads
+	 * GPIOBASE is used to configure the direction and default value
+	 */
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
+		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
+		      gpiobase);
+		return -EINVAL;
+	}
+
+	/*
+	 * Get the IOBASE, this is not mandatory as this is not
+	 * supported by all the CPU
+	 */
+	ret = pch_get_io_base(pch, &iobase);
+	if (ret && ret != -ENOSYS) {
+		debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase);
+		return -EINVAL;
+	}
+
+	for (pin_node = fdt_first_subnode(gd->fdt_blob, dev->of_offset);
+	     pin_node > 0;
+	     pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
+		/* Configure the pin */
+		ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
+		if (ret != 0) {
+			debug("%s: invalid configuration for the pin %d\n",
+			      __func__, pin_node);
+			return ret;
+		}
+	}
+	debug("%s: done\n", __func__);
+
+	return 0;
+}
+
+static const struct udevice_id ich6_pinctrl_match[] = {
+	{ .compatible = "intel,x86-pinctrl", .data = X86_SYSCON_PINCONF },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(ich6_pinctrl) = {
+	.name = "ich6_pinctrl",
+	.id = UCLASS_SYSCON,
+	.of_match = ich6_pinctrl_match,
+	.probe = ich6_pinctrl_probe,
+};
diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index 45ab1af..be5d51c 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -19,6 +19,7 @@ in case of 'mode-gpio' property set:
 - direction         - (optional) this set the direction of the gpio.
 - pull-str          - (optional) this set the pull strength of the pin.
 - pull-assign       - (optional) this set the pull assignement (up/down) of the pin.
+- invert            - (optional) this input pin is inverted
 
 Example:
 
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 29/51] x86: gpio: Allow the pinctrl driver to set up the pin config

[Simon Glass]

Rather than setting up the pin configuration in the GPIO driver, use the
new pinctrl driver to do it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 configs/bayleybay_defconfig     |   2 +
 configs/cougarcanyon2_defconfig |   2 +
 configs/crownbay_defconfig      |   2 +
 configs/galileo_defconfig       |   2 +
 configs/minnowmax_defconfig     |   6 +-
 drivers/gpio/intel_ich6_gpio.c  | 180 ++--------------------------------------
 6 files changed, 17 insertions(+), 177 deletions(-)

diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 0879d1e..8e1347c 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -19,6 +19,8 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index 09306bb..71028cf 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -8,6 +8,8 @@ CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_PCI=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 6bc4b8d..3c5891b 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -17,6 +17,8 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 925d3ee..b5863fc 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -13,6 +13,8 @@ CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index af6a8ec..848d5da 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,16 +8,18 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index c81d033..ae999af 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -32,6 +32,8 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/pci.h>
@@ -51,12 +53,6 @@ struct ich6_bank_priv {
 #define GPIO_IOSEL_OFFSET(x)	(x + 4)
 #define GPIO_LVL_OFFSET(x)	(x + 8)
 
-#define IOPAD_MODE_MASK				0x7
-#define IOPAD_PULL_ASSIGN_SHIFT		7
-#define IOPAD_PULL_ASSIGN_MASK		(0x3 << IOPAD_PULL_ASSIGN_SHIFT)
-#define IOPAD_PULL_STRENGTH_SHIFT	9
-#define IOPAD_PULL_STRENGTH_MASK	(0x3 << IOPAD_PULL_STRENGTH_SHIFT)
-
 /* TODO: Move this to device tree, or platform data */
 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
 {
@@ -77,23 +73,6 @@ static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
 	return 0;
 }
 
-static int _ich6_gpio_set_function(uint16_t base, unsigned offset, int func)
-{
-	u32 val;
-
-	if (func) {
-		val = inl(base);
-		val |= (1UL << offset);
-		outl(val, base);
-	} else {
-		val = inl(base);
-		val &= ~(1UL << offset);
-		outl(val, base);
-	}
-
-	return 0;
-}
-
 static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
 {
 	u32 val;
@@ -111,155 +90,8 @@ static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
 	return 0;
 }
 
-static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
-{
-	u32 gpio_offset[2];
-	int pad_offset;
-	int val;
-	int ret;
-	const void *prop;
-
-	/*
-	 * GPIO node is not mandatory, so we only do the
-	 * pinmuxing if the node exist.
-	 */
-	ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
-			     gpio_offset, 2);
-	if (!ret) {
-		/* Do we want to force the GPIO mode? */
-		prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio",
-				      NULL);
-		if (prop)
-			_ich6_gpio_set_function(GPIO_USESEL_OFFSET
-						(gpiobase) +
-						gpio_offset[0],
-						gpio_offset[1], 1);
-
-		val =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
-		if (val != -1)
-			_ich6_gpio_set_direction(GPIO_IOSEL_OFFSET
-						 (gpiobase) +
-						 gpio_offset[0],
-						 gpio_offset[1], val);
-
-		val =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "output-value", -1);
-		if (val != -1)
-			_ich6_gpio_set_value(GPIO_LVL_OFFSET(gpiobase)
-					     + gpio_offset[0],
-					     gpio_offset[1], val);
-	}
-
-	/* if iobase is present, let's configure the pad */
-	if (iobase != -1) {
-		int iobase_addr;
-
-		/*
-		 * The offset for the same pin for the IOBASE and GPIOBASE are
-		 * different, so instead of maintaining a lookup table,
-		 * the device tree should provide directly the correct
-		 * value for both mapping.
-		 */
-		pad_offset =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "pad-offset", -1);
-		if (pad_offset == -1) {
-			debug("%s: Invalid register io offset %d\n",
-			      __func__, pad_offset);
-			return -EINVAL;
-		}
-
-		/* compute the absolute pad address */
-		iobase_addr = iobase + pad_offset;
-
-		/*
-		 * Do we need to set a specific function mode?
-		 * If someone put also 'mode-gpio', this option will
-		 * be just ignored by the controller
-		 */
-		val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
-		if (val != -1)
-			clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
-
-		/* Configure the pull-up/down if needed */
-		val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
-		if (val != -1)
-			clrsetbits_le32(iobase_addr,
-					IOPAD_PULL_ASSIGN_MASK,
-					val << IOPAD_PULL_ASSIGN_SHIFT);
-
-		val =
-		    fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength", -1);
-		if (val != -1)
-			clrsetbits_le32(iobase_addr,
-					IOPAD_PULL_STRENGTH_MASK,
-					val << IOPAD_PULL_STRENGTH_SHIFT);
-
-		debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
-		      readl(iobase_addr));
-	}
-
-	return 0;
-}
-
 int gpio_ich6_pinctrl_init(void)
 {
-	struct udevice *pch;
-	int pin_node;
-	int node;
-	int ret;
-	u32 gpiobase;
-	u32 iobase = -1;
-
-	ret = uclass_first_device(UCLASS_PCH, &pch);
-	if (ret)
-		return ret;
-	if (!pch)
-		return -ENODEV;
-
-	/*
-	 * Get the memory/io base address to configure every pins.
-	 * IOBASE is used to configure the mode/pads
-	 * GPIOBASE is used to configure the direction and default value
-	 */
-	ret = pch_get_gpio_base(pch, &gpiobase);
-	if (ret) {
-		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
-		      gpiobase);
-		return -EINVAL;
-	}
-
-	/* This is not an error to not have a pinctrl node */
-	node =
-	    fdtdec_next_compatible(gd->fdt_blob, 0, COMPAT_INTEL_X86_PINCTRL);
-	if (node <= 0) {
-		debug("%s: no pinctrl node\n", __func__);
-		return 0;
-	}
-
-	/*
-	 * Get the IOBASE, this is not mandatory as this is not
-	 * supported by all the CPU
-	 */
-	ret = pch_get_io_base(pch, &iobase);
-	if (ret && ret != -ENOSYS) {
-		debug("%s: invalid IOBASE address (%08x)\n", __func__,
-		      iobase);
-		return -EINVAL;
-	}
-
-	for (pin_node = fdt_first_subnode(gd->fdt_blob, node);
-	     pin_node > 0;
-	     pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
-		/* Configure the pin */
-		ret = _gpio_ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
-		if (ret != 0) {
-			debug("%s: invalid configuration for the pin %d\n",
-			      __func__, pin_node);
-			return ret;
-		}
-	}
-
 	return 0;
 }
 
@@ -292,12 +124,10 @@ static int ich6_gpio_probe(struct udevice *dev)
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
+	struct udevice *pinctrl;
 
-	if (gd->arch.gpio_map) {
-		setup_pch_gpios(plat->base_addr - plat->offset,
-				gd->arch.gpio_map);
-		gd->arch.gpio_map = NULL;
-	}
+	/* Set up pin control if available */
+	syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
 
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 30/51] x86: Drop all the old pin configuration code

[Simon Glass]

We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/include/asm/gpio.h               | 141 ------------------------------
 board/coreboot/coreboot/coreboot.c        |   5 --
 board/efi/efi-x86/efi.c                   |   5 --
 board/google/chromebook_link/link.c       | 138 -----------------------------
 board/google/chromebox_panther/panther.c  |   4 -
 board/intel/bayleybay/bayleybay.c         |   5 --
 board/intel/cougarcanyon2/cougarcanyon2.c |   5 --
 board/intel/crownbay/crownbay.c           |   5 --
 board/intel/galileo/galileo.c             |   5 --
 board/intel/minnowmax/minnowmax.c         |   8 --
 drivers/gpio/intel_ich6_gpio.c            |  11 ---
 include/fdtdec.h                          |   1 -
 lib/fdtdec.c                              |   1 -
 13 files changed, 334 deletions(-)

diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 40f4958..586ece6 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -6,7 +6,6 @@
 #ifndef _X86_GPIO_H_
 #define _X86_GPIO_H_
 
-#include <linux/compiler.h>
 #include <asm-generic/gpio.h>
 
 struct ich6_bank_platdata {
@@ -15,144 +14,4 @@ struct ich6_bank_platdata {
 	int offset;
 };
 
-#define GPIO_MODE_NATIVE	0
-#define GPIO_MODE_GPIO		1
-#define GPIO_MODE_NONE		1
-
-#define GPIO_DIR_OUTPUT		0
-#define GPIO_DIR_INPUT		1
-
-#define GPIO_NO_INVERT		0
-#define GPIO_INVERT		1
-
-#define GPIO_LEVEL_LOW		0
-#define GPIO_LEVEL_HIGH		1
-
-#define GPIO_NO_BLINK		0
-#define GPIO_BLINK		1
-
-#define GPIO_RESET_PWROK	0
-#define GPIO_RESET_RSMRST	1
-
-struct pch_gpio_set1 {
-	u32 gpio0:1;
-	u32 gpio1:1;
-	u32 gpio2:1;
-	u32 gpio3:1;
-	u32 gpio4:1;
-	u32 gpio5:1;
-	u32 gpio6:1;
-	u32 gpio7:1;
-	u32 gpio8:1;
-	u32 gpio9:1;
-	u32 gpio10:1;
-	u32 gpio11:1;
-	u32 gpio12:1;
-	u32 gpio13:1;
-	u32 gpio14:1;
-	u32 gpio15:1;
-	u32 gpio16:1;
-	u32 gpio17:1;
-	u32 gpio18:1;
-	u32 gpio19:1;
-	u32 gpio20:1;
-	u32 gpio21:1;
-	u32 gpio22:1;
-	u32 gpio23:1;
-	u32 gpio24:1;
-	u32 gpio25:1;
-	u32 gpio26:1;
-	u32 gpio27:1;
-	u32 gpio28:1;
-	u32 gpio29:1;
-	u32 gpio30:1;
-	u32 gpio31:1;
-} __packed;
-
-struct pch_gpio_set2 {
-	u32 gpio32:1;
-	u32 gpio33:1;
-	u32 gpio34:1;
-	u32 gpio35:1;
-	u32 gpio36:1;
-	u32 gpio37:1;
-	u32 gpio38:1;
-	u32 gpio39:1;
-	u32 gpio40:1;
-	u32 gpio41:1;
-	u32 gpio42:1;
-	u32 gpio43:1;
-	u32 gpio44:1;
-	u32 gpio45:1;
-	u32 gpio46:1;
-	u32 gpio47:1;
-	u32 gpio48:1;
-	u32 gpio49:1;
-	u32 gpio50:1;
-	u32 gpio51:1;
-	u32 gpio52:1;
-	u32 gpio53:1;
-	u32 gpio54:1;
-	u32 gpio55:1;
-	u32 gpio56:1;
-	u32 gpio57:1;
-	u32 gpio58:1;
-	u32 gpio59:1;
-	u32 gpio60:1;
-	u32 gpio61:1;
-	u32 gpio62:1;
-	u32 gpio63:1;
-} __packed;
-
-struct pch_gpio_set3 {
-	u32 gpio64:1;
-	u32 gpio65:1;
-	u32 gpio66:1;
-	u32 gpio67:1;
-	u32 gpio68:1;
-	u32 gpio69:1;
-	u32 gpio70:1;
-	u32 gpio71:1;
-	u32 gpio72:1;
-	u32 gpio73:1;
-	u32 gpio74:1;
-	u32 gpio75:1;
-} __packed;
-
-/*
- * This hilariously complex structure came from Coreboot. The
- * setup_pch_gpios() function uses it. It could be move to device tree, or
- * adjust to use masks instead of bitfields.
- */
-struct pch_gpio_map {
-	struct {
-		const struct pch_gpio_set1 *mode;
-		const struct pch_gpio_set1 *direction;
-		const struct pch_gpio_set1 *level;
-		const struct pch_gpio_set1 *reset;
-		const struct pch_gpio_set1 *invert;
-		const struct pch_gpio_set1 *blink;
-	} set1;
-	struct {
-		const struct pch_gpio_set2 *mode;
-		const struct pch_gpio_set2 *direction;
-		const struct pch_gpio_set2 *level;
-		const struct pch_gpio_set2 *reset;
-	} set2;
-	struct {
-		const struct pch_gpio_set3 *mode;
-		const struct pch_gpio_set3 *direction;
-		const struct pch_gpio_set3 *level;
-		const struct pch_gpio_set3 *reset;
-	} set3;
-};
-
-/*
- * Deprecated functions to set up the GPIO map. The device tree should be used
- * instead.
- */
-int gpio_ich6_pinctrl_init(void);
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
-void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
-
 #endif /* _X86_GPIO_H_ */
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
index 7110f35..bb7f778 100644
--- a/board/coreboot/coreboot/coreboot.c
+++ b/board/coreboot/coreboot/coreboot.c
@@ -12,8 +12,3 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/efi/efi-x86/efi.c b/board/efi/efi-x86/efi.c
index 08958f9..1fbe36a 100644
--- a/board/efi/efi-x86/efi.c
+++ b/board/efi/efi-x86/efi.c
@@ -11,8 +11,3 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index d12d742..42615e1 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -17,145 +17,7 @@ int arch_early_init_r(void)
 	return 0;
 }
 
-static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-	.gpio0 = GPIO_MODE_GPIO,  /* NMI_DBG# */
-	.gpio3 = GPIO_MODE_GPIO,  /* ALS_INT# */
-	.gpio5 = GPIO_MODE_GPIO,  /* SIM_DET */
-	.gpio7 = GPIO_MODE_GPIO,  /* EC_SCI# */
-	.gpio8 = GPIO_MODE_GPIO,  /* EC_SMI# */
-	.gpio9 = GPIO_MODE_GPIO,  /* RECOVERY# */
-	.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
-	.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
-	.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
-	.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
-	.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
-	.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
-	.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
-	.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-	.gpio0 = GPIO_DIR_INPUT,
-	.gpio3 = GPIO_DIR_INPUT,
-	.gpio5 = GPIO_DIR_INPUT,
-	.gpio7 = GPIO_DIR_INPUT,
-	.gpio8 = GPIO_DIR_INPUT,
-	.gpio9 = GPIO_DIR_INPUT,
-	.gpio10 = GPIO_DIR_INPUT,
-	.gpio11 = GPIO_DIR_INPUT,
-	.gpio12 = GPIO_DIR_INPUT,
-	.gpio14 = GPIO_DIR_INPUT,
-	.gpio15 = GPIO_DIR_INPUT,
-	.gpio21 = GPIO_DIR_INPUT,
-	.gpio24 = GPIO_DIR_OUTPUT,
-	.gpio28 = GPIO_DIR_INPUT,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_level = {
-	.gpio1 = GPIO_LEVEL_HIGH,
-	.gpio6 = GPIO_LEVEL_HIGH,
-	.gpio24 = GPIO_LEVEL_LOW,
-};
-
-static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-	.gpio7 = GPIO_INVERT,
-	.gpio8 = GPIO_INVERT,
-	.gpio12 = GPIO_INVERT,
-	.gpio14 = GPIO_INVERT,
-	.gpio15 = GPIO_INVERT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-	.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
-	.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
-	.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
-	.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
-	.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
-	.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-	.gpio36 = GPIO_DIR_OUTPUT,
-	.gpio41 = GPIO_DIR_INPUT,
-	.gpio42 = GPIO_DIR_INPUT,
-	.gpio43 = GPIO_DIR_INPUT,
-	.gpio57 = GPIO_DIR_INPUT,
-	.gpio60 = GPIO_DIR_OUTPUT,
-};
-
-static const struct pch_gpio_set2 pch_gpio_set2_level = {
-	.gpio36 = GPIO_LEVEL_HIGH,
-	.gpio60 = GPIO_LEVEL_HIGH,
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-};
-
-static const struct pch_gpio_set3 pch_gpio_set3_level = {
-};
-
-static const struct pch_gpio_map link_gpio_map = {
-	.set1 = {
-		.mode      = &pch_gpio_set1_mode,
-		.direction = &pch_gpio_set1_direction,
-		.level     = &pch_gpio_set1_level,
-		.invert    = &pch_gpio_set1_invert,
-	},
-	.set2 = {
-		.mode      = &pch_gpio_set2_mode,
-		.direction = &pch_gpio_set2_direction,
-		.level     = &pch_gpio_set2_level,
-	},
-	.set3 = {
-		.mode      = &pch_gpio_set3_mode,
-		.direction = &pch_gpio_set3_direction,
-		.level     = &pch_gpio_set3_level,
-	},
-};
-
 int board_early_init_f(void)
 {
-	ich_gpio_set_gpio_map(&link_gpio_map);
-
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	/* GPIO Set 1 */
-	if (gpio->set1.level)
-		outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
-	if (gpio->set1.mode)
-		outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
-	if (gpio->set1.direction)
-		outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
-	if (gpio->set1.reset)
-		outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
-	if (gpio->set1.invert)
-		outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
-	if (gpio->set1.blink)
-		outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
-
-	/* GPIO Set 2 */
-	if (gpio->set2.level)
-		outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
-	if (gpio->set2.mode)
-		outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
-	if (gpio->set2.direction)
-		outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
-	if (gpio->set2.reset)
-		outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
-
-	/* GPIO Set 3 */
-	if (gpio->set3.level)
-		outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
-	if (gpio->set3.mode)
-		outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
-	if (gpio->set3.direction)
-		outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
-	if (gpio->set3.reset)
-		outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
-}
diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c
index d492a03..e3baf88 100644
--- a/board/google/chromebox_panther/panther.c
+++ b/board/google/chromebox_panther/panther.c
@@ -16,7 +16,3 @@ int board_early_init_f(void)
 {
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-}
diff --git a/board/intel/bayleybay/bayleybay.c b/board/intel/bayleybay/bayleybay.c
index ccbe860..846b2f7 100644
--- a/board/intel/bayleybay/bayleybay.c
+++ b/board/intel/bayleybay/bayleybay.c
@@ -6,8 +6,3 @@
 
 #include <common.h>
 #include <asm/gpio.h>
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/cougarcanyon2/cougarcanyon2.c b/board/intel/cougarcanyon2/cougarcanyon2.c
index c03247c..c350237 100644
--- a/board/intel/cougarcanyon2/cougarcanyon2.c
+++ b/board/intel/cougarcanyon2/cougarcanyon2.c
@@ -52,8 +52,3 @@ int board_early_init_f(void)
 
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/crownbay/crownbay.c b/board/intel/crownbay/crownbay.c
index 3a79e69..562d6d1 100644
--- a/board/intel/crownbay/crownbay.c
+++ b/board/intel/crownbay/crownbay.c
@@ -18,8 +18,3 @@ int board_early_init_f(void)
 
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c
index 212c970..568bd4d 100644
--- a/board/intel/galileo/galileo.c
+++ b/board/intel/galileo/galileo.c
@@ -65,8 +65,3 @@ void board_deassert_perst(void)
 	val |= (1 << 0);
 	outl(val, port);
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c
index 44e5bf4..94b22ed 100644
--- a/board/intel/minnowmax/minnowmax.c
+++ b/board/intel/minnowmax/minnowmax.c
@@ -9,13 +9,5 @@
 
 int arch_early_init_r(void)
 {
-	/* do the pin-muxing */
-	gpio_ich6_pinctrl_init();
-
 	return 0;
 }
-
-void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
-{
-	return;
-}
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index ae999af..b7e379a 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -53,12 +53,6 @@ struct ich6_bank_priv {
 #define GPIO_IOSEL_OFFSET(x)	(x + 4)
 #define GPIO_LVL_OFFSET(x)	(x + 8)
 
-/* TODO: Move this to device tree, or platform data */
-void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
-{
-	gd->arch.gpio_map = map;
-}
-
 static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
 {
 	u32 val;
@@ -90,11 +84,6 @@ static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
 	return 0;
 }
 
-int gpio_ich6_pinctrl_init(void)
-{
-	return 0;
-}
-
 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index eed01e0..fb88273 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -158,7 +158,6 @@ enum fdt_compat_id {
 	COMPAT_AMS_AS3722,		/* AMS AS3722 PMIC */
 	COMPAT_INTEL_ICH_SPI,		/* Intel ICH7/9 SPI controller */
 	COMPAT_INTEL_QRK_MRC,		/* Intel Quark MRC */
-	COMPAT_INTEL_X86_PINCTRL,	/* Intel ICH7/9 pin control */
 	COMPAT_SOCIONEXT_XHCI,		/* Socionext UniPhier xHCI */
 	COMPAT_INTEL_PCH,		/* Intel PCH */
 	COMPAT_ALTERA_SOCFPGA_DWMAC,	/* SoCFPGA Ethernet controller */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 6e89e95..4fec642 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -63,7 +63,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(AMS_AS3722, "ams,as3722"),
 	COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
 	COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
-	COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"),
 	COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
 	COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
 	COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 31/51] x86: Add support for running Intel reference code

[Simon Glass]

Intel has invented yet another binary blob which firmware is required to
run. This is run after SDRAM is ready. It is linked to load at a particular
address, typically 0, but is a relocatable ELF so can be moved if required.

Add support for this in the build system. The file should be placed in the
board directory, and called refcode.elf.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Fix 'PCB' typo (should be 'PCH')

 Makefile                   | 14 +++++++++++++-
 arch/x86/Kconfig           | 11 +++++++++++
 arch/x86/include/asm/cpu.h | 12 ++++++++++++
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index fadf1a3..3fbaea4 100644
--- a/Makefile
+++ b/Makefile
@@ -1044,6 +1044,10 @@ ifneq ($(CONFIG_HAVE_VGA_BIOS),)
 IFDTOOL_FLAGS += -w $(CONFIG_VGA_BIOS_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_VGA_BIOS_FILE)
 endif
 
+ifneq ($(CONFIG_HAVE_REFCODE),)
+IFDTOOL_FLAGS += -w $(CONFIG_X86_REFCODE_ADDR):refcode.bin
+endif
+
 quiet_cmd_ifdtool = IFDTOOL $@
 cmd_ifdtool  = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
 ifneq ($(CONFIG_HAVE_INTEL_ME),)
@@ -1052,7 +1056,15 @@ endif
 cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
 cmd_ifdtool += mv u-boot.tmp $@
 
-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE
+refcode.bin: $(srctree)/board/$(BOARDDIR)/refcode.bin FORCE
+	$(call if_changed,copy)
+
+quiet_cmd_ldr = LD      $@
+cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
+	       $(filter-out FORCE,$^) -o $@
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
+		$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
 	$(call if_changed,ifdtool)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 64c824f..1a9fa40 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -327,6 +327,17 @@ config DCACHE_RAM_MRC_VAR_SIZE
 	  memory reference code and must be set correctly or the board will
 	  not boot.
 
+config HAVE_REFCODE
+        bool "Add a Reference Code binary"
+        help
+          Select this option to add a Reference Code binary to the resulting
+          U-Boot image. This is an Intel binary blob that handles system
+          initialisation, in this case the PCH and System Agent.
+
+          Note: Without this binary (on platforms that need it such as
+          broadwell) U-Boot will be missing some critical setup steps.
+          Various peripherals may fail to work.
+
 config SMP
 	bool "Enable Symmetric Multiprocessing"
 	default n
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 85386da..7892757 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -275,4 +275,16 @@ u32 cpu_get_family_model(void);
  */
 u32 cpu_get_stepping(void);
 
+/**
+ * cpu_run_reference_code() - Run the platform reference code
+ *
+ * Some platforms require a binary blob to be executed once SDRAM is
+ * available. This is used to set up various platform features, such as the
+ * platform controller hub (PCH). This function should be implemented by the
+ * CPU-specific code.
+ *
+ * @return 0 on success, -ve on failure
+ */
+int cpu_run_reference_code(void);
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 32/51] x86: dts: Update the pinctrl binding a little

[Simon Glass]

Make a few minor updates to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
index be5d51c..22d3bec 100644
--- a/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
+++ b/doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt
@@ -8,17 +8,18 @@ The PINCTRL master node requires the following properties:
 
 Pin nodes must be children of the pinctrl master node and can
 contain the following properties:
-- pad-offset        - (required) offset in the IOBASE for the pin to configured.
-- gpio-offset       - (required) offset in the GPIOBASE for the pin to configured and
-					also the bit shift in this register.
-- mode-gpio			- (optional) standalone property to force the pin into GPIO mode.
-- mode-func			- (optional) function number to assign to the pin. if 'mode-gpio'
-					is set, this property will be ignored.
+- pad-offset	- (required) offset in the IOBASE for the pin to configure
+- gpio-offset	- (required) 2 cells
+			- offset in the GPIOBASE for the pin to configure
+			- the bit shift in this register (4 = bit 4)
+- mode-gpio	- (optional) standalone property to force the pin into GPIO mode
+- mode-func	- (optional) function number to assign to the pin. If
+			'mode-gpio' is set, this property will be ignored.
 in case of 'mode-gpio' property set:
-- output-value		- (optional) this set the default output value of the GPIO.
-- direction         - (optional) this set the direction of the gpio.
-- pull-str          - (optional) this set the pull strength of the pin.
-- pull-assign       - (optional) this set the pull assignement (up/down) of the pin.
+- output-value	- (optional) this set the default output value of the GPIO
+- direction	- (optional) this set the direction of the gpio
+- pull-str	- (optional) this set the pull strength of the pin
+- pull-assign	- (optional) this set the pull assignement (up/down) of the pin
 - invert            - (optional) this input pin is inverted
 
 Example:
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 33/51] x86: Add basic support for broadwell

[Simon Glass]

This adds the broadwell architecture, with the CPU driver and some useful
header files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/Kconfig                            |   1 +
 arch/x86/cpu/Makefile                       |   1 +
 arch/x86/cpu/broadwell/Kconfig              |  30 ++
 arch/x86/cpu/broadwell/Makefile             |   7 +
 arch/x86/cpu/broadwell/cpu.c                | 761 ++++++++++++++++++++++++++++
 arch/x86/include/asm/arch-broadwell/cpu.h   |  48 ++
 arch/x86/include/asm/arch-broadwell/iomap.h |  53 ++
 arch/x86/include/asm/arch-broadwell/me.h    | 200 ++++++++
 arch/x86/include/asm/arch-broadwell/rcb.h   |  58 +++
 arch/x86/include/asm/arch-broadwell/spi.h   |  87 ++++
 10 files changed, 1246 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/Kconfig
 create mode 100644 arch/x86/cpu/broadwell/Makefile
 create mode 100644 arch/x86/cpu/broadwell/cpu.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/me.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h
 create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1a9fa40..0b30883 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -34,6 +34,7 @@ source "board/intel/Kconfig"
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
 source "arch/x86/cpu/qemu/Kconfig"
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2583809..2667e0b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -20,6 +20,7 @@ extra-y += call32.o
 
 obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
+obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
 obj-$(CONFIG_EFI_APP) += efi/
 obj-$(CONFIG_QEMU) += qemu/
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
new file mode 100644
index 0000000..1ce3848
--- /dev/null
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2016 Google Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0
+
+config INTEL_BROADWELL
+	bool
+	select CACHE_MRC_BIN
+
+if INTEL_BROADWELL
+
+config DCACHE_RAM_BASE
+	default 0xff7c0000
+
+config DCACHE_RAM_SIZE
+	default 0x40000
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	default 0x30000
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select SMM_TSEG
+	select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
+endif
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
new file mode 100644
index 0000000..c7ef630
--- /dev/null
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cpu.o
diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c
new file mode 100644
index 0000000..3ba21aa
--- /dev/null
+++ b/arch/x86/cpu/broadwell/cpu.c
@@ -0,0 +1,761 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/cpu.c
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <cpu.h>
+#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/msr.h>
+#include <asm/post.h>
+#include <asm/turbo.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/rcb.h>
+
+struct cpu_broadwell_priv {
+	bool ht_disabled;
+};
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+	[0]   = 0x00,
+	[1]   = 0x0a,
+	[2]   = 0x0b,
+	[3]   = 0x4b,
+	[4]   = 0x0c,
+	[5]   = 0x2c,
+	[6]   = 0x4c,
+	[7]   = 0x6c,
+	[8]   = 0x0d,
+	[10]  = 0x2d,
+	[12]  = 0x4d,
+	[14]  = 0x6d,
+	[16]  = 0x0e,
+	[20]  = 0x2e,
+	[24]  = 0x4e,
+	[28]  = 0x6e,
+	[32]  = 0x0f,
+	[40]  = 0x2f,
+	[48]  = 0x4f,
+	[56]  = 0x6f,
+	[64]  = 0x10,
+	[80]  = 0x30,
+	[96]  = 0x50,
+	[112] = 0x70,
+	[128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+	[0x00] = 0,
+	[0x0a] = 1,
+	[0x0b] = 2,
+	[0x4b] = 3,
+	[0x0c] = 4,
+	[0x2c] = 5,
+	[0x4c] = 6,
+	[0x6c] = 7,
+	[0x0d] = 8,
+	[0x2d] = 10,
+	[0x4d] = 12,
+	[0x6d] = 14,
+	[0x0e] = 16,
+	[0x2e] = 20,
+	[0x4e] = 24,
+	[0x6e] = 28,
+	[0x0f] = 32,
+	[0x2f] = 40,
+	[0x4f] = 48,
+	[0x6f] = 56,
+	[0x10] = 64,
+	[0x30] = 80,
+	[0x50] = 96,
+	[0x70] = 112,
+	[0x11] = 128,
+};
+
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	/* Start up the LPC so we have serial */
+	ret = uclass_first_device(UCLASS_LPC, &dev);
+	if (ret)
+		return ret;
+	if (!dev)
+		return -ENODEV;
+	ret = cpu_set_flex_ratio_to_tdp_nominal();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void set_max_freq(void)
+{
+	msr_t msr, perf_ctl, platform_info;
+
+	/* Check for configurable TDP option */
+	platform_info = msr_read(MSR_PLATFORM_INFO);
+
+	if ((platform_info.hi >> 1) & 3) {
+		/* Set to nominal TDP ratio */
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = msr_read(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+
+	perf_ctl.hi = 0;
+	msr_write(IA32_PERF_CTL, perf_ctl);
+
+	debug("CPU: frequency set to %d MHz\n",
+	      ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}
+
+int arch_cpu_init(void)
+{
+	post_code(POST_CPU_INIT);
+
+	return x86_cpu_init_f();
+}
+
+int print_cpuinfo(void)
+{
+	char processor_name[CPU_MAX_NAME_LEN];
+	const char *name;
+	int ret;
+
+	set_max_freq();
+
+	ret = cpu_common_init();
+	if (ret)
+		return ret;
+	gd->arch.pei_boot_mode = PEI_BOOT_NONE;
+
+	/* Print processor name */
+	name = cpu_get_name(processor_name);
+	printf("CPU:   %s\n", name);
+
+	return 0;
+}
+
+/*
+ * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
+ * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
+ * when a core is woken up
+ */
+static int pcode_ready(void)
+{
+	int wait_count;
+	const int delay_step = 10;
+
+	wait_count = 0;
+	do {
+		if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
+				MAILBOX_RUN_BUSY))
+			return 0;
+		wait_count += delay_step;
+		udelay(delay_step);
+	} while (wait_count < 1000);
+
+	return -ETIMEDOUT;
+}
+
+static u32 pcode_mailbox_read(u32 command)
+{
+	int ret;
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on wait ready\n");
+		return ret;
+	}
+
+	/* Send command and start transaction */
+	writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on completion\n");
+		return ret;
+	}
+
+	/* Read mailbox */
+	return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
+}
+
+static int pcode_mailbox_write(u32 command, u32 data)
+{
+	int ret;
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on wait ready\n");
+		return ret;
+	}
+
+	writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
+
+	/* Send command and start transaction */
+	writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret) {
+		debug("PCODE: mailbox timeout on completion\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+/* @dev is the CPU device */
+static void initialize_vr_config(struct udevice *dev)
+{
+	int ramp, min_vid;
+	msr_t msr;
+
+	debug("Initializing VR config\n");
+
+	/* Configure VR_CURRENT_CONFIG */
+	msr = msr_read(MSR_VR_CURRENT_CONFIG);
+	/*
+	 * Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
+	 * on ULT systems
+	 */
+	msr.hi &= 0xc0000000;
+	msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold -  1A */
+	msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A */
+	msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
+	msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */
+	/* Leave the max instantaneous current limit (12:0) to default */
+	msr_write(MSR_VR_CURRENT_CONFIG, msr);
+
+	/* Configure VR_MISC_CONFIG MSR */
+	msr = msr_read(MSR_VR_MISC_CONFIG);
+	/* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
+	msr.hi &= ~(0x3ff << (40 - 32));
+	msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
+	/* Set IOUT_OFFSET to 0 */
+	msr.hi &= ~0xff;
+	/* Set entry ramp rate to slow */
+	msr.hi &= ~(1 << (51 - 32));
+	/* Enable decay mode on C-state entry */
+	msr.hi |= (1 << (52 - 32));
+	/* Set the slow ramp rate */
+	msr.hi &= ~(0x3 << (53 - 32));
+	/* Configure the C-state exit ramp rate */
+	ramp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,slow-ramp",
+			      -1);
+	if (ramp != -1) {
+		/* Configured slow ramp rate */
+		msr.hi |= ((ramp & 0x3) << (53 - 32));
+		/* Set exit ramp rate to slow */
+		msr.hi &= ~(1 << (50 - 32));
+	} else {
+		/* Fast ramp rate / 4 */
+		msr.hi |= (0x01 << (53 - 32));
+		/* Set exit ramp rate to fast */
+		msr.hi |= (1 << (50 - 32));
+	}
+	/* Set MIN_VID (31:24) to allow CPU to have full control */
+	msr.lo &= ~0xff000000;
+	min_vid = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,min-vid",
+				 0);
+	msr.lo |= (min_vid & 0xff) << 24;
+	msr_write(MSR_VR_MISC_CONFIG, msr);
+
+	/*  Configure VR_MISC_CONFIG2 MSR */
+	msr = msr_read(MSR_VR_MISC_CONFIG2);
+	msr.lo &= ~0xffff;
+	/*
+	 * Allow CPU to control minimum voltage completely (15:8) and
+	 * set the fast ramp voltage in 10mV steps
+	 */
+	if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
+		msr.lo |= 0x006a; /* 1.56V */
+	else
+		msr.lo |= 0x006f; /* 1.60V */
+	msr_write(MSR_VR_MISC_CONFIG2, msr);
+
+	/* Set C9/C10 VCC Min */
+	pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
+}
+
+static int calibrate_24mhz_bclk(void)
+{
+	int err_code;
+	int ret;
+
+	ret = pcode_ready();
+	if (ret)
+		return ret;
+
+	/* A non-zero value initiates the PCODE calibration */
+	writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
+	writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
+	       MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret)
+		return ret;
+
+	err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
+
+	debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
+
+	/* Read the calibrated value */
+	writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
+	       MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
+
+	ret = pcode_ready();
+	if (ret)
+		return ret;
+
+	debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
+	      readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
+
+	return 0;
+}
+
+static void configure_pch_power_sharing(void)
+{
+	u32 pch_power, pch_power_ext, pmsync, pmsync2;
+	int i;
+
+	/* Read PCH Power levels from PCODE */
+	pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
+	pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
+
+	debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
+	      pch_power_ext);
+
+	pmsync = readl(RCB_REG(PMSYNC_CONFIG));
+	pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
+
+	/*
+	 * Program PMSYNC_TPR_CONFIG PCH power limit values
+	 *  pmsync[0:4]   = mailbox[0:5]
+	 *  pmsync[8:12]  = mailbox[6:11]
+	 *  pmsync[16:20] = mailbox[12:17]
+	 */
+	for (i = 0; i < 3; i++) {
+		u32 level = pch_power & 0x3f;
+		pch_power >>= 6;
+		pmsync &= ~(0x1f << (i * 8));
+		pmsync |= (level & 0x1f) << (i * 8);
+	}
+	writel(pmsync, RCB_REG(PMSYNC_CONFIG));
+
+	/*
+	 * Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
+	 *  pmsync2[0:4]   = mailbox[23:18]
+	 *  pmsync2[8:12]  = mailbox_ext[6:11]
+	 *  pmsync2[16:20] = mailbox_ext[12:17]
+	 *  pmsync2[24:28] = mailbox_ext[18:22]
+	 */
+	pmsync2 &= ~0x1f;
+	pmsync2 |= pch_power & 0x1f;
+
+	for (i = 1; i < 4; i++) {
+		u32 level = pch_power_ext & 0x3f;
+		pch_power_ext >>= 6;
+		pmsync2 &= ~(0x1f << (i * 8));
+		pmsync2 |= (level & 0x1f) << (i * 8);
+	}
+	writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
+}
+
+static int bsp_init_before_ap_bringup(struct udevice *dev)
+{
+	int ret;
+
+	initialize_vr_config(dev);
+	ret = calibrate_24mhz_bclk();
+	if (ret)
+		return ret;
+	configure_pch_power_sharing();
+
+	return 0;
+}
+
+int cpu_config_tdp_levels(void)
+{
+	msr_t platform_info;
+
+	/* Bits 34:33 indicate how many levels supported */
+	platform_info = msr_read(MSR_PLATFORM_INFO);
+	return (platform_info.hi >> 1) & 3;
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Check for configurable TDP option */
+	if (turbo_get_state() == TURBO_ENABLED) {
+		msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else if (cpu_config_tdp_levels()) {
+		/* Set to nominal TDP ratio */
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		perf_ctl.lo = (msr.lo & 0xff) << 8;
+	} else {
+		/* Platform Info bits 15:8 give max ratio */
+		msr = msr_read(MSR_PLATFORM_INFO);
+		perf_ctl.lo = msr.lo & 0xff00;
+	}
+	msr_write(IA32_PERF_CTL, perf_ctl);
+
+	debug("cpu: frequency set to %d\n",
+	      ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+}
+
+int broadwell_init(struct udevice *dev)
+{
+	struct cpu_broadwell_priv *priv = dev_get_priv(dev);
+	int num_threads;
+	int num_cores;
+	msr_t msr;
+	int ret;
+
+	msr = msr_read(CORE_THREAD_COUNT_MSR);
+	num_threads = (msr.lo >> 0) & 0xffff;
+	num_cores = (msr.lo >> 16) & 0xffff;
+	debug("CPU has %u cores, %u threads enabled\n", num_cores,
+	      num_threads);
+
+	priv->ht_disabled = num_threads == num_cores;
+
+	ret = bsp_init_before_ap_bringup(dev);
+	if (ret)
+		return ret;
+
+	set_max_ratio();
+
+	return ret;
+}
+
+static void configure_mca(void)
+{
+	msr_t msr;
+	const unsigned int mcg_cap_msr = 0x179;
+	int i;
+	int num_banks;
+
+	msr = msr_read(mcg_cap_msr);
+	num_banks = msr.lo & 0xff;
+	msr.lo = 0;
+	msr.hi = 0;
+	/*
+	 * TODO(adurbin): This should only be done on a cold boot. Also, some
+	 * of these banks are core vs package scope. For now every CPU clears
+	 * every bank
+	 */
+	for (i = 0; i < num_banks; i++)
+		msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	msr_write(MSR_PIC_MSG_CONTROL, msr);
+}
+
+
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 31);	/* Timed MWAIT Enable */
+	msr.lo |= (1 << 30);	/* Package c-state Undemotion Enable */
+	msr.lo |= (1 << 29);	/* Package c-state Demotion Enable */
+	msr.lo |= (1 << 28);	/* C1 Auto Undemotion Enable */
+	msr.lo |= (1 << 27);	/* C3 Auto Undemotion Enable */
+	msr.lo |= (1 << 26);	/* C1 Auto Demotion Enable */
+	msr.lo |= (1 << 25);	/* C3 Auto Demotion Enable */
+	msr.lo &= ~(1 << 10);	/* Disable IO MWAIT redirection */
+	/* The deepest package c-state defaults to factory-configured value */
+	msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = msr_read(MSR_MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	/* Enable P-state HW_ALL coordination */
+	msr_write(MSR_MISC_PWR_MGMT, msr);
+
+	msr = msr_read(MSR_POWER_CTL);
+	msr.lo |= (1 << 18);	/* Enable Energy Perf Bias MSR 0x1b0 */
+	msr.lo |= (1 << 1);	/* C1E Enable */
+	msr.lo |= (1 << 0);	/* Bi-directional PROCHOT# */
+	msr_write(MSR_POWER_CTL, msr);
+
+	/* C-state Interrupt Response Latency Control 0 - package C3 latency */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
+
+	/* C-state Interrupt Response Latency Control 1 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
+
+	/* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
+
+	/* C-state Interrupt Response Latency Control 3 - package C8 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
+
+	/* C-state Interrupt Response Latency Control 4 - package C9 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
+
+	/* C-state Interrupt Response Latency Control 5 - package C10 */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
+	msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = msr_read(MSR_IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3);	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	msr_write(MSR_IA32_MISC_ENABLE, msr);
+
+	/* Disable thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	msr_write(MSR_IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void configure_thermal_target(struct udevice *dev)
+{
+	int tcc_offset;
+	msr_t msr;
+
+	tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+				    "intel,tcc-offset", 0);
+
+	/* Set TCC activaiton offset if supported */
+	msr = msr_read(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && tcc_offset) {
+		msr = msr_read(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+		msr.lo |= (tcc_offset & 0xf) << 24;
+		msr_write(MSR_TEMPERATURE_TARGET, msr);
+	}
+}
+
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+	int ecx;
+
+	/* Determine if energy efficient policy is supported */
+	ecx = cpuid_ecx(0x6);
+	if (!(ecx & (1 << 3)))
+		return;
+
+	/* Energy Policy is bits 3:0 */
+	msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	debug("cpu: energy policy set to %u\n", policy);
+}
+
+/* All CPUs including BSP will run the following function */
+static void cpu_core_init(struct udevice *dev)
+{
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target(dev);
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Enable Turbo */
+	turbo_enable();
+}
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void cpu_set_power_limits(int power_limit_1_time)
+{
+	msr_t msr;
+	msr_t limit;
+	unsigned power_unit;
+	unsigned tdp, min_power, max_power, max_time;
+	u8 power_limit_1_val;
+
+	msr = msr_read(MSR_PLATFORM_INFO);
+	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+		power_limit_1_time = 28;
+
+	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+		return;
+
+	/* Get units */
+	msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+	/* Get power defaults for this SKU */
+	msr = msr_read(MSR_PKG_POWER_SKU);
+	tdp = msr.lo & 0x7fff;
+	min_power = (msr.lo >> 16) & 0x7fff;
+	max_power = msr.hi & 0x7fff;
+	max_time = (msr.hi >> 16) & 0x7f;
+
+	debug("CPU TDP: %u Watts\n", tdp / power_unit);
+
+	if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+		power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+	if (min_power > 0 && tdp < min_power)
+		tdp = min_power;
+
+	if (max_power > 0 && tdp > max_power)
+		tdp = max_power;
+
+	power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+	/* Set long term power limit to TDP */
+	limit.lo = 0;
+	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	limit.lo |= PKG_POWER_LIMIT_EN;
+	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+		PKG_POWER_LIMIT_TIME_SHIFT;
+
+	/* Set short term power limit to 1.25 * TDP */
+	limit.hi = 0;
+	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	limit.hi |= PKG_POWER_LIMIT_EN;
+	/* Power limit 2 time is only programmable on server SKU */
+
+	msr_write(MSR_PKG_POWER_LIMIT, limit);
+
+	/* Set power limit values in MCHBAR as well */
+	writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
+	writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
+
+	/* Set DDR RAPL power limit by copying from MMIO to MSR */
+	msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
+	msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
+	msr_write(MSR_DDR_RAPL_LIMIT, msr);
+
+	/* Use nominal TDP values for CPUs with configurable TDP */
+	if (cpu_config_tdp_levels()) {
+		msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+		limit.hi = 0;
+		limit.lo = msr.lo & 0xff;
+		msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
+	}
+}
+
+static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
+{
+	msr_t msr;
+
+	msr = msr_read(IA32_PERF_CTL);
+	info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
+	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+		1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+
+	return 0;
+}
+
+static int broadwell_get_count(struct udevice *dev)
+{
+	return 4;
+}
+
+static int cpu_x86_broadwell_probe(struct udevice *dev)
+{
+	if (dev->seq == 0) {
+		cpu_core_init(dev);
+		return broadwell_init(dev);
+	}
+
+	return 0;
+}
+
+static const struct cpu_ops cpu_x86_broadwell_ops = {
+	.get_desc	= cpu_x86_get_desc,
+	.get_info	= broadwell_get_info,
+	.get_count	= broadwell_get_count,
+};
+
+static const struct udevice_id cpu_x86_broadwell_ids[] = {
+	{ .compatible = "intel,core-i3-gen5" },
+	{ }
+};
+
+U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
+	.name		= "cpu_x86_broadwell",
+	.id		= UCLASS_CPU,
+	.of_match	= cpu_x86_broadwell_ids,
+	.bind		= cpu_x86_bind,
+	.probe		= cpu_x86_broadwell_probe,
+	.ops		= &cpu_x86_broadwell_ops,
+	.priv_auto_alloc_size	= sizeof(struct cpu_broadwell_priv),
+};
diff --git a/arch/x86/include/asm/arch-broadwell/cpu.h b/arch/x86/include/asm/arch-broadwell/cpu.h
new file mode 100644
index 0000000..eb2046b
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __asm_arch_cpu_h
+#define __asm_arch_cpu_h
+
+/* CPU types */
+#define HASWELL_FAMILY_ULT	0x40650
+#define BROADWELL_FAMILY_ULT	0x306d0
+
+/* Supported CPUIDs */
+#define CPUID_HASWELL_A0	0x306c1
+#define CPUID_HASWELL_B0	0x306c2
+#define CPUID_HASWELL_C0	0x306c3
+#define CPUID_HASWELL_ULT_B0	0x40650
+#define CPUID_HASWELL_ULT	0x40651
+#define CPUID_HASWELL_HALO	0x40661
+#define CPUID_BROADWELL_C0	0x306d2
+#define CPUID_BROADWELL_D0	0x306d3
+#define CPUID_BROADWELL_E0	0x306d4
+
+/* Broadwell bus clock is fixed at 100MHz */
+#define BROADWELL_BCLK		100
+
+#define BROADWELL_FAMILY_ULT	0x306d0
+
+#define CORE_THREAD_COUNT_MSR		0x35
+
+#define MSR_VR_CURRENT_CONFIG		0x601
+#define MSR_VR_MISC_CONFIG		0x603
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_DDR_RAPL_LIMIT		0x618
+#define MSR_VR_MISC_CONFIG2		0x636
+
+/* Latency times in units of 1024ns. */
+#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
+#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
+#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
+#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
+#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
+#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+
+void cpu_set_power_limits(int power_limit_1_time);
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/iomap.h b/arch/x86/include/asm/arch-broadwell/iomap.h
new file mode 100644
index 0000000..431bc23
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/iomap.h
@@ -0,0 +1,53 @@
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/iomap.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __asm_arch_iomap_h
+#define __asm_arch_iomap_h
+
+#define MCFG_BASE_ADDRESS	0xf0000000
+#define MCFG_BASE_SIZE		0x4000000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_BASE_SIZE		0x8000
+
+#define DMI_BASE_ADDRESS	0xfed18000
+#define DMI_BASE_SIZE		0x1000
+
+#define EP_BASE_ADDRESS		0xfed19000
+#define EP_BASE_SIZE		0x1000
+
+#define EDRAM_BASE_ADDRESS	0xfed80000
+#define EDRAM_BASE_SIZE		0x4000
+
+#define GDXC_BASE_ADDRESS	0xfed84000
+#define GDXC_BASE_SIZE		0x1000
+
+#define RCBA_BASE_ADDRESS	0xfed1c000
+#define RCBA_BASE_SIZE		0x4000
+
+#define HPET_BASE_ADDRESS	0xfed00000
+
+#define ACPI_BASE_ADDRESS	0x1000
+#define ACPI_BASE_SIZE		0x100
+
+#define GPIO_BASE_ADDRESS	0x1400
+#define GPIO_BASE_SIZE		0x400
+
+#define SMBUS_BASE_ADDRESS	0x0400
+#define SMBUS_BASE_SIZE		0x10
+
+/* Temporary addresses used before relocation */
+#define EARLY_GTT_BAR		0xe0000000
+#define EARLY_XHCI_BAR		0xd7000000
+#define EARLY_EHCI_BAR		0xd8000000
+#define EARLY_UART_BAR		0x3f8
+#define EARLY_TEMP_MMIO		0xfed08000
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/me.h b/arch/x86/include/asm/arch-broadwell/me.h
new file mode 100644
index 0000000..a66a8bb
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/me.h
@@ -0,0 +1,200 @@
+/*
+ * From coreboot soc/intel/broadwell/include/soc/me.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _asm_arch_me_h
+#define _asm_arch_me_h
+
+#include <asm/me_common.h>
+
+#define  ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
+
+#define ME_HSIO_MESSAGE		(7 << 28)
+#define ME_HSIO_CMD_GETHSIOVER	1
+#define ME_HSIO_CMD_CLOSE	0
+
+/*
+ * Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
+ * to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
+ */
+#define PCI_ME_HFS2		0x48
+/* Infrastructure Progress Values */
+#define  ME_HFS2_PHASE_ROM		0
+#define  ME_HFS2_PHASE_BUP		1
+#define  ME_HFS2_PHASE_UKERNEL		2
+#define  ME_HFS2_PHASE_POLICY		3
+#define  ME_HFS2_PHASE_MODULE_LOAD	4
+#define  ME_HFS2_PHASE_UNKNOWN		5
+#define  ME_HFS2_PHASE_HOST_COMM	6
+/* Current State - Based on Infra Progress values. */
+/*       ROM State */
+#define  ME_HFS2_STATE_ROM_BEGIN 0
+#define  ME_HFS2_STATE_ROM_DISABLE 6
+/*       BUP State */
+#define  ME_HFS2_STATE_BUP_INIT 0
+#define  ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
+#define  ME_HFS2_STATE_BUP_FLOW_DET 4
+#define  ME_HFS2_STATE_BUP_VSCC_ERR 8
+#define  ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
+#define  ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
+#define  ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
+#define  ME_HFS2_STATE_BUP_M3 0x11
+#define  ME_HFS2_STATE_BUP_M0 0x12
+#define  ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
+#define  ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
+#define  ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
+#define  ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
+#define  ME_HFS2_STATE_BUP_T32_MISSING 0x1c
+#define  ME_HFS2_STATE_BUP_WAIT_DID 0x1f
+#define  ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
+#define  ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
+#define  ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
+#define  ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
+#define  ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
+#define  ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
+#define  ME_HFS2_STATE_BUP_M0_CLK 0x26
+#define  ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
+#define  ME_HFS2_STATE_BUP_TEMP_DIS 0x28
+#define  ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
+/*       Policy Module State */
+#define  ME_HFS2_STATE_POLICY_ENTRY 0
+#define  ME_HFS2_STATE_POLICY_RCVD_S3 3
+#define  ME_HFS2_STATE_POLICY_RCVD_S4 4
+#define  ME_HFS2_STATE_POLICY_RCVD_S5 5
+#define  ME_HFS2_STATE_POLICY_RCVD_UPD 6
+#define  ME_HFS2_STATE_POLICY_RCVD_PCR 7
+#define  ME_HFS2_STATE_POLICY_RCVD_NPCR 8
+#define  ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
+#define  ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
+#define  ME_HFS2_STATE_POLICY_RCVD_DID 0xb
+#define  ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
+#define  ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
+#define  ME_HFS2_STATE_POLICY_FPB_ERR 0xe
+#define  ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
+#define  ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
+/* Current PM Event Values */
+#define  ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
+#define  ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
+#define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
+#define  ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
+#define  ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
+#define  ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
+#define  ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
+#define  ME_HFS2_PMEVENT_S0MO_SXM3 7
+#define  ME_HFS2_PMEVENT_SXM3_S0M0 8
+#define  ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
+#define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
+#define  ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
+#define  ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
+
+struct me_hfs2 {
+	u32 bist_in_progress:1;
+	u32 reserved1:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_reset_request:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved2:4;
+	u32 mbp_cleared:1;
+	u32 reserved3:2;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HFS5		0x68
+
+#define PCI_ME_H_GS2		0x70
+#define   PCI_ME_MBP_GIVE_UP	0x01
+
+/* ICC Messages */
+#define ICC_SET_CLOCK_ENABLES		0x3
+#define ICC_API_VERSION_LYNXPOINT	0x00030000
+
+struct icc_header {
+	u32 api_version;
+	u32 icc_command;
+	u32 icc_status;
+	u32 length;
+	u32 reserved;
+} __packed;
+
+struct icc_clock_enables_msg {
+	u32 clock_enables;
+	u32 clock_mask;
+	u32 no_response:1;
+	u32 reserved:31;
+} __packed;
+
+/*
+ * ME to BIOS Payload Datastructures and definitions. The ordering of the
+ * structures follows the ordering in the ME9 BWG.
+ */
+
+#define MBP_APPID_KERNEL 1
+#define MBP_APPID_INTEL_AT 3
+#define MBP_APPID_HWA 4
+#define MBP_APPID_ICC 5
+#define MBP_APPID_NFC 6
+/* Kernel items: */
+#define MBP_KERNEL_FW_VER_ITEM 1
+#define MBP_KERNEL_FW_CAP_ITEM 2
+#define MBP_KERNEL_ROM_BIST_ITEM 3
+#define MBP_KERNEL_PLAT_KEY_ITEM 4
+#define MBP_KERNEL_FW_TYPE_ITEM 5
+#define MBP_KERNEL_MFS_FAILURE_ITEM 6
+#define MBP_KERNEL_PLAT_TIME_ITEM 7
+/* Intel AT items: */
+#define MBP_INTEL_AT_STATE_ITEM 1
+/* ICC Items: */
+#define MBP_ICC_PROFILE_ITEM 1
+/* HWA Items: */
+#define MBP_HWA_REQUEST_ITEM 1
+/* NFC Items: */
+#define MBP_NFC_SUPPORT_DATA_ITEM 1
+
+#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
+#define MBP_IDENT(appid, item) \
+	MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
+
+struct mbp_fw_version_name {
+	u32	major_version:16;
+	u32	minor_version:16;
+	u32	hotfix_version:16;
+	u32	build_version:16;
+} __packed;
+
+struct icc_address_mask {
+	u16 icc_start_address;
+	u16 mask;
+} __packed;
+
+struct mbp_icc_profile {
+	u8	num_icc_profiles;
+	u8	icc_profile_soft_strap;
+	u8	icc_profile_index;
+	u8	reserved;
+	u32	icc_reg_bundles;
+	struct icc_address_mask icc_address_mask[0];
+} __packed;
+
+struct me_bios_payload {
+	struct mbp_fw_version_name	*fw_version_name;
+	struct mbp_mefwcaps	*fw_capabilities;
+	struct mbp_rom_bist_data *rom_bist_data;
+	struct mbp_platform_key *platform_key;
+	struct mbp_plat_type	*fw_plat_type;
+	struct mbp_icc_profile	*icc_profile;
+	struct mbp_at_state	*at_state;
+	u32		*mfsintegrity;
+	struct mbp_plat_time	*plat_time;
+	struct mbp_nfc_data	*nfc_data;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/rcb.h b/arch/x86/include/asm/arch-broadwell/rcb.h
new file mode 100644
index 0000000..44fcddd
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/rcb.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __asm_arch_rcba_h
+#define __asm_arch_rcba_h
+
+#define PMSYNC_CONFIG	0x33c4	/* 32bit */
+#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+
+#define DEEP_S3_POL	0x3328	/* 32bit */
+#define  DEEP_S3_EN_AC		(1 << 0)
+#define  DEEP_S3_EN_DC		(1 << 1)
+#define DEEP_S5_POL	0x3330	/* 32bit */
+#define  DEEP_S5_EN_AC		(1 << 14)
+#define  DEEP_S5_EN_DC		(1 << 15)
+#define DEEP_SX_CONFIG	0x3334	/* 32bit */
+#define  DEEP_SX_WAKE_PIN_EN	(1 << 2)
+#define  DEEP_SX_ACPRESENT_PD	(1 << 1)
+#define  DEEP_SX_GP27_PIN_EN	(1 << 0)
+#define PMSYNC_CONFIG	0x33c4	/* 32bit */
+#define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+
+#define RC		0x3400	/* 32bit */
+#define HPTC		0x3404	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+#define BUC		0x3414	/* 32bit */
+#define PCH_DISABLE_GBE		(1 << 5)
+#define FD		0x3418	/* 32bit */
+#define FDSW		0x3420	/* 8bit */
+#define DISPBDF		0x3424  /* 16bit */
+#define FD2		0x3428	/* 32bit */
+#define CG		0x341c	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	(1 << 0)
+#define PCH_DISABLE_ADSPD	(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+#define PCH_DISABLE_XHCI	(1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
+#endif
diff --git a/arch/x86/include/asm/arch-broadwell/spi.h b/arch/x86/include/asm/arch-broadwell/spi.h
new file mode 100644
index 0000000..aeb4926
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/spi.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This file is from coreboot soc/intel/broadwell/include/soc/spi.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _BROADWELL_SPI_H_
+#define _BROADWELL_SPI_H_
+
+/*
+ * SPI Opcode Menu setup for SPIBAR lockdown
+ * should support most common flash chips.
+ */
+
+#define SPIBAR_OFFSET		0x3800
+#define SPI_REG(x)		(RCB_REG(SPIBAR_OFFSET + (x)))
+
+/* Reigsters within the SPIBAR */
+#define SPIBAR_SSFC		0x91
+#define SPIBAR_FDOC		0xb0
+#define SPIBAR_FDOD		0xb4
+
+#define SPIBAR_PREOP		0x94
+#define SPIBAR_OPTYPE		0x96
+#define SPIBAR_OPMENU_LOWER	0x98
+#define SPIBAR_OPMENU_UPPER	0x9c
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
+		    (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |	  \
+		    (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+#define SPIBAR_HSFS                 0x04   /* SPI hardware sequence status */
+#define  SPIBAR_HSFS_FLOCKDN        (1 << 15)/* Flash Configuration Lock-Down */
+#define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
+#define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
+#define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
+#define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
+#define SPIBAR_HSFC                 0x06   /* SPI hardware sequence control */
+#define  SPIBAR_HSFC_BYTE_COUNT(c)  (((c - 1) & 0x3f) << 8)
+#define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
+#define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
+#define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
+#define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
+#define SPIBAR_FADDR                0x08   /* SPI flash address */
+#define SPIBAR_FDATA(n)             (0x10 + (4 * n)) /* SPI flash data */
+#define SPIBAR_SSFS                 0x90
+#define  SPIBAR_SSFS_ERROR          (1 << 3)
+#define  SPIBAR_SSFS_DONE           (1 << 2)
+#define SPIBAR_SSFC                 0x91
+#define  SPIBAR_SSFC_DATA           (1 << 14)
+#define  SPIBAR_SSFC_GO             (1 << 1)
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 34/51] x86: broadwell: Add a PCH driver

[Simon Glass]

Add a driver for the broadwell low-power platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use setio_32() instead of setio_le32(), etc.
- Use capitals for header guard

 arch/x86/cpu/broadwell/Makefile           |   2 +
 arch/x86/cpu/broadwell/iobp.c             | 144 ++++++++
 arch/x86/cpu/broadwell/pch.c              | 540 ++++++++++++++++++++++++++++++
 arch/x86/include/asm/arch-broadwell/pch.h | 153 +++++++++
 4 files changed, 839 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/iobp.c
 create mode 100644 arch/x86/cpu/broadwell/pch.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index c7ef630..128829a 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -5,3 +5,5 @@
 #
 
 obj-y += cpu.o
+obj-y += iobp.o
+obj-y += pch.o
diff --git a/arch/x86/cpu/broadwell/iobp.c b/arch/x86/cpu/broadwell/iobp.c
new file mode 100644
index 0000000..5eed849
--- /dev/null
+++ b/arch/x86/cpu/broadwell/iobp.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * Modified from coreboot
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/arch/pch.h>
+
+#define IOBP_RETRY 1000
+
+/* IO Buffer Programming */
+#define IOBPIRI		0x2330
+#define IOBPD		0x2334
+#define IOBPS		0x2338
+#define  IOBPS_READY	0x0001
+#define  IOBPS_TX_MASK	0x0006
+#define  IOBPS_MASK     0xff00
+#define  IOBPS_READ     0x0600
+#define  IOBPS_WRITE	0x0700
+#define IOBPU		0x233a
+#define  IOBPU_MAGIC	0xf000
+#define  IOBP_PCICFG_READ	0x0400
+#define  IOBP_PCICFG_WRITE	0x0500
+
+static inline int iobp_poll(void)
+{
+	unsigned try;
+
+	for (try = IOBP_RETRY; try > 0; try--) {
+		u16 status = readw(RCB_REG(IOBPS));
+		if ((status & IOBPS_READY) == 0)
+			return 1;
+		udelay(10);
+	}
+
+	printf("IOBP: timeout waiting for transaction to complete\n");
+	return 0;
+}
+
+int pch_iobp_trans_start(u32 address, int op)
+{
+	if (!iobp_poll())
+		return 0;
+
+	/* Set the address */
+	writel(address, RCB_REG(IOBPIRI));
+
+	/* READ OPCODE */
+	clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op);
+
+	return 1;
+}
+
+int pch_iobp_trans_finish(void)
+{
+	u16 status;
+
+	/* Undocumented magic */
+	writew(IOBPU_MAGIC, RCB_REG(IOBPU));
+
+	/* Set ready bit */
+	setbits_le16(RCB_REG(IOBPS), IOBPS_READY);
+
+	if (!iobp_poll())
+		return 1;
+
+	/* Check for successful transaction */
+	status = readw(RCB_REG(IOBPS));
+	if (status & IOBPS_TX_MASK)
+		return 1;
+
+	return 0;
+}
+
+u32 pch_iobp_read(u32 address)
+{
+	if (!pch_iobp_trans_start(address, IOBPS_READ))
+		return 0;
+	if (pch_iobp_trans_finish()) {
+		printf("IOBP: read 0x%08x failed\n", address);
+		return 0;
+	}
+
+	/* Read IOBP data */
+	return readl(RCB_REG(IOBPD));
+}
+
+int pch_iobp_write(u32 address, u32 data)
+{
+	if (!pch_iobp_trans_start(address, IOBPS_WRITE))
+		return -EIO;
+
+	writel(data, RCB_REG(IOBPD));
+
+	if (pch_iobp_trans_finish()) {
+		printf("IOBP: write 0x%08x failed\n", address);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data = pch_iobp_read(address);
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	return pch_iobp_write(address, data);
+}
+
+int pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
+{
+	if (!data || !resp)
+		return 0;
+
+	*resp = -1;
+	if (!iobp_poll())
+		return -EIO;
+
+	writel(addr, RCB_REG(IOBPIRI));
+	clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code);
+	writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU));
+
+	writel(*data, RCB_REG(IOBPD));
+	/* Set IOBPS[0] to trigger IOBP transaction*/
+	setbits_le16(RCB_REG(IOBPS), 1);
+
+	if (!iobp_poll())
+		return -EIO;
+
+	*resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1;
+	*data = readl(RCB_REG(IOBPD));
+
+	return 0;
+}
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
new file mode 100644
index 0000000..f0798a7
--- /dev/null
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -0,0 +1,540 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/i8259.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/ioapic.h>
+#include <asm/lpc_common.h>
+#include <asm/pch_common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pm.h>
+#include <asm/arch/rcb.h>
+#include <asm/arch/spi.h>
+
+#define BIOS_CTRL	0xdc
+
+bool cpu_is_ult(void)
+{
+	u32 fm = cpu_get_family_model();
+
+	return fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT;
+}
+
+static int broadwell_pch_early_init(struct udevice *dev)
+{
+	struct gpio_desc desc;
+	struct udevice *bus;
+	pci_dev_t bdf;
+	int ret;
+
+	dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1);
+
+	dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1);
+	dm_pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
+	dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
+	dm_pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
+
+	/* Enable IOAPIC */
+	writew(0x1000, RCB_REG(OIC));
+	/* Read back for posted write */
+	readw(RCB_REG(OIC));
+
+	/* Set HPET address and enable it */
+	clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);
+	/* Read back for posted write */
+	readl(RCB_REG(HPTC));
+	/* Enable HPET to start counter */
+	setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0);
+
+	setbits_le32(RCB_REG(GCS), 1 << 5);
+
+	/*
+	 * Enable PP3300_AUTOBAHN_EN after initial GPIO setup
+	 * to prevent possible brownout. This will cause the GPIOs to be set
+	 * up if it has not been done already.
+	 */
+	ret = gpio_request_by_name(dev, "power-enable-gpio", 0, &desc,
+				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	if (ret)
+		return ret;
+
+	/* 8.14 Additional PCI Express Programming Steps, step #1 */
+	bdf = PCI_BDF(0, 0x1c, 0);
+	bus = pci_get_controller(dev);
+	pci_bus_clrset_config32(bus, bdf, 0xf4, 0x60, 0);
+	pci_bus_clrset_config32(bus, bdf, 0xf4, 0x80, 0x80);
+	pci_bus_clrset_config32(bus, bdf, 0xe2, 0x30, 0x30);
+
+	return 0;
+}
+
+static void pch_misc_init(struct udevice *dev)
+{
+	/* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */
+	dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10,
+			      1 << 3 | 1 << 11 | 1 << 12);
+	/* Prepare sleep mode */
+	clrsetio_32(ACPI_BASE_ADDRESS + PM1_CNT, SLP_TYP, SCI_EN);
+
+	/* Setup NMI on errors, disable SERR */
+	clrsetio_8(0x61, 0xf0, 1 << 2);
+	/* Disable NMI sources */
+	setio_8(0x70, 1 << 7);
+	/* Indicate DRAM init done for MRC */
+	dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7);
+
+	/* Clear status bits to prevent unexpected wake */
+	setbits_le32(RCB_REG(0x3310), 0x0000002f);
+	clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0);
+	/* Enable PCIe Relaxed Order */
+	setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7);
+	setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14);
+	/* Setup SERIRQ, enable continuous mode */
+	dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6);
+};
+
+static void pch_enable_ioapic(void)
+{
+	u32 reg32;
+
+	io_apic_set_id(0x02);
+
+	/* affirm full set of redirection table entries ("write once") */
+	reg32 = io_apic_read(0x01);
+
+	/* PCH-LP has 39 redirection entries */
+	reg32 &= ~0x00ff0000;
+	reg32 |= 0x00270000;
+
+	io_apic_write(0x01, reg32);
+
+	/*
+	 * Select Boot Configuration register (0x03) and
+	 * use Processor System Bus (0x01) to deliver interrupts.
+	 */
+	io_apic_write(0x03, 0x01);
+}
+
+/* Enable all requested GPE */
+void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
+{
+	outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0));
+	outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
+	outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64));
+	outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
+}
+
+/*
+ * Enable GPIO SMI events - it would be good to put this in the GPIO driver
+ * but it would need a new driver operation.
+ */
+int enable_alt_smi(struct udevice *pch, u32 mask)
+{
+	struct pch_lp_gpio_regs *regs;
+	u32 gpiobase;
+	int ret;
+
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
+		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
+		      gpiobase);
+		return -EINVAL;
+	}
+
+	regs = (struct pch_lp_gpio_regs *)gpiobase;
+	setio_32(regs->alt_gpi_smi_en, mask);
+
+	return 0;
+}
+
+static int pch_power_options(struct udevice *dev)
+{
+	int pwr_on_after_power_fail = MAINBOARD_POWER_OFF;
+	const char *state;
+	u32 enable[4];
+	u16 reg16;
+	int ret;
+
+	dm_pci_read_config16(dev, GEN_PMCON_3, &reg16);
+	reg16 &= 0xfffe;
+	switch (pwr_on_after_power_fail) {
+	case MAINBOARD_POWER_OFF:
+		reg16 |= 1;
+		state = "off";
+		break;
+	case MAINBOARD_POWER_ON:
+		reg16 &= ~1;
+		state = "on";
+		break;
+	case MAINBOARD_POWER_KEEP:
+		reg16 &= ~1;
+		state = "state keep";
+		break;
+	default:
+		state = "undefined";
+	}
+	dm_pci_write_config16(dev, GEN_PMCON_3, reg16);
+	debug("Set power %s after power failure.\n", state);
+
+	/* GPE setup based on device tree configuration */
+	ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+				   "intel,gpe0-en", enable, ARRAY_SIZE(enable));
+	if (ret)
+		return -EINVAL;
+	enable_all_gpe(enable[0], enable[1], enable[2], enable[3]);
+
+	/* SMI setup based on device tree configuration */
+	enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					   "intel,alt-gp-smi-enable", 0));
+
+	return 0;
+}
+
+/* Magic register settings for power management */
+static void pch_pm_init_magic(struct udevice *dev)
+{
+	dm_pci_write_config8(dev, 0xa9, 0x46);
+	clrbits_le32(RCB_REG(0x232c), 1),
+	setbits_le32(RCB_REG(0x1100), 0x0000c13f);
+	clrsetbits_le32(RCB_REG(0x2320), 0x60, 0x10);
+	writel(0x00012fff, RCB_REG(0x3314));
+	clrsetbits_le32(RCB_REG(0x3318), 0x000f0330, 0x0dcf0400);
+	writel(0x04000000, RCB_REG(0x3324));
+	writel(0x00041400, RCB_REG(0x3368));
+	writel(0x3f8ddbff, RCB_REG(0x3388));
+	writel(0x00007001, RCB_REG(0x33ac));
+	writel(0x00181900, RCB_REG(0x33b0));
+	writel(0x00060A00, RCB_REG(0x33c0));
+	writel(0x06200840, RCB_REG(0x33d0));
+	writel(0x01010101, RCB_REG(0x3a28));
+	writel(0x040c0404, RCB_REG(0x3a2c));
+	writel(0x9000000a, RCB_REG(0x3a9c));
+	writel(0x03808033, RCB_REG(0x2b1c));
+	writel(0x80000009, RCB_REG(0x2b34));
+	writel(0x022ddfff, RCB_REG(0x3348));
+	writel(0x00000001, RCB_REG(0x334c));
+	writel(0x0001c000, RCB_REG(0x3358));
+	writel(0x3f8ddbff, RCB_REG(0x3380));
+	writel(0x0001c7e1, RCB_REG(0x3384));
+	writel(0x0001c7e1, RCB_REG(0x338c));
+	writel(0x0001c000, RCB_REG(0x3398));
+	writel(0x00181900, RCB_REG(0x33a8));
+	writel(0x00080000, RCB_REG(0x33dc));
+	writel(0x00000001, RCB_REG(0x33e0));
+	writel(0x0000040c, RCB_REG(0x3a20));
+	writel(0x01010101, RCB_REG(0x3a24));
+	writel(0x01010101, RCB_REG(0x3a30));
+	dm_pci_clrset_config32(dev, 0xac, 0x00200000, 0);
+	setbits_le32(RCB_REG(0x0410), 0x00000003);
+	setbits_le32(RCB_REG(0x2618), 0x08000000);
+	setbits_le32(RCB_REG(0x2300), 0x00000002);
+	setbits_le32(RCB_REG(0x2600), 0x00000008);
+	writel(0x00007001, RCB_REG(0x33b4));
+	writel(0x022ddfff, RCB_REG(0x3350));
+	writel(0x00000001, RCB_REG(0x3354));
+	/* Power Optimizer */
+	setbits_le32(RCB_REG(0x33d4), 0x08000000);
+	/*
+	 * This stops the LCD from turning on:
+	 * setbits_le32(RCB_REG(0x33c8), 0x08000080);
+	 */
+	writel(0x0000883c, RCB_REG(0x2b10));
+	writel(0x1e0a4616, RCB_REG(0x2b14));
+	writel(0x40000005, RCB_REG(0x2b24));
+	writel(0x0005db01, RCB_REG(0x2b20));
+	writel(0x05145005, RCB_REG(0x3a80));
+	writel(0x00001005, RCB_REG(0x3a84));
+	setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1);
+	setbits_le32(RCB_REG(0x33c8), 0x00008000);
+};
+
+static int pch_type(struct udevice *dev)
+{
+	u16 type;
+
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &type);
+
+	return type;
+}
+
+/* Return 1 if PCH type is WildcatPoint */
+static int pch_is_wpt(struct udevice *dev)
+{
+	return ((pch_type(dev) & 0xfff0) == 0x9cc0) ? 1 : 0;
+}
+
+/* Return 1 if PCH type is WildcatPoint ULX */
+static int pch_is_wpt_ulx(struct udevice *dev)
+{
+	u16 lpcid = pch_type(dev);
+
+	switch (lpcid) {
+	case PCH_WPT_BDW_Y_SAMPLE:
+	case PCH_WPT_BDW_Y_PREMIUM:
+	case PCH_WPT_BDW_Y_BASE:
+		return 1;
+	}
+
+	return 0;
+}
+
+static u32 pch_read_soft_strap(int id)
+{
+	clrbits_le32(SPI_REG(SPIBAR_FDOC), 0x00007ffc);
+	setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4);
+
+	return readl(SPI_REG(SPIBAR_FDOD));
+}
+
+static void pch_enable_mphy(struct udevice *dev)
+{
+	u32 data_and = 0xffffffff;
+	u32 data_or = (1 << 14) | (1 << 13) | (1 << 12);
+
+	data_or |= (1 << 0);
+	if (pch_is_wpt(dev)) {
+		data_and &= ~((1 << 7) | (1 << 6) | (1 << 3));
+		data_or |= (1 << 5) | (1 << 4);
+
+		if (pch_is_wpt_ulx(dev)) {
+			/* Check if SATA and USB3 MPHY are enabled */
+			u32 strap19 = pch_read_soft_strap(19);
+			strap19 &= ((1 << 31) | (1 << 30));
+			strap19 >>= 30;
+			if (strap19 == 3) {
+				data_or |= (1 << 3);
+				debug("Enable ULX MPHY PG control in single domain\n");
+			} else if (strap19 == 0) {
+				debug("Enable ULX MPHY PG control in split domains\n");
+			} else {
+				debug("Invalid PCH Soft Strap 19 configuration\n");
+			}
+		} else {
+			data_or |= (1 << 3);
+		}
+	}
+
+	pch_iobp_update(0xCF000000, data_and, data_or);
+}
+
+static void pch_init_deep_sx(bool deep_sx_enable_ac, bool deep_sx_enable_dc)
+{
+	if (deep_sx_enable_ac) {
+		setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC);
+		setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC);
+	}
+
+	if (deep_sx_enable_dc) {
+		setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC);
+		setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC);
+	}
+
+	if (deep_sx_enable_ac || deep_sx_enable_dc) {
+		setbits_le32(RCB_REG(DEEP_SX_CONFIG),
+			     DEEP_SX_WAKE_PIN_EN | DEEP_SX_GP27_PIN_EN);
+	}
+}
+
+/* Power Management init */
+static void pch_pm_init(struct udevice *dev)
+{
+	debug("PCH PM init\n");
+
+	pch_init_deep_sx(false, false);
+	pch_enable_mphy(dev);
+	pch_pm_init_magic(dev);
+
+	if (pch_is_wpt(dev)) {
+		setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1);
+		setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13);
+		writel(0x16bf0002, RCB_REG(0x33e4));
+		setbits_le32(RCB_REG(0x33e4), 0x1);
+	}
+
+	pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
+
+	/* Set RCBA 0x2b1c[29]=1 if DSP disabled */
+	if (readl(RCB_REG(FD)) & PCH_DISABLE_ADSPD)
+		setbits_le32(RCB_REG(0x2b1c), 1 << 29);
+}
+
+static void pch_cg_init(struct udevice *dev)
+{
+	struct udevice *bus = pci_get_controller(dev);
+	u32 reg32;
+	u16 reg16;
+	ulong val;
+
+	/* DMI */
+	setbits_le32(RCB_REG(0x2234), 0xf);
+
+	dm_pci_read_config16(dev, GEN_PMCON_1, &reg16);
+	reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
+	if (pch_is_wpt(dev))
+		reg16 &= ~(1 << 11);
+	else
+		reg16 |= 1 << 11;
+	reg16 |= 1 << 5 | 1 << 6 | 1 << 7 | 1 << 12;
+	reg16 |= 1 << 2; /* PCI CLKRUN# Enable */
+	dm_pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	/*
+	 * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1
+	 * RCBA + 0x2614[23:16] = 0x20
+	 * RCBA + 0x2614[30:28] = 0x0
+	 * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b)
+	 */
+	clrsetbits_le32(RCB_REG(0x2614), 0x64ff0000, 0x0a206500);
+
+	/* Check for 0:2.0 at 0x08 >= 0x0b */
+	pci_bus_read_config(bus, PCI_BDF(0, 0x2, 0), 0x8, &val, PCI_SIZE_8);
+	if (pch_is_wpt(dev) || val >= 0x0b)
+		setbits_le32(RCB_REG(0x2614), 1 << 26);
+
+	setbits_le32(RCB_REG(0x900), 0x0000031f);
+
+	reg32 = readl(RCB_REG(CG));
+	if (readl(RCB_REG(0x3454)) & (1 << 4))
+		reg32 &= ~(1 << 29); /* LPC Dynamic */
+	else
+		reg32 |= (1 << 29); /* LPC Dynamic */
+	reg32 |= 1 << 31; /* LP LPC */
+	reg32 |= 1 << 30; /* LP BLA */
+	if (readl(RCB_REG(0x3454)) & (1 << 4))
+		reg32 &= ~(1 << 29);
+	else
+		reg32 |= 1 << 29;
+	reg32 |= 1 << 28; /* GPIO Dynamic */
+	reg32 |= 1 << 27; /* HPET Dynamic */
+	reg32 |= 1 << 26; /* Generic Platform Event Clock */
+	if (readl(RCB_REG(BUC)) & PCH_DISABLE_GBE)
+		reg32 |= 1 << 23; /* GbE Static */
+	if (readl(RCB_REG(FD)) & PCH_DISABLE_HD_AUDIO)
+		reg32 |= 1 << 21; /* HDA Static */
+	reg32 |= 1 << 22; /* HDA Dynamic */
+	writel(reg32, RCB_REG(CG));
+
+	/* PCH-LP LPC */
+	if (pch_is_wpt(dev))
+		clrsetbits_le32(RCB_REG(0x3434), 0x1f, 0x17);
+	else
+		setbits_le32(RCB_REG(0x3434), 0x7);
+
+	/* SPI */
+	setbits_le32(RCB_REG(0x38c0), 0x3c07);
+
+	pch_iobp_update(0xCE00C000, ~1UL, 0x00000000);
+}
+
+static void systemagent_init(void)
+{
+	/* Enable Power Aware Interrupt Routing */
+	clrsetbits_8(MCHBAR_REG(MCH_PAIR), 0x7, 0x4); /* Fixed Priority */
+
+	/*
+	 * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
+	 * that BIOS has initialized memory and power management
+	 */
+	setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
+	debug("Set BIOS_RESET_CPL\n");
+
+	/* Configure turbo power limits 1ms after reset complete bit */
+	mdelay(1);
+
+	cpu_set_power_limits(28);
+}
+
+static int broadwell_pch_init(struct udevice *dev)
+{
+	int ret;
+
+	/* Enable upper 128 bytes of CMOS */
+	setbits_le32(RCB_REG(RC), 1 << 2);
+
+	/*
+	 * TODO: TCO timer halt - this hangs
+	 * setio_16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT);
+	 */
+
+	/* Disable unused device (always) */
+	setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
+
+	pch_misc_init(dev);
+
+	/* Interrupt configuration */
+	pch_enable_ioapic();
+
+	/* Initialize power management */
+	ret = pch_power_options(dev);
+	if (ret)
+		return ret;
+	pch_pm_init(dev);
+	pch_cg_init(dev);
+	systemagent_init();
+
+	return 0;
+}
+
+static int broadwell_pch_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		return broadwell_pch_early_init(dev);
+	else
+		return broadwell_pch_init(dev);
+}
+
+static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
+{
+	u32 rcba;
+
+	dm_pci_read_config32(dev, PCH_RCBA, &rcba);
+	/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
+	rcba = rcba & 0xffffc000;
+	*sbasep = rcba + 0x3800;
+
+	return 0;
+}
+
+static int broadwell_set_spi_protect(struct udevice *dev, bool protect)
+{
+	return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
+}
+
+static int broadwell_get_gpio_base(struct udevice *dev, u32 *gbasep)
+{
+	dm_pci_read_config32(dev, GPIO_BASE, gbasep);
+	*gbasep &= PCI_BASE_ADDRESS_IO_MASK;
+
+	return 0;
+}
+
+static const struct pch_ops broadwell_pch_ops = {
+	.get_spi_base	= broadwell_pch_get_spi_base,
+	.set_spi_protect = broadwell_set_spi_protect,
+	.get_gpio_base	= broadwell_get_gpio_base,
+};
+
+static const struct udevice_id broadwell_pch_ids[] = {
+	{ .compatible = "intel,broadwell-pch" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_pch) = {
+	.name		= "broadwell_pch",
+	.id		= UCLASS_PCH,
+	.of_match	= broadwell_pch_ids,
+	.probe		= broadwell_pch_probe,
+	.ops		= &broadwell_pch_ops,
+};
diff --git a/arch/x86/include/asm/arch-broadwell/pch.h b/arch/x86/include/asm/arch-broadwell/pch.h
new file mode 100644
index 0000000..3e346ad
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pch.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_PCH_H
+#define __ASM_ARCH_PCH_H
+
+/* CPU bus clock is fixed at 100MHz */
+#define CPU_BCLK		100
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+#define  ACPI_EN		(1 << 7)
+
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+#define  GPIO_EN		(1 << 4)
+
+#define PCIEXBAR	0x60
+
+#define  PCH_DEV_LPC		PCI_BDF(0, 0x1f, 0)
+
+/* RCB registers */
+#define OIC		0x31fe	/* 16bit */
+#define HPTC		0x3404	/* 32bit */
+#define FD		0x3418	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	(1 << 0)
+
+/* PM registers */
+#define TCO1_CNT		0x60
+#define  TCO_TMR_HLT		(1 << 11)
+
+
+/* Device 0:0.0 PCI configuration space */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define GGC		0x50	/* GMCH Graphics Control */
+#define DEVEN		0x54	/* Device Enable */
+#define  DEVEN_D7EN	(1 << 14)
+#define  DEVEN_D4EN	(1 << 7)
+#define  DEVEN_D3EN	(1 << 5)
+#define  DEVEN_D2EN	(1 << 4)
+#define  DEVEN_D1F0EN	(1 << 3)
+#define  DEVEN_D1F1EN	(1 << 2)
+#define  DEVEN_D1F2EN	(1 << 1)
+#define  DEVEN_D0EN	(1 << 0)
+#define DPR		0x5c
+#define  DPR_EPM	(1 << 2)
+#define  DPR_PRS	(1 << 1)
+#define  DPR_SIZE_MASK	0xff0
+
+#define MCHBAR_PEI_VERSION	0x5034
+#define BIOS_RESET_CPL		0x5da8
+#define EDRAMBAR		0x5408
+#define MCH_PAIR		0x5418
+#define GDXCBAR			0x5420
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+/* PCODE MMIO communications live in the MCHBAR. */
+#define BIOS_MAILBOX_INTERFACE			0x5da4
+#define  MAILBOX_RUN_BUSY			(1 << 31)
+#define  MAILBOX_BIOS_CMD_READ_PCS		1
+#define  MAILBOX_BIOS_CMD_WRITE_PCS		2
+#define  MAILBOX_BIOS_CMD_READ_CALIBRATION	0x509
+#define  MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL	0x909
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER	0xa
+#define  MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT	0xb
+#define  MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE	0x26
+#define  MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE	0x27
+/* Errors are returned back in bits 7:0. */
+#define  MAILBOX_BIOS_ERROR_NONE		0
+#define  MAILBOX_BIOS_ERROR_INVALID_COMMAND	1
+#define  MAILBOX_BIOS_ERROR_TIMEOUT		2
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_DATA	3
+#define  MAILBOX_BIOS_ERROR_RESERVED		4
+#define  MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID	5
+#define  MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED	6
+#define  MAILBOX_BIOS_ERROR_VR_ERROR		7
+/* Data is passed through bits 31:0 of the data register. */
+#define BIOS_MAILBOX_DATA			0x5da0
+
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0_SECRT88	0xea002688
+#define SATA_IOBP_SP1_SECRT88	0xea002488
+
+#define SATA_SECRT88_VADJ_MASK	0xff
+#define SATA_SECRT88_VADJ_SHIFT	16
+
+#define SATA_IOBP_SP0DTLE_DATA	0xea002550
+#define SATA_IOBP_SP0DTLE_EDGE	0xea002554
+#define SATA_IOBP_SP1DTLE_DATA	0xea002750
+#define SATA_IOBP_SP1DTLE_EDGE	0xea002754
+
+#define SATA_DTLE_MASK		0xF
+#define SATA_DTLE_DATA_SHIFT	24
+#define SATA_DTLE_EDGE_SHIFT	16
+
+/* Power Management */
+#define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
+#define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
+#define GEN_PMCON_LOCK		0xa6
+#define  SLP_STR_POL_LOCK	(1 << 2)
+#define  ACPI_BASE_LOCK		(1 << 1)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
+
+/* Broadwell PCH (Wildcat Point) */
+#define PCH_WPT_HSW_U_SAMPLE	0x9cc1
+#define PCH_WPT_BDW_U_SAMPLE	0x9cc2
+#define PCH_WPT_BDW_U_PREMIUM	0x9cc3
+#define PCH_WPT_BDW_U_BASE	0x9cc5
+#define PCH_WPT_BDW_Y_SAMPLE	0x9cc6
+#define PCH_WPT_BDW_Y_PREMIUM	0x9cc7
+#define PCH_WPT_BDW_Y_BASE	0x9cc9
+#define PCH_WPT_BDW_H		0x9ccb
+
+#define SA_IGD_OPROM_VENDEV	0x80860406
+
+/* Dynamically determine if the part is ULT */
+bool cpu_is_ult(void);
+
+u32 pch_iobp_read(u32 address);
+int pch_iobp_write(u32 address, u32 data);
+int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+int  pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 35/51] x86: broadwell: Add a pinctrl driver

[Simon Glass]

GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use capitals for header guard

 arch/x86/cpu/broadwell/Makefile                    |   1 +
 arch/x86/cpu/broadwell/pinctrl_broadwell.c         | 278 +++++++++++++++++++++
 arch/x86/include/asm/arch-broadwell/gpio.h         |  91 +++++++
 .../gpio/intel,x86-broadwell-pinctrl.txt           | 208 +++++++++++++++
 include/dt-bindings/gpio/x86-gpio.h                |  12 +
 5 files changed, 590 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h
 create mode 100644 doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 128829a..db60e30 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -7,3 +7,4 @@
 obj-y += cpu.o
 obj-y += iobp.o
 obj-y += pch.o
+obj-y += pinctrl_broadwell.o
diff --git a/arch/x86/cpu/broadwell/pinctrl_broadwell.c b/arch/x86/cpu/broadwell/pinctrl_broadwell.c
new file mode 100644
index 0000000..2a3fced
--- /dev/null
+++ b/arch/x86/cpu/broadwell/pinctrl_broadwell.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/gpio.h>
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	MAX_GPIOS	= 95,
+};
+
+#define PIRQ_SHIFT	16
+#define CONF_MASK	0xffff
+
+struct pin_info {
+	int node;
+	int phandle;
+	bool mode_gpio;
+	bool dir_input;
+	bool invert;
+	bool trigger_level;
+	bool output_high;
+	bool sense_disable;
+	bool owner_gpio;
+	bool route_smi;
+	bool irq_enable;
+	bool reset_rsmrst;
+	bool pirq_apic_route;
+};
+
+static int broadwell_pinctrl_read_configs(struct udevice *dev,
+					  struct pin_info *conf, int max_pins)
+{
+	const void *blob = gd->fdt_blob;
+	int count = 0;
+	int node;
+
+	debug("%s: starting\n", __func__);
+	for (node = fdt_first_subnode(blob, dev->of_offset);
+	     node > 0;
+	     node = fdt_next_subnode(blob, node)) {
+		int phandle = fdt_get_phandle(blob, node);
+
+		if (!phandle)
+			continue;
+		if (count == max_pins)
+			return -ENOSPC;
+
+		/* We've found a new configuration */
+		memset(conf, '\0', sizeof(*conf));
+		conf->node = node;
+		conf->phandle = phandle;
+		conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio");
+		if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT)
+			conf->dir_input = true;
+		conf->invert = fdtdec_get_bool(blob, node, "invert");
+		if (fdtdec_get_int(blob, node, "trigger", -1) == TRIGGER_LEVEL)
+			conf->trigger_level = true;
+		if (fdtdec_get_int(blob, node, "output-value", -1) == 1)
+			conf->output_high = true;
+		conf->sense_disable = fdtdec_get_bool(blob, node,
+						      "sense-disable");
+		if (fdtdec_get_int(blob, node, "owner", -1) == OWNER_GPIO)
+			conf->owner_gpio = true;
+		if (fdtdec_get_int(blob, node, "route", -1) == ROUTE_SMI)
+			conf->route_smi = true;
+		conf->irq_enable = fdtdec_get_bool(blob, node, "irq-enable");
+		conf->reset_rsmrst = fdtdec_get_bool(blob, node,
+						     "reset-rsmrst");
+		if (fdtdec_get_int(blob, node, "pirq-apic", -1) ==
+				PIRQ_APIC_ROUTE)
+			conf->pirq_apic_route = true;
+		debug("config: phandle=%d\n", phandle);
+		count++;
+		conf++;
+	}
+	debug("%s: Found %d configurations\n", __func__, count);
+
+	return count;
+}
+
+static int broadwell_pinctrl_lookup_phandle(struct pin_info *conf,
+					    int conf_count, int phandle)
+{
+	int i;
+
+	for (i = 0; i < conf_count; i++) {
+		if (conf[i].phandle == phandle)
+			return i;
+	}
+
+	return -ENOENT;
+}
+
+static int broadwell_pinctrl_read_pins(struct udevice *dev,
+		struct pin_info *conf, int conf_count, int gpio_conf[],
+		int num_gpios)
+{
+	const void *blob = gd->fdt_blob;
+	int count = 0;
+	int node;
+
+	for (node = fdt_first_subnode(blob, dev->of_offset);
+	     node > 0;
+	     node = fdt_next_subnode(blob, node)) {
+		int len, i;
+		const u32 *prop = fdt_getprop(blob, node, "config", &len);
+
+		if (!prop)
+			continue;
+
+		/* There are three cells per pin */
+		count = len / (sizeof(u32) * 3);
+		debug("Found %d GPIOs to configure\n", count);
+		for (i = 0; i < count; i++) {
+			uint gpio = fdt32_to_cpu(prop[i * 3]);
+			uint phandle = fdt32_to_cpu(prop[i * 3 + 1]);
+			int val;
+
+			if (gpio >= num_gpios) {
+				debug("%s: GPIO %d out of range\n", __func__,
+				      gpio);
+				return -EDOM;
+			}
+			val = broadwell_pinctrl_lookup_phandle(conf, conf_count,
+							       phandle);
+			if (val < 0) {
+				debug("%s: Cannot find phandle %d\n", __func__,
+				      phandle);
+				return -EINVAL;
+			}
+			gpio_conf[gpio] = val |
+				fdt32_to_cpu(prop[i * 3 + 2]) << PIRQ_SHIFT;
+		}
+	}
+
+	return 0;
+}
+
+static void broadwell_pinctrl_commit(struct pch_lp_gpio_regs *regs,
+				     struct pin_info *pin_info,
+				     int gpio_conf[], int count)
+{
+	u32 owner_gpio[GPIO_BANKS] = {0};
+	u32 route_smi[GPIO_BANKS] = {0};
+	u32 irq_enable[GPIO_BANKS] = {0};
+	u32 reset_rsmrst[GPIO_BANKS] = {0};
+	u32 pirq2apic = 0;
+	int set, bit, gpio = 0;
+
+	for (gpio = 0; gpio < MAX_GPIOS; gpio++) {
+		int confnum = gpio_conf[gpio] & CONF_MASK;
+		struct pin_info *pin = &pin_info[confnum];
+		u32 val;
+
+		val = pin->mode_gpio << CONFA_MODE_SHIFT |
+			pin->dir_input << CONFA_DIR_SHIFT |
+			pin->invert << CONFA_INVERT_SHIFT |
+			pin->trigger_level << CONFA_TRIGGER_SHIFT |
+			pin->output_high << CONFA_OUTPUT_SHIFT;
+		outl(val, &regs->config[gpio].conf_a);
+		outl(pin->sense_disable << CONFB_SENSE_SHIFT,
+		     &regs->config[gpio].conf_b);
+
+		/* Determine set and bit based on GPIO number */
+		set = gpio / GPIO_PER_BANK;
+		bit = gpio % GPIO_PER_BANK;
+
+		/* Apply settings to set specific bits */
+		owner_gpio[set] |= pin->owner_gpio << bit;
+		route_smi[set] |= pin->route_smi << bit;
+		irq_enable[set] |= pin->irq_enable << bit;
+		reset_rsmrst[set] |= pin->reset_rsmrst << bit;
+
+		/* PIRQ to IO-APIC map */
+		if (pin->pirq_apic_route)
+			pirq2apic |= gpio_conf[gpio] >> PIRQ_SHIFT;
+		debug("gpio %d: conf %d, mode_gpio %d, dir_input %d, output_high %d\n",
+		      gpio, confnum, pin->mode_gpio, pin->dir_input,
+		      pin->output_high);
+	}
+
+	for (set = 0; set < GPIO_BANKS; set++) {
+		outl(owner_gpio[set], &regs->own[set]);
+		outl(route_smi[set], &regs->gpi_route[set]);
+		outl(irq_enable[set], &regs->gpi_ie[set]);
+		outl(reset_rsmrst[set], &regs->rst_sel[set]);
+	}
+
+	outl(pirq2apic, &regs->pirq_to_ioxapic);
+}
+
+static int broadwell_pinctrl_probe(struct udevice *dev)
+{
+	struct pch_lp_gpio_regs *regs;
+	struct pin_info conf[12];
+	int gpio_conf[MAX_GPIOS];
+	struct udevice *pch;
+	int conf_count;
+	u32 gpiobase;
+	int ret;
+
+	ret = uclass_first_device(UCLASS_PCH, &pch);
+	if (ret)
+		return ret;
+	if (!pch)
+		return -ENODEV;
+	debug("%s: start\n", __func__);
+
+	/* Only init once, before relocation */
+	if (gd->flags & GD_FLG_RELOC)
+		return 0;
+
+	/*
+	 * Get the memory/io base address to configure every pins.
+	 * IOBASE is used to configure the mode/pads
+	 * GPIOBASE is used to configure the direction and default value
+	 */
+	ret = pch_get_gpio_base(pch, &gpiobase);
+	if (ret) {
+		debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
+		      gpiobase);
+		return -EINVAL;
+	}
+
+	conf_count = broadwell_pinctrl_read_configs(dev, conf,
+						    ARRAY_SIZE(conf));
+	if (conf_count < 0) {
+		debug("%s: Cannot read configs: err=%d\n", __func__, ret);
+		return conf_count;
+	}
+
+	/*
+	 * Assume that pin settings are provided for every pin. Pins not
+	 * mentioned will get the first config mentioned in the list.
+	 */
+	ret = broadwell_pinctrl_read_pins(dev, conf, conf_count, gpio_conf,
+					  MAX_GPIOS);
+	if (ret) {
+		debug("%s: Cannot read pin settings: err=%d\n", __func__, ret);
+		return ret;
+	}
+
+	regs = (struct pch_lp_gpio_regs *)gpiobase;
+	broadwell_pinctrl_commit(regs, conf, gpio_conf, ARRAY_SIZE(conf));
+
+	debug("%s: done\n", __func__);
+
+	return 0;
+}
+
+static const struct udevice_id broadwell_pinctrl_match[] = {
+	{ .compatible = "intel,x86-broadwell-pinctrl",
+		.data = X86_SYSCON_PINCONF },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(broadwell_pinctrl) = {
+	.name = "broadwell_pinctrl",
+	.id = UCLASS_SYSCON,
+	.of_match = broadwell_pinctrl_match,
+	.probe = broadwell_pinctrl_probe,
+};
diff --git a/arch/x86/include/asm/arch-broadwell/gpio.h b/arch/x86/include/asm/arch-broadwell/gpio.h
new file mode 100644
index 0000000..0ed881b
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/gpio.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From Coreboot src/soc/intel/broadwell/include/soc/gpio.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_GPIO
+#define __ASM_ARCH_GPIO
+
+#define GPIO_PER_BANK	32
+#define GPIO_BANKS	3
+
+struct broadwell_bank_platdata {
+	uint16_t base_addr;
+	const char *bank_name;
+	int bank;
+};
+
+/* PCH-LP GPIOBASE Registers */
+struct pch_lp_gpio_regs {
+	u32 own[GPIO_BANKS];
+	u32 reserved0;
+
+	u16 pirq_to_ioxapic;
+	u16 reserved1[3];
+	u32 blink;
+	u32 ser_blink;
+
+	u32 ser_blink_cmdsts;
+	u32 ser_blink_data;
+	u16 gpi_nmi_en;
+	u16 gpi_nmi_sts;
+	u32 reserved2;
+
+	u32 gpi_route[GPIO_BANKS];
+	u32 reserved3;
+
+	u32 reserved4[4];
+
+	u32 alt_gpi_smi_sts;
+	u32 alt_gpi_smi_en;
+	u32 reserved5[2];
+
+	u32 rst_sel[GPIO_BANKS];
+	u32 reserved6;
+
+	u32 reserved9[3];
+	u32 gpio_gc;
+
+	u32 gpi_is[GPIO_BANKS];
+	u32 reserved10;
+
+	u32 gpi_ie[GPIO_BANKS];
+	u32 reserved11;
+
+	u32 reserved12[24];
+
+	struct {
+		u32 conf_a;
+		u32 conf_b;
+	} config[GPIO_BANKS * GPIO_PER_BANK];
+};
+check_member(pch_lp_gpio_regs, gpi_ie[0], 0x90);
+check_member(pch_lp_gpio_regs, config[0], 0x100);
+
+enum {
+	CONFA_MODE_SHIFT	= 0,
+	CONFA_MODE_GPIO		= 1 << CONFA_MODE_SHIFT,
+
+	CONFA_DIR_SHIFT		= 2,
+	CONFA_DIR_INPUT		= 1 << CONFA_DIR_SHIFT,
+
+	CONFA_INVERT_SHIFT	= 3,
+	CONFA_INVERT		= 1 << CONFA_INVERT_SHIFT,
+
+	CONFA_TRIGGER_SHIFT	= 4,
+	CONFA_TRIGGER_LEVEL	= 1 << CONFA_TRIGGER_SHIFT,
+
+	CONFA_LEVEL_SHIFT	= 30,
+	CONFA_LEVEL_HIGH	= 1UL << CONFA_LEVEL_SHIFT,
+
+	CONFA_OUTPUT_SHIFT	= 31,
+	CONFA_OUTPUT_HIGH	= 1UL << CONFA_OUTPUT_SHIFT,
+
+	CONFB_SENSE_SHIFT	= 2,
+	CONFB_SENSE_DISABLE	= 1 << CONFB_SENSE_SHIFT,
+};
+
+#endif
diff --git a/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt b/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
new file mode 100644
index 0000000..a644381
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
@@ -0,0 +1,208 @@
+Intel x86 PINCTRL/GPIO controller
+
+Pin-muxing on broadwell devices can be described with a node for the PINCTRL
+master node and a set of child nodes for each required pin state on the SoC.
+These pin states use phandles and are referred to but a configuration section
+which lists all pins in the device.
+
+The PINCTRL master node requires the following properties:
+- compatible : "intel,x86-broadwell-pinctrl"
+
+Pin state nodes must be sub-nodes of the pinctrl master node. The must have
+a phandle. They can contain the following optional properties:
+- mode-gpio	- forces the pin into GPIO mode
+- output-value	- sets the default output value of the GPIO, 0 (low, default)
+			or 1 (high)
+- direction	- sets the direction of the gpio, either PIN_INPUT (default)
+			or PIN_OUTPUT
+- invert	- the input pin is inverted
+- trigger	- sets the trigger type, either TRIGGER_EDGE (default) or
+			TRIGGER_LEVEL
+- sense-disable - the input state sense is disabled
+- owner		0 sets the owner of the pin, either OWNER_ACPI (default) or
+			ONWER_GPIO
+- route		- sets whether the pin is routed, either PIRQ_APIC_MASK or
+			PIRQ_APIC_ROUTE
+- irq-enable	- the interrupt is enabled
+- reset-rsmrst	- the pin will only be reset by RSMRST
+- pirq-apic	- the pin will be routed to the IOxAPIC
+
+The first pin state will be the default, so pins without a configuration will
+use that.
+
+The pin configuration node is also a sub-node of the pinctrl master node, but
+does not have a phandle. It has a single property:
+
+- config	- configuration to use for each pin. Each entry has of 3 cells:
+			- GPIO number (0..94)
+			- phandle of configuration (above)
+			- interrupt number (0..15)
+
+		  There should be one entry for each pin (i.e. 95 entries).
+		  But missing pins will receive the default configuration.
+
+Example:
+
+pch_pinctrl {
+	compatible = "intel,x86-broadwell-pinctrl";
+
+	/* Put this first: it is the default */
+	gpio_unused: gpio-unused {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+		sense-disable;
+	};
+
+	gpio_acpi_sci: acpi-sci {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		invert;
+		route = <ROUTE_SCI>;
+	};
+
+	gpio_acpi_smi: acpi-smi {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		invert;
+		route = <ROUTE_SMI>;
+	};
+
+	gpio_input: gpio-input {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+	};
+
+	gpio_input_invert: gpio-input-invert {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+		invert;
+	};
+
+	gpio_native: gpio-native {
+	};
+
+	gpio_out_high: gpio-out-high {
+		mode-gpio;
+		direction = <PIN_OUTPUT>;
+		output-value = <1>;
+		owner = <OWNER_GPIO>;
+		sense-disable;
+	};
+
+	gpio_out_low: gpio-out-low {
+		mode-gpio;
+		direction = <PIN_OUTPUT>;
+		output-value = <0>;
+		owner = <OWNER_GPIO>;
+		sense-disable;
+	};
+
+	gpio_pirq: gpio-pirq {
+		mode-gpio;
+		direction = <PIN_INPUT>;
+		owner = <OWNER_GPIO>;
+		pirq-apic = <PIRQ_APIC_ROUTE>;
+	};
+
+	soc_gpio at 0 {
+		config =
+			<0 &gpio_unused 0>,	/* unused */
+			<1 &gpio_unused 0>,	/* unused */
+			<2 &gpio_unused 0>,	/* unused */
+			<3 &gpio_unused 0>,	/* unused */
+			<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
+			<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
+			<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
+			<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
+			<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
+			<9 &gpio_input_invert 0>,/* trackpad_int_l (wake) */
+			<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
+			<11 &gpio_unused 0>,	/* unused */
+			<12 &gpio_unused 0>,	/* unused */
+			<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
+			<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
+			<15 &gpio_unused 0>,	/* unused (strap) */
+			<16 &gpio_input 0>,	/* pch_wp */
+			<17 &gpio_unused 0>,	/* unused */
+			<18 &gpio_unused 0>,	/* unused */
+			<19 &gpio_unused 0>,	/* unused */
+			<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
+			<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
+			<22 &gpio_unused 0>,	/* unused */
+			<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
+			<24 &gpio_unused 0>,	/* unused */
+			<25 &gpio_input 0>,	/* ec_in_rw */
+			<26 &gpio_unused 0>,	/* unused */
+			<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
+			<28 &gpio_unused 0>,	/* unused */
+			<29 &gpio_unused 0>,	/* unused */
+			<30 &gpio_native 0>,	/* native: pch_suswarn_l */
+			<31 &gpio_native 0>,	/* native: acok_buf */
+			<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
+			<33 &gpio_native 0>,	/* native: ssd_devslp */
+			<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
+			<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
+			<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
+			<37 &gpio_unused 0>,	/* unused */
+			<38 &gpio_unused 0>,	/* unused */
+			<39 &gpio_unused 0>,	/* unused */
+			<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
+			<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
+			<42 &gpio_unused 0>,	/* wlan_disable_l */
+			<43 &gpio_out_high 0>,	/* pp1800_codec_en */
+			<44 &gpio_unused 0>,	/* unused */
+			<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
+			<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
+			<47 &gpio_out_low 0>,	/* ssd_reset_l */
+			<48 &gpio_unused 0>,	/* unused */
+			<49 &gpio_unused 0>,	/* unused */
+			<50 &gpio_unused 0>,	/* unused */
+			<51 &gpio_unused 0>,	/* unused */
+			<52 &gpio_input 0>,	/* sim_det */
+			<53 &gpio_unused 0>,	/* unused */
+			<54 &gpio_unused 0>,	/* unused */
+			<55 &gpio_unused 0>,	/* unused */
+			<56 &gpio_unused 0>,	/* unused */
+			<57 &gpio_out_high 0>,	/* codec_reset_l */
+			<58 &gpio_unused 0>,	/* unused */
+			<59 &gpio_out_high 0>,	/* lte_disable_l */
+			<60 &gpio_unused 0>,	/* unused */
+			<61 &gpio_native 0>,	/* native: pch_sus_stat */
+			<62 &gpio_native 0>,	/* native: pch_susclk */
+			<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
+			<64 &gpio_unused 0>,	/* unused */
+			<65 &gpio_input 0>,	/* ram_id3 */
+			<66 &gpio_input 0>,	/* ram_id3_old (strap) */
+			<67 &gpio_input 0>,	/* ram_id0 */
+			<68 &gpio_input 0>,	/* ram_id1 */
+			<69 &gpio_input 0>,	/* ram_id2 */
+			<70 &gpio_unused 0>,	/* unused */
+			<71 &gpio_native 0>,	/* native: modphy_en */
+			<72 &gpio_unused 0>,	/* unused */
+			<73 &gpio_unused 0>,	/* unused */
+			<74 &gpio_unused 0>,	/* unused */
+			<75 &gpio_unused 0>,	/* unused */
+			<76 &gpio_unused 0>,	/* unused */
+			<77 &gpio_unused 0>,	/* unused */
+			<78 &gpio_unused 0>,	/* unused */
+			<79 &gpio_unused 0>,	/* unused */
+			<80 &gpio_unused 0>,	/* unused */
+			<81 &gpio_unused 0>,	/* unused */
+			<82 &gpio_native 0>,	/* native: ec_rcin_l */
+			<83 &gpio_native 0>,	/* gspi0_cs */
+			<84 &gpio_native 0>,	/* gspi0_clk */
+			<85 &gpio_native 0>,	/* gspi0_miso */
+			<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
+			<87 &gpio_unused 0>,	/* unused */
+			<88 &gpio_unused 0>,	/* unused */
+			<89 &gpio_out_high 0>,	/* pp3300_sd_en */
+			<90 &gpio_unused 0>,	/* unused */
+			<91 &gpio_unused 0>,	/* unused */
+			<92 &gpio_unused 0>,	/* unused */
+			<93 &gpio_unused 0>,	/* unused */
+			<94 &gpio_unused 0 >;	/* unused */
+	};
+};
diff --git a/include/dt-bindings/gpio/x86-gpio.h b/include/dt-bindings/gpio/x86-gpio.h
index 7f1de30..3998a8e 100644
--- a/include/dt-bindings/gpio/x86-gpio.h
+++ b/include/dt-bindings/gpio/x86-gpio.h
@@ -28,4 +28,16 @@
 #define PULL_STR_2K		0
 #define PULL_STR_20K	2
 
+#define ROUTE_SCI	0
+#define ROUTE_SMI	1
+
+#define OWNER_ACPI	0
+#define OWNER_GPIO	1
+
+#define PIRQ_APIC_MASK	0
+#define PIRQ_APIC_ROUTE	1
+
+#define TRIGGER_EDGE	0
+#define TRIGGER_LEVEL	1
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 36/51] x86: broadwell: Add a SATA driver

[Simon Glass]

Add a SATA driver for broadwell. This supports connecting an SSD and the
usual U-Boot commands to read and write data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/cpu/broadwell/Makefile |   1 +
 arch/x86/cpu/broadwell/sata.c   | 269 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 270 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/sata.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index db60e30..d422a1c 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -8,3 +8,4 @@ obj-y += cpu.o
 obj-y += iobp.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
+obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/sata.c b/arch/x86/cpu/broadwell/sata.c
new file mode 100644
index 0000000..dfb8486
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sata.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/sata.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/intel_regs.h>
+#include <asm/lpc_common.h>
+#include <asm/pch_common.h>
+#include <asm/pch_common.h>
+#include <asm/arch/pch.h>
+
+struct sata_platdata {
+	int port_map;
+	uint port0_gen3_tx;
+	uint port1_gen3_tx;
+	uint port0_gen3_dtle;
+	uint port1_gen3_dtle;
+
+	/*
+	 * SATA DEVSLP Mux
+	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
+	 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
+	 */
+	int devslp_mux;
+
+	/*
+	 * DEVSLP Disable
+	 * 0: DEVSLP is enabled
+	 * 1: DEVSLP is disabled
+	 */
+	int devslp_disable;
+};
+
+static void broadwell_sata_init(struct udevice *dev)
+{
+	struct sata_platdata *plat = dev_get_platdata(dev);
+	u32 reg32;
+	u8 *abar;
+	u16 reg16;
+	int port;
+
+	debug("SATA: Initializing controller in AHCI mode.\n");
+
+	/* Set timings */
+	dm_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+	dm_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
+
+	/* for AHCI, Port Enable is managed in memory mapped space */
+	dm_pci_read_config16(dev, 0x92, &reg16);
+	reg16 &= ~0xf;
+	reg16 |= 0x8000 | plat->port_map;
+	dm_pci_write_config16(dev, 0x92, reg16);
+	udelay(2);
+
+	/* Setup register 98h */
+	dm_pci_read_config32(dev, 0x98, &reg32);
+	reg32 &= ~((1 << 31) | (1 << 30));
+	reg32 |= 1 << 23;
+	reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */
+	dm_pci_write_config32(dev, 0x98, reg32);
+
+	/* Setup register 9Ch */
+	reg16 = 0;           /* Disable alternate ID */
+	reg16 = 1 << 5;      /* BWG step 12 */
+	dm_pci_write_config16(dev, 0x9c, reg16);
+
+	/* SATA Initialization register */
+	reg32 = 0x183;
+	reg32 |= (plat->port_map ^ 0xf) << 24;
+	reg32 |= (plat->devslp_mux & 1) << 15;
+	dm_pci_write_config32(dev, 0x94, reg32);
+
+	/* Initialize AHCI memory-mapped space */
+	dm_pci_read_config32(dev, PCI_BASE_ADDRESS_5, &reg32);
+	abar = (u8 *)reg32;
+	debug("ABAR: %p\n", abar);
+
+	/* CAP (HBA Capabilities) : enable power management */
+	clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */,
+			0x0c006000 /* PSC+SSC+SALP+SSS */ |
+			1 << 18); /* SAM: SATA AHCI MODE ONLY */
+
+	/* PI (Ports implemented) */
+	writel(plat->port_map, abar + 0x0c);
+	(void) readl(abar + 0x0c); /* Read back 1 */
+	(void) readl(abar + 0x0c); /* Read back 2 */
+
+	/* CAP2 (HBA Capabilities Extended)*/
+	if (plat->devslp_disable) {
+		clrbits_le32(abar + 0x24, 1 << 3);
+	} else {
+		/* Enable DEVSLP */
+		setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2);
+
+		for (port = 0; port < 4; port++) {
+			if (!(plat->port_map & (1 << port)))
+				continue;
+			/* DEVSLP DSP */
+			setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1);
+		}
+	}
+
+	/* Static Power Gating for unused ports */
+	reg32 = readl(RCB_REG(0x3a84));
+	/* Port 3 and 2 disabled */
+	if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0)
+		reg32 |= (1 << 24) | (1 << 26);
+	/* Port 1 and 0 disabled */
+	if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0)
+		reg32 |= (1 << 20) | (1 << 18);
+	writel(reg32, RCB_REG(0x3a84));
+
+	/* Set Gen3 Transmitter settings if needed */
+	if (plat->port0_gen3_tx)
+		pch_iobp_update(SATA_IOBP_SP0_SECRT88,
+				~(SATA_SECRT88_VADJ_MASK <<
+				  SATA_SECRT88_VADJ_SHIFT),
+				(plat->port0_gen3_tx &
+				 SATA_SECRT88_VADJ_MASK)
+				<< SATA_SECRT88_VADJ_SHIFT);
+
+	if (plat->port1_gen3_tx)
+		pch_iobp_update(SATA_IOBP_SP1_SECRT88,
+				~(SATA_SECRT88_VADJ_MASK <<
+				  SATA_SECRT88_VADJ_SHIFT),
+				(plat->port1_gen3_tx &
+				 SATA_SECRT88_VADJ_MASK)
+				<< SATA_SECRT88_VADJ_SHIFT);
+
+	/* Set Gen3 DTLE DATA / EDGE registers if needed */
+	if (plat->port0_gen3_dtle) {
+		pch_iobp_update(SATA_IOBP_SP0DTLE_DATA,
+				~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
+				(plat->port0_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_DATA_SHIFT);
+
+		pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE,
+				~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
+				(plat->port0_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_EDGE_SHIFT);
+	}
+
+	if (plat->port1_gen3_dtle) {
+		pch_iobp_update(SATA_IOBP_SP1DTLE_DATA,
+				~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT),
+				(plat->port1_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_DATA_SHIFT);
+
+		pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE,
+				~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT),
+				(plat->port1_gen3_dtle & SATA_DTLE_MASK)
+				<< SATA_DTLE_EDGE_SHIFT);
+	}
+
+	/*
+	 * Additional Programming Requirements for Power Optimizer
+	 */
+
+	/* Step 1 */
+	pch_common_sir_write(dev, 0x64, 0x883c9003);
+
+	/* Step 2: SIR 68h[15:0] = 880Ah */
+	reg32 = pch_common_sir_read(dev, 0x68);
+	reg32 &= 0xffff0000;
+	reg32 |= 0x880a;
+	pch_common_sir_write(dev, 0x68, reg32);
+
+	/* Step 3: SIR 60h[3] = 1 */
+	reg32 = pch_common_sir_read(dev, 0x60);
+	reg32 |= (1 << 3);
+	pch_common_sir_write(dev, 0x60, reg32);
+
+	/* Step 4: SIR 60h[0] = 1 */
+	reg32 = pch_common_sir_read(dev, 0x60);
+	reg32 |= (1 << 0);
+	pch_common_sir_write(dev, 0x60, reg32);
+
+	/* Step 5: SIR 60h[1] = 1 */
+	reg32 = pch_common_sir_read(dev, 0x60);
+	reg32 |= (1 << 1);
+	pch_common_sir_write(dev, 0x60, reg32);
+
+	/* Clock Gating */
+	pch_common_sir_write(dev, 0x70, 0x3f00bf1f);
+	pch_common_sir_write(dev, 0x54, 0xcf000f0f);
+	pch_common_sir_write(dev, 0x58, 0x00190000);
+	clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000);
+
+	dm_pci_read_config32(dev, 0x300, &reg32);
+	reg32 |= 1 << 17 | 1 << 16 | 1 << 19;
+	reg32 |= 1 << 31 | 1 << 30 | 1 << 29;
+	dm_pci_write_config32(dev, 0x300, reg32);
+
+	dm_pci_read_config32(dev, 0x98, &reg32);
+	reg32 |= 1 << 29;
+	dm_pci_write_config32(dev, 0x98, reg32);
+
+	/* Register Lock */
+	dm_pci_read_config32(dev, 0x9c, &reg32);
+	reg32 |= 1 << 31;
+	dm_pci_write_config32(dev, 0x9c, reg32);
+}
+
+static int broadwell_sata_enable(struct udevice *dev)
+{
+	struct sata_platdata *plat = dev_get_platdata(dev);
+	struct gpio_desc desc;
+	u16 map;
+	int ret;
+
+	/*
+	 * Set SATA controller mode early so the resource allocator can
+	 * properly assign IO/Memory resources for the controller.
+	 */
+	map = 0x0060;
+
+	map |= (plat->port_map ^ 0x3f) << 8;
+	dm_pci_write_config16(dev, 0x90, map);
+
+	ret = gpio_request_by_name(dev, "reset-gpio", 0, &desc, GPIOD_IS_OUT);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
+{
+	struct sata_platdata *plat = dev_get_platdata(dev);
+	const void *blob = gd->fdt_blob;
+	int node = dev->of_offset;
+
+	plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
+	plat->port0_gen3_tx = fdtdec_get_int(blob, node,
+					"intel,sata-port0-gen3-tx", 0);
+
+	return 0;
+}
+
+static int broadwell_sata_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		return broadwell_sata_enable(dev);
+	else
+		broadwell_sata_init(dev);
+
+	return 0;
+}
+
+static const struct udevice_id broadwell_ahci_ids[] = {
+	{ .compatible = "intel,wildcatpoint-ahci" },
+	{ }
+};
+
+U_BOOT_DRIVER(ahci_broadwell_drv) = {
+	.name		= "ahci_broadwell",
+	.id		= UCLASS_DISK,
+	.of_match	= broadwell_ahci_ids,
+	.ofdata_to_platdata	= broadwell_sata_ofdata_to_platdata,
+	.probe		= broadwell_sata_probe,
+	.platdata_auto_alloc_size	 = sizeof(struct sata_platdata),
+};
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 37/51] x86: broadwell: Add a northbridge driver

[Simon Glass]

Add a driver for the broadwell northbridge. This sets up the location of
several blocks of registers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/cpu/broadwell/Makefile      |  1 +
 arch/x86/cpu/broadwell/northbridge.c | 59 ++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/northbridge.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index d422a1c..39bf733 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += cpu.o
 obj-y += iobp.o
+obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/northbridge.c b/arch/x86/cpu/broadwell/northbridge.c
new file mode 100644
index 0000000..aa64808
--- /dev/null
+++ b/arch/x86/cpu/broadwell/northbridge.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 The Chromium Authors
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+
+static int broadwell_northbridge_early_init(struct udevice *dev)
+{
+	/* Move earlier? */
+	dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
+	/* 64MiB - 0-63 buses */
+	dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
+
+	dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+	dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
+	dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
+	writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
+	writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
+
+	/* Set C0000-FFFFF to access RAM on both reads and writes */
+	dm_pci_write_config8(dev, PAM0, 0x30);
+	dm_pci_write_config8(dev, PAM1, 0x33);
+	dm_pci_write_config8(dev, PAM2, 0x33);
+	dm_pci_write_config8(dev, PAM3, 0x33);
+	dm_pci_write_config8(dev, PAM4, 0x33);
+	dm_pci_write_config8(dev, PAM5, 0x33);
+	dm_pci_write_config8(dev, PAM6, 0x33);
+
+	/* Device enable: IGD and Mini-HD */
+	dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
+
+	return 0;
+}
+
+static int broadwell_northbridge_probe(struct udevice *dev)
+{
+	if (!(gd->flags & GD_FLG_RELOC))
+		return broadwell_northbridge_early_init(dev);
+
+	return 0;
+}
+
+static const struct udevice_id broadwell_northbridge_ids[] = {
+	{ .compatible = "intel,broadwell-northbridge" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_northbridge_drv) = {
+	.name		= "broadwell_northbridge",
+	.id		= UCLASS_NORTHBRIDGE,
+	.of_match	= broadwell_northbridge_ids,
+	.probe		= broadwell_northbridge_probe,
+};
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 38/51] x86: broadwell: Add an LPC driver

[Simon Glass]

Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
uses common code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use capitals for header guard

 arch/x86/cpu/broadwell/Makefile           |  1 +
 arch/x86/cpu/broadwell/lpc.c              | 77 +++++++++++++++++++++++++++++++
 arch/x86/include/asm/arch-broadwell/lpc.h | 32 +++++++++++++
 3 files changed, 110 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/lpc.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 39bf733..3054a89 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -6,6 +6,7 @@
 
 obj-y += cpu.o
 obj-y += iobp.o
+obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
diff --git a/arch/x86/cpu/broadwell/lpc.c b/arch/x86/cpu/broadwell/lpc.c
new file mode 100644
index 0000000..ee3ac18
--- /dev/null
+++ b/arch/x86/cpu/broadwell/lpc.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot broadwell support
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/spi.h>
+
+static void set_spi_speed(void)
+{
+	u32 fdod;
+	u8 ssfc;
+
+	/* Observe SPI Descriptor Component Section 0 */
+	writel(0x1000, SPI_REG(SPIBAR_FDOC));
+
+	/* Extract the Write/Erase SPI Frequency from descriptor */
+	fdod = readl(SPI_REG(SPIBAR_FDOD));
+	fdod >>= 24;
+	fdod &= 7;
+
+	/* Set Software Sequence frequency to match */
+	ssfc = readb(SPI_REG(SPIBAR_SSFC + 2));
+	ssfc &= ~7;
+	ssfc |= fdod;
+	writeb(ssfc, SPI_REG(SPIBAR_SSFC + 2));
+}
+
+static int broadwell_lpc_early_init(struct udevice *dev)
+{
+	set_spi_speed();
+
+	return 0;
+}
+
+static int lpc_init_extra(struct udevice *dev)
+{
+	return 0;
+}
+
+static int broadwell_lpc_probe(struct udevice *dev)
+{
+	int ret;
+
+	if (!(gd->flags & GD_FLG_RELOC)) {
+		ret = lpc_common_early_init(dev);
+		if (ret) {
+			debug("%s: lpc_early_init() failed\n", __func__);
+			return ret;
+		}
+
+		return broadwell_lpc_early_init(dev);
+	}
+
+	return lpc_init_extra(dev);
+}
+
+static const struct udevice_id broadwell_lpc_ids[] = {
+	{ .compatible = "intel,broadwell-lpc" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_lpc_drv) = {
+	.name		= "lpc",
+	.id		= UCLASS_LPC,
+	.of_match	= broadwell_lpc_ids,
+	.probe		= broadwell_lpc_probe,
+};
diff --git a/arch/x86/include/asm/arch-broadwell/lpc.h b/arch/x86/include/asm/arch-broadwell/lpc.h
new file mode 100644
index 0000000..a718667
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/lpc.h
@@ -0,0 +1,32 @@
+/*
+ * From coreboot soc/intel/broadwell/include/soc/lpc.h
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_LPC_H
+#define _ASM_ARCH_LPC_H
+
+#define GEN_PMCON_1		0xa0
+#define  SMI_LOCK		(1 << 4)
+#define GEN_PMCON_2		0xa2
+#define  SYSTEM_RESET_STS	(1 << 4)
+#define  THERMTRIP_STS		(1 << 3)
+#define  SYSPWR_FLR		(1 << 1)
+#define  PWROK_FLR		(1 << 0)
+#define GEN_PMCON_3		0xa4
+#define  SUS_PWR_FLR		(1 << 14)
+#define  GEN_RST_STS		(1 << 9)
+#define  RTC_BATTERY_DEAD	(1 << 2)
+#define  PWR_FLR		(1 << 1)
+#define  SLEEP_AFTER_POWER_FAIL	(1 << 0)
+#define GEN_PMCON_LOCK		0xa6
+#define  SLP_STR_POL_LOCK	(1 << 2)
+#define  ACPI_BASE_LOCK		(1 << 1)
+#define PMIR			0xac
+#define  PMIR_CF9LOCK		(1 << 31)
+#define  PMIR_CF9GR		(1 << 20)
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 39/51] x86: broadwell: Add reference code support

[Simon Glass]

Broadwell needs a special binary blob to set up the PCH. Add code to run
this on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Fix comment style

 arch/x86/cpu/broadwell/Makefile  |   1 +
 arch/x86/cpu/broadwell/refcode.c | 113 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 114 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/refcode.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 3054a89..a542fef 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -10,4 +10,5 @@ obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
+obj-y += refcode.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c
new file mode 100644
index 0000000..436c6c4
--- /dev/null
+++ b/arch/x86/cpu/broadwell/refcode.c
@@ -0,0 +1,113 @@
+/*
+ * Read a coreboot rmodule and execute it.
+ * The rmodule_header struct is from coreboot.
+ *
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/pei_data.h>
+
+#define RMODULE_MAGIC		0xf8fe
+#define RMODULE_VERSION_1	1
+
+/*
+ * All fields with '_offset' in the name are byte offsets into the flat blob.
+ * The linker and the linker script takes are of assigning the values.
+ */
+struct rmodule_header {
+	uint16_t magic;
+	uint8_t version;
+	uint8_t type;
+	/* The payload represents the program's loadable code and data */
+	uint32_t payload_begin_offset;
+	uint32_t payload_end_offset;
+	/* Begin and of relocation information about the program module */
+	uint32_t relocations_begin_offset;
+	uint32_t relocations_end_offset;
+	/*
+	 * The starting address of the linked program. This address is vital
+	 * for determining relocation offsets as the relocation info and other
+	 * symbols (bss, entry point) need this value as a basis to calculate
+	 * the offsets.
+	 */
+	uint32_t module_link_start_address;
+	/*
+	 * The module_program_size is the size of memory used while running
+	 * the program. The program is assumed to consume a contiguous amount
+	 * of memory
+	 */
+	uint32_t module_program_size;
+	/* This is program's execution entry point */
+	uint32_t module_entry_point;
+	/*
+	 * Optional parameter structure that can be used to pass data into
+	 * the module
+	 */
+	uint32_t parameters_begin;
+	uint32_t parameters_end;
+	/* BSS section information so the loader can clear the bss */
+	uint32_t bss_begin;
+	uint32_t bss_end;
+	/* Add some room for growth */
+	uint32_t padding[4];
+} __packed;
+
+int cpu_run_reference_code(void)
+{
+	struct pei_data _pei_data __aligned(8);
+	struct pei_data *pei_data = &_pei_data;
+	asmlinkage int (*func)(void *);
+	struct rmodule_header *hdr;
+	char *src, *dest;
+	int ret, dummy;
+	int size;
+
+	hdr = (struct rmodule_header *)CONFIG_X86_REFCODE_ADDR;
+	debug("Extracting code from rmodule at %p\n", hdr);
+	if (hdr->magic != RMODULE_MAGIC) {
+		debug("Invalid rmodule magic\n");
+		return -EINVAL;
+	}
+	if (hdr->module_link_start_address != 0) {
+		debug("Link start address must be 0\n");
+		return -EPERM;
+	}
+	if (hdr->module_entry_point != 0) {
+		debug("Entry point must be 0\n");
+		return -EPERM;
+	}
+
+	memset(pei_data, '\0', sizeof(struct pei_data));
+	broadwell_fill_pei_data(pei_data);
+	mainboard_fill_pei_data(pei_data);
+	pei_data->saved_data = (void *)&dummy;
+
+	src = (char *)hdr + hdr->payload_begin_offset;
+	dest = (char *)CONFIG_X86_REFCODE_RUN_ADDR;
+
+	size = hdr->payload_end_offset - hdr->payload_begin_offset;
+	debug("Copying refcode from %p to %p, size %x\n", src, dest, size);
+	memcpy(dest, src, size);
+
+	size = hdr->bss_end - hdr->bss_begin;
+	debug("Zeroing BSS at %p, size %x\n", dest + hdr->bss_begin, size);
+	memset(dest + hdr->bss_begin, '\0', size);
+
+	func = (asmlinkage int (*)(void *))dest;
+	debug("Running reference code at %p\n", func);
+#ifdef DEBUG
+	print_buffer(CONFIG_X86_REFCODE_RUN_ADDR, (void *)func, 1, 0x40, 0);
+#endif
+	ret = func(pei_data);
+	if (ret != 0) {
+		debug("Reference code returned %d\n", ret);
+		return -EL2HLT;
+	}
+	debug("Refereence code completed\n");
+
+	return 0;
+}
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 40/51] x86: broadwell: Add power-control support

[Simon Glass]

Broadwell requires quite a bit of power-management setup. Add code to set
this up correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use capitals for header guard

 arch/x86/cpu/broadwell/Makefile          |   1 +
 arch/x86/cpu/broadwell/power_state.c     |  89 +++++++++++++++++++++
 arch/x86/include/asm/arch-broadwell/pm.h | 129 +++++++++++++++++++++++++++++++
 3 files changed, 219 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/power_state.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index a542fef..5a62afa 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -10,5 +10,6 @@ obj-y += lpc.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
+obj-y += power_state.o
 obj-y += refcode.o
 obj-y += sata.o
diff --git a/arch/x86/cpu/broadwell/power_state.c b/arch/x86/cpu/broadwell/power_state.c
new file mode 100644
index 0000000..3380323
--- /dev/null
+++ b/arch/x86/cpu/broadwell/power_state.c
@@ -0,0 +1,89 @@
+/*
+ * From coreboot src/soc/intel/broadwell/romstage/power_state.c
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/intel_regs.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/lpc.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pm.h>
+
+/* Return 0, 3, or 5 to indicate the previous sleep state. */
+static int prev_sleep_state(struct chipset_power_state *ps)
+{
+	/* Default to S0. */
+	int prev_sleep_state = SLEEP_STATE_S0;
+
+	if (ps->pm1_sts & WAK_STS) {
+		switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
+#if CONFIG_HAVE_ACPI_RESUME
+		case SLP_TYP_S3:
+			prev_sleep_state = SLEEP_STATE_S3;
+			break;
+#endif
+		case SLP_TYP_S5:
+			prev_sleep_state = SLEEP_STATE_S5;
+			break;
+		}
+		/* Clear SLP_TYP. */
+		outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+	}
+
+	if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
+		prev_sleep_state = SLEEP_STATE_S5;
+
+	return prev_sleep_state;
+}
+
+static void dump_power_state(struct chipset_power_state *ps)
+{
+	debug("PM1_STS:   %04x\n", ps->pm1_sts);
+	debug("PM1_EN:    %04x\n", ps->pm1_en);
+	debug("PM1_CNT:   %08x\n", ps->pm1_cnt);
+	debug("TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
+
+	debug("GPE0_STS:  %08x %08x %08x %08x\n",
+	      ps->gpe0_sts[0], ps->gpe0_sts[1],
+	      ps->gpe0_sts[2], ps->gpe0_sts[3]);
+	debug("GPE0_EN:   %08x %08x %08x %08x\n",
+	      ps->gpe0_en[0], ps->gpe0_en[1],
+	      ps->gpe0_en[2], ps->gpe0_en[3]);
+
+	debug("GEN_PMCON: %04x %04x %04x\n",
+	      ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
+
+	debug("Previous Sleep State: S%d\n",
+	      ps->prev_sleep_state);
+}
+
+/* Fill power state structure from ACPI PM registers */
+void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
+{
+	ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+	ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+	ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
+	ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
+	ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
+	ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
+	ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
+	ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
+	ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
+	ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
+	ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
+	ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
+
+	dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
+	dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
+	dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
+
+	ps->prev_sleep_state = prev_sleep_state(ps);
+
+	dump_power_state(ps);
+}
diff --git a/arch/x86/include/asm/arch-broadwell/pm.h b/arch/x86/include/asm/arch-broadwell/pm.h
new file mode 100644
index 0000000..36ad842
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pm.h
@@ -0,0 +1,129 @@
+/*
+ * From coreboot src/soc/intel/broadwell/include/soc/pm.h
+ *
+ * Copyright (C) 2016 Google, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_PM_H
+#define __ASM_ARCH_PM_H
+
+#define PM1_STS			0x00
+#define  WAK_STS		(1 << 15)
+#define  PCIEXPWAK_STS		(1 << 14)
+#define  PRBTNOR_STS		(1 << 11)
+#define  RTC_STS		(1 << 10)
+#define  PWRBTN_STS		(1 << 8)
+#define  GBL_STS		(1 << 5)
+#define  BM_STS			(1 << 4)
+#define  TMROF_STS		(1 << 0)
+#define PM1_EN			0x02
+#define  PCIEXPWAK_DIS		(1 << 14)
+#define  RTC_EN			(1 << 10)
+#define  PWRBTN_EN		(1 << 8)
+#define  GBL_EN			(1 << 5)
+#define  TMROF_EN		(1 << 0)
+#define PM1_CNT			0x04
+#define  SLP_EN			(1 << 13)
+#define  SLP_TYP		(7 << 10)
+#define   SLP_TYP_SHIFT         10
+#define   SLP_TYP_S0		0
+#define   SLP_TYP_S1		1
+#define   SLP_TYP_S3		5
+#define   SLP_TYP_S4		6
+#define   SLP_TYP_S5		7
+#define  GBL_RLS		(1 << 2)
+#define  BM_RLD			(1 << 1)
+#define  SCI_EN			(1 << 0)
+#define PM1_TMR			0x08
+#define SMI_EN			0x30
+#define  XHCI_SMI_EN		(1 << 31)
+#define  ME_SMI_EN		(1 << 30)
+#define  GPIO_UNLOCK_SMI_EN	(1 << 27)
+#define  INTEL_USB2_EN		(1 << 18)
+#define  LEGACY_USB2_EN		(1 << 17)
+#define  PERIODIC_EN		(1 << 14)
+#define  TCO_EN			(1 << 13)
+#define  MCSMI_EN		(1 << 11)
+#define  BIOS_RLS		(1 <<  7)
+#define  SWSMI_TMR_EN		(1 <<  6)
+#define  APMC_EN		(1 <<  5)
+#define  SLP_SMI_EN		(1 <<  4)
+#define  LEGACY_USB_EN		(1 <<  3)
+#define  BIOS_EN		(1 <<  2)
+#define  EOS			(1 <<  1)
+#define  GBL_SMI_EN		(1 <<  0)
+#define SMI_STS			0x34
+#define UPWRC			0x3c
+#define  UPWRC_WS		(1 << 8)
+#define  UPWRC_WE		(1 << 1)
+#define  UPWRC_SMI		(1 << 0)
+#define GPE_CNTL		0x42
+#define  SWGPE_CTRL		(1 << 1)
+#define DEVACT_STS		0x44
+#define PM2_CNT			0x50
+#define TCO1_CNT		0x60
+#define  TCO_TMR_HLT		(1 << 11)
+#define TCO1_STS		0x64
+#define  DMISCI_STS		(1 << 9)
+#define TCO2_STS		0x66
+#define  TCO2_STS_SECOND_TO	(1 << 1)
+
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x)		(0x80 + (x * 4))
+#define  GPE_31_0		0	/* 0x80/0x90 = GPE[31:0] */
+#define  GPE_63_32		1	/* 0x84/0x94 = GPE[63:32] */
+#define  GPE_94_64		2	/* 0x88/0x98 = GPE[94:64] */
+#define  GPE_STD		3	/* 0x8c/0x9c = Standard GPE */
+#define   WADT_STS		(1 << 18)
+#define   GP27_STS		(1 << 16)
+#define   PME_B0_STS		(1 << 13)
+#define   ME_SCI_STS		(1 << 12)
+#define   PME_STS		(1 << 11)
+#define   BATLOW_STS		(1 << 10)
+#define   PCI_EXP_STS		(1 << 9)
+#define   SMB_WAK_STS		(1 << 7)
+#define   TCOSCI_STS		(1 << 6)
+#define   SWGPE_STS		(1 << 2)
+#define   HOT_PLUG_STS		(1 << 1)
+#define GPE0_EN(x)		(0x90 + (x * 4))
+#define   WADT_en		(1 << 18)
+#define   GP27_EN		(1 << 16)
+#define   PME_B0_EN		(1 << 13)
+#define   ME_SCI_EN		(1 << 12)
+#define   PME_EN		(1 << 11)
+#define   BATLOW_EN		(1 << 10)
+#define   PCI_EXP_EN		(1 << 9)
+#define   TCOSCI_EN		(1 << 6)
+#define   SWGPE_EN		(1 << 2)
+#define   HOT_PLUG_EN		(1 << 1)
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
+#define SLEEP_STATE_S0		0
+#define SLEEP_STATE_S3		3
+#define SLEEP_STATE_S5		5
+
+struct chipset_power_state {
+	uint16_t pm1_sts;
+	uint16_t pm1_en;
+	uint32_t pm1_cnt;
+	uint16_t tco1_sts;
+	uint16_t tco2_sts;
+	uint32_t gpe0_sts[4];
+	uint32_t gpe0_en[4];
+	uint16_t gen_pmcon1;
+	uint16_t gen_pmcon2;
+	uint16_t gen_pmcon3;
+	int prev_sleep_state;
+	uint16_t hsio_version;
+	uint16_t hsio_checksum;
+};
+
+void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
+
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 41/51] x86: broadwell: Add support for SDRAM setup

[Simon Glass]

Broadwell uses a binary blob called the memory reference code (MRC) to start
up its SDRAM. This is similar to ivybridge so we can mostly use common code
for running this blob.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Rename sdram to mrc

 arch/x86/cpu/broadwell/Makefile                |   1 +
 arch/x86/cpu/broadwell/sdram.c                 | 307 +++++++++++++++++++++++++
 arch/x86/include/asm/arch-broadwell/pei_data.h | 177 ++++++++++++++
 arch/x86/include/asm/global_data.h             |  24 ++
 4 files changed, 509 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/sdram.c
 create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 5a62afa..012798f 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -13,3 +13,4 @@ obj-y += pinctrl_broadwell.o
 obj-y += power_state.o
 obj-y += refcode.o
 obj-y += sata.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
new file mode 100644
index 0000000..4bf5d15
--- /dev/null
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * From coreboot src/soc/intel/broadwell/romstage/raminit.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/io.h>
+#include <asm/lpc_common.h>
+#include <asm/mrccache.h>
+#include <asm/mrc_common.h>
+#include <asm/mtrr.h>
+#include <asm/pci.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pch.h>
+#include <asm/arch/pei_data.h>
+#include <asm/arch/pm.h>
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return mrc_common_board_get_usable_ram_top(total_size);
+}
+
+void dram_init_banksize(void)
+{
+	mrc_common_dram_init_banksize();
+}
+
+void broadwell_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->pei_version = PEI_VERSION;
+	pei_data->board_type = BOARD_TYPE_ULT;
+	pei_data->pciexbar = MCFG_BASE_ADDRESS;
+	pei_data->smbusbar = SMBUS_BASE_ADDRESS;
+	pei_data->ehcibar = EARLY_EHCI_BAR;
+	pei_data->xhcibar = EARLY_XHCI_BAR;
+	pei_data->gttbar = EARLY_GTT_BAR;
+	pei_data->pmbase = ACPI_BASE_ADDRESS;
+	pei_data->gpiobase = GPIO_BASE_ADDRESS;
+	pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+	pei_data->tx_byte = sdram_console_tx_byte;
+	pei_data->ddr_refresh_2x = 1;
+}
+
+static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
+				      uint16_t length, uint8_t enable,
+				      uint8_t oc_pin, uint8_t location)
+{
+	pei_data->usb2_ports[port].length   = length;
+	pei_data->usb2_ports[port].enable   = enable;
+	pei_data->usb2_ports[port].oc_pin   = oc_pin;
+	pei_data->usb2_ports[port].location = location;
+}
+
+static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
+				      uint8_t enable, uint8_t oc_pin,
+				      uint8_t fixed_eq)
+{
+	pei_data->usb3_ports[port].enable   = enable;
+	pei_data->usb3_ports[port].oc_pin   = oc_pin;
+	pei_data->usb3_ports[port].fixed_eq = fixed_eq;
+}
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	/* DQ byte map for Samus board */
+	const u8 dq_map[2][6][2] = {
+		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
+		{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
+		  { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
+	/* DQS CPU<>DRAM map for Samus board */
+	const u8 dqs_map[2][8] = {
+		{ 2, 0, 1, 3, 6, 4, 7, 5 },
+		{ 2, 1, 0, 3, 6, 5, 4, 7 } };
+
+	pei_data->ec_present = 1;
+
+	/* One installed DIMM per channel */
+	pei_data->dimm_channel0_disabled = 2;
+	pei_data->dimm_channel1_disabled = 2;
+
+	memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
+	memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
+
+	/* P0: HOST PORT */
+	pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
+			   USB_PORT_BACK_PANEL);
+	/* P1: HOST PORT */
+	pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
+			   USB_PORT_BACK_PANEL);
+	/* P2: RAIDEN */
+	pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P3: SD CARD */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P4: RAIDEN */
+	pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_BACK_PANEL);
+	/* P5: WWAN (Disabled) */
+	pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
+			   USB_PORT_SKIP);
+	/* P6: CAMERA */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: BT */
+	pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+
+	/* P1: HOST PORT */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: HOST PORT */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: RAIDEN */
+	pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+	/* P4: RAIDEN */
+	pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
+}
+
+static unsigned long get_top_of_ram(struct udevice *dev)
+{
+	/*
+	 * Base of DPR is top of usable DRAM below 4GiB. The register has
+	 * 1 MiB alignment and reports the TOP of the range, the base
+	 * must be calculated from the size in MiB in bits 11:4.
+	 */
+	u32 dpr, tom;
+
+	dm_pci_read_config32(dev, DPR, &dpr);
+	tom = dpr & ~((1 << 20) - 1);
+
+	debug("dpt %08x tom %08x\n", dpr, tom);
+	/* Subtract DMA Protected Range size if enabled */
+	if (dpr & DPR_EPM)
+		tom -= (dpr & DPR_SIZE_MASK) << 16;
+
+	return (unsigned long)tom;
+}
+
+/**
+ * sdram_find() - Find available memory
+ *
+ * This is a bit complicated since on x86 there are system memory holes all
+ * over the place. We create a list of available memory blocks
+ *
+ * @dev:	Northbridge device
+ */
+static int sdram_find(struct udevice *dev)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	ulong top_of_ram;
+
+	top_of_ram = get_top_of_ram(dev);
+	mrc_add_memory_area(info, 0, top_of_ram);
+
+	/* Add MTRRs for memory */
+	mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
+
+	return 0;
+}
+
+static int prepare_mrc_cache(struct pei_data *pei_data)
+{
+	struct mrc_data_container *mrc_cache;
+	struct mrc_region entry;
+	int ret;
+
+	ret = mrccache_get_region(NULL, &entry);
+	if (ret)
+		return ret;
+	mrc_cache = mrccache_find_current(&entry);
+	if (!mrc_cache)
+		return -ENOENT;
+
+	pei_data->saved_data = mrc_cache->data;
+	pei_data->saved_data_size = mrc_cache->data_size;
+	debug("%s: at %p, size %x checksum %04x\n", __func__,
+	      pei_data->saved_data, pei_data->saved_data_size,
+	      mrc_cache->checksum);
+
+	return 0;
+}
+
+int reserve_arch(void)
+{
+	return mrccache_reserve();
+}
+
+int dram_init(void)
+{
+	struct pei_data _pei_data __aligned(8);
+	struct pei_data *pei_data = &_pei_data;
+	struct udevice *dev, *me_dev, *pch_dev;
+	struct chipset_power_state ps;
+	const void *spd_data;
+	int ret, size;
+
+	memset(pei_data, '\0', sizeof(struct pei_data));
+
+	/* Print ME state before MRC */
+	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
+	if (ret)
+		return ret;
+	intel_me_status(me_dev);
+
+	/* Save ME HSIO version */
+	ret = uclass_first_device(UCLASS_PCH, &pch_dev);
+	if (ret)
+		return ret;
+	if (!pch_dev)
+		return -ENODEV;
+	power_state_get(pch_dev, &ps);
+
+	intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
+
+	broadwell_fill_pei_data(pei_data);
+	mainboard_fill_pei_data(pei_data);
+
+	ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+	if (ret)
+		return ret;
+	if (!dev)
+		return -ENODEV;
+	size = 256;
+	ret = mrc_locate_spd(dev, size, &spd_data);
+	if (ret)
+		return ret;
+	memcpy(pei_data->spd_data[0][0], spd_data, size);
+	memcpy(pei_data->spd_data[1][0], spd_data, size);
+
+	ret = prepare_mrc_cache(pei_data);
+	if (ret)
+		debug("prepare_mrc_cache failed: %d\n", ret);
+
+	debug("PEI version %#x\n", pei_data->pei_version);
+	ret = mrc_common_init(dev, pei_data, true);
+	if (ret)
+		return ret;
+	debug("Memory init done\n");
+
+	ret = sdram_find(dev);
+	if (ret)
+		return ret;
+	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
+	debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
+
+	debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
+	      pei_data->data_to_save);
+	/* S3 resume: don't save scrambler seed or MRC data */
+	if (pei_data->boot_mode != SLEEP_STATE_S3) {
+		/*
+		 * This will be copied to SDRAM in reserve_arch(), then written
+		 * to SPI flash in mrccache_save()
+		 */
+		gd->arch.mrc_output = (char *)pei_data->data_to_save;
+		gd->arch.mrc_output_len = pei_data->data_to_save_size;
+	}
+	gd->arch.pei_meminfo = pei_data->meminfo;
+
+	return 0;
+}
+
+/* Use this hook to save our SDRAM parameters */
+int misc_init_r(void)
+{
+	int ret;
+
+	ret = mrccache_save();
+	if (ret)
+		printf("Unable to save MRC data: %d\n", ret);
+	else
+		debug("Saved MRC cache data\n");
+
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	struct udevice *bus = NULL;
+
+	/* com1 / com2 decode range */
+	pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
+
+	pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
+			     PCI_SIZE_16);
+}
+
+static const struct udevice_id broadwell_syscon_ids[] = {
+	{ .compatible = "intel,me", .data = X86_SYSCON_ME },
+	{ .compatible = "intel,gma", .data = X86_SYSCON_GMA },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_intel_me) = {
+	.name = "intel_me_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = broadwell_syscon_ids,
+};
diff --git a/arch/x86/include/asm/arch-broadwell/pei_data.h b/arch/x86/include/asm/arch-broadwell/pei_data.h
new file mode 100644
index 0000000..b2cc8b8
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell/pei_data.h
@@ -0,0 +1,177 @@
+/*
+ * From Coreboot soc/intel/broadwell/include/soc/pei_data.h
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+#include <linux/linkage.h>
+
+#define PEI_VERSION 22
+
+typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
+
+enum board_type {
+	BOARD_TYPE_CRB_MOBILE = 0,	/* CRB Mobile */
+	BOARD_TYPE_CRB_DESKTOP,		/* CRB Desktop */
+	BOARD_TYPE_USER1,		/* SV mobile */
+	BOARD_TYPE_USER2,		/* SV desktop */
+	BOARD_TYPE_USER3,		/* SV server */
+	BOARD_TYPE_ULT,			/* ULT */
+	BOARD_TYPE_CRB_EMBDEDDED,	/* CRB Embedded */
+	BOARD_TYPE_UNKNOWN,
+};
+
+#define MAX_USB2_PORTS 14
+#define MAX_USB3_PORTS 6
+#define USB_OC_PIN_SKIP 8
+
+enum usb2_port_location {
+	USB_PORT_BACK_PANEL = 0,
+	USB_PORT_FRONT_PANEL,
+	USB_PORT_DOCK,
+	USB_PORT_MINI_PCIE,
+	USB_PORT_FLEX,
+	USB_PORT_INTERNAL,
+	USB_PORT_SKIP,
+	USB_PORT_NGFF_DEVICE_DOWN,
+};
+
+struct usb2_port_setting {
+	/*
+	 * Usb Port Length:
+	 * [16:4] = length in inches in octal format
+	 * [3:0]  = decimal point
+	 */
+	uint16_t length;
+	uint8_t enable;
+	uint8_t oc_pin;
+	uint8_t location;
+} __packed;
+
+struct usb3_port_setting {
+	uint8_t enable;
+	uint8_t oc_pin;
+	/*
+	 * Set to 0 if trace length is > 5 inches
+	 * Set to 1 if trace length is <= 5 inches
+	 */
+	uint8_t fixed_eq;
+} __packed;
+
+
+struct pei_data {
+	uint32_t pei_version;
+
+	enum board_type board_type;
+	int boot_mode;
+	int ec_present;
+	int usbdebug;
+
+	/* Base addresses */
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t xhcibar;
+	uint32_t ehcibar;
+	uint32_t gttbar;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t temp_mmio_base;
+	uint32_t tseg_size;
+
+	/*
+	 * 0 = leave channel enabled
+	 * 1 = disable dimm 0 on channel
+	 * 2 = disable dimm 1 on channel
+	 * 3 = disable dimm 0+1 on channel
+	 */
+	int dimm_channel0_disabled;
+	int dimm_channel1_disabled;
+	/* Set to 0 for memory down */
+	uint8_t spd_addresses[4];
+	/* Enable 2x Refresh Mode */
+	int ddr_refresh_2x;
+	/* DQ pins are interleaved on board */
+	int dq_pins_interleaved;
+	/* Limit DDR3 frequency */
+	int max_ddr3_freq;
+	/* Disable self refresh */
+	int disable_self_refresh;
+	/* Disable cmd power/CKEPD */
+	int disable_cmd_pwr;
+
+	/* USB port configuration */
+	struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
+	struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
+
+	/*
+	 * USB3 board specific PHY tuning
+	 */
+
+	/* Valid range: 0x69 - 0x80 */
+	uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x80 - 0x9c */
+	uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x39 - 0x80 */
+	uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
+	/* Valid range: 0x3d - 0x4a */
+	uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
+
+	/* Console output function */
+	tx_byte_func tx_byte;
+
+	/*
+	 * DIMM SPD data for memory down configurations
+	 * [CHANNEL][SLOT][SPD]
+	 */
+	uint8_t spd_data[2][2][512];
+
+	/*
+	 * LPDDR3 DQ byte map
+	 * [CHANNEL][ITERATION][2]
+	 *
+	 * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
+	 * DQByteMap[0] - ClkDQByteMap:
+	 * - If clock is per rank, program to [0xFF, 0xFF]
+	 * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+	 * - If clock is shared by 2 ranks but does not go to all bytes,
+	 *   Entry[i] defines which DQ bytes Group i services
+	 * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
+	 * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
+	 * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
+	 *                For DDR, DQByteMap[3:1] = [0xFF, 0]
+	 * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
+	 *                since we have 1 CTL / rank
+	 * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
+	 *                since we have 1 CA Vref
+	 */
+	uint8_t dq_map[2][6][2];
+
+	/*
+	 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
+	 * [CHANNEL][MAX_BYTES]
+	 */
+	uint8_t dqs_map[2][8];
+
+	/* Data read from flash and passed into MRC */
+	const void *saved_data;
+	int saved_data_size;
+
+	/* Disable use of saved data (can be set by mainboard) */
+	int disable_saved_data;
+
+	/* Data from MRC that should be saved to flash */
+	void *data_to_save;
+	int data_to_save_size;
+	struct pei_memory_info meminfo;
+} __packed;
+
+void mainboard_fill_pei_data(struct pei_data *pei_data);
+void broadwell_fill_pei_data(struct pei_data *pei_data);
+
+#endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 0ca518c..3bc2ac2 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -19,6 +19,29 @@ enum pei_boot_mode_t {
 
 };
 
+struct dimm_info {
+	uint32_t dimm_size;
+	uint16_t ddr_type;
+	uint16_t ddr_frequency;
+	uint8_t rank_per_dimm;
+	uint8_t channel_num;
+	uint8_t dimm_num;
+	uint8_t bank_locator;
+	/* The 5th byte is '\0' for the end of string */
+	uint8_t serial[5];
+	/* The 19th byte is '\0' for the end of string */
+	uint8_t module_part_number[19];
+	uint16_t mod_id;
+	uint8_t mod_type;
+	uint8_t bus_width;
+} __packed;
+
+struct pei_memory_info {
+	uint8_t dimm_cnt;
+	/* Maximum num of dimm is 8 */
+	struct dimm_info dimm[8];
+} __packed;
+
 struct memory_area {
 	uint64_t start;
 	uint64_t size;
@@ -59,6 +82,7 @@ struct arch_global_data {
 	enum pei_boot_mode_t pei_boot_mode;
 	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
 	struct memory_info meminfo;	/* Memory information */
+	struct pei_memory_info pei_meminfo;	/* PEI memory information */
 #ifdef CONFIG_HAVE_FSP
 	void *hob_list;			/* FSP HOB list */
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 42/51] x86: broadwell: Add a GPIO driver

[Simon Glass]

Add a GPIO driver for the GPIO peripheral found on broadwell devices.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Use setio_32() instead of setio_le32(), etc.
- Fix 'configure' typo

 drivers/gpio/Kconfig                |   9 ++
 drivers/gpio/Makefile               |   1 +
 drivers/gpio/intel_broadwell_gpio.c | 198 ++++++++++++++++++++++++++++++++++++
 3 files changed, 208 insertions(+)
 create mode 100644 drivers/gpio/intel_broadwell_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 94fabb9..a5da5e7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -39,6 +39,15 @@ config ATMEL_PIO4
 	  may be dedicated as a general purpose I/O or be assigned to
 	  a function of an embedded peripheral.
 
+config INTEL_BROADWELL_GPIO
+	bool "Intel Broadwell GPIO driver"
+	depends on DM
+	help
+	  This driver supports Broadwell U devices which have an expanded
+	  GPIO feature set. The difference is large enough to merit a separate
+	  driver from the common Intel ICH6 driver. It supports a total of
+	  95 GPIOs which can be configured from the device tree.
+
 config LPC32XX_GPIO
 	bool "LPC32XX GPIO driver"
 	depends on DM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ca8c487..e7b7ec4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_DM_GPIO)		+= gpio-uclass.o
 obj-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 obj-$(CONFIG_ATMEL_PIO4)	+= atmel_pio4.o
 obj-$(CONFIG_INTEL_ICH6_GPIO)	+= intel_ich6_gpio.o
+obj-$(CONFIG_INTEL_BROADWELL_GPIO)	+= intel_broadwell_gpio.o
 obj-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
 obj-$(CONFIG_KONA_GPIO)	+= kona_gpio.o
 obj-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
diff --git a/drivers/gpio/intel_broadwell_gpio.c b/drivers/gpio/intel_broadwell_gpio.c
new file mode 100644
index 0000000..8cf76f9
--- /dev/null
+++ b/drivers/gpio/intel_broadwell_gpio.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>
+#include <pci.h>
+#include <syscon.h>
+#include <asm/cpu.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/arch/gpio.h>
+#include <dt-bindings/gpio/x86-gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct broadwell_bank_priv - Private driver data
+ *
+ * @regs:	Pointer to GPIO registers
+ * @bank:	Bank number for this bank (0, 1 or 2)
+ * @offset:	GPIO offset for this bank (0, 32 or 64)
+ */
+struct broadwell_bank_priv {
+	struct pch_lp_gpio_regs *regs;
+	int bank;
+	int offset;
+};
+
+static int broadwell_gpio_request(struct udevice *dev, unsigned offset,
+			     const char *label)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+	u32 val;
+
+	/*
+	 * Make sure that the GPIO pin we want isn't already in use for some
+	 * built-in hardware function. We have to check this for every
+	 * requested pin.
+	 */
+	debug("%s: request bank %d offset %d: ", __func__, priv->bank, offset);
+	val = inl(&regs->own[priv->bank]);
+	if (!(val & (1UL << offset))) {
+		debug("gpio is reserved for internal use\n");
+		return -EPERM;
+	}
+	debug("ok\n");
+
+	return 0;
+}
+
+static int broadwell_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	setio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
+
+	return 0;
+}
+
+static int broadwell_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	return inl(&regs->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ?
+		1 : 0;
+}
+
+static int broadwell_gpio_set_value(struct udevice *dev, unsigned offset,
+				    int value)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	debug("%s: dev=%s, offset=%d, value=%d\n", __func__, dev->name, offset,
+	      value);
+	clrsetio_32(&regs->config[priv->offset + offset], CONFA_OUTPUT_HIGH,
+		      value ? CONFA_OUTPUT_HIGH : 0);
+
+	return 0;
+}
+
+static int broadwell_gpio_direction_output(struct udevice *dev, unsigned offset,
+					   int value)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+
+	broadwell_gpio_set_value(dev, offset, value);
+	clrio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT);
+
+	return 0;
+}
+
+static int broadwell_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct pch_lp_gpio_regs *regs = priv->regs;
+	u32 mask = 1UL << offset;
+
+	if (!(inl(&regs->own[priv->bank]) & mask))
+		return GPIOF_FUNC;
+	if (inl(&regs->config[priv->offset + offset]) & CONFA_DIR_INPUT)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int broadwell_gpio_probe(struct udevice *dev)
+{
+	struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct broadwell_bank_priv *priv = dev_get_priv(dev);
+	struct udevice *pinctrl;
+	int ret;
+
+	/* Set up pin control if available */
+	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
+	debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
+
+	uc_priv->gpio_count = GPIO_PER_BANK;
+	uc_priv->bank_name = plat->bank_name;
+
+	priv->regs = (struct pch_lp_gpio_regs *)(uintptr_t)plat->base_addr;
+	priv->bank = plat->bank;
+	priv->offset = priv->bank * 32;
+	debug("%s: probe done, regs %p, bank %d\n", __func__, priv->regs,
+	      priv->bank);
+
+	return 0;
+}
+
+static int broadwell_gpio_ofdata_to_platdata(struct udevice *dev)
+{
+	struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
+	u32 gpiobase;
+	int bank;
+	int ret;
+
+	ret = pch_get_gpio_base(dev->parent, &gpiobase);
+	if (ret)
+		return ret;
+
+	bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+	if (bank == -1) {
+		debug("%s: Invalid bank number %d\n", __func__, bank);
+		return -EINVAL;
+	}
+	plat->bank = bank;
+	plat->base_addr = gpiobase;
+	plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+				      "bank-name", NULL);
+
+	return 0;
+}
+
+static int broadwell_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+				struct fdtdec_phandle_args *args)
+{
+	desc->offset = args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_broadwell_ops = {
+	.request		= broadwell_gpio_request,
+	.direction_input	= broadwell_gpio_direction_input,
+	.direction_output	= broadwell_gpio_direction_output,
+	.get_value		= broadwell_gpio_get_value,
+	.set_value		= broadwell_gpio_set_value,
+	.get_function		= broadwell_gpio_get_function,
+	.xlate			= broadwell_gpio_xlate,
+};
+
+static const struct udevice_id intel_broadwell_gpio_ids[] = {
+	{ .compatible = "intel,broadwell-gpio" },
+	{ }
+};
+
+U_BOOT_DRIVER(gpio_broadwell) = {
+	.name	= "gpio_broadwell",
+	.id	= UCLASS_GPIO,
+	.of_match = intel_broadwell_gpio_ids,
+	.ops	= &gpio_broadwell_ops,
+	.ofdata_to_platdata	= broadwell_gpio_ofdata_to_platdata,
+	.probe	= broadwell_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct broadwell_bank_priv),
+	.platdata_auto_alloc_size = sizeof(struct broadwell_bank_platdata),
+};
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 43/51] x86: broadwell: Add support for high-speed I/O lane with ME

[Simon Glass]

Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/broadwell/Makefile |  1 +
 arch/x86/cpu/broadwell/me.c     | 57 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 arch/x86/cpu/broadwell/me.c

diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/broadwell/Makefile
index 012798f..7edb6f6 100644
--- a/arch/x86/cpu/broadwell/Makefile
+++ b/arch/x86/cpu/broadwell/Makefile
@@ -7,6 +7,7 @@
 obj-y += cpu.o
 obj-y += iobp.o
 obj-y += lpc.o
+obj-y += me.o
 obj-y += northbridge.o
 obj-y += pch.o
 obj-y += pinctrl_broadwell.o
diff --git a/arch/x86/cpu/broadwell/me.c b/arch/x86/cpu/broadwell/me.c
new file mode 100644
index 0000000..e03b87c
--- /dev/null
+++ b/arch/x86/cpu/broadwell/me.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Based on code from coreboot src/soc/intel/broadwell/me_status.c
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/me.h>
+
+static inline void me_read_dword_ptr(struct udevice *dev, void *ptr, int offset)
+{
+	u32 dword;
+
+	dm_pci_read_config32(dev, offset, &dword);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+int intel_me_hsio_version(struct udevice *dev, uint16_t *versionp,
+			  uint16_t *checksump)
+{
+	int count;
+	u32 hsiover;
+	struct me_hfs hfs;
+
+	/* Query for HSIO version, overloads H_GS and HFS */
+	dm_pci_write_config32(dev, PCI_ME_H_GS,
+			      ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+	/* Must wait for ME acknowledgement */
+	for (count = ME_RETRY; count > 0; --count) {
+		me_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+		if (hfs.bios_msg_ack)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		debug("ERROR: ME failed to respond\n");
+		return -ETIMEDOUT;
+	}
+
+	/* HSIO version should be in HFS_5 */
+	dm_pci_read_config32(dev, PCI_ME_HFS5, &hsiover);
+	*versionp = hsiover >> 16;
+	*checksump = hsiover & 0xffff;
+
+	debug("ME: HSIO Version            : %d (CRC 0x%04x)\n",
+	      *versionp, *checksump);
+
+	/* Reset registers to normal behavior */
+	dm_pci_write_config32(dev, PCI_ME_H_GS,
+			      ME_HSIO_MESSAGE | ME_HSIO_CMD_GETHSIOVER);
+
+	return 0;
+}
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 44/51] x86: Support a chained-boot development flow

[Simon Glass]

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/start.S | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 485868f..5fbc2b5 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -18,6 +18,13 @@
 #include <generated/generic-asm-offsets.h>
 #include <generated/asm-offsets.h>
 
+/*
+ * Define this to boot U-Boot from a 32-bit program which sets the GDT
+ * differently. This can be used to boot directly from coreboot, for example.
+ * This is only useful for development.
+ */
+#undef LOAD_FROM_32_BIT
+
 .section .text
 .code32
 .globl _start
@@ -68,6 +75,10 @@ _start:
 	/* Save table pointer */
 	movl	%ecx, %esi
 
+#ifdef LOAD_FROM_32_BIT
+	lgdt	gdt_ptr2
+#endif
+
 	/* Load the segement registers to match the GDT loaded in start16.S */
 	movl	$(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax
 	movw	%ax, %fs
@@ -220,3 +231,71 @@ multiboot_header:
 	.long	0
 	/* entry addr */
 	.long	CONFIG_SYS_TEXT_BASE
+
+#ifdef LOAD_FROM_32_BIT
+	/*
+	 * The following Global Descriptor Table is just enough to get us into
+	 * 'Flat Protected Mode' - It will be discarded as soon as the final
+	 * GDT is setup in a safe location in RAM
+	 */
+gdt_ptr2:
+	.word	0x1f		/* limit (31 bytes = 4 GDT entries - 1) */
+	.long	gdt_rom2	/* base */
+
+	/* Some CPUs are picky about GDT alignment... */
+	.align	16
+.globl gdt_rom2
+gdt_rom2:
+	/*
+	 * The GDT table ...
+	 *
+	 *	 Selector	Type
+	 *	 0x00		NULL
+	 *	 0x08		Unused
+	 *	 0x10		32bit code
+	 *	 0x18		32bit data/stack
+	 */
+	/* The NULL Desciptor - Mandatory */
+	.word	0x0000		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x00		/* access */
+	.byte	0x00		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+
+	/* Unused Desciptor - (matches Linux) */
+	.word	0x0000		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x00		/* access */
+	.byte	0x00		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+
+	/*
+	 * The Code Segment Descriptor:
+	 * - Base   = 0x00000000
+	 * - Size   = 4GB
+	 * - Access = Present, Ring 0, Exec (Code), Readable
+	 * - Flags  = 4kB Granularity, 32-bit
+	 */
+	.word	0xffff		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x9b		/* access */
+	.byte	0xcf		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+
+	/*
+	 * The Data Segment Descriptor:
+	 * - Base   = 0x00000000
+	 * - Size   = 4GB
+	 * - Access = Present, Ring 0, Non-Exec (Data), Writable
+	 * - Flags  = 4kB Granularity, 32-bit
+	 */
+	.word	0xffff		/* limit_low */
+	.word	0x0000		/* base_low */
+	.byte	0x00		/* base_middle */
+	.byte	0x93		/* access */
+	.byte	0xcf		/* flags + limit_high */
+	.byte	0x00		/* base_high */
+#endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 45/51] x86: broadwell: Add video support

[Simon Glass]

Add a video driver for Intel's broadwell integrated graphics controller.
This uses a binary blob for most init, with the driver just performing a few
basic tasks.

This driver supports VESA as the mode-setting mechanism. Since most boards
don't support driver model yet with VESA, a special case is added to the
Kconfig for broadwell. Eventually all boards will use driver model and this
can be removed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 drivers/video/Kconfig         |  14 +-
 drivers/video/Makefile        |   2 +
 drivers/video/broadwell_igd.c | 797 ++++++++++++++++++++++++++++++++++++++++++
 drivers/video/i915_reg.h      | 362 +++++++++++++++++++
 4 files changed, 1174 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/broadwell_igd.c
 create mode 100644 drivers/video/i915_reg.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ff4179f..8361a71 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -112,7 +112,7 @@ config VIDEO_VESA
 
 config FRAMEBUFFER_SET_VESA_MODE
 	bool "Set framebuffer graphics resolution"
-	depends on VIDEO_VESA
+	depends on VIDEO_VESA || VIDEO_BROADWELL_IGD
 	help
 	  Set VESA/native framebuffer mode (needed for bootsplash and graphical
 	  framebuffer console)
@@ -362,6 +362,18 @@ config DISPLAY
 	   The devices provide a simple interface to start up the display,
 	   read display information and enable it.
 
+config VIDEO_BROADWELL_IGD
+	bool "Enable Intel Broadwell integrated graphics device"
+	depends on X86
+	help
+	  This enabled support for integrated graphics on Intel broadwell
+	  devices. Initialisation is mostly performed by a VGA boot ROM, with
+	  some setup handled by U-Boot itself. The graphics adaptor works as
+	  a VESA device and supports LCD panels, eDP and LVDS outputs.
+	  Configuration of most aspects of device operation is performed using
+	  a special tool which configures the VGA ROM, but the graphics
+	  resolution can be selected in U-Boot.
+
 config VIDEO_ROCKCHIP
 	bool "Enable Rockchip video support"
 	depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9b635fc..2fd0891 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -19,6 +19,8 @@ obj-$(CONFIG_CONSOLE_ROTATION) += console_rotate.o
 obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
 endif
 
+obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
+
 obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
diff --git a/drivers/video/broadwell_igd.c b/drivers/video/broadwell_igd.c
new file mode 100644
index 0000000..ce4f296
--- /dev/null
+++ b/drivers/video/broadwell_igd.c
@@ -0,0 +1,797 @@
+/*
+ * From coreboot src/soc/intel/broadwell/igd.c
+ *
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <bios_emul.h>
+#include <dm.h>
+#include <pci_rom.h>
+#include <vbe.h>
+#include <video.h>
+#include <video_fb.h>
+#include <asm/cpu.h>
+#include <asm/intel_regs.h>
+#include <asm/io.h>
+#include <asm/mtrr.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/iomap.h>
+#include <asm/arch/pch.h>
+#include <linux/log2.h>
+#include "i915_reg.h"
+
+struct broadwell_igd_priv {
+	GraphicDevice ctfb;
+	u8 *regs;
+};
+
+struct broadwell_igd_plat {
+	u32 dp_hotplug[3];
+
+	int port_select;
+	int power_up_delay;
+	int power_backlight_on_delay;
+	int power_down_delay;
+	int power_backlight_off_delay;
+	int power_cycle_delay;
+	int cpu_backlight;
+	int pch_backlight;
+	int cdclk;
+	int pre_graphics_delay;
+};
+
+#define GT_RETRY		1000
+#define GT_CDCLK_337		0
+#define GT_CDCLK_450		1
+#define GT_CDCLK_540		2
+#define GT_CDCLK_675		3
+
+u32 board_map_oprom_vendev(u32 vendev)
+{
+	return SA_IGD_OPROM_VENDEV;
+}
+
+static int poll32(u8 *addr, uint mask, uint value)
+{
+	ulong start;
+
+	start = get_timer(0);
+	debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
+	while ((readl(addr) & mask) != value) {
+		if (get_timer(start) > GT_RETRY) {
+			debug("poll32: timeout: %x\n", readl(addr));
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int haswell_early_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Enable Force Wake */
+	writel(0x00000020, regs + 0xa180);
+	writel(0x00010001, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 1);
+	if (ret)
+		goto err;
+
+	/* Enable Counters */
+	setbits_le32(regs + 0xa248, 0x00000016);
+
+	/* GFXPAUSE settings */
+	writel(0x00070020, regs + 0xa000);
+
+	/* ECO Settings */
+	clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
+
+	/* Enable DOP Clock Gating */
+	writel(0x000003fd, regs + 0x9424);
+
+	/* Enable Unit Level Clock Gating */
+	writel(0x00000080, regs + 0x9400);
+	writel(0x40401000, regs + 0x9404);
+	writel(0x00000000, regs + 0x9408);
+	writel(0x02000001, regs + 0x940c);
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	setbits_le32(regs + 0xa090, 0x00000000);
+	setbits_le32(regs + 0xa098, 0x03e80000);
+	setbits_le32(regs + 0xa09c, 0x00280000);
+	setbits_le32(regs + 0xa0a8, 0x0001e848);
+	setbits_le32(regs + 0xa0ac, 0x00000019);
+
+	/* Render/Video/Blitter Idle Max Count */
+	writel(0x0000000a, regs + 0x02054);
+	writel(0x0000000a, regs + 0x12054);
+	writel(0x0000000a, regs + 0x22054);
+	writel(0x0000000a, regs + 0x1a054);
+
+	/* RC Sleep / RCx Thresholds */
+	setbits_le32(regs + 0xa0b0, 0x00000000);
+	setbits_le32(regs + 0xa0b4, 0x000003e8);
+	setbits_le32(regs + 0xa0b8, 0x0000c350);
+
+	/* RP Settings */
+	setbits_le32(regs + 0xa010, 0x000f4240);
+	setbits_le32(regs + 0xa014, 0x12060000);
+	setbits_le32(regs + 0xa02c, 0x0000e808);
+	setbits_le32(regs + 0xa030, 0x0003bd08);
+	setbits_le32(regs + 0xa068, 0x000101d0);
+	setbits_le32(regs + 0xa06c, 0x00055730);
+	setbits_le32(regs + 0xa070, 0x0000000a);
+
+	/* RP Control */
+	writel(0x00000b92, regs + 0xa024);
+
+	/* HW RC6 Control */
+	writel(0x88040000, regs + 0xa090);
+
+	/* Video Frequency Request */
+	writel(0x08000000, regs + 0xa00c);
+
+	/* Set RC6 VIDs */
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+	writel(0, regs + 0x138128);
+	writel(0x80000004, regs + 0x138124);
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+
+	/* Enable PM Interrupts */
+	writel(0x03000076, regs + 0x4402c);
+
+	/* Enable RC6 in idle */
+	writel(0x00040000, regs + 0xa094);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+static int haswell_late_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Lock settings */
+	setbits_le32(regs + 0x0a248, (1 << 31));
+	setbits_le32(regs + 0x0a004, (1 << 4));
+	setbits_le32(regs + 0x0a080, (1 << 2));
+	setbits_le32(regs + 0x0a180, (1 << 31));
+
+	/* Disable Force Wake */
+	writel(0x00010000, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 0);
+	if (ret)
+		goto err;
+	writel(0x00000001, regs + 0xa188);
+
+	/* Enable power well for DP and Audio */
+	setbits_le32(regs + 0x45400, (1 << 31));
+	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+static int broadwell_early_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Enable Force Wake */
+	writel(0x00010001, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 1);
+	if (ret)
+		goto err;
+
+	/* Enable push bus metric control and shift */
+	writel(0x00000004, regs + 0xa248);
+	writel(0x000000ff, regs + 0xa250);
+	writel(0x00000010, regs + 0xa25c);
+
+	/* GFXPAUSE settings (set based on stepping) */
+
+	/* ECO Settings */
+	writel(0x45200000, regs + 0xa180);
+
+	/* Enable DOP Clock Gating */
+	writel(0x000000fd, regs + 0x9424);
+
+	/* Enable Unit Level Clock Gating */
+	writel(0x00000000, regs + 0x9400);
+	writel(0x40401000, regs + 0x9404);
+	writel(0x00000000, regs + 0x9408);
+	writel(0x02000001, regs + 0x940c);
+	writel(0x0000000a, regs + 0x1a054);
+
+	/* Video Frequency Request */
+	writel(0x08000000, regs + 0xa00c);
+
+	writel(0x00000009, regs + 0x138158);
+	writel(0x0000000d, regs + 0x13815c);
+
+	/*
+	 * RC6 Settings
+	 */
+
+	/* Wake Rate Limits */
+	clrsetbits_le32(regs + 0x0a090, ~0, 0);
+	setbits_le32(regs + 0x0a098, 0x03e80000);
+	setbits_le32(regs + 0x0a09c, 0x00280000);
+	setbits_le32(regs + 0x0a0a8, 0x0001e848);
+	setbits_le32(regs + 0x0a0ac, 0x00000019);
+
+	/* Render/Video/Blitter Idle Max Count */
+	writel(0x0000000a, regs + 0x02054);
+	writel(0x0000000a, regs + 0x12054);
+	writel(0x0000000a, regs + 0x22054);
+
+	/* RC Sleep / RCx Thresholds */
+	setbits_le32(regs + 0x0a0b0, 0x00000000);
+	setbits_le32(regs + 0x0a0b8, 0x00000271);
+
+	/* RP Settings */
+	setbits_le32(regs + 0x0a010, 0x000f4240);
+	setbits_le32(regs + 0x0a014, 0x12060000);
+	setbits_le32(regs + 0x0a02c, 0x0000e808);
+	setbits_le32(regs + 0x0a030, 0x0003bd08);
+	setbits_le32(regs + 0x0a068, 0x000101d0);
+	setbits_le32(regs + 0x0a06c, 0x00055730);
+	setbits_le32(regs + 0x0a070, 0x0000000a);
+	setbits_le32(regs + 0x0a168, 0x00000006);
+
+	/* RP Control */
+	writel(0x00000b92, regs + 0xa024);
+
+	/* HW RC6 Control */
+	writel(0x90040000, regs + 0xa090);
+
+	/* Set RC6 VIDs */
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+	writel(0, regs + 0x138128);
+	writel(0x80000004, regs + 0x138124);
+	ret = poll32(regs + 0x138124, (1 << 31), 0);
+	if (ret)
+		goto err;
+
+	/* Enable PM Interrupts */
+	writel(0x03000076, regs + 0x4402c);
+
+	/* Enable RC6 in idle */
+	writel(0x00040000, regs + 0xa094);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int broadwell_late_init(struct udevice *dev)
+{
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u8 *regs = priv->regs;
+	int ret;
+
+	/* Lock settings */
+	setbits_le32(regs + 0x0a248, 1 << 31);
+	setbits_le32(regs + 0x0a000, 1 << 18);
+	setbits_le32(regs + 0x0a180, 1 << 31);
+
+	/* Disable Force Wake */
+	writel(0x00010000, regs + 0xa188);
+	ret = poll32(regs + 0x130044, 1, 0);
+	if (ret)
+		goto err;
+
+	/* Enable power well for DP and Audio */
+	setbits_le32(regs + 0x45400, 1 << 31);
+	ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
+	if (ret)
+		goto err;
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+};
+
+
+static unsigned long gtt_read(struct broadwell_igd_priv *priv,
+			      unsigned long reg)
+{
+	u32 val;
+
+	val = readl(priv->regs + reg);
+	return val;
+}
+
+static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
+		      unsigned long data)
+{
+	writel(data, priv->regs + reg);
+}
+
+static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
+				  u32 bic, u32 or)
+{
+	clrsetbits_le32(priv->regs + reg, bic, or);
+}
+
+static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
+		    u32 value)
+{
+	unsigned try = GT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(priv, reg);
+		if ((data & mask) == value)
+			return 0;
+		udelay(10);
+	}
+
+	debug("GT init timeout\n");
+	return -ETIMEDOUT;
+}
+
+static void igd_setup_panel(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u32 reg32;
+
+	/* Setup Digital Port Hotplug */
+	reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
+	reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
+	reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
+	gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
+
+	/* Setup Panel Power On Delays */
+	reg32 = (plat->port_select & 0x3) << 30;
+	reg32 |= (plat->power_up_delay & 0x1fff) << 16;
+	reg32 |= (plat->power_backlight_on_delay & 0x1fff);
+	gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
+
+	/* Setup Panel Power Off Delays */
+	reg32 = (plat->power_down_delay & 0x1fff) << 16;
+	reg32 |= (plat->power_backlight_off_delay & 0x1fff);
+	gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
+
+	/* Setup Panel Power Cycle Delay */
+	if (plat->power_cycle_delay) {
+		reg32 = gtt_read(priv, PCH_PP_DIVISOR);
+		reg32 &= ~0xff;
+		reg32 |= plat->power_cycle_delay & 0xff;
+		gtt_write(priv, PCH_PP_DIVISOR, reg32);
+	}
+
+	/* Enable Backlight if needed */
+	if (plat->cpu_backlight) {
+		gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
+		gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
+	}
+	if (plat->pch_backlight) {
+		gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
+		gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
+	}
+}
+
+static int igd_cdclk_init_haswell(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int cdclk = plat->cdclk;
+	u16 devid;
+	int gpu_is_ulx = 0;
+	u32 dpdiv, lpcll;
+	int ret;
+
+	dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
+
+	/* Check for ULX GT1 or GT2 */
+	if (devid == 0x0a0e || devid == 0x0a1e)
+		gpu_is_ulx = 1;
+
+	/* 675MHz is not supported on haswell */
+	if (cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_337;
+
+	/* If CD clock is fixed or ULT then set to 450MHz */
+	if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
+		cdclk = GT_CDCLK_450;
+
+	/* 540MHz is not supported on ULX */
+	if (gpu_is_ulx && cdclk == GT_CDCLK_540)
+		cdclk = GT_CDCLK_337;
+
+	/* 337.5MHz is not supported on non-ULT/ULX */
+	if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
+		cdclk = GT_CDCLK_450;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		dpdiv = 169;
+		lpcll = (1 << 26);
+		break;
+	case GT_CDCLK_450:
+		dpdiv = 225;
+		lpcll = 0;
+		break;
+	case GT_CDCLK_540:
+		dpdiv = 270;
+		lpcll = (1 << 26);
+		break;
+	default:
+		ret = -EDOM;
+		goto err;
+	}
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
+
+	/* ULX: Inform power controller of selected frequency */
+	if (gpu_is_ulx) {
+		if (cdclk == GT_CDCLK_450)
+			gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
+		else
+			gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
+		gtt_write(priv, 0x13812c, 0x00000000);
+		gtt_write(priv, 0x138124, 0x80000017);
+	}
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
+	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int igd_cdclk_init_broadwell(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int cdclk = plat->cdclk;
+	u32 dpdiv, lpcll, pwctl, cdset;
+	int ret;
+
+	/* Inform power controller of upcoming frequency change */
+	gtt_write(priv, 0x138128, 0);
+	gtt_write(priv, 0x13812c, 0);
+	gtt_write(priv, 0x138124, 0x80000018);
+
+	/* Poll GT driver mailbox for run/busy clear */
+	if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
+		cdclk = GT_CDCLK_450;
+
+	if (gtt_read(priv, 0x42014) & 0x1000000) {
+		/* If CD clock is fixed then set to 450MHz */
+		cdclk = GT_CDCLK_450;
+	} else {
+		/* Program CD clock to highest supported freq */
+		if (cpu_is_ult())
+			cdclk = GT_CDCLK_540;
+		else
+			cdclk = GT_CDCLK_675;
+	}
+
+	/* CD clock frequency 675MHz not supported on ULT */
+	if (cpu_is_ult() && cdclk == GT_CDCLK_675)
+		cdclk = GT_CDCLK_540;
+
+	/* Set variables based on CD Clock setting */
+	switch (cdclk) {
+	case GT_CDCLK_337:
+		cdset = 337;
+		lpcll = (1 << 27);
+		pwctl = 2;
+		dpdiv = 169;
+		break;
+	case GT_CDCLK_450:
+		cdset = 449;
+		lpcll = 0;
+		pwctl = 0;
+		dpdiv = 225;
+		break;
+	case GT_CDCLK_540:
+		cdset = 539;
+		lpcll = (1 << 26);
+		pwctl = 1;
+		dpdiv = 270;
+		break;
+	case GT_CDCLK_675:
+		cdset = 674;
+		lpcll = (1 << 26) | (1 << 27);
+		pwctl = 3;
+		dpdiv = 338;
+		break;
+	default:
+		ret = -EDOM;
+		goto err;
+	}
+	debug("%s: frequency = %d\n", __func__, cdclk);
+
+	/* Set LPCLL_CTL CD Clock Frequency Select */
+	gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
+
+	/* Inform power controller of selected frequency */
+	gtt_write(priv, 0x138128, pwctl);
+	gtt_write(priv, 0x13812c, 0);
+	gtt_write(priv, 0x138124, 0x80000017);
+
+	/* Program CD Clock Frequency */
+	gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
+
+	/* Set CPU DP AUX 2X bit clock dividers */
+	gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
+	gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+u8 systemagent_revision(struct udevice *bus)
+{
+	ulong val;
+
+	pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
+			    PCI_SIZE_32);
+
+	return val;
+}
+
+static int igd_pre_init(struct udevice *dev, bool is_broadwell)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	u32 rp1_gfx_freq;
+	int ret;
+
+	mdelay(plat->pre_graphics_delay);
+
+	/* Early init steps */
+	if (is_broadwell) {
+		ret = broadwell_early_init(dev);
+		if (ret)
+			goto err;
+
+		/* Set GFXPAUSE based on stepping */
+		if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
+		    systemagent_revision(pci_get_controller(dev)) <= 9) {
+			gtt_write(priv, 0xa000, 0x300ff);
+		} else {
+			gtt_write(priv, 0xa000, 0x30020);
+		}
+	} else {
+		ret = haswell_early_init(dev);
+		if (ret)
+			goto err;
+	}
+
+	/* Set RP1 graphics frequency */
+	rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
+	gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
+
+	/* Post VBIOS panel setup */
+	igd_setup_panel(dev);
+
+	return 0;
+err:
+	debug("%s: ret=%d\n", __func__, ret);
+	return ret;
+}
+
+static int igd_post_init(struct udevice *dev, bool is_broadwell)
+{
+	int ret;
+
+	/* Late init steps */
+	if (is_broadwell) {
+		ret = igd_cdclk_init_broadwell(dev);
+		if (ret)
+			return ret;
+		ret = broadwell_late_init(dev);
+		if (ret)
+			return ret;
+	} else {
+		igd_cdclk_init_haswell(dev);
+		ret = haswell_late_init(dev);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int broadwell_igd_int15_handler(void)
+{
+	int res = 0;
+
+	debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP)
+		 *  bit 2 = EFP
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP)
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000; /* Use video bios default */
+		res = 1;
+		break;
+	default:
+		debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
+		break;
+	}
+
+	return res;
+}
+
+static int broadwell_igd_probe(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	bool is_broadwell;
+	GraphicDevice *gdev = &priv->ctfb;
+	int bits_per_pixel;
+	int ret;
+
+	if (!ll_boot_init()) {
+		/*
+		 * If we are running from EFI or coreboot, this driver can't
+		 * work.
+		 */
+		printf("Not available (previous bootloader prevents it)\n");
+		return -EPERM;
+	}
+	is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
+	bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
+	debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
+	ret = igd_pre_init(dev, is_broadwell);
+	if (!ret) {
+		ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler,
+					  PCI_ROM_USE_NATIVE |
+					  PCI_ROM_ALLOW_FALLBACK);
+		if (ret) {
+			printf("failed to run video BIOS: %d\n", ret);
+			ret = -EIO;
+		}
+	}
+	if (!ret)
+		ret = igd_post_init(dev, is_broadwell);
+	bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
+	if (ret)
+		return ret;
+
+	if (vbe_get_video_info(gdev)) {
+		printf("No video mode configured\n");
+		return -ENXIO;
+	}
+
+	/* Use write-through for the graphics memory, 256MB */
+	ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20);
+	if (!ret)
+		ret = mtrr_commit(true);
+	if (ret && ret != -ENOSYS) {
+		printf("Failed to add MTRR: Display will be slow (err %d)\n",
+		       ret);
+	}
+
+	bits_per_pixel = gdev->gdfBytesPP * 8;
+	sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
+		bits_per_pixel);
+	printf("%s\n", gdev->modeIdent);
+	uc_priv->xsize = gdev->winSizeX;
+	uc_priv->ysize = gdev->winSizeY;
+	uc_priv->bpix = ilog2(bits_per_pixel);
+	plat->base = gdev->pciBase;
+	plat->size = gdev->memSize;
+	debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase,
+	      gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
+
+	return 0;
+}
+
+static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
+{
+	struct broadwell_igd_plat *plat = dev_get_platdata(dev);
+	struct broadwell_igd_priv *priv = dev_get_priv(dev);
+	int node = dev->of_offset;
+	const void *blob = gd->fdt_blob;
+
+	if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
+				 plat->dp_hotplug,
+				 ARRAY_SIZE(plat->dp_hotplug)))
+		return -EINVAL;
+	plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
+	plat->power_cycle_delay = fdtdec_get_int(blob, node,
+			"intel,power-cycle-delay", 0);
+	plat->power_up_delay = fdtdec_get_int(blob, node,
+			"intel,power-up-delay", 0);
+	plat->power_down_delay = fdtdec_get_int(blob, node,
+			"intel,power-down-delay", 0);
+	plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
+			"intel,power-backlight-on-delay", 0);
+	plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
+			"intel,power-backlight-off-delay", 0);
+	plat->cpu_backlight = fdtdec_get_int(blob, node,
+			"intel,cpu-backlight", 0);
+	plat->pch_backlight = fdtdec_get_int(blob, node,
+			"intel,pch-backlight", 0);
+	plat->pre_graphics_delay = fdtdec_get_int(blob, node,
+			"intel,pre-graphics-delay", 0);
+	priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
+	debug("%s: regs at %p\n", __func__, priv->regs);
+	debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
+	      plat->dp_hotplug[2]);
+	debug("port_select = %d\n", plat->port_select);
+	debug("power_up_delay = %d\n", plat->power_up_delay);
+	debug("power_backlight_on_delay = %d\n",
+	      plat->power_backlight_on_delay);
+	debug("power_down_delay = %d\n", plat->power_down_delay);
+	debug("power_backlight_off_delay = %d\n",
+	      plat->power_backlight_off_delay);
+	debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
+	debug("cpu_backlight = %x\n", plat->cpu_backlight);
+	debug("pch_backlight = %x\n", plat->pch_backlight);
+	debug("cdclk = %d\n", plat->cdclk);
+	debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
+
+	return 0;
+}
+
+static const struct video_ops broadwell_igd_ops = {
+};
+
+static const struct udevice_id broadwell_igd_ids[] = {
+	{ .compatible = "intel,broadwell-igd" },
+	{ }
+};
+
+U_BOOT_DRIVER(broadwell_igd) = {
+	.name	= "broadwell_igd",
+	.id	= UCLASS_VIDEO,
+	.of_match = broadwell_igd_ids,
+	.ops	= &broadwell_igd_ops,
+	.ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
+	.probe	= broadwell_igd_probe,
+	.priv_auto_alloc_size	= sizeof(struct broadwell_igd_priv),
+	.platdata_auto_alloc_size	= sizeof(struct broadwell_igd_plat),
+};
diff --git a/drivers/video/i915_reg.h b/drivers/video/i915_reg.h
new file mode 100644
index 0000000..f540b15
--- /dev/null
+++ b/drivers/video/i915_reg.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef _I915_REG_H_
+#define _I915_REG_H_
+
+/* Hotplug control (945+ only) */
+#define PORT_HOTPLUG_EN		0x61110
+#define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
+#define   DPB_HOTPLUG_INT_EN			(1 << 29)
+#define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
+#define   DPC_HOTPLUG_INT_EN			(1 << 28)
+#define   HDMID_HOTPLUG_INT_EN			(1 << 27)
+#define   DPD_HOTPLUG_INT_EN			(1 << 27)
+#define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
+#define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
+#define   TV_HOTPLUG_INT_EN			(1 << 18)
+#define   CRT_HOTPLUG_INT_EN			(1 << 9)
+#define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
+/* must use period 64 on GM45 according to docs */
+#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
+#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
+#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
+#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
+#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
+#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
+#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
+
+/* Backlight control */
+#define BLC_PWM_CTL2		0x61250 /* 965+ only */
+#define   BLM_PWM_ENABLE		(1 << 31)
+#define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
+#define   BLM_PIPE_SELECT		(1 << 29)
+#define   BLM_PIPE_SELECT_IVB		(3 << 29)
+#define   BLM_PIPE_A			(0 << 29)
+#define   BLM_PIPE_B			(1 << 29)
+#define   BLM_PIPE_C			(2 << 29) /* ivb + */
+#define   BLM_PIPE(pipe)		((pipe) << 29)
+#define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
+#define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
+#define   BLM_PHASE_IN_ENABLE		(1 << 25)
+#define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
+#define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
+#define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
+#define   BLM_PHASE_IN_COUNT_SHIFT	(8)
+#define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
+#define   BLM_PHASE_IN_INCR_SHIFT	(0)
+#define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
+#define BLC_PWM_CTL		0x61254
+/*
+ * This is the most significant 15 bits of the number of backlight cycles in a
+ * complete cycle of the modulated backlight control.
+ *
+ * The actual value is this field multiplied by two.
+ */
+#define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
+#define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
+#define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
+/*
+ * This is the number of cycles out of the backlight modulation cycle for which
+ * the backlight is on.
+ *
+ * This field must be no greater than the number of cycles in the complete
+ * backlight modulation cycle.
+ */
+#define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
+#define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
+#define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
+#define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
+
+#define BLC_HIST_CTL		0x61260
+
+/*
+ * New registers for PCH-split platforms. Safe where new bits show up, the
+ * register layout machtes with gen4 BLC_PWM_CTL[12]
+ */
+#define BLC_PWM_CPU_CTL2	0x48250
+#define  BLC_PWM2_ENABLE        (1<<31)
+#define BLC_PWM_CPU_CTL		0x48254
+
+#define BLM_HIST_CTL			0x48260
+#define  ENH_HIST_ENABLE		(1<<31)
+#define  ENH_MODIF_TBL_ENABLE		(1<<30)
+#define  ENH_PIPE_A_SELECT		(0<<29)
+#define  ENH_PIPE_B_SELECT		(1<<29)
+#define  ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
+#define  HIST_MODE_YUV			(0<<24)
+#define  HIST_MODE_HSV			(1<<24)
+#define  ENH_MODE_DIRECT		(0<<13)
+#define  ENH_MODE_ADDITIVE		(1<<13)
+#define  ENH_MODE_MULTIPLICATIVE	(2<<13)
+#define  BIN_REGISTER_SET		(1<<11)
+#define  ENH_NUM_BINS			32
+
+#define BLM_HIST_ENH			0x48264
+
+#define BLM_HIST_GUARD_BAND		0x48268
+#define  BLM_HIST_INTR_ENABLE		(1<<31)
+#define  BLM_HIST_EVENT_STATUS		(1<<30)
+#define  BLM_HIST_INTR_DELAY_MASK	(0xFF<<22)
+#define  BLM_HIST_INTR_DELAY_SHIFT	22
+
+/*
+ * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
+ * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
+ */
+#define BLC_PWM_PCH_CTL1	0xc8250
+#define   BLM_PCH_PWM_ENABLE			(1 << 31)
+#define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
+#define   BLM_PCH_POLARITY			(1 << 29)
+#define BLC_PWM_PCH_CTL2	0xc8254
+
+/* digital port hotplug */
+#define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
+#define PORTD_HOTPLUG_ENABLE            (1 << 20)
+#define PORTD_PULSE_DURATION_2ms        (0)
+#define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
+#define PORTD_PULSE_DURATION_6ms        (2 << 18)
+#define PORTD_PULSE_DURATION_100ms      (3 << 18)
+#define PORTD_PULSE_DURATION_MASK	(3 << 18)
+#define PORTD_HOTPLUG_NO_DETECT         (0)
+#define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
+#define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
+#define PORTC_HOTPLUG_ENABLE            (1 << 12)
+#define PORTC_PULSE_DURATION_2ms        (0)
+#define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
+#define PORTC_PULSE_DURATION_6ms        (2 << 10)
+#define PORTC_PULSE_DURATION_100ms      (3 << 10)
+#define PORTC_PULSE_DURATION_MASK	(3 << 10)
+#define PORTC_HOTPLUG_NO_DETECT         (0)
+#define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
+#define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
+#define PORTB_HOTPLUG_ENABLE            (1 << 4)
+#define PORTB_PULSE_DURATION_2ms        (0)
+#define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
+#define PORTB_PULSE_DURATION_6ms        (2 << 2)
+#define PORTB_PULSE_DURATION_100ms      (3 << 2)
+#define PORTB_PULSE_DURATION_MASK	(3 << 2)
+#define PORTB_HOTPLUG_NO_DETECT         (0)
+#define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
+#define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
+
+#define PCH_GPIOA               0xc5010
+#define PCH_GPIOB               0xc5014
+#define PCH_GPIOC               0xc5018
+#define PCH_GPIOD               0xc501c
+#define PCH_GPIOE               0xc5020
+#define PCH_GPIOF               0xc5024
+
+#define PCH_GMBUS0		0xc5100
+#define PCH_GMBUS1		0xc5104
+#define PCH_GMBUS2		0xc5108
+#define PCH_GMBUS3		0xc510c
+#define PCH_GMBUS4		0xc5110
+#define PCH_GMBUS5		0xc5120
+
+#define _PCH_DPLL_A              0xc6014
+#define _PCH_DPLL_B              0xc6018
+#define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
+
+#define _PCH_FPA0                0xc6040
+#define  FP_CB_TUNE		(0x3<<22)
+#define _PCH_FPA1                0xc6044
+#define _PCH_FPB0                0xc6048
+#define _PCH_FPB1                0xc604c
+#define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
+#define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
+
+#define PCH_DPLL_TEST           0xc606c
+
+#define PCH_DREF_CONTROL        0xC6200
+#define  DREF_CONTROL_MASK      0x7fc3
+#define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
+#define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
+#define  DREF_SSC_SOURCE_DISABLE                (0<<11)
+#define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
+#define  DREF_SSC_SOURCE_MASK			(3<<11)
+#define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
+#define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
+#define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
+#define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
+#define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
+#define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
+#define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
+#define  DREF_SSC4_DOWNSPREAD                   (0<<6)
+#define  DREF_SSC4_CENTERSPREAD                 (1<<6)
+#define  DREF_SSC1_DISABLE                      (0<<1)
+#define  DREF_SSC1_ENABLE                       (1<<1)
+#define  DREF_SSC4_DISABLE                      (0)
+#define  DREF_SSC4_ENABLE                       (1)
+
+#define PCH_RAWCLK_FREQ         0xc6204
+#define  FDL_TP1_TIMER_SHIFT    12
+#define  FDL_TP1_TIMER_MASK     (3<<12)
+#define  FDL_TP2_TIMER_SHIFT    10
+#define  FDL_TP2_TIMER_MASK     (3<<10)
+#define  RAWCLK_FREQ_MASK       0x3ff
+
+#define PCH_DPLL_TMR_CFG        0xc6208
+
+#define PCH_SSC4_PARMS          0xc6210
+#define PCH_SSC4_AUX_PARMS      0xc6214
+
+#define PCH_DPLL_SEL		0xc7000
+#define  TRANSA_DPLL_ENABLE	(1<<3)
+#define	 TRANSA_DPLLB_SEL	(1<<0)
+#define	 TRANSA_DPLLA_SEL	0
+#define  TRANSB_DPLL_ENABLE	(1<<7)
+#define	 TRANSB_DPLLB_SEL	(1<<4)
+#define	 TRANSB_DPLLA_SEL	(0)
+#define  TRANSC_DPLL_ENABLE	(1<<11)
+#define	 TRANSC_DPLLB_SEL	(1<<8)
+#define	 TRANSC_DPLLA_SEL	(0)
+
+/* transcoder */
+
+#define _TRANS_HTOTAL_A          0xe0000
+#define  TRANS_HTOTAL_SHIFT     16
+#define  TRANS_HACTIVE_SHIFT    0
+#define _TRANS_HBLANK_A          0xe0004
+#define  TRANS_HBLANK_END_SHIFT 16
+#define  TRANS_HBLANK_START_SHIFT 0
+#define _TRANS_HSYNC_A           0xe0008
+#define  TRANS_HSYNC_END_SHIFT  16
+#define  TRANS_HSYNC_START_SHIFT 0
+#define _TRANS_VTOTAL_A          0xe000c
+#define  TRANS_VTOTAL_SHIFT     16
+#define  TRANS_VACTIVE_SHIFT    0
+#define _TRANS_VBLANK_A          0xe0010
+#define  TRANS_VBLANK_END_SHIFT 16
+#define  TRANS_VBLANK_START_SHIFT 0
+#define _TRANS_VSYNC_A           0xe0014
+#define  TRANS_VSYNC_END_SHIFT  16
+#define  TRANS_VSYNC_START_SHIFT 0
+#define _TRANS_VSYNCSHIFT_A	0xe0028
+
+#define _TRANSA_DATA_M1          0xe0030
+#define _TRANSA_DATA_N1          0xe0034
+#define _TRANSA_DATA_M2          0xe0038
+#define _TRANSA_DATA_N2          0xe003c
+#define _TRANSA_DP_LINK_M1       0xe0040
+#define _TRANSA_DP_LINK_N1       0xe0044
+#define _TRANSA_DP_LINK_M2       0xe0048
+#define _TRANSA_DP_LINK_N2       0xe004c
+
+/* Per-transcoder DIP controls */
+
+#define _VIDEO_DIP_CTL_A         0xe0200
+#define _VIDEO_DIP_DATA_A        0xe0208
+#define _VIDEO_DIP_GCP_A         0xe0210
+
+#define _VIDEO_DIP_CTL_B         0xe1200
+#define _VIDEO_DIP_DATA_B        0xe1208
+#define _VIDEO_DIP_GCP_B         0xe1210
+
+#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
+#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
+#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
+
+#define VLV_VIDEO_DIP_CTL_A		0x60200
+#define VLV_VIDEO_DIP_DATA_A		0x60208
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
+
+#define VLV_VIDEO_DIP_CTL_B		0x61170
+#define VLV_VIDEO_DIP_DATA_B		0x61174
+#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
+
+#define VLV_TVIDEO_DIP_CTL(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
+#define VLV_TVIDEO_DIP_DATA(pipe) \
+	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
+#define VLV_TVIDEO_DIP_GCP(pipe) \
+	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
+
+/* vlv has 2 sets of panel control regs. */
+#define PIPEA_PP_STATUS         0x61200
+#define PIPEA_PP_CONTROL        0x61204
+#define PIPEA_PP_ON_DELAYS      0x61208
+#define PIPEA_PP_OFF_DELAYS     0x6120c
+#define PIPEA_PP_DIVISOR        0x61210
+
+#define PIPEB_PP_STATUS         0x61300
+#define PIPEB_PP_CONTROL        0x61304
+#define PIPEB_PP_ON_DELAYS      0x61308
+#define PIPEB_PP_OFF_DELAYS     0x6130c
+#define PIPEB_PP_DIVISOR        0x61310
+
+#define PCH_PP_STATUS		0xc7200
+#define PCH_PP_CONTROL		0xc7204
+#define  PANEL_UNLOCK_REGS	(0xabcd << 16)
+#define  PANEL_UNLOCK_MASK	(0xffff << 16)
+#define  EDP_FORCE_VDD		(1 << 3)
+#define  EDP_BLC_ENABLE		(1 << 2)
+#define  PANEL_POWER_RESET	(1 << 1)
+#define  PANEL_POWER_OFF	(0 << 0)
+#define  PANEL_POWER_ON		(1 << 0)
+#define PCH_PP_ON_DELAYS	0xc7208
+#define  PANEL_PORT_SELECT_MASK	(3 << 30)
+#define  PANEL_PORT_SELECT_LVDS	(0 << 30)
+#define  PANEL_PORT_SELECT_DPA	(1 << 30)
+#define  EDP_PANEL		(1 << 30)
+#define  PANEL_PORT_SELECT_DPC	(2 << 30)
+#define  PANEL_PORT_SELECT_DPD	(3 << 30)
+#define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_UP_DELAY_SHIFT	16
+#define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_ON_DELAY_SHIFT	0
+
+#define PCH_PP_OFF_DELAYS	0xc720c
+#define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
+#define  PANEL_POWER_PORT_LVDS		(0 << 30)
+#define  PANEL_POWER_PORT_DP_A		(1 << 30)
+#define  PANEL_POWER_PORT_DP_C		(2 << 30)
+#define  PANEL_POWER_PORT_DP_D		(3 << 30)
+#define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
+#define  PANEL_POWER_DOWN_DELAY_SHIFT	16
+#define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
+#define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
+
+#define PCH_PP_DIVISOR		0xc7210
+#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
+#define  PP_REFERENCE_DIVIDER_SHIFT	8
+#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
+#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
+
+#define PCH_DP_B		0xe4100
+#define PCH_DPB_AUX_CH_CTL	0xe4110
+#define PCH_DPB_AUX_CH_DATA1	0xe4114
+#define PCH_DPB_AUX_CH_DATA2	0xe4118
+#define PCH_DPB_AUX_CH_DATA3	0xe411c
+#define PCH_DPB_AUX_CH_DATA4	0xe4120
+#define PCH_DPB_AUX_CH_DATA5	0xe4124
+
+#define PCH_DP_C		0xe4200
+#define PCH_DPC_AUX_CH_CTL	0xe4210
+#define PCH_DPC_AUX_CH_DATA1	0xe4214
+#define PCH_DPC_AUX_CH_DATA2	0xe4218
+#define PCH_DPC_AUX_CH_DATA3	0xe421c
+#define PCH_DPC_AUX_CH_DATA4	0xe4220
+#define PCH_DPC_AUX_CH_DATA5	0xe4224
+
+#define PCH_DP_D		0xe4300
+#define PCH_DPD_AUX_CH_CTL	0xe4310
+#define PCH_DPD_AUX_CH_DATA1	0xe4314
+#define PCH_DPD_AUX_CH_DATA2	0xe4318
+#define PCH_DPD_AUX_CH_DATA3	0xe431c
+#define PCH_DPD_AUX_CH_DATA4	0xe4320
+#define PCH_DPD_AUX_CH_DATA5	0xe4324
+
+#endif /* _I915_REG_H_ */
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 46/51] x86: Add a default address for reference code

[Simon Glass]

Add an address which can be used for loading and running the reference code
when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 include/configs/x86-chromebook.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c575dab..057d4be 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -14,6 +14,8 @@
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_X86_MRC_ADDR			0xfffa0000
+#define CONFIG_X86_REFCODE_ADDR			0xffea0000
+#define CONFIG_X86_REFCODE_RUN_ADDR		0
 
 #define CONFIG_SCSI_DEV_LIST	\
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 47/51] x86: Use white on black for the console on chromebooks

[Simon Glass]

This is a little easier on the eyes, particularly when the backlight is set
to maximum.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 include/configs/x86-chromebook.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 057d4be..ae969b9 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -51,6 +51,8 @@
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_OFFSET		0x003f8000
 
+#define CONFIG_SYS_WHITE_ON_BLACK
+
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
 					"stdout=vga,serial\0" \
 					"stderr=vga,serial\0"
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 48/51] x86: Update README for new developments

[Simon Glass]

Update a few points which have become out-of-date.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2:
- Correct naming of Intel platforms

 doc/README.x86 | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/doc/README.x86 b/doc/README.x86
index 889373e..5b51559 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -20,8 +20,17 @@ most of the low-level details.
 
 U-Boot also supports booting directly from x86 reset vector, without coreboot.
 In this case, known as bare mode, from the fact that it runs on the
-'bare metal', U-Boot acts like a BIOS replacement. Currently Link, QEMU x86
-targets and all Intel boards support running U-Boot 'bare metal'.
+'bare metal', U-Boot acts like a BIOS replacement. The following platforms
+are supported:
+
+   - Bayley Bay
+   - Cougar Canyon 2 CRB
+   - Crown Bay CRB
+   - Galileo
+   - Link (Chromebook Pixel)
+   - Minnowboard MAX
+   - Samus (Chromebook Pixel 2015)
+   - QEMU x86
 
 As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
 Linux kernel as part of a FIT image. It also supports a compressed zImage.
@@ -371,7 +380,8 @@ options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
 
 Driver Model
 ------------
-x86 has been converted to use driver model for serial and GPIO.
+x86 has been converted to use driver model for serial, GPIO, SPI, SPI flash,
+keyboard, real-time clock, USB. Video is in progress.
 
 Device Tree
 -----------
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 49/51] x86: Add a function to set the IOAPIC ID

[Simon Glass]

Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/cpu/ioapic.c         | 16 ++++++++++++++++
 arch/x86/include/asm/ioapic.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/arch/x86/cpu/ioapic.c b/arch/x86/cpu/ioapic.c
index 112a9c6..d15e86c 100644
--- a/arch/x86/cpu/ioapic.c
+++ b/arch/x86/cpu/ioapic.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/ioapic.h>
+#include <asm/lapic.h>
 
 u32 io_apic_read(u32 reg)
 {
@@ -19,3 +20,18 @@ void io_apic_write(u32 reg, u32 val)
 	writel(reg, IO_APIC_INDEX);
 	writel(val, IO_APIC_DATA);
 }
+
+void io_apic_set_id(int ioapic_id)
+{
+	int bsp_lapicid = lapicid();
+
+	debug("IOAPIC: Initialising IOAPIC at %08x\n", IO_APIC_ADDR);
+	debug("IOAPIC: Bootstrap Processor Local APIC = %#02x\n", bsp_lapicid);
+
+	if (ioapic_id) {
+		debug("IOAPIC: ID = 0x%02x\n", ioapic_id);
+		/* Set IOAPIC ID if it has been specified */
+		io_apic_write(0x00, (io_apic_read(0x00) & 0xf0ffffff) |
+			      (ioapic_id << 24));
+	}
+}
diff --git a/arch/x86/include/asm/ioapic.h b/arch/x86/include/asm/ioapic.h
index 77c443e..2feed86 100644
--- a/arch/x86/include/asm/ioapic.h
+++ b/arch/x86/include/asm/ioapic.h
@@ -39,4 +39,6 @@ u32 io_apic_read(u32 reg);
  */
 void io_apic_write(u32 reg, u32 val);
 
+void io_apic_set_id(int ioapic_id);
+
 #endif
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 50/51] x86: Fix a header nit in x86-chromebook.h

[Simon Glass]

There is an extra line in the comment in the header. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 include/configs/x86-chromebook.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index ae969b9..c94096a 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -1,5 +1,4 @@
 /*
- *
  * Copyright (c) 2015 Google, Inc
  *
  * SPDX-License-Identifier:	GPL-2.0+
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 51/51] x86: Add support for the samus chromebook

[Simon Glass]

This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v2: None

 arch/x86/dts/Makefile                     |   1 +
 arch/x86/dts/chromebook_samus.dts         | 628 ++++++++++++++++++++++++++++++
 board/google/Kconfig                      |  13 +
 board/google/chromebook_samus/Kconfig     |  40 ++
 board/google/chromebook_samus/MAINTAINERS |   6 +
 board/google/chromebook_samus/Makefile    |   7 +
 board/google/chromebook_samus/samus.c     |  18 +
 configs/chromebook_samus_defconfig        |  51 +++
 doc/README.x86                            |  81 ++++
 include/configs/chromebook_samus.h        |  29 ++
 include/configs/x86-chromebook.h          |   3 +-
 11 files changed, 876 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/dts/chromebook_samus.dts
 create mode 100644 board/google/chromebook_samus/Kconfig
 create mode 100644 board/google/chromebook_samus/MAINTAINERS
 create mode 100644 board/google/chromebook_samus/Makefile
 create mode 100644 board/google/chromebook_samus/samus.c
 create mode 100644 configs/chromebook_samus_defconfig
 create mode 100644 include/configs/chromebook_samus.h

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 84feb19..fcfce95 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -5,6 +5,7 @@
 dtb-y += bayleybay.dtb \
 	chromebook_link.dtb \
 	chromebox_panther.dtb \
+	chromebook_samus.dtb \
 	cougarcanyon2.dtb \
 	crownbay.dtb \
 	efi.dtb \
diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
new file mode 100644
index 0000000..5dd3e57
--- /dev/null
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -0,0 +1,628 @@
+/dts-v1/;
+
+#include <dt-bindings/gpio/x86-gpio.h>
+
+/include/ "skeleton.dtsi"
+/include/ "keyboard.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+
+/ {
+	model = "Google Samus";
+	compatible = "google,samus", "intel,broadwell";
+
+	aliases {
+		spi0 = &spi;
+		usb0 = &usb_0;
+		usb1 = &usb_1;
+	};
+
+	config {
+	       silent_console = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <0>;
+			intel,apic-id = <0>;
+			intel,slow-ramp = <3>;
+		};
+
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <1>;
+			intel,apic-id = <1>;
+		};
+
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <2>;
+			intel,apic-id = <2>;
+		};
+
+		cpu at 3 {
+			device_type = "cpu";
+			compatible = "intel,core-i3-gen5";
+			reg = <3>;
+			intel,apic-id = <3>;
+		};
+
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	keyboard {
+		intel,duplicate-por;
+	};
+
+	pch_pinctrl {
+		compatible = "intel,x86-broadwell-pinctrl";
+		u-boot,dm-pre-reloc;
+		reg = <0 0>;
+
+		/* Put this first: it is the default */
+		gpio_unused: gpio-unused {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_acpi_sci: acpi-sci {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+			route = <ROUTE_SCI>;
+		};
+
+		gpio_acpi_smi: acpi-smi {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			invert;
+			route = <ROUTE_SMI>;
+		};
+
+		gpio_input: gpio-input {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+		};
+
+		gpio_input_invert: gpio-input-invert {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			invert;
+		};
+
+		gpio_native: gpio-native {
+		};
+
+		gpio_out_high: gpio-out-high {
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <1>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_out_low: gpio-out-low {
+			mode-gpio;
+			direction = <PIN_OUTPUT>;
+			output-value = <0>;
+			owner = <OWNER_GPIO>;
+			sense-disable;
+		};
+
+		gpio_pirq: gpio-pirq {
+			mode-gpio;
+			direction = <PIN_INPUT>;
+			owner = <OWNER_GPIO>;
+			pirq-apic = <PIRQ_APIC_ROUTE>;
+		};
+
+		soc_gpio at 0 {
+			config =
+				<0 &gpio_unused 0>,	/* unused */
+				<1 &gpio_unused 0>,	/* unused */
+				<2 &gpio_unused 0>,	/* unused */
+				<3 &gpio_unused 0>,	/* unused */
+				<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
+				<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
+				<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
+				<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
+				<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
+				<9 &gpio_input_invert 0>,	/* trackpad_int_l (wake) */
+				<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
+				<11 &gpio_unused 0>,	/* unused */
+				<12 &gpio_unused 0>,	/* unused */
+				<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
+				<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
+				<15 &gpio_unused 0>,	/* unused (strap) */
+				<16 &gpio_input 0>,	/* pch_wp */
+				<17 &gpio_unused 0>,	/* unused */
+				<18 &gpio_unused 0>,	/* unused */
+				<19 &gpio_unused 0>,	/* unused */
+				<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
+				<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
+				<22 &gpio_unused 0>,	/* unused */
+				<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
+				<24 &gpio_unused 0>,	/* unused */
+				<25 &gpio_input 0>,	/* ec_in_rw */
+				<26 &gpio_unused 0>,	/* unused */
+				<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
+				<28 &gpio_unused 0>,	/* unused */
+				<29 &gpio_unused 0>,	/* unused */
+				<30 &gpio_native 0>,	/* native: pch_suswarn_l */
+				<31 &gpio_native 0>,	/* native: acok_buf */
+				<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
+				<33 &gpio_native 0>,	/* native: ssd_devslp */
+				<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
+				<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
+				<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
+				<37 &gpio_unused 0>,	/* unused */
+				<38 &gpio_unused 0>,	/* unused */
+				<39 &gpio_unused 0>,	/* unused */
+				<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
+				<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
+				<42 &gpio_unused 0>,	/* wlan_disable_l */
+				<43 &gpio_out_high 0>,	/* pp1800_codec_en */
+				<44 &gpio_unused 0>,	/* unused */
+				<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
+				<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
+				<47 &gpio_out_low 0>,	/* ssd_reset_l */
+				<48 &gpio_unused 0>,	/* unused */
+				<49 &gpio_unused 0>,	/* unused */
+				<50 &gpio_unused 0>,	/* unused */
+				<51 &gpio_unused 0>,	/* unused */
+				<52 &gpio_input 0>,	/* sim_det */
+				<53 &gpio_unused 0>,	/* unused */
+				<54 &gpio_unused 0>,	/* unused */
+				<55 &gpio_unused 0>,	/* unused */
+				<56 &gpio_unused 0>,	/* unused */
+				<57 &gpio_out_high 0>,	/* codec_reset_l */
+				<58 &gpio_unused 0>,	/* unused */
+				<59 &gpio_out_high 0>,	/* lte_disable_l */
+				<60 &gpio_unused 0>,	/* unused */
+				<61 &gpio_native 0>,	/* native: pch_sus_stat */
+				<62 &gpio_native 0>,	/* native: pch_susclk */
+				<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
+				<64 &gpio_unused 0>,	/* unused */
+				<65 &gpio_input 0>,	/* ram_id3 */
+				<66 &gpio_input 0>,	/* ram_id3_old (strap) */
+				<67 &gpio_input 0>,	/* ram_id0 */
+				<68 &gpio_input 0>,	/* ram_id1 */
+				<69 &gpio_input 0>,	/* ram_id2 */
+				<70 &gpio_unused 0>,	/* unused */
+				<71 &gpio_native 0>,	/* native: modphy_en */
+				<72 &gpio_unused 0>,	/* unused */
+				<73 &gpio_unused 0>,	/* unused */
+				<74 &gpio_unused 0>,	/* unused */
+				<75 &gpio_unused 0>,	/* unused */
+				<76 &gpio_unused 0>,	/* unused */
+				<77 &gpio_unused 0>,	/* unused */
+				<78 &gpio_unused 0>,	/* unused */
+				<79 &gpio_unused 0>,	/* unused */
+				<80 &gpio_unused 0>,	/* unused */
+				<81 &gpio_unused 0>,	/* unused */
+				<82 &gpio_native 0>,	/* native: ec_rcin_l */
+				<83 &gpio_native 0>,	/* gspi0_cs */
+				<84 &gpio_native 0>,	/* gspi0_clk */
+				<85 &gpio_native 0>,	/* gspi0_miso */
+				<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
+				<87 &gpio_unused 0>,	/* unused */
+				<88 &gpio_unused 0>,	/* unused */
+				<89 &gpio_out_high 0>,	/* pp3300_sd_en */
+				<90 &gpio_unused 0>,	/* unused */
+				<91 &gpio_unused 0>,	/* unused */
+				<92 &gpio_unused 0>,	/* unused */
+				<93 &gpio_unused 0>,	/* unused */
+				<94 &gpio_unused 0>;	/* unused */
+		};
+	};
+
+	pci {
+		compatible = "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
+			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
+
+		northbridge at 0,0 {
+			reg = <0x00000000 0 0 0 0>;
+			compatible = "intel,broadwell-northbridge";
+			board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
+					<&gpio_c 3 0>, <&gpio_c 1 0>;
+			u-boot,dm-pre-reloc;
+			spd {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				samsung_4 {
+					reg = <6>;
+					data = [91 20 f1 03 04 11 05 0b
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 55 00 00 00 00 00
+						4b 34 45 38 45 33 30 34
+						45 44 2d 45 47 43 45 20
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
+					/*
+					 * banks 8, ranks 2, rows 14,
+					 * columns 10, density 4096 mb, x32
+					 */
+					reg = <8>;
+					data = [91 20 f1 03 04 11 05 0b
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 42
+						4c 54 4d 4c 41 52 2d 4e
+						54 4d 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+					};
+				samsung_8 {
+					reg = <10>;
+					data = [91 20 f1 03 04 12 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 11 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ce 01
+						00 00 55 00 00 00 00 00
+						4b 34 45 36 45 33 30 34
+						45 44 2d 45 47 43 45 20
+						20 20 00 00 80 ce 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
+					/*
+					 * banks 8, ranks 2, rows 14,
+					 * columns 11, density 4096 mb, x16
+					 */
+					reg = <12>;
+					data = [91 20 f1 03 04 12 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						10 04 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 42
+						4c 54 4d 4c 41 52 2d 4e
+						54 4d 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				hynix-h9ccnnncltmlar-lpddr3 {
+					/*
+					 * banks 8, ranks 2, rows 15,
+					 * columns 11, density 8192 mb, x16
+					 */
+					reg = <13>;
+					data = [91 20 f1 03 05 1a 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						90 06 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 80 ad 00
+						00 00 55 00 00 00 00 00
+						48 39 43 43 4e 4e 4e 43
+						4c 54 4d 4c 41 52 00 00
+						00 00 00 00 80 ad 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+				elpida-edfb232a1ma {
+					/*
+					 * banks 8, ranks 2, rows 15,
+					 * columns 11, density 8192 mb, x16
+					 */
+					reg = <15>;
+					data = [91 20 f1 03 05 1a 05 0a
+						03 11 01 08 0a 00 50 01
+						78 78 90 50 90 11 50 e0
+						90 06 3c 3c 01 90 00 00
+						00 80 00 00 00 00 00 a8
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 0f 01 02 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 02 fe 00
+						00 00 00 00 00 00 00 00
+						45 44 46 42 32 33 32 41
+						31 4d 41 2d 47 44 2d 46
+						00 00 00 00 02 fe 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00
+						00 00 00 00 00 00 00 00];
+				};
+			};
+		};
+
+		gma at 2,0 {
+			reg = <0x00001000 0 0 0 0>;
+			compatible = "intel,broadwell-igd";
+			intel,dp-hotplug = <6 6 6>;
+			intel,port-select = <1>;	/* eDP */
+			intel,power-cycle-delay = <6>;
+			intel,power-up-delay = <2000>;
+			intel,power-down-delay = <500>;
+			intel,power-backlight-on-delay = <2000>;
+			intel,power-backlight-off-delay = <2000>;
+			intel,cpu-backlight = <0x00000200>;
+			intel,pch-backlight = <0x04000200>;
+			intel,pre-graphics-delay = <200>;
+		};
+
+		me at 16,0 {
+			reg = <0x0000b000 0 0 0 0>;
+			compatible = "intel,me";
+			u-boot,dm-pre-reloc;
+		};
+
+		usb_1: usb at 14,0 {
+			reg = <0x0000a000 0 0 0 0>;
+			compatible = "xhci-pci";
+		};
+
+		usb_0: usb at 1d,0 {
+			status = "disabled";
+			reg = <0x0000e800 0 0 0 0>;
+			compatible = "ehci-pci";
+		};
+
+		pch at 1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,broadwell-pch";
+			u-boot,dm-pre-reloc;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
+						0x80 0x80 0x80 0x80>;
+			intel,gpi-routing = <0 0 0 0 0 0 0 2
+						1 0 0 0 0 0 0 0>;
+			/* Enable EC SMI source */
+			intel,alt-gp-smi-enable = <0x0040>;
+
+			/* EC-SCI is GPIO36 */
+			intel,gpe0-en = <0 0x10 0 0>;
+
+			power-enable-gpio = <&gpio_a 23 0>;
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+				spi-flash at 0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+							"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x003e0000 0x00010000>;
+					};
+				};
+			};
+
+			gpio_a: gpioa {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <0 0>;
+				bank-name = "A";
+			};
+
+			gpio_b: gpiob {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <1 0>;
+				bank-name = "B";
+			};
+
+			gpio_c: gpioc {
+				compatible = "intel,broadwell-gpio";
+				u-boot,dm-pre-reloc;
+				#gpio-cells = <2>;
+				gpio-controller;
+				reg = <2 0>;
+				bank-name = "C";
+			};
+
+			lpc {
+				compatible = "intel,broadwell-lpc";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				u-boot,dm-pre-reloc;
+				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
+				cros-ec at 200 {
+					compatible = "google,cros-ec-lpc";
+					reg = <0x204 1 0x200 1 0x880 0x80>;
+
+					/*
+					 * Describes the flash memory within
+					 * the EC
+					 */
+					#address-cells = <1>;
+					#size-cells = <1>;
+					flash at 8000000 {
+						reg = <0x08000000 0x20000>;
+						erase-value = <0xff>;
+					};
+				};
+			};
+		};
+
+		sata at 1f,2 {
+			compatible = "intel,wildcatpoint-ahci";
+			reg = <0x0000fa00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+			intel,sata-mode = "ahci";
+			intel,sata-port-map = <1>;
+			intel,sata-port0-gen3-tx = <0x72>;
+			reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
+		};
+
+		smbus: smbus at 1f,3 {
+			compatible = "intel,ich-i2c";
+			reg = <0x0000fb00 0 0 0 0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	tpm {
+		reg = <0xfed40000 0x5000>;
+		compatible = "infineon,slb9635lpc";
+	};
+
+	microcode {
+		update at 0 {
+#include "microcode/mc0306d4_00000018.dtsi"
+		};
+	};
+
+};
diff --git a/board/google/Kconfig b/board/google/Kconfig
index e9559c9..7ba73a2 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -36,9 +36,22 @@ config TARGET_CHROMEBOX_PANTHER
 	  video output and a 16GB SATA solid state drive. There is no Chrome
 	  OS EC on this model.
 
+config TARGET_CHROMEBOOK_SAMUS
+	bool "Chromebook samus"
+	help
+	  This is the Chromebook Pixel released in 2015. It uses an Intel
+	  Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
+	  LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
+	  720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
+	  C ports which can support charging and up to a 4K external display.
+	  There is a solid state drive, either 32GB or 64GB. There is a
+	  Chrome OS EC connected on LPC, and it provides a 2560x1700 high
+	  resolution touch-enabled LCD display.
+
 endchoice
 
 source "board/google/chromebook_link/Kconfig"
 source "board/google/chromebox_panther/Kconfig"
+source "board/google/chromebook_samus/Kconfig"
 
 endif
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
new file mode 100644
index 0000000..f2b9481
--- /dev/null
+++ b/board/google/chromebook_samus/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_CHROMEBOOK_SAMUS
+
+config SYS_BOARD
+	default "chromebook_samus"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "broadwell"
+
+config SYS_CONFIG_NAME
+	default "chromebook_samus"
+
+config SYS_TEXT_BASE
+	default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR
+	select INTEL_BROADWELL
+	select HAVE_INTEL_ME
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xf0000000
+
+config EARLY_POST_CROS_EC
+	bool "Enable early post to Chrome OS EC"
+	default y
+
+config SYS_CAR_ADDR
+	hex
+	default 0xff7c0000
+
+config SYS_CAR_SIZE
+	hex
+	default 0x40000
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
new file mode 100644
index 0000000..5500e46
--- /dev/null
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK SAMUS BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_defconfig
diff --git a/board/google/chromebook_samus/Makefile b/board/google/chromebook_samus/Makefile
new file mode 100644
index 0000000..1522286
--- /dev/null
+++ b/board/google/chromebook_samus/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= samus.o
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
new file mode 100644
index 0000000..3c3f5d4
--- /dev/null
+++ b/board/google/chromebook_samus/samus.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+
+int arch_early_init_r(void)
+{
+	return cpu_run_reference_code();
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
new file mode 100644
index 0000000..448446d
--- /dev/null
+++ b/configs/chromebook_samus_defconfig
@@ -0,0 +1,51 @@
+CONFIG_X86=y
+CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+CONFIG_TARGET_CHROMEBOOK_SAMUS=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_INTEL_BROADWELL_GPIO=y
+CONFIG_CMD_CROS_EC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_BROADWELL_IGD=y
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_TPM=y
diff --git a/doc/README.x86 b/doc/README.x86
index 5b51559..c5c3010 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -105,6 +105,87 @@ $ make all
 
 ---
 
+Chromebook Samus (2015 Pixel) instructions for bare mode:
+
+First, you need the following binary blobs:
+
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* refcode.elf - Additional Reference code
+* vga.bin - video ROM, which sets up the display
+
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root'):
+
+   cd /tmp
+   flashrom -w samus.bin
+   scp samus.bin username at ip_address:/path/to/somewhere
+
+If not see the coreboot tree [4] where you can use:
+
+   bash crosfirmware.sh samus
+
+to get the image. There is also an 'extract_blobs.sh' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+
+Then 'ifdtool -x samus.bin' on your development machine will produce:
+
+   flashregion_0_flashdescriptor.bin
+   flashregion_1_bios.bin
+   flashregion_2_intel_me.bin
+
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+
+To get the rest, use 'cbfstool samus.bin print':
+
+samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+alignment: 64 bytes, architecture: x86
+
+Name                           Offset     Type         Size
+cmos_layout.bin                0x700000   cmos_layout  1164
+pci8086,0406.rom               0x7004c0   optionrom    65536
+spd.bin                        0x710500   (unknown)    4096
+cpu_microcode_blob.bin         0x711540   microcode    70720
+fallback/romstage              0x722a00   stage        54210
+fallback/ramstage              0x72fe00   stage        96382
+config                         0x7476c0   raw          6075
+fallback/vboot                 0x748ec0   stage        15980
+fallback/refcode               0x74cd80   stage        75578
+fallback/payload               0x75f500   payload      62878
+u-boot.dtb                     0x76eb00   (unknown)    5318
+(empty)                        0x770000   null         196504
+mrc.bin                        0x79ffc0   (unknown)    222876
+(empty)                        0x7d66c0   null         167320
+
+You can extract what you need:
+
+   cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+   cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+   cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+
+Put all 5 files into board/google/chromebook_samus.
+
+Now you can build U-Boot and obtain u-boot.rom:
+
+$ make chromebook_link_defconfig
+$ make all
+
+If you are using em100, then this command will flash write -Boot:
+
+   em100 -s -d filename.rom -c W25Q64CV -r
+
+---
+
 Intel Crown Bay specific instructions for bare mode:
 
 U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
new file mode 100644
index 0000000..b89ba41
--- /dev/null
+++ b/include/configs/chromebook_samus.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+#include <configs/x86-chromebook.h>
+
+#undef CONFIG_CFB_CONSOLE
+
+#undef CONFIG_STD_DEVICES_SETTINGS
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,i8042-kbd,serial\0" \
+					"stdout=vidconsole,serial\0" \
+					"stderr=vidconsole,serial\0"
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x003f8000
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index c94096a..312987e 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -21,7 +21,8 @@
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
-	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
 
 #define CONFIG_PCI_MEM_BUS	0xe0000000
 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-- 
2.7.0.rc3.207.g0ac5344

[U-Boot] [PATCH v2 01/51] dm: timer: Correct timer init ordering after relocation

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> Commit 1057e6c broke use of the timer with driver model. If the timer is used
> before relocation, then it becomes broken after relocation. This prevents
> some x86 boards from booting. Fix it.
>
> Fixes: 1057e6c (timer: Set up the real timer after driver model is available)
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  common/board_r.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 04/51] syscon: Avoid returning a device on failure

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> If the device cannot be probed, syscon_get_by_driver_data() will still
> return a useful value in its devp parameter. Ensure that it returns NULL
> instead.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  drivers/core/syscon-uclass.c | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 05/51] input: i8042: Make sure the keyboard is enabled

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> Add one more step into the init sequence. This fixes the keyboard on samus,
> which otherwise does not work.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Use a #define for the output flush command
> - Adjust the code order slightly
>
>  drivers/input/i8042.c | 4 ++++
>  include/i8042.h       | 1 +
>  2 files changed, 5 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Tested on QEMU and Crown Bay
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 06/51] x86: Allow use of serial soon after relocation

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> At present on x86 machines with use cache-as-RAM, the memory goes away just
> before board_init_r() is called. This means that serial drivers are
> no-longer unavailable, until initr_dm() it called, etc.
>
> Any attempt to use printf() within this period will cause a hang.
>
> To fix this, mark the serial devices as 'unavailable' when it is no-longer
> available. Bring it back when serial_initialize() is called. This means that
> the debug UART will be used instead for this period.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Simplify the code in serial_initialize()
>
>  common/board_f.c               | 7 +++++++
>  drivers/serial/serial-uclass.c | 2 +-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 07/51] x86: cpu: Add functions to return the family and stepping

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> These two identifiers can be useful for drivers which need to adjust their
> behaviour depending on the CPU family or stepping (revision).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Use gd->arch.x86_mask to get the stepping value
>
>  arch/x86/cpu/cpu.c         | 10 ++++++++++
>  arch/x86/include/asm/cpu.h | 14 ++++++++++++++
>  2 files changed, 24 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 01/51] dm: timer: Correct timer init ordering after relocation

[Bin Meng]

On Mon, Mar 14, 2016 at 12:08 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> Commit 1057e6c broke use of the timer with driver model. If the timer is used
>> before relocation, then it becomes broken after relocation. This prevents
>> some x86 boards from booting. Fix it.
>>
>> Fixes: 1057e6c (timer: Set up the real timer after driver model is available)
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  common/board_r.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 04/51] syscon: Avoid returning a device on failure

[Bin Meng]

On Mon, Mar 14, 2016 at 12:10 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> If the device cannot be probed, syscon_get_by_driver_data() will still
>> return a useful value in its devp parameter. Ensure that it returns NULL
>> instead.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  drivers/core/syscon-uclass.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 05/51] input: i8042: Make sure the keyboard is enabled

[Bin Meng]

On Mon, Mar 14, 2016 at 12:17 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> Add one more step into the init sequence. This fixes the keyboard on samus,
>> which otherwise does not work.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Use a #define for the output flush command
>> - Adjust the code order slightly
>>
>>  drivers/input/i8042.c | 4 ++++
>>  include/i8042.h       | 1 +
>>  2 files changed, 5 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>
> Tested on QEMU and Crown Bay
> Tested-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 06/51] x86: Allow use of serial soon after relocation

[Bin Meng]

On Mon, Mar 14, 2016 at 12:18 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> At present on x86 machines with use cache-as-RAM, the memory goes away just
>> before board_init_r() is called. This means that serial drivers are
>> no-longer unavailable, until initr_dm() it called, etc.
>>
>> Any attempt to use printf() within this period will cause a hang.
>>
>> To fix this, mark the serial devices as 'unavailable' when it is no-longer
>> available. Bring it back when serial_initialize() is called. This means that
>> the debug UART will be used instead for this period.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Simplify the code in serial_initialize()
>>
>>  common/board_f.c               | 7 +++++++
>>  drivers/serial/serial-uclass.c | 2 +-
>>  2 files changed, 8 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 07/51] x86: cpu: Add functions to return the family and stepping

[Bin Meng]

On Mon, Mar 14, 2016 at 12:20 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> These two identifiers can be useful for drivers which need to adjust their
>> behaviour depending on the CPU family or stepping (revision).
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Use gd->arch.x86_mask to get the stepping value
>>
>>  arch/x86/cpu/cpu.c         | 10 ++++++++++
>>  arch/x86/include/asm/cpu.h | 14 ++++++++++++++
>>  2 files changed, 24 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 08/51] x86: Move cache-as-RAM code into a common location

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
> intel_common directory and move it in there.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/Makefile                          | 1 +
>  arch/x86/cpu/intel_common/Makefile             | 7 +++++++
>  arch/x86/cpu/{ivybridge => intel_common}/car.S | 0
>  arch/x86/cpu/ivybridge/Makefile                | 1 -
>  4 files changed, 8 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/cpu/intel_common/Makefile
>  rename arch/x86/cpu/{ivybridge => intel_common}/car.S (100%)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 10/51] x86: Create a common header for Intel register access

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> There are several blocks of registers that are accessed from all over the
> code on Intel CPUs. These don't currently have their own driver and it is
> not clear whether having a driver makes sense.
>
> An example is the Memory Controller Hub (MCH). We map it to a known location
> on some Intel chips (mostly those without FSP - Firmware Support Package).
>
> Add a new header file for these registers, and move MCH into it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Use capitals for header guard
>
>  arch/x86/cpu/ivybridge/cpu.c                      |  1 +
>  arch/x86/cpu/ivybridge/gma.c                      |  1 +
>  arch/x86/cpu/ivybridge/northbridge.c              |  5 +++--
>  arch/x86/cpu/ivybridge/sdram.c                    |  3 ++-
>  arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
>  arch/x86/include/asm/intel_regs.h                 | 15 +++++++++++++++
>  6 files changed, 22 insertions(+), 6 deletions(-)
>  create mode 100644 arch/x86/include/asm/intel_regs.h
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 11/51] x86: Add the root-complex block to common intel registers

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> This is similar to MCH in that it is used in various drivers. Add it to
> the common header.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/ivybridge/bd82x6x.c          | 1 +
>  arch/x86/cpu/ivybridge/lpc.c              | 6 ++++--
>  arch/x86/include/asm/arch-ivybridge/pch.h | 5 -----
>  arch/x86/include/asm/intel_regs.h         | 4 ++++
>  4 files changed, 9 insertions(+), 7 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 08/51] x86: Move cache-as-RAM code into a common location

[Bin Meng]

On Mon, Mar 14, 2016 at 12:27 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
>> intel_common directory and move it in there.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/Makefile                          | 1 +
>>  arch/x86/cpu/intel_common/Makefile             | 7 +++++++
>>  arch/x86/cpu/{ivybridge => intel_common}/car.S | 0
>>  arch/x86/cpu/ivybridge/Makefile                | 1 -
>>  4 files changed, 8 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/x86/cpu/intel_common/Makefile
>>  rename arch/x86/cpu/{ivybridge => intel_common}/car.S (100%)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 10/51] x86: Create a common header for Intel register access

[Bin Meng]

On Mon, Mar 14, 2016 at 12:28 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> There are several blocks of registers that are accessed from all over the
>> code on Intel CPUs. These don't currently have their own driver and it is
>> not clear whether having a driver makes sense.
>>
>> An example is the Memory Controller Hub (MCH). We map it to a known location
>> on some Intel chips (mostly those without FSP - Firmware Support Package).
>>
>> Add a new header file for these registers, and move MCH into it.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Use capitals for header guard
>>
>>  arch/x86/cpu/ivybridge/cpu.c                      |  1 +
>>  arch/x86/cpu/ivybridge/gma.c                      |  1 +
>>  arch/x86/cpu/ivybridge/northbridge.c              |  5 +++--
>>  arch/x86/cpu/ivybridge/sdram.c                    |  3 ++-
>>  arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
>>  arch/x86/include/asm/intel_regs.h                 | 15 +++++++++++++++
>>  6 files changed, 22 insertions(+), 6 deletions(-)
>>  create mode 100644 arch/x86/include/asm/intel_regs.h
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 11/51] x86: Add the root-complex block to common intel registers

[Bin Meng]

On Mon, Mar 14, 2016 at 12:29 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> This is similar to MCH in that it is used in various drivers. Add it to
>> the common header.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/ivybridge/bd82x6x.c          | 1 +
>>  arch/x86/cpu/ivybridge/lpc.c              | 6 ++++--
>>  arch/x86/include/asm/arch-ivybridge/pch.h | 5 -----
>>  arch/x86/include/asm/intel_regs.h         | 4 ++++
>>  4 files changed, 9 insertions(+), 7 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 09/51] x86: Move microcode code to a common location

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> This code is used on several Intel CPUs. Move it into a common location.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Rename microcode_intel.c to microcode.c
>
>  arch/x86/cpu/intel_common/Makefile                                    | 3 +++
>  arch/x86/cpu/intel_common/car.S                                       | 2 +-
>  .../x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} | 4 +++-
>  arch/x86/cpu/ivybridge/Makefile                                       | 1 -
>  arch/x86/cpu/ivybridge/cpu.c                                          | 2 +-
>  arch/x86/include/asm/{arch-ivybridge => }/microcode.h                 | 0
>  6 files changed, 8 insertions(+), 4 deletions(-)
>  rename arch/x86/cpu/{ivybridge/microcode_intel.c => intel_common/microcode.c} (98%)
>  rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (100%)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 14/51] x86: Rename PORT_RESET to IO_PORT_RESET

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> This same name is used in USB. Add a prefix to distinguish it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/cpu.c               | 4 ++--
>  arch/x86/cpu/intel_common/cpu.c  | 4 ++--
>  arch/x86/include/asm/processor.h | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 12/51] x86: Move common LPC code to its own place

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> Some of the LPC code is common to several Intel LPC devices. Move it into a
> common location.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use capitals for header guard
> - Move cougarcanyon lpc_common.h include to this patch
>
>  arch/x86/cpu/intel_common/Makefile        |   1 +
>  arch/x86/cpu/intel_common/lpc.c           | 100 ++++++++++++++++++++++++++++++
>  arch/x86/cpu/ivybridge/bd82x6x.c          |  16 +----
>  arch/x86/cpu/ivybridge/lpc.c              |  73 ++--------------------
>  arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
>  arch/x86/include/asm/lpc_common.h         |  59 ++++++++++++++++++
>  board/intel/cougarcanyon2/cougarcanyon2.c |   1 +
>  7 files changed, 167 insertions(+), 85 deletions(-)
>  create mode 100644 arch/x86/cpu/intel_common/lpc.c
>  create mode 100644 arch/x86/include/asm/lpc_common.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 13/51] x86: Move common CPU code to its own place

[Bin Meng]

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> Some of the Intel CPU code is common to several Intel CPUs. Move it into a
> common location along with required declarations.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use capitals for header guard
>
>  arch/x86/cpu/intel_common/Makefile        |   1 +
>  arch/x86/cpu/intel_common/cpu.c           | 111 ++++++++++++++++++++++++++++++
>  arch/x86/cpu/ivybridge/cpu.c              |  82 ++--------------------
>  arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
>  arch/x86/include/asm/cpu_common.h         |  35 ++++++++++
>  arch/x86/include/asm/intel_regs.h         |   9 +++
>  6 files changed, 162 insertions(+), 78 deletions(-)
>  create mode 100644 arch/x86/cpu/intel_common/cpu.c
>  create mode 100644 arch/x86/include/asm/cpu_common.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 14/51] x86: Rename PORT_RESET to IO_PORT_RESET

[Bin Meng]

On Mon, Mar 14, 2016 at 12:37 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
>> This same name is used in USB. Add a prefix to distinguish it.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/cpu.c               | 4 ++--
>>  arch/x86/cpu/intel_common/cpu.c  | 4 ++--
>>  arch/x86/include/asm/processor.h | 2 +-
>>  3 files changed, 5 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 15/51] x86: Move Intel Management Engine code to a common place

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Some of the Intel ME code is common to several Intel CPUs. Move it into a
> common location. Add a header file for report_platform.c also.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use capitals for header guard
>
>  arch/x86/cpu/intel_common/Makefile                 |   2 +
>  .../cpu/{ivybridge => intel_common}/me_status.c    |  20 +-
>  .../{ivybridge => intel_common}/report_platform.c  |   2 +-
>  arch/x86/cpu/ivybridge/Makefile                    |   2 -
>  arch/x86/cpu/ivybridge/early_me.c                  |  31 +-
>  arch/x86/cpu/ivybridge/sdram.c                     |   3 +-
>  arch/x86/include/asm/arch-ivybridge/me.h           | 333 +-----------------
>  arch/x86/include/asm/arch-ivybridge/sandybridge.h  |   2 -
>  arch/x86/include/asm/me_common.h                   | 372 +++++++++++++++++++++
>  arch/x86/include/asm/report_platform.h             |  19 ++
>  10 files changed, 417 insertions(+), 369 deletions(-)
>  rename arch/x86/cpu/{ivybridge => intel_common}/me_status.c (93%)
>  rename arch/x86/cpu/{ivybridge => intel_common}/report_platform.c (98%)
>  create mode 100644 arch/x86/include/asm/me_common.h
>  create mode 100644 arch/x86/include/asm/report_platform.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 16/51] x86: ivybridge: Drop sandybridge_early_init()

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> This function was removed in the previous clean-up. Drop it from the header
> file also.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 --
>  1 file changed, 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 17/51] x86: Move common PCH code into a common place

[Bin Meng]

Hi Simon,

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> The SATA indexed register write functions are common to several Intel PCHs.
> Move this into a common location.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/intel_common/Makefile        |  1 +
>  arch/x86/cpu/intel_common/pch_common.c    | 25 ++++++++++++++

Can you rename this to pch.c, to keep consistency with other files in
the same directory?

>  arch/x86/cpu/ivybridge/cpu.c              |  1 +
>  arch/x86/cpu/ivybridge/sata.c             | 47 +++++++++-----------------
>  arch/x86/include/asm/arch-ivybridge/pch.h | 53 -----------------------------
>  arch/x86/include/asm/pch_common.h         | 56 +++++++++++++++++++++++++++++++
>  6 files changed, 99 insertions(+), 84 deletions(-)
>  create mode 100644 arch/x86/cpu/intel_common/pch_common.c
>  create mode 100644 arch/x86/include/asm/pch_common.h
>

Regards,
Bin

[U-Boot] [PATCH v2 18/51] x86: Add common SDRAM-init code

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> The code to call the memory reference code is common to several Intel CPUs.
> Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
> (PEI), where EFI stands for Extensible Firmware Interface.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Rename sdram_common.c to mrc.c
>
>  arch/x86/cpu/intel_common/Makefile |   1 +
>  arch/x86/cpu/intel_common/mrc.c    | 271 +++++++++++++++++++++++++++++++++++++
>  arch/x86/include/asm/mrc_common.h  |  55 ++++++++
>  3 files changed, 327 insertions(+)
>  create mode 100644 arch/x86/cpu/intel_common/mrc.c
>  create mode 100644 arch/x86/include/asm/mrc_common.h
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 16/51] x86: ivybridge: Drop sandybridge_early_init()

[Bin Meng]

On Mon, Mar 14, 2016 at 12:58 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> This function was removed in the previous clean-up. Drop it from the header
>> file also.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 --
>>  1 file changed, 2 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 20/51] x86: dts: Drop memory SPD compatible string

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> This is not needed now that the memory controller driver has the SPD data
> in its own node.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/dts/chromebook_link.dts | 1 -
>  include/fdtdec.h                 | 1 -
>  lib/fdtdec.c                     | 1 -
>  3 files changed, 3 deletions(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 21/51] x86: Add macros to clear and set I/O bits

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> The clrsetbits_...() macros are useful for working with memory mapped I/O.
> But they do not work with I/O space, as used on x86 machines.
>
> Add some macros to provide similar features for I/O.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Use setio_32() instead of setio_le32(), etc.
>
>  arch/x86/include/asm/io.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 23/51] x86: Move common MRC Kconfig options to the common file

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> At present the MRC options are private to ivybridge. Other Intel CPUs also
> use these settings. Move them to a common place.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Add Kconfig help for the moved options
> - Fix tab indentation
>
>  arch/x86/Kconfig               | 61 ++++++++++++++++++++++++++++++++++++++++++
>  arch/x86/cpu/ivybridge/Kconfig | 27 +------------------
>  2 files changed, 62 insertions(+), 26 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 24/51] x86: Record the CPU details when starting each core

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> As each core starts up, record its microcode version and CPU ID so these can
> be presented with the 'cpu detail' command.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Don't try to read microcode version on quark
> - Use gd->arch.x86_device instead of reading the device ID again
>
>  arch/x86/cpu/intel_common/microcode.c | 7 ++++++-
>  arch/x86/cpu/mp_init.c                | 5 +++++
>  arch/x86/include/asm/microcode.h      | 9 +++++++++
>  3 files changed, 20 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 20/51] x86: dts: Drop memory SPD compatible string

[Bin Meng]

On Mon, Mar 14, 2016 at 1:07 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> This is not needed now that the memory controller driver has the SPD data
>> in its own node.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/dts/chromebook_link.dts | 1 -
>>  include/fdtdec.h                 | 1 -
>>  lib/fdtdec.c                     | 1 -
>>  3 files changed, 3 deletions(-)
>>
>
> applied to u-boot-x86/next, thanks!

Ah, this one does not pass buildman as it has dependencies on previous
patches. Revert this one.

Regards,
Bin

[U-Boot] [PATCH v2 21/51] x86: Add macros to clear and set I/O bits

[Bin Meng]

On Mon, Mar 14, 2016 at 1:10 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> The clrsetbits_...() macros are useful for working with memory mapped I/O.
>> But they do not work with I/O space, as used on x86 machines.
>>
>> Add some macros to provide similar features for I/O.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Use setio_32() instead of setio_le32(), etc.
>>
>>  arch/x86/include/asm/io.h | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 22/51] x86: Allow I/O functions to use pointers

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> It is common with memory-mapped I/O to use the address of a structure member
> to access memory, as in:
>
>    struct some_regs {
>       u32 ctrl;
>       u32 data;
>    }
>
>    struct some_regs *regs = (struct some_regs *)BASE_ADDRESS;
>
>    writel(1, &reg->ctrl);
>    writel(2, &reg->data);
>
> This does not currently work with inl(), outl(), etc. Add a cast to permit
> this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/io.h | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 23/51] x86: Move common MRC Kconfig options to the common file

[Bin Meng]

On Mon, Mar 14, 2016 at 1:13 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> At present the MRC options are private to ivybridge. Other Intel CPUs also
>> use these settings. Move them to a common place.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Add Kconfig help for the moved options
>> - Fix tab indentation
>>
>>  arch/x86/Kconfig               | 61 ++++++++++++++++++++++++++++++++++++++++++
>>  arch/x86/cpu/ivybridge/Kconfig | 27 +------------------
>>  2 files changed, 62 insertions(+), 26 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 24/51] x86: Record the CPU details when starting each core

[Bin Meng]

On Mon, Mar 14, 2016 at 1:15 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> As each core starts up, record its microcode version and CPU ID so these can
>> be presented with the 'cpu detail' command.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Don't try to read microcode version on quark
>> - Use gd->arch.x86_device instead of reading the device ID again
>>
>>  arch/x86/cpu/intel_common/microcode.c | 7 ++++++-
>>  arch/x86/cpu/mp_init.c                | 5 +++++
>>  arch/x86/include/asm/microcode.h      | 9 +++++++++
>>  3 files changed, 20 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 25/51] x86: ivybridge: Show microcode version for each core

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Enable the microcode feature so that the microcode version is shown with the
> 'cpu detail' command.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Rename subject to 'core' instead of 'code'
>
>  arch/x86/cpu/ivybridge/model_206ax.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 26/51] x86: Update microcode for secondary CPUs

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Each CPU needs to have its microcode loaded. Add support for this so that
> all CPUs will have the same version.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Fix micrcode typo
> - Don't try to update microcode on FSP platforms
>
>  arch/x86/cpu/cpu.c               | 1 +
>  arch/x86/cpu/intel_common/car.S  | 2 ++
>  arch/x86/cpu/mp_init.c           | 6 ++++--
>  arch/x86/include/asm/microcode.h | 3 +++
>  arch/x86/lib/fsp/fsp_car.S       | 2 ++
>  5 files changed, 12 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 27/51] x86: link: Add pin configuration to the device tree

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> At present pin configuration on link does not use the standard mechanism,
> but some rather ugly custom code. As a first step to resolving this, add the
> pin configuration to the device tree.
>
> Four of the GPIOs must be available before relocation (for SDRAM pin
> strapping).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Add GPIO output definition for a1 and a6
>
>  arch/x86/dts/chromebook_link.dts | 155 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 155 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 28/51] x86: Add an ICH6 pin configuration driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a driver which sets up the pin configuration on x86 devices with an ICH6
> (or later) Platform Controller Hub.
>
> The driver is not in the pinctrl uclass due to some oddities of the way x86
> devices work:
>
> - The GPIO controller is not present in I/O space until it is set up
> - This is done by writing a register in the PCH
> - The PCH has a driver which itself uses PCI, another driver
> - The pinctrl uclass requires that a pinctrl device be available before any
> other device can be probed
>
> It would be possible to work around the limitations by:
> - Hard-coding the GPIO address rather than reading it from the PCH
> - Using special x86 PCI access to set the GPIO address in the PCH
>
> However it is not clear that this is better, since the pin configuration
> driver does not actually provide normal pin configuration services - it
> simply sets up all the pins statically when probed. While this remains the
> case, it seems better to use a syscon uclass instead. This can be probed
> whenever it is needed, without any limitations.
>
> Also add an 'invert' property to support inverting the input.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Use setio_32() instead of setio_le32(), etc.
>
>  arch/x86/include/asm/cpu.h                         |   1 +
>  arch/x86/lib/Makefile                              |   1 +
>  arch/x86/lib/pinctrl_ich6.c                        | 216 +++++++++++++++++++++
>  .../gpio/intel,x86-pinctrl.txt                     |   1 +
>  4 files changed, 219 insertions(+)
>  create mode 100644 arch/x86/lib/pinctrl_ich6.c
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 26/51] x86: Update microcode for secondary CPUs

[Bin Meng]

On Mon, Mar 14, 2016 at 1:41 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> Each CPU needs to have its microcode loaded. Add support for this so that
>> all CPUs will have the same version.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Fix micrcode typo
>> - Don't try to update microcode on FSP platforms
>>
>>  arch/x86/cpu/cpu.c               | 1 +
>>  arch/x86/cpu/intel_common/car.S  | 2 ++
>>  arch/x86/cpu/mp_init.c           | 6 ++++--
>>  arch/x86/include/asm/microcode.h | 3 +++
>>  arch/x86/lib/fsp/fsp_car.S       | 2 ++
>>  5 files changed, 12 insertions(+), 2 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 27/51] x86: link: Add pin configuration to the device tree

[Bin Meng]

On Mon, Mar 14, 2016 at 1:43 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> At present pin configuration on link does not use the standard mechanism,
>> but some rather ugly custom code. As a first step to resolving this, add the
>> pin configuration to the device tree.
>>
>> Four of the GPIOs must be available before relocation (for SDRAM pin
>> strapping).
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Add GPIO output definition for a1 and a6
>>
>>  arch/x86/dts/chromebook_link.dts | 155 +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 155 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 28/51] x86: Add an ICH6 pin configuration driver

[Bin Meng]

On Mon, Mar 14, 2016 at 1:44 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> Add a driver which sets up the pin configuration on x86 devices with an ICH6
>> (or later) Platform Controller Hub.
>>
>> The driver is not in the pinctrl uclass due to some oddities of the way x86
>> devices work:
>>
>> - The GPIO controller is not present in I/O space until it is set up
>> - This is done by writing a register in the PCH
>> - The PCH has a driver which itself uses PCI, another driver
>> - The pinctrl uclass requires that a pinctrl device be available before any
>> other device can be probed
>>
>> It would be possible to work around the limitations by:
>> - Hard-coding the GPIO address rather than reading it from the PCH
>> - Using special x86 PCI access to set the GPIO address in the PCH
>>
>> However it is not clear that this is better, since the pin configuration
>> driver does not actually provide normal pin configuration services - it
>> simply sets up all the pins statically when probed. While this remains the
>> case, it seems better to use a syscon uclass instead. This can be probed
>> whenever it is needed, without any limitations.
>>
>> Also add an 'invert' property to support inverting the input.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Use setio_32() instead of setio_le32(), etc.
>>
>>  arch/x86/include/asm/cpu.h                         |   1 +
>>  arch/x86/lib/Makefile                              |   1 +
>>  arch/x86/lib/pinctrl_ich6.c                        | 216 +++++++++++++++++++++
>>  .../gpio/intel,x86-pinctrl.txt                     |   1 +
>>  4 files changed, 219 insertions(+)
>>  create mode 100644 arch/x86/lib/pinctrl_ich6.c
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 29/51] x86: gpio: Allow the pinctrl driver to set up the pin config

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Rather than setting up the pin configuration in the GPIO driver, use the
> new pinctrl driver to do it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  configs/bayleybay_defconfig     |   2 +
>  configs/cougarcanyon2_defconfig |   2 +
>  configs/crownbay_defconfig      |   2 +
>  configs/galileo_defconfig       |   2 +
>  configs/minnowmax_defconfig     |   6 +-
>  drivers/gpio/intel_ich6_gpio.c  | 180 ++--------------------------------------
>  6 files changed, 17 insertions(+), 177 deletions(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 30/51] x86: Drop all the old pin configuration code

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> We don't need this anymore - we can use device tree and the new pinconfig
> driver instead.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/include/asm/gpio.h               | 141 ------------------------------
>  board/coreboot/coreboot/coreboot.c        |   5 --
>  board/efi/efi-x86/efi.c                   |   5 --
>  board/google/chromebook_link/link.c       | 138 -----------------------------
>  board/google/chromebox_panther/panther.c  |   4 -
>  board/intel/bayleybay/bayleybay.c         |   5 --
>  board/intel/cougarcanyon2/cougarcanyon2.c |   5 --
>  board/intel/crownbay/crownbay.c           |   5 --
>  board/intel/galileo/galileo.c             |   5 --
>  board/intel/minnowmax/minnowmax.c         |   8 --
>  drivers/gpio/intel_ich6_gpio.c            |  11 ---
>  include/fdtdec.h                          |   1 -
>  lib/fdtdec.c                              |   1 -
>  13 files changed, 334 deletions(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 31/51] x86: Add support for running Intel reference code

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Intel has invented yet another binary blob which firmware is required to
> run. This is run after SDRAM is ready. It is linked to load at a particular
> address, typically 0, but is a relocatable ELF so can be moved if required.
>
> Add support for this in the build system. The file should be placed in the
> board directory, and called refcode.elf.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Fix 'PCB' typo (should be 'PCH')
>
>  Makefile                   | 14 +++++++++++++-
>  arch/x86/Kconfig           | 11 +++++++++++
>  arch/x86/include/asm/cpu.h | 12 ++++++++++++
>  3 files changed, 36 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 31/51] x86: Add support for running Intel reference code

[Bin Meng]

On Mon, Mar 14, 2016 at 2:03 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> Intel has invented yet another binary blob which firmware is required to
>> run. This is run after SDRAM is ready. It is linked to load at a particular
>> address, typically 0, but is a relocatable ELF so can be moved if required.
>>
>> Add support for this in the build system. The file should be placed in the
>> board directory, and called refcode.elf.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Fix 'PCB' typo (should be 'PCH')
>>
>>  Makefile                   | 14 +++++++++++++-
>>  arch/x86/Kconfig           | 11 +++++++++++
>>  arch/x86/include/asm/cpu.h | 12 ++++++++++++
>>  3 files changed, 36 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 32/51] x86: dts: Update the pinctrl binding a little

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Make a few minor updates to make the meaning clearer.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  doc/device-tree-bindings/gpio/intel,x86-pinctrl.txt | 21 +++++++++++----------
>  1 file changed, 11 insertions(+), 10 deletions(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 33/51] x86: Add basic support for broadwell

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> This adds the broadwell architecture, with the CPU driver and some useful
> header files.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/Kconfig                            |   1 +
>  arch/x86/cpu/Makefile                       |   1 +
>  arch/x86/cpu/broadwell/Kconfig              |  30 ++
>  arch/x86/cpu/broadwell/Makefile             |   7 +
>  arch/x86/cpu/broadwell/cpu.c                | 761 ++++++++++++++++++++++++++++
>  arch/x86/include/asm/arch-broadwell/cpu.h   |  48 ++
>  arch/x86/include/asm/arch-broadwell/iomap.h |  53 ++
>  arch/x86/include/asm/arch-broadwell/me.h    | 200 ++++++++
>  arch/x86/include/asm/arch-broadwell/rcb.h   |  58 +++
>  arch/x86/include/asm/arch-broadwell/spi.h   |  87 ++++
>  10 files changed, 1246 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/Kconfig
>  create mode 100644 arch/x86/cpu/broadwell/Makefile
>  create mode 100644 arch/x86/cpu/broadwell/cpu.c
>  create mode 100644 arch/x86/include/asm/arch-broadwell/cpu.h
>  create mode 100644 arch/x86/include/asm/arch-broadwell/iomap.h
>  create mode 100644 arch/x86/include/asm/arch-broadwell/me.h
>  create mode 100644 arch/x86/include/asm/arch-broadwell/rcb.h
>  create mode 100644 arch/x86/include/asm/arch-broadwell/spi.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 34/51] x86: broadwell: Add a PCH driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a driver for the broadwell low-power platform controller hub.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use setio_32() instead of setio_le32(), etc.
> - Use capitals for header guard
>
>  arch/x86/cpu/broadwell/Makefile           |   2 +
>  arch/x86/cpu/broadwell/iobp.c             | 144 ++++++++
>  arch/x86/cpu/broadwell/pch.c              | 540 ++++++++++++++++++++++++++++++
>  arch/x86/include/asm/arch-broadwell/pch.h | 153 +++++++++
>  4 files changed, 839 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/iobp.c
>  create mode 100644 arch/x86/cpu/broadwell/pch.c
>  create mode 100644 arch/x86/include/asm/arch-broadwell/pch.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 35/51] x86: broadwell: Add a pinctrl driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> GPIO pins need to be set up on start-up. Add a driver to provide this,
> configured from the device tree.
>
> The binding is slightly different from the existing ICH6 binding, since that
> is quite verbose. The new binding should be just as extensible.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use capitals for header guard
>
>  arch/x86/cpu/broadwell/Makefile                    |   1 +
>  arch/x86/cpu/broadwell/pinctrl_broadwell.c         | 278 +++++++++++++++++++++
>  arch/x86/include/asm/arch-broadwell/gpio.h         |  91 +++++++
>  .../gpio/intel,x86-broadwell-pinctrl.txt           | 208 +++++++++++++++
>  include/dt-bindings/gpio/x86-gpio.h                |  12 +
>  5 files changed, 590 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/pinctrl_broadwell.c
>  create mode 100644 arch/x86/include/asm/arch-broadwell/gpio.h
>  create mode 100644 doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 36/51] x86: broadwell: Add a SATA driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a SATA driver for broadwell. This supports connecting an SSD and the
> usual U-Boot commands to read and write data.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/broadwell/Makefile |   1 +
>  arch/x86/cpu/broadwell/sata.c   | 269 ++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 270 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/sata.c
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 37/51] x86: broadwell: Add a northbridge driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a driver for the broadwell northbridge. This sets up the location of
> several blocks of registers.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/broadwell/Makefile      |  1 +
>  arch/x86/cpu/broadwell/northbridge.c | 59 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 60 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/northbridge.c
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 38/51] x86: broadwell: Add an LPC driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a driver for the broadwell LPC (low-pin-count peripheral). This mostly
> uses common code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use capitals for header guard
>
>  arch/x86/cpu/broadwell/Makefile           |  1 +
>  arch/x86/cpu/broadwell/lpc.c              | 77 +++++++++++++++++++++++++++++++
>  arch/x86/include/asm/arch-broadwell/lpc.h | 32 +++++++++++++
>  3 files changed, 110 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/lpc.c
>  create mode 100644 arch/x86/include/asm/arch-broadwell/lpc.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 39/51] x86: broadwell: Add reference code support

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Broadwell needs a special binary blob to set up the PCH. Add code to run
> this on start-up.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Fix comment style
>
>  arch/x86/cpu/broadwell/Makefile  |   1 +
>  arch/x86/cpu/broadwell/refcode.c | 113 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 114 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/refcode.c
>

Acked-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 39/51] x86: broadwell: Add reference code support

[Bin Meng]

On Mon, Mar 14, 2016 at 2:29 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> Broadwell needs a special binary blob to set up the PCH. Add code to run
>> this on start-up.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Fix comment style
>>
>>  arch/x86/cpu/broadwell/Makefile  |   1 +
>>  arch/x86/cpu/broadwell/refcode.c | 113 +++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 114 insertions(+)
>>  create mode 100644 arch/x86/cpu/broadwell/refcode.c
>>
>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 40/51] x86: broadwell: Add power-control support

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Broadwell requires quite a bit of power-management setup. Add code to set
> this up correctly.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use capitals for header guard
>
>  arch/x86/cpu/broadwell/Makefile          |   1 +
>  arch/x86/cpu/broadwell/power_state.c     |  89 +++++++++++++++++++++
>  arch/x86/include/asm/arch-broadwell/pm.h | 129 +++++++++++++++++++++++++++++++
>  3 files changed, 219 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/power_state.c
>  create mode 100644 arch/x86/include/asm/arch-broadwell/pm.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 41/51] x86: broadwell: Add support for SDRAM setup

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Broadwell uses a binary blob called the memory reference code (MRC) to start
> up its SDRAM. This is similar to ivybridge so we can mostly use common code
> for running this blob.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Rename sdram to mrc
>
>  arch/x86/cpu/broadwell/Makefile                |   1 +
>  arch/x86/cpu/broadwell/sdram.c                 | 307 +++++++++++++++++++++++++
>  arch/x86/include/asm/arch-broadwell/pei_data.h | 177 ++++++++++++++
>  arch/x86/include/asm/global_data.h             |  24 ++
>  4 files changed, 509 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/sdram.c
>  create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h
>

Acked-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 43/51] x86: broadwell: Add support for high-speed I/O lane with ME

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Provide a way to determine the HSIO (high-speed I/O) version supported by
> the Intel Management Engine (ME) implementation on the platform.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/broadwell/Makefile |  1 +
>  arch/x86/cpu/broadwell/me.c     | 57 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 58 insertions(+)
>  create mode 100644 arch/x86/cpu/broadwell/me.c
>

Acked-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 41/51] x86: broadwell: Add support for SDRAM setup

[Bin Meng]

On Mon, Mar 14, 2016 at 2:33 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> Broadwell uses a binary blob called the memory reference code (MRC) to start
>> up its SDRAM. This is similar to ivybridge so we can mostly use common code
>> for running this blob.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2:
>> - Rename sdram to mrc
>>
>>  arch/x86/cpu/broadwell/Makefile                |   1 +
>>  arch/x86/cpu/broadwell/sdram.c                 | 307 +++++++++++++++++++++++++
>>  arch/x86/include/asm/arch-broadwell/pei_data.h | 177 ++++++++++++++
>>  arch/x86/include/asm/global_data.h             |  24 ++
>>  4 files changed, 509 insertions(+)
>>  create mode 100644 arch/x86/cpu/broadwell/sdram.c
>>  create mode 100644 arch/x86/include/asm/arch-broadwell/pei_data.h
>>
>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 42/51] x86: broadwell: Add a GPIO driver

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a GPIO driver for the GPIO peripheral found on broadwell devices.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Use setio_32() instead of setio_le32(), etc.
> - Fix 'configure' typo
>
>  drivers/gpio/Kconfig                |   9 ++
>  drivers/gpio/Makefile               |   1 +
>  drivers/gpio/intel_broadwell_gpio.c | 198 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 208 insertions(+)
>  create mode 100644 drivers/gpio/intel_broadwell_gpio.c
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 43/51] x86: broadwell: Add support for high-speed I/O lane with ME

[Bin Meng]

On Mon, Mar 14, 2016 at 2:35 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
>> Provide a way to determine the HSIO (high-speed I/O) version supported by
>> the Intel Management Engine (ME) implementation on the platform.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/broadwell/Makefile |  1 +
>>  arch/x86/cpu/broadwell/me.c     | 57 +++++++++++++++++++++++++++++++++++++++++
>>  2 files changed, 58 insertions(+)
>>  create mode 100644 arch/x86/cpu/broadwell/me.c
>>
>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 45/51] x86: broadwell: Add video support

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a video driver for Intel's broadwell integrated graphics controller.
> This uses a binary blob for most init, with the driver just performing a few
> basic tasks.
>
> This driver supports VESA as the mode-setting mechanism. Since most boards
> don't support driver model yet with VESA, a special case is added to the
> Kconfig for broadwell. Eventually all boards will use driver model and this
> can be removed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  drivers/video/Kconfig         |  14 +-
>  drivers/video/Makefile        |   2 +
>  drivers/video/broadwell_igd.c | 797 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/video/i915_reg.h      | 362 +++++++++++++++++++
>  4 files changed, 1174 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/video/broadwell_igd.c
>  create mode 100644 drivers/video/i915_reg.h
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 46/51] x86: Add a default address for reference code

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add an address which can be used for loading and running the reference code
> when needed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  include/configs/x86-chromebook.h | 2 ++
>  1 file changed, 2 insertions(+)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 47/51] x86: Use white on black for the console on chromebooks

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> This is a little easier on the eyes, particularly when the backlight is set
> to maximum.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  include/configs/x86-chromebook.h | 2 ++
>  1 file changed, 2 insertions(+)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 48/51] x86: Update README for new developments

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Update a few points which have become out-of-date.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2:
> - Correct naming of Intel platforms
>
>  doc/README.x86 | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 49/51] x86: Add a function to set the IOAPIC ID

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a function to set the ID in the IOAPIC.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/ioapic.c         | 16 ++++++++++++++++
>  arch/x86/include/asm/ioapic.h |  2 ++
>  2 files changed, 18 insertions(+)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 50/51] x86: Fix a header nit in x86-chromebook.h

[Bin Meng]

On Sat, Mar 12, 2016 at 1:07 PM, Simon Glass <sjg@chromium.org> wrote:
> There is an extra line in the comment in the header. Remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  include/configs/x86-chromebook.h | 1 -
>  1 file changed, 1 deletion(-)
>

applied to u-boot-x86/next, thanks!

[U-Boot] [PATCH v2 00/51] x86: Add support for samus

[Bin Meng]

Hi Simon,

On Sat, Mar 12, 2016 at 1:06 PM, Simon Glass <sjg@chromium.org> wrote:
> This series adds support for samus, the Chromebook Pixel 2015. Since it is
> only the second board added that does not use an FSP, there is quite a bit
> of refactoring involved to avoid code duplication.
>
> Samus uses roughly the same binary blobs as link, except now there is one
> more called the reference code binary. The only available binary for this
> is a coreboot 'rmodule' extracted from flash. This is a simplified ELF
> format so it fairly easy to load and use.
>
> It is also possible to boot U-Boot from coreboot on samus. This works well
> but for a delay for non-existent IDE on start-up. The standard build does
> not work with binaries taken from flash, so it isn't easy to replicate
> this - you'll just have to take my word for it. I am working on getting that
> figured out - coreboot recently gained upstream support for loading U-Boot
> as a payload, so it should be possible to get this working nicely before
> long.
>
> In any case much of the code comes from coreboot - individual files are
> credited with their source.
>
> Perhaps the main value of this series is the improved non-FSP support and
> additions for broadwell, which samus uses. It should make it easier to add
> support for future non-FSP platforms.
>
> Changes in v2:
> - Use a #define for the output flush command
> - Adjust the code order slightly
> - Simplify the code in serial_initialize()
> - Use gd->arch.x86_mask to get the stepping value
> - Rename microcode_intel.c to microcode.c
> - Use capitals for header guard
> - Use capitals for header guard
> - Move cougarcanyon lpc_common.h include to this patch
> - Use capitals for header guard
> - Use capitals for header guard
> - Rename sdram_common.c to mrc.c
> - Rename sdram to mrc
> - Use setio_32() instead of setio_le32(), etc.
> - Add Kconfig help for the moved options
> - Fix tab indentation
> - Don't try to read microcode version on quark
> - Use gd->arch.x86_device instead of reading the device ID again
> - Rename subject to 'core' instead of 'code'
> - Fix micrcode typo
> - Don't try to update microcode on FSP platforms
> - Add GPIO output definition for a1 and a6
> - Use setio_32() instead of setio_le32(), etc.
> - Fix 'PCB' typo (should be 'PCH')
> - Use setio_32() instead of setio_le32(), etc.
> - Use capitals for header guard
> - Use capitals for header guard
> - Use capitals for header guard
> - Fix comment style
> - Use capitals for header guard
> - Rename sdram to mrc
> - Use setio_32() instead of setio_le32(), etc.
> - Fix 'configure' typo
> - Correct naming of Intel platforms
>

I've applied most of the series to u-boot-x86/next to make things
easier for the next spin. Please work on the remaining 8 patches.
Thanks!

Regards,
Bin