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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v4 1/4] fu540: prci: add request and free clock handlers
Date: Wed, 24 Jun 2020 09:20:14 +0800	[thread overview]
Message-ID: <CAEUhbmUmQ4a4fRPhDtPD+0_z8iY2gotA23cM59Nw6yC71_wL2Q@mail.gmail.com> (raw)
In-Reply-To: <1592745008-17196-2-git-send-email-sagar.kadam@sifive.com>

Hi Sagar,

On Sun, Jun 21, 2020 at 9:10 PM Sagar Shrikant Kadam
<sagar.kadam@sifive.com> wrote:
>
> Add clk_request handler to check if a valid clock is requested.
> Here clk_free handler is added for debug purpose which will display
> details of clock passed to clk_free.
>
> Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
> ---
>  drivers/clk/sifive/fu540-prci.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
> index fe6e0d4..9a9ff6b 100644
> --- a/drivers/clk/sifive/fu540-prci.c
> +++ b/drivers/clk/sifive/fu540-prci.c
> @@ -686,6 +686,25 @@ static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
>         return rate;
>  }
>
> +static int sifive_fu540_prci_clk_request(struct clk *clk)
> +{
> +       debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
> +             clk->id);
> +
> +       if (clk->id >= ARRAY_SIZE(__prci_init_clocks))
> +               return -EINVAL;
> +
> +       return 0;
> +}
> +
> +static int sifive_fu540_prci_clk_free(struct clk *clk)
> +{
> +       debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
> +             clk->id);
> +
> +       return 0;
> +}

It seems these 2 routines do not actually do anything? Is this for
debugging purposes?

Regards,
Bin

  parent reply	other threads:[~2020-06-24  1:20 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-21 13:10 [PATCH v4 0/4] update clock handler and proper cpu features Sagar Shrikant Kadam
2020-06-21 13:10 ` [PATCH v4 1/4] fu540: prci: add request and free clock handlers Sagar Shrikant Kadam
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA471B1E9@ATCPCS16.andestech.com>
2020-06-22  1:53     ` Rick Chen
2020-06-22  4:46       ` Sagar Kadam
2020-06-24  1:35         ` Rick Chen
2020-06-24  1:38           ` Bin Meng
2020-06-24  1:46             ` Rick Chen
2020-06-24  9:51               ` Sagar Kadam
2020-06-24  1:20   ` Bin Meng [this message]
2020-06-24 10:58     ` Sagar Kadam
2020-06-24 23:21       ` Bin Meng
2020-06-25  4:46         ` Sagar Kadam
2020-06-25  5:41           ` Sagar Kadam
2020-06-21 13:10 ` [PATCH v4 2/4] riscv: dts: hifive-unleashed-a00: add cpu aliases Sagar Shrikant Kadam
2020-06-24  1:21   ` Bin Meng
2020-06-24  6:53     ` Sagar Kadam
2020-06-21 13:10 ` [PATCH v4 3/4] riscv: cpu: fixes to display proper CPU features Sagar Shrikant Kadam
2020-06-24  1:26   ` Bin Meng
2020-06-24  1:46     ` Simon Glass
2020-06-21 13:10 ` [PATCH v4 4/4] riscv: cpu: check and append L1 cache to cpu features Sagar Shrikant Kadam
2020-06-24  1:28   ` Bin Meng
2020-06-24  6:37     ` Sagar Kadam
2020-06-24  1:15 ` [PATCH v4 0/4] update clock handler and proper " Bin Meng
2020-06-24  6:01   ` Sagar Kadam
2020-06-24  7:37     ` Bin Meng

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