[U-Boot] [PATCH v3 00/62] x86: Add initial support for 64-bit U-Boot

[U-Boot] [PATCH v3 00/62] x86: Add initial support for 64-bit U-Boot

[Simon Glass]

At present U-Boot runs entirely in 32-bit mode on x86, except for the
initial switch from 16-bit mode. On 64-bit machines it is possible to run
in 64-bit mode. This series starts the process of adding this support.

The main benefit of 64-bit mode for a boot loader is direct access to all
available memory. There are also more registers, but this makes very little
difference.

This feature is implemented by putting all of the 32-bit code in an SPL
build. SPL then runs through all the init that has to be done in 32-bit
mode, changes to 64-bit mode and then jumps to U-Boot proper.

Typically the total code size increases slightly. For example, on link in
32-bit mode, U-Boot has around 480KB of code (admittedly with a large
number of features enabled). In 64-bit mode, U-Boot falls to around 460KB,
but SPL adds another 60KB, for a net increase of 40KB. Partly this is due
to code duplication and partly it is due to the worse code density of
64-bit code on x86.

Many major features are not implemented yet, for example:
- SDRAM sizing
- Booting linux
- FSP support
- EFI support
- SCSI device init
- Running video ROMs

Still, this is a big step forward towards full 64-bit support. To enable it,
select CONFIG_X86_RUN_64BIT.

This series is available at u-boot-x86/64-working

Changes in v3:
- update iomux.c and usb_kbd.c also
- Drop WIP tag as this patch is actually needed
- Use tab instead of space in Kconfig help line
- Fix s/32-bit init/16-bit init/ and expand the comment
- Drop unused headers
- Drop unused board_debug_uart_init function
- Use call instead of callq
- Move 'const' change into its own patch
- Add new patch to use static const for the board_f/r init sequences
- Add a TODO to board_init_r() regarding the use of the new_gd parameter
- Mention the commit ID containing information about the need for reloc checks
- Drop the pre-panic printf() of the relocation addresses
- Update copyright year
- Drop duplicate line in header commment
- Add a comment about stack position to x86_spl_init()
- Add a parameter to the use of the SPL_LOAD_IMAGE_METHOD() macro
- Fix printf() warning in spl_board_load_image()
- Drop blank line at end of arch/x86/cpu/x86_64/interrupts.c
- Drop #include of debug_uart.h
- Add a TODO to look at using a fixed register for gd on x86_64
- Expand the TODO about the necessary printch() call
- Add a required debug_uart.h #include in this patch
- Fix 'skipt' typo in the subject
- Put dummy misc_init_r() and print_cpuinfo() functions into cpu.c
- Drop duplicate comment line in header
- Add a TODO indicating that booting 32- and 64-bit kernels should be supported
- Expand pre-reloc malloc() size in this patch to prevent boot failure
- Remove duplicate CONFIG_VIDEO_IVYBRIDGE_IGD in defconfig file
- Drop the unnecessary defconfig changes for chromebook_link
- Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application'
- Drop patch 'Mention the MRC region in the README'
- Drop patch 'x86: link: Add build options for SPL'
- Drop unnecessary defconfig options for chromebook_link64
- Avoid including helloworld.efi in the 64-bit U-Boot

Changes in v2:
- Show the error value in spl_spi_load_image()
- Move table-related changes from a later patch
- Rebase to mainline
- Drop the write_smbios_table_wrapper() function
- Drop change to gma.c
- Output error code values in debug() statements
- Fix cast in bd82x6x_video_probe() also
- Fix cast in get_guid_hob_data() also
- Move table-related changes to an earlier patch
- Add the 'val' parameter to longjmp()
- Drop patch 'video: Use ulong for video frame buffer address'
- Add a new 64-bit link config instead of changing the existing one

Simon Glass (62):
  console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL
  spl: spi: Add a debug message if loading fails
  spl: Makefile: Define SPL_ earlier
  spl: Allow CPU drivers to be used in SPL
  spl: Allow PCI drivers to be used in SPL
  spl: Allow RTC drivers to be used in SPL
  spl: Allow timer drivers to be used in SPL
  spl: Allow PCH drivers to be used in SPL
  spl: Don't create a BSS padding when it is separate
  x86: Use unsigned long for address in table generation
  x86: Update mpspec to build on 64-bit machines
  x86: ivybridge: Declare global data where it is used
  x86: ivybridge: Add more debugging for failures
  x86: ivybridge: Fix types for 64-bit compilation
  x86: dts: Mark serial as needed before relocation
  x86: fsp: Fix cast for 64-bit compilation
  x86: lib: Fix types and casts for 64-bit compilation
  x86: Add Kconfig options to build 64-bit U-Boot
  x86: Kconfig: Add location options for 16/32-bit init
  x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR
  x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR
  x86: ivybridge: Allow 32-bit init to move to SPL
  x86: Add 64-bit start-up code
  x86: board_f: Update init sequence for 64-bit startup
  board_f/r: Use static const for the init sequences
  x86: board_r: Set the global data pointer after relocation
  x86: Do relocation before clearing BSS
  x86: Refactor relocation to prepare for 64-bit
  x86: Add support for 64-bit relocation
  x86: Tidy up use of size_t in relocation
  x86: Add an SPL implementation
  x86: Move the i386 code into its own directory
  x86: Add cpu code for x86_64
  x86: Support global_data on x86_64
  x86: Fix up CONFIG_X86_64 check
  x86: Add a link script for 64-bit x86
  x86: Add a link script for SPL
  x86: Add SPL build rules for start-up code
  x86: Fix up byteorder.h for x86_64
  x86: Drop flag_is_changable() on x86_64
  x86: Fix up type sizes for 64-bit
  x86: ivybridge: Skip SATA init in SPL
  x86: ivybridge: Provide a dummy SDRAM init for 64-bit
  x86: Don't try to run the VGA BIOS in 64-bit mode
  x86: Don't build call64 and setjmp on 64-bit
  x86: Don't build cpu files which are not supported on 64-bit
  x86: Don't build 32-bit efi files on x86_64
  x86: Don't try to boot Linux from SPL
  x86: Drop interrupt support in 64-bit mode
  x86: Support jumping from SPL to U-Boot
  x86: Move pirq_routing_table to global_data
  x86: Move turbo_state to global_data
  x86: Change irq_already_routed to a local variable
  x86: Move call64 to the i386 directory
  x86: Move setjmp to the i386 directory
  x86: Add a dummy setjmp implementation for x86_64
  x86: link: Add a text base for 64-bit U-Boot
  x86: link: Add SPL declarations to the binman image
  x86: link: Set up device tree for SPL
  x86: link: Add build options for SPL
  x86: Update compile/link flags to support 64-bit U-Boot
  x86: link: Add a config for 64-bit U-Boot

 Makefile                                        |   7 +-
 arch/x86/Kconfig                                |  86 ++++
 arch/x86/Makefile                               |   9 +-
 arch/x86/config.mk                              |  30 +-
 arch/x86/cpu/Makefile                           |  24 +-
 arch/x86/cpu/config.mk                          |   8 +-
 arch/x86/cpu/cpu.c                              | 504 --------------------
 arch/x86/cpu/i386/Makefile                      |   9 +
 arch/x86/cpu/{ => i386}/call64.S                |   3 +
 arch/x86/cpu/i386/cpu.c                         | 599 ++++++++++++++++++++++++
 arch/x86/cpu/{interrupts.c => i386/interrupt.c} |   6 +-
 arch/x86/cpu/{ => i386}/setjmp.S                |   0
 arch/x86/cpu/intel_common/Makefile              |  10 +-
 arch/x86/cpu/irq.c                              |  14 +-
 arch/x86/cpu/ivybridge/Makefile                 |   9 +-
 arch/x86/cpu/ivybridge/bd82x6x.c                |   2 +
 arch/x86/cpu/ivybridge/cpu.c                    |   4 +-
 arch/x86/cpu/ivybridge/lpc.c                    |   2 +
 arch/x86/cpu/ivybridge/model_206ax.c            |   2 +
 arch/x86/cpu/ivybridge/northbridge.c            |   2 +
 arch/x86/cpu/ivybridge/sata.c                   |   4 +-
 arch/x86/cpu/ivybridge/sdram.c                  |  37 +-
 arch/x86/cpu/ivybridge/sdram_nop.c              |  18 +
 arch/x86/cpu/start64.S                          |  28 ++
 arch/x86/cpu/turbo.c                            |   8 +-
 arch/x86/cpu/u-boot-64.lds                      |  76 +++
 arch/x86/cpu/u-boot-spl.lds                     |  74 +++
 arch/x86/cpu/u-boot.lds                         |   2 +-
 arch/x86/cpu/x86_64/Makefile                    |   6 +
 arch/x86/cpu/x86_64/cpu.c                       |  71 +++
 arch/x86/cpu/x86_64/interrupts.c                |  29 ++
 arch/x86/cpu/x86_64/setjmp.c                    |  20 +
 arch/x86/dts/chromebook_link.dts                |  15 +-
 arch/x86/dts/serial.dtsi                        |   1 +
 arch/x86/dts/u-boot.dtsi                        |  19 +
 arch/x86/include/asm/acpi_table.h               |   2 +-
 arch/x86/include/asm/byteorder.h                |  17 +-
 arch/x86/include/asm/cpu.h                      |  12 +
 arch/x86/include/asm/fsp/fsp_hob.h              |   4 +-
 arch/x86/include/asm/global_data.h              |   9 +-
 arch/x86/include/asm/mp.h                       |   3 +
 arch/x86/include/asm/mpspec.h                   |  10 +-
 arch/x86/include/asm/posix_types.h              |   5 +
 arch/x86/include/asm/sfi.h                      |   2 +-
 arch/x86/include/asm/spl.h                      |   8 +
 arch/x86/include/asm/tables.h                   |   2 +-
 arch/x86/include/asm/types.h                    |   5 +
 arch/x86/lib/Makefile                           |  11 +
 arch/x86/lib/acpi_table.c                       |   4 +-
 arch/x86/lib/bios.c                             |   4 +-
 arch/x86/lib/bootm.c                            |   7 +
 arch/x86/lib/init_helpers.c                     |   2 +-
 arch/x86/lib/interrupts.c                       |   5 +
 arch/x86/lib/mpspec.c                           |  14 +-
 arch/x86/lib/pinctrl_ich6.c                     |   2 +-
 arch/x86/lib/pirq_routing.c                     |  14 +-
 arch/x86/lib/relocate.c                         | 100 +++-
 arch/x86/lib/sfi.c                              |   6 +-
 arch/x86/lib/spl.c                              | 153 ++++++
 arch/x86/lib/tables.c                           |  11 +-
 arch/x86/lib/zimage.c                           |   2 +-
 board/google/Kconfig                            |   7 +
 board/google/chromebook_link/Kconfig            |   5 +-
 board/google/chromebook_link/MAINTAINERS        |   7 +
 common/board_f.c                                |  16 +-
 common/board_r.c                                |  12 +-
 common/console.c                                |  30 +-
 common/iomux.c                                  |   4 +-
 common/spl/Kconfig                              |  47 ++
 common/spl/spl_spi.c                            |   5 +-
 common/usb_kbd.c                                |   6 +-
 configs/chromebook_link64_defconfig             |  89 ++++
 configs/chromebook_link_defconfig               |   4 +-
 drivers/Makefile                                |   5 +
 drivers/misc/qfw.c                              |   4 +-
 drivers/pci/pci_rom.c                           |   2 +-
 drivers/video/ivybridge_igd.c                   |   6 +-
 include/configs/chromebook_link.h               |   9 +
 include/smbios.h                                |   4 +-
 lib/smbios.c                                    |  22 +-
 scripts/Makefile.spl                            |  18 +-
 81 files changed, 1773 insertions(+), 681 deletions(-)
 create mode 100644 arch/x86/cpu/i386/Makefile
 rename arch/x86/cpu/{ => i386}/call64.S (98%)
 create mode 100644 arch/x86/cpu/i386/cpu.c
 rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%)
 rename arch/x86/cpu/{ => i386}/setjmp.S (100%)
 create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c
 create mode 100644 arch/x86/cpu/start64.S
 create mode 100644 arch/x86/cpu/u-boot-64.lds
 create mode 100644 arch/x86/cpu/u-boot-spl.lds
 create mode 100644 arch/x86/cpu/x86_64/Makefile
 create mode 100644 arch/x86/cpu/x86_64/cpu.c
 create mode 100644 arch/x86/cpu/x86_64/interrupts.c
 create mode 100644 arch/x86/cpu/x86_64/setjmp.c
 create mode 100644 arch/x86/include/asm/spl.h
 create mode 100644 arch/x86/lib/spl.c
 create mode 100644 configs/chromebook_link64_defconfig

-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 01/62] console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL

[Simon Glass]

CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable
for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these
options will be inactive in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- update iomux.c and usb_kbd.c also

Changes in v2: None

 common/console.c | 30 +++++++++++++++---------------
 common/iomux.c   |  4 ++--
 common/usb_kbd.c |  6 +++---
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/common/console.c b/common/console.c
index e1d84763bdc..1232808df52 100644
--- a/common/console.c
+++ b/common/console.c
@@ -41,14 +41,14 @@ static int on_console(const char *name, const char *value, enum env_op op,
 	case env_op_create:
 	case env_op_overwrite:
 
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 		if (iomux_doenv(console, value))
 			return 1;
 #else
 		/* Try assigning specified device */
 		if (console_assign(console, value) < 0)
 			return 1;
-#endif /* CONFIG_CONSOLE_MUX */
+#endif
 		return 0;
 
 	case env_op_delete:
@@ -85,7 +85,7 @@ static int on_silent(const char *name, const char *value, enum env_op op,
 U_BOOT_ENV_CALLBACK(silent, on_silent);
 #endif
 
-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
+#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
 /*
  * if overwrite_console returns 1, the stdin, stderr and stdout
  * are switched to the serial port, else the settings in the
@@ -98,7 +98,7 @@ extern int overwrite_console(void);
 #define OVERWRITE_CONSOLE 0
 #endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
 
-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
+#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
 
 static int console_setfile(int file, struct stdio_dev * dev)
 {
@@ -145,7 +145,7 @@ static int console_setfile(int file, struct stdio_dev * dev)
 	return error;
 }
 
-#if defined(CONFIG_CONSOLE_MUX)
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 /** Console I/O multiplexing *******************************************/
 
 static struct stdio_dev *tstcdev;
@@ -265,7 +265,7 @@ static inline void console_doenv(int file, struct stdio_dev *dev)
 {
 	console_setfile(file, dev);
 }
-#endif /* defined(CONFIG_CONSOLE_MUX) */
+#endif /* CONIFIG_IS_ENABLED(CONSOLE_MUX) */
 
 /** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/
 
@@ -290,7 +290,7 @@ int serial_printf(const char *fmt, ...)
 int fgetc(int file)
 {
 	if (file < MAX_FILES) {
-#if defined(CONFIG_CONSOLE_MUX)
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 		/*
 		 * Effectively poll for input wherever it may be available.
 		 */
@@ -736,7 +736,7 @@ void stdio_print_current_devices(void)
 	}
 }
 
-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV
+#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV)
 /* Called after the relocation - use desired console functions */
 int console_init_r(void)
 {
@@ -745,7 +745,7 @@ int console_init_r(void)
 #ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 	int i;
 #endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 	int iomux_err = 0;
 #endif
 
@@ -766,7 +766,7 @@ int console_init_r(void)
 		inputdev  = search_device(DEV_FLAGS_INPUT,  stdinname);
 		outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname);
 		errdev    = search_device(DEV_FLAGS_OUTPUT, stderrname);
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 		iomux_err = iomux_doenv(stdin, stdinname);
 		iomux_err += iomux_doenv(stdout, stdoutname);
 		iomux_err += iomux_doenv(stderr, stderrname);
@@ -799,7 +799,7 @@ int console_init_r(void)
 		console_doenv(stdin, inputdev);
 	}
 
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 done:
 #endif
 
@@ -829,7 +829,7 @@ done:
 	return 0;
 }
 
-#else /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
+#else /* !CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
 
 /* Called after the relocation - use desired console functions */
 int console_init_r(void)
@@ -873,7 +873,7 @@ int console_init_r(void)
 	if (outputdev != NULL) {
 		console_setfile(stdout, outputdev);
 		console_setfile(stderr, outputdev);
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 		console_devices[stdout][0] = outputdev;
 		console_devices[stderr][0] = outputdev;
 #endif
@@ -882,7 +882,7 @@ int console_init_r(void)
 	/* Initializes input console */
 	if (inputdev != NULL) {
 		console_setfile(stdin, inputdev);
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 		console_devices[stdin][0] = inputdev;
 #endif
 	}
@@ -907,4 +907,4 @@ int console_init_r(void)
 	return 0;
 }
 
-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */
+#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */
diff --git a/common/iomux.c b/common/iomux.c
index 3d8d00b4486..0e4e6803e7a 100644
--- a/common/iomux.c
+++ b/common/iomux.c
@@ -10,7 +10,7 @@
 #include <serial.h>
 #include <malloc.h>
 
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 void iomux_printdevs(const int console)
 {
 	int i;
@@ -145,4 +145,4 @@ int iomux_doenv(const int console, const char *arg)
 	free(cons_set);
 	return 0;
 }
-#endif /* CONFIG_CONSOLE_MUX */
+#endif /* CONSOLE_MUX */
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 5f9a64ad1c5..d2d29cc98f5 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -516,7 +516,7 @@ static int probe_usb_keyboard(struct usb_device *dev)
 		return error;
 
 	stdinname = getenv("stdin");
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 	error = iomux_doenv(stdin, stdinname);
 	if (error)
 		return error;
@@ -581,7 +581,7 @@ int usb_kbd_deregister(int force)
 		data = usb_kbd_dev->privptr;
 		if (stdio_deregister_dev(dev, force) != 0)
 			return 1;
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 		if (iomux_doenv(stdin, getenv("stdin")) != 0)
 			return 1;
 #endif
@@ -626,7 +626,7 @@ static int usb_kbd_remove(struct udevice *dev)
 		ret = -EPERM;
 		goto err;
 	}
-#ifdef CONFIG_CONSOLE_MUX
+#if CONFIG_IS_ENABLED(CONSOLE_MUX)
 	if (iomux_doenv(stdin, getenv("stdin"))) {
 		ret = -ENOLINK;
 		goto err;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 02/62] spl: spi: Add a debug message if loading fails

[Simon Glass]

This currently fails silently. Add a debug message to aid debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Show the error value in spl_spi_load_image()

 common/spl/spl_spi.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c
index cd1d6b285ef..925a1b14915 100644
--- a/common/spl/spl_spi.c
+++ b/common/spl/spl_spi.c
@@ -96,8 +96,11 @@ static int spl_spi_load_image(struct spl_image_info *spl_image,
 		/* Load u-boot, mkimage header is 64 bytes. */
 		err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40,
 				     (void *)header);
-		if (err)
+		if (err) {
+			debug("%s: Failed to read from SPI flash (err=%d)\n",
+			      __func__, err);
 			return err;
+		}
 
 		if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 			image_get_magic(header) == FDT_MAGIC) {
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 03/62] spl: Makefile: Define SPL_ earlier

[Simon Glass]

This Makefile variable can be used in the architecture's main Makefile but
at present it is not set up until later. Set it just before this Makefile is
included.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 scripts/Makefile.spl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index c962bbca2c1..ced10e6f95a 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -35,6 +35,12 @@ else
 SPL_BIN := u-boot-spl
 endif
 
+ifdef CONFIG_SPL_BUILD
+SPL_ := SPL_
+else
+SPL_ :=
+endif
+
 include $(srctree)/config.mk
 include $(srctree)/arch/$(ARCH)/Makefile
 
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 04/62] spl: Allow CPU drivers to be used in SPL

[Simon Glass]

Add a new Kconfig option to allow CPU drivers to be used in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 10 ++++++++++
 drivers/Makefile   |  1 +
 2 files changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b1aa1483c97..4c07f49dafa 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -150,6 +150,16 @@ config SPL_SHA256_SUPPORT
 	  SHA256 variant is supported: SHA512 and others are not currently
 	  supported in U-Boot.
 
+config SPL_CPU_SUPPORT
+	bool "Support CPU drivers"
+	depends on SPL
+	help
+	  Enable this to support CPU drivers in SPL. These drivers can set
+	  up CPUs and provide information about them such as the model and
+	  name. This can be useful in SPL since setting up the CPUs earlier
+	  may improve boot performance. Enable this option to build the
+	  drivers in drivers/cpu as part of an SPL build.
+
 config SPL_CRYPTO_SUPPORT
 	bool "Support crypto drivers"
 	depends on SPL
diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa142f3a..4ced2bbb6c5 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM)	+= ram/
 
 ifdef CONFIG_SPL_BUILD
 
+obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 05/62] spl: Allow PCI drivers to be used in SPL

[Simon Glass]

Add a new Kconfig option to allow PCI drivers to be used in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 9 +++++++++
 drivers/Makefile   | 1 +
 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 4c07f49dafa..f361f2c122a 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -436,6 +436,15 @@ config SYS_OS_BASE
 
 endif # SPL_OS_BOOT
 
+config SPL_PCI_SUPPORT
+	bool "Support PCI drivers"
+	depends on SPL
+	help
+	  Enable support for PCI in SPL. For platforms that need PCI to boot,
+	  or must perform some init using PCI in SPL, this provides the
+	  necessary driver support. This enables the drivers in drivers/pci
+	  as part of an SPL build.
+
 config SPL_POST_MEM_SUPPORT
 	bool "Support POST drivers"
 	depends on SPL
diff --git a/drivers/Makefile b/drivers/Makefile
index 4ced2bbb6c5..553577acad5 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
+obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
 obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 06/62] spl: Allow RTC drivers to be used in SPL

[Simon Glass]

Add a new Kconfig option to allow RTC drivers to be used in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 10 ++++++++++
 drivers/Makefile   |  1 +
 2 files changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index f361f2c122a..503adaf6707 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -485,6 +485,16 @@ config SPL_RAM_DEVICE
 	  be already in memory when SPL takes over, e.g. loaded by the boot
 	  ROM.
 
+config SPL_RTC_SUPPORT
+	bool "Support RTC drivers"
+	depends on SPL
+	help
+	  Enable RTC (Real-time Clock) support in SPL. This includes support
+	  for reading and setting the time. Some RTC devices also have some
+	  non-volatile (battery-backed) memory which is accessible if
+	  needed. This enables the drivers in drivers/rtc as part of an SPL
+	  build.
+
 config SPL_SATA_SUPPORT
 	bool "Support loading from SATA"
 	depends on SPL
diff --git a/drivers/Makefile b/drivers/Makefile
index 553577acad5..f070ea9b2bc 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
+obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/
 obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 07/62] spl: Allow timer drivers to be used in SPL

[Simon Glass]

Add a new Kconfig option to allow timer drivers to be used in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 9 +++++++++
 drivers/Makefile   | 1 +
 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 503adaf6707..57d38924c84 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -538,6 +538,15 @@ config SPL_SPI_SUPPORT
 	  enable SPI drivers that are needed for other purposes also, such
 	  as a SPI PMIC.
 
+config SPL_TIMER_SUPPORT
+	bool "Support timer drivers"
+	depends on SPL
+	help
+	  Enable support for timer drivers in SPL. These can be used to get
+	  a timer value when in SPL, or perhaps for implementing a delay
+	  function. This enables the drivers in drivers/timer as part of an
+	  SPL build.
+
 config SPL_USB_HOST_SUPPORT
 	bool "Support USB host drivers"
 	depends on SPL
diff --git a/drivers/Makefile b/drivers/Makefile
index f070ea9b2bc..00dc041f1b2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
 obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/
+obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/
 obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/
 obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 08/62] spl: Allow PCH drivers to be used in SPL

[Simon Glass]

Add an option for building Platorm Controller Hub drivers in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 common/spl/Kconfig | 9 +++++++++
 drivers/Makefile   | 1 +
 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 57d38924c84..e07a6c8f853 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -445,6 +445,15 @@ config SPL_PCI_SUPPORT
 	  necessary driver support. This enables the drivers in drivers/pci
 	  as part of an SPL build.
 
+config SPL_PCH_SUPPORT
+	bool "Support PCH drivers"
+	depends on SPL
+	help
+	  Enable support for PCH (Platform Controller Hub) devices in SPL.
+	  These are used to set up GPIOs and the SPI peripheral early in
+	  boot. This enables the drivers in drivers/pch as part of an SPL
+	  build.
+
 config SPL_POST_MEM_SUPPORT
 	bool "Support POST drivers"
 	depends on SPL
diff --git a/drivers/Makefile b/drivers/Makefile
index 00dc041f1b2..34c55bfb2ff 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/
 obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/
+obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/
 obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/
 obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/
 obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 09/62] spl: Don't create a BSS padding when it is separate

[Simon Glass]

When BSS does not immediate follow the SPL image we don't need padding
before the device tree. Remove it in this case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 scripts/Makefile.spl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ced10e6f95a..82cfc601b29 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -191,7 +191,8 @@ quiet_cmd_copy = COPY    $@
       cmd_copy = cp $< $@
 
 ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy)
-$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \
+$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
+		$(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \
 		$(obj)/$(SPL_BIN).dtb FORCE
 	$(call if_changed,cat)
 
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 10/62] x86: Use unsigned long for address in table generation

[Simon Glass]

We should use unsigned long rather than u32 for addresses. Update this so
that the table-generation code builds correctly on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Move table-related changes from a later patch
- Rebase to mainline
- Drop the write_smbios_table_wrapper() function

 arch/x86/cpu/irq.c                |  2 +-
 arch/x86/include/asm/acpi_table.h |  2 +-
 arch/x86/include/asm/mpspec.h     |  2 +-
 arch/x86/include/asm/sfi.h        |  2 +-
 arch/x86/include/asm/tables.h     |  2 +-
 arch/x86/lib/acpi_table.c         |  4 ++--
 arch/x86/lib/mpspec.c             |  2 +-
 arch/x86/lib/sfi.c                |  6 +++---
 arch/x86/lib/tables.c             | 11 ++---------
 arch/x86/lib/zimage.c             |  2 +-
 drivers/misc/qfw.c                |  4 ++--
 include/smbios.h                  |  4 ++--
 lib/smbios.c                      | 22 +++++++++++-----------
 13 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 9364410a0f8..e3e928bb79b 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -264,7 +264,7 @@ int irq_router_probe(struct udevice *dev)
 	return irq_router_common_init(dev);
 }
 
-u32 write_pirq_routing_table(u32 addr)
+ulong write_pirq_routing_table(ulong addr)
 {
 	if (!pirq_routing_table)
 		return addr;
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index caff4d8a1e0..bbd80a1dd9a 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -316,4 +316,4 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 			       u8 cpu, u16 flags, u8 lint);
 u32 acpi_fill_madt(u32 current);
 void acpi_create_gnvs(struct acpi_global_nvs *gnvs);
-u32 write_acpi_tables(u32 start);
+ulong write_acpi_tables(ulong start);
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index ad8eba947b9..146a4b0cbb8 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -456,6 +456,6 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq);
  * @addr:	start address to write MP table
  * @return:	end address of MP table
  */
-u32 write_mp_table(u32 addr);
+ulong write_mp_table(ulong addr);
 
 #endif /* __ASM_MPSPEC_H */
diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h
index d1f0f0cb6b8..d6c44c978a9 100644
--- a/arch/x86/include/asm/sfi.h
+++ b/arch/x86/include/asm/sfi.h
@@ -132,6 +132,6 @@ typedef int (*sfi_table_handler) (struct sfi_table_header *table);
  * @base:	Address to write table to
  * @return address to use for the next table
  */
-u32 write_sfi_table(u32 base);
+ulong write_sfi_table(ulong base);
 
 #endif /*_LINUX_SFI_H */
diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
index 81f98f27745..d1b23880219 100644
--- a/arch/x86/include/asm/tables.h
+++ b/arch/x86/include/asm/tables.h
@@ -65,6 +65,6 @@ void write_tables(void);
  * @start:	start address to write PIRQ routing table
  * @return:	end address of PIRQ routing table
  */
-u32 write_pirq_routing_table(u32 start);
+ulong write_pirq_routing_table(ulong start);
 
 #endif /* _X86_TABLES_H_ */
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 7001e8ba348..355456dc19e 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -327,7 +327,7 @@ static void enter_acpi_mode(int pm1_cnt)
  * QEMU's version of write_acpi_tables is defined in
  * arch/x86/cpu/qemu/acpi_table.c
  */
-u32 write_acpi_tables(u32 start)
+ulong write_acpi_tables(ulong start)
 {
 	u32 current;
 	struct acpi_rsdp *rsdp;
@@ -345,7 +345,7 @@ u32 write_acpi_tables(u32 start)
 	/* Align ACPI tables to 16 byte */
 	current = ALIGN(current, 16);
 
-	debug("ACPI: Writing ACPI tables at %x\n", start);
+	debug("ACPI: Writing ACPI tables at %lx\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (struct acpi_rsdp *)current;
diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c
index 6ab43f1055f..516d7b3452c 100644
--- a/arch/x86/lib/mpspec.c
+++ b/arch/x86/lib/mpspec.c
@@ -365,7 +365,7 @@ static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa)
 			 bus_isa, 0, MP_APIC_ALL, 1);
 }
 
-u32 write_mp_table(u32 addr)
+ulong write_mp_table(ulong addr)
 {
 	struct mp_config_table *mc;
 	int ioapic_id, ioapic_ver;
diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c
index 3d3658088ad..507e037b998 100644
--- a/arch/x86/lib/sfi.c
+++ b/arch/x86/lib/sfi.c
@@ -38,14 +38,14 @@ static void *get_entry_start(struct table_info *tab)
 	tab->table[tab->count] = tab->entry_start;
 	tab->entry_start += sizeof(struct sfi_table_header);
 
-	return (void *)tab->entry_start;
+	return (void *)(uintptr_t)tab->entry_start;
 }
 
 static void finish_table(struct table_info *tab, const char *sig, void *entry)
 {
 	struct sfi_table_header *hdr;
 
-	hdr = (struct sfi_table_header *)(tab->base + tab->ptr);
+	hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr);
 	strcpy(hdr->sig, sig);
 	hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start);
 	hdr->rev = 1;
@@ -131,7 +131,7 @@ static int sfi_write_xsdt(struct table_info *tab)
 	return 0;
 }
 
-u32 write_sfi_table(u32 base)
+ulong write_sfi_table(ulong base)
 {
 	struct table_info table;
 
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 5966e5862a3..4f5fe742882 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -12,20 +12,13 @@
 #include <asm/acpi_table.h>
 #include <asm/coreboot_tables.h>
 
-#ifdef CONFIG_GENERATE_SMBIOS_TABLE
-static u32 write_smbios_table_wrapper(u32 addr)
-{
-	return write_smbios_table(addr);
-}
-#endif
-
 /**
  * Function prototype to write a specific configuration table
  *
  * @addr:	start address to write the table
  * @return:	end address of the table
  */
-typedef u32 (*table_write)(u32 addr);
+typedef ulong (*table_write)(ulong addr);
 
 static table_write table_write_funcs[] = {
 #ifdef CONFIG_GENERATE_PIRQ_TABLE
@@ -41,7 +34,7 @@ static table_write table_write_funcs[] = {
 	write_acpi_tables,
 #endif
 #ifdef CONFIG_GENERATE_SMBIOS_TABLE
-	write_smbios_table_wrapper,
+	write_smbios_table,
 #endif
 };
 
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 1b33c771391..b6b0f2beb3a 100644
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
@@ -165,7 +165,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
 		 * A very old kernel MUST have its real-mode code
 		 * loaded at 0x90000
 		 */
-		if ((u32)setup_base != 0x90000) {
+		if ((ulong)setup_base != 0x90000) {
 			/* Copy the real-mode kernel */
 			memmove((void *)0x90000, setup_base, setup_size);
 
diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c
index d43d1d300ac..a8af9e0c537 100644
--- a/drivers/misc/qfw.c
+++ b/drivers/misc/qfw.c
@@ -32,7 +32,7 @@ static LIST_HEAD(fw_list);
  *          be ignored.
  * @return: 0 on success, or negative value on failure
  */
-static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr)
+static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr)
 {
 	uint32_t size, align;
 	struct fw_file *file;
@@ -147,7 +147,7 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry)
 }
 
 /* This function loads and patches ACPI tables provided by QEMU */
-u32 write_acpi_tables(u32 addr)
+ulong write_acpi_tables(ulong addr)
 {
 	int i, ret = 0;
 	struct fw_file *file;
diff --git a/include/smbios.h b/include/smbios.h
index d582d4f7abb..c24d00e38dd 100644
--- a/include/smbios.h
+++ b/include/smbios.h
@@ -225,7 +225,7 @@ static inline void fill_smbios_header(void *table, int type,
  * @handle:	the structure's handle, a unique 16-bit number
  * @return:	size of the structure
  */
-typedef int (*smbios_write_type)(uintptr_t *addr, int handle);
+typedef int (*smbios_write_type)(ulong *addr, int handle);
 
 /**
  * write_smbios_table() - Write SMBIOS table
@@ -235,6 +235,6 @@ typedef int (*smbios_write_type)(uintptr_t *addr, int handle);
  * @addr:	start address to write SMBIOS table
  * @return:	end address of SMBIOS table
  */
-uintptr_t write_smbios_table(uintptr_t addr);
+ulong write_smbios_table(ulong addr);
 
 #endif /* _SMBIOS_H_ */
diff --git a/lib/smbios.c b/lib/smbios.c
index ce1974d86f7..22ca247fec8 100644
--- a/lib/smbios.c
+++ b/lib/smbios.c
@@ -73,7 +73,7 @@ static int smbios_string_table_len(char *start)
 	return len + 1;
 }
 
-static int smbios_write_type0(uintptr_t *current, int handle)
+static int smbios_write_type0(ulong *current, int handle)
 {
 	struct smbios_type0 *t = (struct smbios_type0 *)*current;
 	int len = sizeof(struct smbios_type0);
@@ -108,7 +108,7 @@ static int smbios_write_type0(uintptr_t *current, int handle)
 	return len;
 }
 
-static int smbios_write_type1(uintptr_t *current, int handle)
+static int smbios_write_type1(ulong *current, int handle)
 {
 	struct smbios_type1 *t = (struct smbios_type1 *)*current;
 	int len = sizeof(struct smbios_type1);
@@ -129,7 +129,7 @@ static int smbios_write_type1(uintptr_t *current, int handle)
 	return len;
 }
 
-static int smbios_write_type2(uintptr_t *current, int handle)
+static int smbios_write_type2(ulong *current, int handle)
 {
 	struct smbios_type2 *t = (struct smbios_type2 *)*current;
 	int len = sizeof(struct smbios_type2);
@@ -147,7 +147,7 @@ static int smbios_write_type2(uintptr_t *current, int handle)
 	return len;
 }
 
-static int smbios_write_type3(uintptr_t *current, int handle)
+static int smbios_write_type3(ulong *current, int handle)
 {
 	struct smbios_type3 *t = (struct smbios_type3 *)*current;
 	int len = sizeof(struct smbios_type3);
@@ -199,7 +199,7 @@ static void smbios_write_type4_dm(struct smbios_type4 *t)
 	t->processor_version = smbios_add_string(t->eos, name);
 }
 
-static int smbios_write_type4(uintptr_t *current, int handle)
+static int smbios_write_type4(ulong *current, int handle)
 {
 	struct smbios_type4 *t = (struct smbios_type4 *)*current;
 	int len = sizeof(struct smbios_type4);
@@ -221,7 +221,7 @@ static int smbios_write_type4(uintptr_t *current, int handle)
 	return len;
 }
 
-static int smbios_write_type32(uintptr_t *current, int handle)
+static int smbios_write_type32(ulong *current, int handle)
 {
 	struct smbios_type32 *t = (struct smbios_type32 *)*current;
 	int len = sizeof(struct smbios_type32);
@@ -234,7 +234,7 @@ static int smbios_write_type32(uintptr_t *current, int handle)
 	return len;
 }
 
-static int smbios_write_type127(uintptr_t *current, int handle)
+static int smbios_write_type127(ulong *current, int handle)
 {
 	struct smbios_type127 *t = (struct smbios_type127 *)*current;
 	int len = sizeof(struct smbios_type127);
@@ -257,10 +257,10 @@ static smbios_write_type smbios_write_funcs[] = {
 	smbios_write_type127
 };
 
-uintptr_t write_smbios_table(uintptr_t addr)
+ulong write_smbios_table(ulong addr)
 {
 	struct smbios_entry *se;
-	u32 tables;
+	ulong tables;
 	int len = 0;
 	int max_struct_size = 0;
 	int handle = 0;
@@ -271,7 +271,7 @@ uintptr_t write_smbios_table(uintptr_t addr)
 	/* 16 byte align the table address */
 	addr = ALIGN(addr, 16);
 
-	se = (struct smbios_entry *)addr;
+	se = (struct smbios_entry *)(uintptr_t)addr;
 	memset(se, 0, sizeof(struct smbios_entry));
 
 	addr += sizeof(struct smbios_entry);
@@ -280,7 +280,7 @@ uintptr_t write_smbios_table(uintptr_t addr)
 
 	/* populate minimum required tables */
 	for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) {
-		int tmp = smbios_write_funcs[i](&addr, handle++);
+		int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++);
 		max_struct_size = max(max_struct_size, tmp);
 		len += tmp;
 	}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 11/62] x86: Update mpspec to build on 64-bit machines

[Simon Glass]

At present this uses u32 to store an address. We should use unsigned long
and avoid special types in function return values and parameters unless
necessary. This makes the code more portable.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Drop WIP tag as this patch is actually needed

Changes in v2: None

 arch/x86/include/asm/mpspec.h |  8 ++++----
 arch/x86/lib/mpspec.c         | 12 ++++++------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index 146a4b0cbb8..30dbdca90db 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -224,9 +224,9 @@ struct mp_ext_compat_address_space {
  * @mc:		configuration table header address
  * @return:	configuration table end address
  */
-static inline u32 mp_next_mpc_entry(struct mp_config_table *mc)
+static inline ulong mp_next_mpc_entry(struct mp_config_table *mc)
 {
-	return (u32)mc + mc->mpc_length;
+	return (ulong)mc + mc->mpc_length;
 }
 
 /**
@@ -254,9 +254,9 @@ static inline void mp_add_mpc_entry(struct mp_config_table *mc, uint length)
  * @mc:		configuration table header address
  * @return:	configuration table end address
  */
-static inline u32 mp_next_mpe_entry(struct mp_config_table *mc)
+static inline ulong mp_next_mpe_entry(struct mp_config_table *mc)
 {
-	return (u32)mc + mc->mpc_length + mc->mpe_length;
+	return (ulong)mc + mc->mpc_length + mc->mpe_length;
 }
 
 /**
diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c
index 516d7b3452c..17e977ce5e3 100644
--- a/arch/x86/lib/mpspec.c
+++ b/arch/x86/lib/mpspec.c
@@ -25,10 +25,10 @@ static bool isa_irq_occupied[16];
 
 struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
 {
-	u32 mc;
+	ulong mc;
 
 	memcpy(mf->mpf_signature, MPF_SIGNATURE, 4);
-	mf->mpf_physptr = (u32)mf + sizeof(struct mp_floating_table);
+	mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table);
 	mf->mpf_length = 1;
 	mf->mpf_spec = MPSPEC_V14;
 	mf->mpf_checksum = 0;
@@ -41,7 +41,7 @@ struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf)
 	mf->mpf_feature5 = 0;
 	mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);
 
-	mc = (u32)mf + sizeof(struct mp_floating_table);
+	mc = (ulong)mf + sizeof(struct mp_floating_table);
 	return (struct mp_config_table *)mc;
 }
 
@@ -219,14 +219,14 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid,
 
 u32 mptable_finalize(struct mp_config_table *mc)
 {
-	u32 end;
+	ulong end;
 
 	mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc),
 						  mc->mpe_length);
 	mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length);
 	end = mp_next_mpe_entry(mc);
 
-	debug("Write the MP table at: %x - %x\n", (u32)mc, end);
+	debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);
 
 	return end;
 }
@@ -371,7 +371,7 @@ ulong write_mp_table(ulong addr)
 	int ioapic_id, ioapic_ver;
 	int bus_isa = 0xff;
 	int ret;
-	u32 end;
+	ulong end;
 
 	/* 16 byte align the table address */
 	addr = ALIGN(addr, 16);
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 12/62] x86: ivybridge: Declare global data where it is used

[Simon Glass]

Some files are missing this declaration. Add it to avoid build errors when
we actually need the declaration.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Drop change to gma.c

 arch/x86/cpu/ivybridge/bd82x6x.c     | 2 ++
 arch/x86/cpu/ivybridge/lpc.c         | 2 ++
 arch/x86/cpu/ivybridge/model_206ax.c | 2 ++
 arch/x86/cpu/ivybridge/northbridge.c | 2 ++
 drivers/video/ivybridge_igd.c        | 2 ++
 5 files changed, 10 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index e63ea6b22e3..e3eff69cf67 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -19,6 +19,8 @@
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define GPIO_BASE	0x48
 #define BIOS_CTRL	0xdc
 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 4af89b3a7cb..aef1206be41 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -20,6 +20,8 @@
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define NMI_OFF				0
 
 #define ENABLE_ACPI_MODE_IN_COREBOOT	0
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 09b534255ca..d5f32196ae3 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -22,6 +22,8 @@
 #include <asm/turbo.h>
 #include <asm/arch/model_206ax.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void enable_vmx(void)
 {
 	struct cpuid_result regs;
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index 491f2894f9e..94f31c40beb 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -19,6 +19,8 @@
 #include <asm/arch/model_206ax.h>
 #include <asm/arch/sandybridge.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int bridge_silicon_revision(struct udevice *dev)
 {
 	struct cpuid_result result;
diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c
index 94db3dda442..95d62a5392d 100644
--- a/drivers/video/ivybridge_igd.c
+++ b/drivers/video/ivybridge_igd.c
@@ -18,6 +18,8 @@
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 struct gt_powermeter {
 	u16 reg;
 	u32 value;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 13/62] x86: ivybridge: Add more debugging for failures

[Simon Glass]

Add various debug() messages in places where errors occur. This aids with
debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Output error code values in debug() statements

 arch/x86/cpu/ivybridge/cpu.c   |  4 +++-
 arch/x86/cpu/ivybridge/sdram.c | 37 ++++++++++++++++++++++++++++---------
 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 85e361a58f0..c4aca08f0df 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -169,8 +169,10 @@ int print_cpuinfo(void)
 
 	/* Enable SPD ROMs and DDR-III DRAM */
 	ret = uclass_first_device_err(UCLASS_I2C, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	/* Prepare USB controller early in S3 resume */
 	if (boot_mode == PEI_BOOT_RESUME) {
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e0b06b5ada5..201368c9c7c 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -207,8 +207,10 @@ static int copy_spd(struct udevice *dev, struct pei_data *peid)
 	int ret;
 
 	ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
 
@@ -460,18 +462,27 @@ int dram_init(void)
 
 	/* We need the pinctrl set up early */
 	ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get northbridge (ret=%d)\n", __func__,
+		      ret);
 		return ret;
+	}
 	ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get ME (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	ret = copy_spd(dev, pei_data);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not get SPD (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	pei_data->boot_mode = gd->arch.pei_boot_mode;
 	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
 	debug("mrc_input %p\n", pei_data->mrc_input);
@@ -498,19 +509,27 @@ int dram_init(void)
 
 	/* Wait for ME to be ready */
 	ret = intel_early_me_init(me_dev);
-	if (ret)
+	if (ret) {
+		debug("%s: Could not init ME (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	ret = intel_early_me_uma_size(me_dev);
-	if (ret < 0)
+	if (ret < 0) {
+		debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	ret = mrc_common_init(dev, pei_data, false);
-	if (ret)
+	if (ret) {
+		debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 
 	ret = sdram_find(dev);
-	if (ret)
+	if (ret) {
+		debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret);
 		return ret;
+	}
 	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
 
 	debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 14/62] x86: ivybridge: Fix types for 64-bit compilation

[Simon Glass]

Fix a few types that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Fix cast in bd82x6x_video_probe() also

 arch/x86/cpu/ivybridge/sata.c | 4 ++--
 drivers/video/ivybridge_igd.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index 87ff872e20a..c7ffbc11fd9 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -53,7 +53,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 
 	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
 	if (!mode || !strcmp(mode, "ahci")) {
-		u32 abar;
+		ulong abar;
 
 		debug("SATA: Controller in AHCI mode\n");
 
@@ -72,7 +72,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
 
 		/* Initialize AHCI memory-mapped space */
 		abar = dm_pci_read_bar32(dev, 5);
-		debug("ABAR: %08X\n", abar);
+		debug("ABAR: %08lx\n", abar);
 		/* CAP (HBA Capabilities) : enable power management */
 		reg32 = readl(abar + 0x00);
 		reg32 |= 0x0c006000;  /* set PSC+SSC+SALP+SSS */
diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c
index 95d62a5392d..f16d725f3c7 100644
--- a/drivers/video/ivybridge_igd.c
+++ b/drivers/video/ivybridge_igd.c
@@ -802,7 +802,7 @@ static int gma_func0_init(struct udevice *dev)
 	mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
 	mtrr_commit(true);
 
-	gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
+	gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
 	debug("GT bar %p\n", gtt_bar);
 	ret = gma_pm_init_pre_vbios(gtt_bar, rev);
 	if (ret)
@@ -824,7 +824,7 @@ static int bd82x6x_video_probe(struct udevice *dev)
 		return ret;
 
 	/* Post VBIOS init */
-	gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
+	gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0);
 	ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
 	if (ret)
 		return ret;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 15/62] x86: dts: Mark serial as needed before relocation

[Simon Glass]

We almost always need the serial port before relocation, so mark it as such.
This will ensure that it appears in the device tree for SPL, if used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/serial.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi
index 54c3faf4514..22f7b54fed3 100644
--- a/arch/x86/dts/serial.dtsi
+++ b/arch/x86/dts/serial.dtsi
@@ -1,5 +1,6 @@
 / {
 	serial: serial {
+		u-boot,dm-pre-reloc;
 		compatible = "ns16550";
 		reg = <0x3f8 8>;
 		reg-shift = <0>;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 16/62] x86: fsp: Fix cast for 64-bit compilation

[Simon Glass]

Fix a cast in get_next_hob() that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Fix cast in get_guid_hob_data() also

 arch/x86/include/asm/fsp/fsp_hob.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h
index 3fb3546e27f..7c22bcd5cd8 100644
--- a/arch/x86/include/asm/fsp/fsp_hob.h
+++ b/arch/x86/include/asm/fsp/fsp_hob.h
@@ -139,7 +139,7 @@ struct hob_guid {
  */
 static inline const struct hob_header *get_next_hob(const struct hob_header *hdr)
 {
-	return (const struct hob_header *)((u32)hdr + hdr->len);
+	return (const struct hob_header *)((uintptr_t)hdr + hdr->len);
 }
 
 /**
@@ -172,7 +172,7 @@ static inline bool end_of_hob(const struct hob_header *hdr)
  */
 static inline void *get_guid_hob_data(const struct hob_header *hdr)
 {
-	return (void *)((u32)hdr + sizeof(struct hob_guid));
+	return (void *)((uintptr_t)hdr + sizeof(struct hob_guid));
 }
 
 /**
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 17/62] x86: lib: Fix types and casts for 64-bit compilation

[Simon Glass]

Fix various compiler warnings in the x86 library code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Move table-related changes to an earlier patch

 arch/x86/lib/bios.c         | 4 ++--
 arch/x86/lib/pinctrl_ich6.c | 2 +-
 arch/x86/lib/pirq_routing.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index 9324bdb83e8..66d7629a6dd 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -157,7 +157,7 @@ static void setup_realmode_idt(void)
 	 for (i = 0; i < 256; i++) {
 		idts[i].cs = 0;
 		idts[i].offset = 0x1000 + (i * __idt_handler_size);
-		write_idt_stub((void *)((u32)idts[i].offset), i);
+		write_idt_stub((void *)((ulong)idts[i].offset), i);
 	}
 
 	/*
@@ -227,7 +227,7 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info)
 	mode_info->video_mode = (1 << 14) | vesa_mode;
 	vbe_get_mode_info(mode_info);
 
-	framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr;
+	framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr;
 	debug("VBE: resolution:  %dx%d@%d\n",
 	      le16_to_cpu(mode_info->vesa.x_resolution),
 	      le16_to_cpu(mode_info->vesa.y_resolution),
diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c
index 3f94cdf2dac..fb2d2940c95 100644
--- a/arch/x86/lib/pinctrl_ich6.c
+++ b/arch/x86/lib/pinctrl_ich6.c
@@ -104,7 +104,7 @@ static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
 
 	/* if iobase is present, let's configure the pad */
 	if (iobase != -1) {
-		int iobase_addr;
+		ulong iobase_addr;
 
 		/*
 		 * The offset for the same pin for the IOBASE and GPIOBASE are
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index a93d355d8a2..c98526d6aa8 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -114,14 +114,14 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
 	addr = ALIGN(addr, 16);
 
 	debug("Copying Interrupt Routing Table to 0x%x\n", addr);
-	memcpy((void *)addr, rt, rt->size);
+	memcpy((void *)(uintptr_t)addr, rt, rt->size);
 
 	/*
 	 * We do the sanity check here against the copied table after memcpy,
 	 * as something might go wrong after the memcpy, which is normally
 	 * due to the F segment decode is not turned on to systeam RAM.
 	 */
-	rom_rt = (struct irq_routing_table *)addr;
+	rom_rt = (struct irq_routing_table *)(uintptr_t)addr;
 	if (rom_rt->signature != PIRQ_SIGNATURE ||
 	    rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) {
 		printf("Interrupt Routing Table not valid\n");
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 18/62] x86: Add Kconfig options to build 64-bit U-Boot

[Simon Glass]

Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be
built as a 64-bit application, with SPL doing the 16/32-bit init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Use tab instead of space in Kconfig help line

Changes in v2: None

 arch/x86/Kconfig | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0884af22a79..5cd58d450b5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -5,6 +5,52 @@ config SYS_ARCH
 	default "x86"
 
 choice
+	prompt "Run U-Boot in 32/64-bit mode"
+	default X86_RUN_32BIT
+	help
+	  U-Boot can be built as a 32-bit binary which runs in 32-bit mode
+	  even on 64-bit machines. In this case SPL is not used, and U-Boot
+	  runs directly from the reset vector (via 16-bit start-up).
+
+	  Alternatively it can be run as a 64-bit binary, thus requiring a
+	  64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
+	  start-up) then jumps to U-Boot in 64-bit mode.
+
+	  For now, 32-bit mode is recommended, as 64-bit is still
+	  experimental and is missing a lot of features.
+
+config X86_RUN_32BIT
+	bool "32-bit"
+	help
+	  Build U-Boot as a 32-bit binary with no SPL. This is the currently
+	  supported normal setup. U-Boot will stay in 32-bit mode even on
+	  64-bit machines. When booting a 64-bit kernel, U-Boot will switch
+	  to 64-bit just before starting the kernel. Only the bottom 4GB of
+	  memory can be accessed through normal means, although
+	  arch_phys_memset() can be used for basic access to other memory.
+
+config X86_RUN_64BIT
+	bool "64-bit"
+	select X86_64
+	select SUPPORT_SPL
+	select SPL
+	select SPL_SEPARATE_BSS
+	help
+	  Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
+	  experimental and many features are missing. U-Boot SPL starts up,
+	  runs through the 16-bit and 32-bit init, then switches to 64-bit
+	  mode and jumps to U-Boot proper.
+
+endchoice
+
+config X86_64
+	bool
+
+config SPL_X86_64
+	bool
+	depends on SPL
+
+choice
 	prompt "Mainboard vendor"
 	default VENDOR_EMULATION
 
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 19/62] x86: Kconfig: Add location options for 16/32-bit init

[Simon Glass]

At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If
this is enabled, then U-Boot is the 'first' boot loader and handles execution
from the reset vector through to U-Boot's command prompt. If it is not
enabled then U-Boot starts at the 32-bit entry and skips most of its init,
assuming that the previous boot loader has done this already.

With the move to suport 64-bit operation, we have more cases to consider.
The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper.

Add Kconfig options which control the location of the 16-bit and the 32-bit
init. These are not intended to be user-setting except for experimentation.
Their values should be determined by whether 64-bit U-Boot is used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Fix s/32-bit init/16-bit init/ and expand the comment

Changes in v2: None

 arch/x86/Kconfig | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5cd58d450b5..675b56f617e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -135,6 +135,46 @@ config X86_RESET_VECTOR
 	bool
 	default n
 
+# The following options control where the 16-bit and 32-bit init lies
+# If SPL is enabled then it normally holds this init code, and U-Boot proper
+# is normally a 64-bit build.
+#
+# The 16-bit init refers to the reset vector and the small amount of code to
+# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
+# or missing altogether if U-Boot is started from EFI or coreboot.
+#
+# The 32-bit init refers to processor init, running binary blobs including
+# FSP, setting up interrupts and anything else that needs to be done in
+# 32-bit code. It is normally in the same place as 16-bit init if that is
+# enabled (i.e. they are both in SPL, or both in U-Boot proper).
+config X86_16BIT_INIT
+	bool
+	depends on X86_RESET_VECTOR
+	default y if X86_RESET_VECTOR && !SPL
+	help
+	  This is enabled when 16-bit init is in U-Boot proper
+
+config SPL_X86_16BIT_INIT
+	bool
+	depends on X86_RESET_VECTOR
+	default y if X86_RESET_VECTOR && SPL
+	help
+	  This is enabled when 16-bit init is in SPL
+
+config X86_32BIT_INIT
+	bool
+	depends on X86_RESET_VECTOR
+	default y if X86_RESET_VECTOR && !SPL
+	help
+	  This is enabled when 32-bit init is in U-Boot proper
+
+config SPL_X86_32BIT_INIT
+	bool
+	depends on X86_RESET_VECTOR
+	default y if X86_RESET_VECTOR && SPL
+	help
+	  This is enabled when 32-bit init is in SPL
+
 config RESET_SEG_START
 	hex
 	depends on X86_RESET_VECTOR
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 20/62] x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR

[Simon Glass]

Use this new option to control the location of 16-bit init. This will allow
us to place this in SPL if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 Makefile                | 7 ++++---
 arch/x86/Makefile       | 6 ++----
 arch/x86/cpu/Makefile   | 2 +-
 arch/x86/cpu/u-boot.lds | 2 +-
 4 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile
index 262df7cd63b..1361e5d04f5 100644
--- a/Makefile
+++ b/Makefile
@@ -883,7 +883,7 @@ u-boot.hex u-boot.srec: u-boot FORCE
 	$(call if_changed,objcopy)
 
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
-		$(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
+		$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
 
 binary_size_check: u-boot-nodtb.bin FORCE
 	@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
@@ -1076,8 +1076,9 @@ quiet_cmd_ldr = LD      $@
 cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \
 	       $(filter-out FORCE,$^) -o $@
 
-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \
-		$(if $(CONFIG_HAVE_REFCODE),refcode.bin)
+u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \
+		$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
+		$(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE
 	$(call if_changed,binman)
 
 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index d104a497301..dd0e22f970d 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -5,10 +5,8 @@
 ifeq ($(CONFIG_EFI_APP),)
 head-y := arch/x86/cpu/start.o
 endif
-ifeq ($(CONFIG_SPL_BUILD),y)
-head-y += arch/x86/cpu/start16.o
-head-y += arch/x86/cpu/resetvec.o
-endif
+head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
+head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
 
 libs-y += arch/x86/cpu/
 libs-y += arch/x86/lib/
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index f5b8c9e3632..fd81310df69 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -9,7 +9,7 @@
 #
 
 extra-y	= start.o
-obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
+extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
 obj-y	+= interrupts.o cpu.o cpu_x86.o call64.o setjmp.o
 
 AFLAGS_REMOVE_call32.o := -mregparm=3 \
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index cca536b2723..186718d8f9d 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -103,7 +103,7 @@ SECTIONS
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
 
-#ifdef CONFIG_X86_RESET_VECTOR
+#ifdef CONFIG_X86_16BIT_INIT
 	/*
 	 * The following expressions place the 16-bit Real-Mode code and
 	 * Reset Vector at the end of the Flash ROM
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 21/62] x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR

[Simon Glass]

Use this new option to control the location of 32-bit init. This will allow
us to place this in SPL if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/intel_common/Makefile | 10 ++++++----
 arch/x86/lib/init_helpers.c        |  2 +-
 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 804c539ca4b..1145e7896cc 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -4,13 +4,15 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_HAVE_MRC) += car.o
+ifdef CONFIG_HAVE_MRC
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o
+endif
 obj-y += cpu.o
 obj-y += lpc.o
-obj-$(CONFIG_HAVE_MRC) += me_status.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode.o
 endif
 obj-y += pch.o
-obj-$(CONFIG_HAVE_MRC) += report_platform.o
-obj-$(CONFIG_HAVE_MRC) += mrc.o
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 2a186fc22f6..420393b843e 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -19,7 +19,7 @@ __weak ulong board_get_usable_ram_top(ulong total_size)
 
 int init_cache_f_r(void)
 {
-#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP)
+#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP)
 	int ret;
 
 	ret = mtrr_commit(false);
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 22/62] x86: ivybridge: Allow 32-bit init to move to SPL

[Simon Glass]

Update the Makefile so that some 32-bit init can be built into SPL rather
than U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/ivybridge/Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 498e71a1b90..d13d0d3f694 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,12 +7,12 @@
 ifdef CONFIG_HAVE_FSP
 obj-y += fsp_configs.o ivybridge.o
 else
-obj-y += cpu.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o
 obj-y += early_me.o
 obj-y += lpc.o
 obj-y += model_206ax.o
 obj-y += northbridge.o
 obj-y += sata.o
-obj-y += sdram.o
+obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o
 endif
 obj-y += bd82x6x.o
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 23/62] x86: Add 64-bit start-up code

[Simon Glass]

Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are
running from RAM and SPL has done the low-level init.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Drop unused headers
- Drop unused board_debug_uart_init function
- Use call instead of callq

Changes in v2: None

 arch/x86/Makefile      |  5 +++++
 arch/x86/cpu/Makefile  |  4 ++++
 arch/x86/cpu/start64.S | 28 ++++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)
 create mode 100644 arch/x86/cpu/start64.S

diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index dd0e22f970d..4be1c353cc9 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -3,8 +3,13 @@
 #
 
 ifeq ($(CONFIG_EFI_APP),)
+ifdef CONFIG_$(SPL_)X86_64
+head-y := arch/x86/cpu/start64.o
+else
 head-y := arch/x86/cpu/start.o
 endif
+endif
+
 head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
 head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
 
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index fd81310df69..97b26b0fe76 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -8,7 +8,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifeq ($(CONFIG_$(SPL_)X86_64),y)
+extra-y	= start64.o
+else
 extra-y	= start.o
+endif
 extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
 obj-y	+= interrupts.o cpu.o cpu_x86.o call64.o setjmp.o
 
diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S
new file mode 100644
index 00000000000..651f16ac89c
--- /dev/null
+++ b/arch/x86/cpu/start64.S
@@ -0,0 +1,28 @@
+/*
+ * 64-bit x86 Startup Code
+ *
+ * (C) Copyright 216 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.section .text
+.code64
+.globl _start
+.type _start, @function
+_start:
+	/* Set up memory using the existing stack */
+	mov	%rsp, %rdi
+	call	board_init_f_alloc_reserve
+	mov	%rax, %rsp
+
+	call	board_init_f_init_reserve
+
+	call	board_init_f
+	call	board_init_f_r
+
+	/* Should not return here */
+	jmp	.
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 24/62] x86: board_f: Update init sequence for 64-bit startup

[Simon Glass]

Adjust the code so that 64-bit startup works. Since we don't need to do CAR
changes in U-Boot proper anymore (they are done in SPL) we can simplify the
flow and return normally from board_init_f().

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Move 'const' change into its own patch

Changes in v2: None

 common/board_f.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c
index cc8aee74f03..3555ffafee4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -768,7 +768,8 @@ static int setup_reloc(void)
 }
 
 /* ARM calls relocate_code from its crt0.S */
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
+		!CONFIG_IS_ENABLED(X86_64)
 
 static int jump_to_copy(void)
 {
@@ -1048,7 +1049,8 @@ static init_fnc_t init_sequence_f[] = {
 #if defined(CONFIG_XTENSA)
 	clear_bss,
 #endif
-#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
+#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
+		!CONFIG_IS_ENABLED(X86_64)
 	jump_to_copy,
 #endif
 	NULL,
@@ -1082,7 +1084,7 @@ void board_init_f(ulong boot_flags)
 		hang();
 
 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
-		!defined(CONFIG_EFI_APP)
+		!defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64)
 	/* NOTREACHED - jump_to_copy() does not return */
 	hang();
 #endif
@@ -1107,7 +1109,9 @@ void board_init_f(ulong boot_flags)
  * all archs will move to this when generic relocation is implemented.
  */
 static init_fnc_t init_sequence_f_r[] = {
+#if !CONFIG_IS_ENABLED(X86_64)
 	init_cache_f_r,
+#endif
 
 	NULL,
 };
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 25/62] board_f/r: Use static const for the init sequences

[Simon Glass]

These tables should be declared static const. Unfortunately the table in
board_r is updated on machines with manual relocation.

Update them.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Add new patch to use static const for the board_f/r init sequences

Changes in v2: None

 common/board_f.c | 4 ++--
 common/board_r.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/common/board_f.c b/common/board_f.c
index 3555ffafee4..0b135e4fe1b 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -846,7 +846,7 @@ __weak int arch_cpu_init_dm(void)
 	return 0;
 }
 
-static init_fnc_t init_sequence_f[] = {
+static const init_fnc_t init_sequence_f[] = {
 #ifdef CONFIG_SANDBOX
 	setup_ram_buf,
 #endif
@@ -1108,7 +1108,7 @@ void board_init_f(ulong boot_flags)
  * NOTE: At present only x86 uses this route, but it is intended that
  * all archs will move to this when generic relocation is implemented.
  */
-static init_fnc_t init_sequence_f_r[] = {
+static const init_fnc_t init_sequence_f_r[] = {
 #if !CONFIG_IS_ENABLED(X86_64)
 	init_cache_f_r,
 #endif
diff --git a/common/board_r.c b/common/board_r.c
index a3733526c69..1bdd5a35366 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -757,7 +757,7 @@ static int run_main_loop(void)
  *
  * TODO: perhaps reset the watchdog in the initcall function after each call?
  */
-init_fnc_t init_sequence_r[] = {
+static init_fnc_t init_sequence_r[] = {
 	initr_trace,
 	initr_reloc,
 	/* TODO: could x86/PPC have this also perhaps? */
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 26/62] x86: board_r: Set the global data pointer after relocation

[Simon Glass]

Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the
time we get to board_init_r(). The old 'gd' variable is passed in as
parameter to board_init_r(), presumably for this situation.

Assign it on 64-bit x86 so that gd points to the correct data.

Options to improve this:
- Make gd a fixed register and remove the board_init_r() parameter
- Make all archs use this board_init_r() parameter

The second has a TODO in the code. The first has a TODO in a future commit
('x86: Support global_data on x86_64')

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Add a TODO to board_init_r() regarding the use of the new_gd parameter

Changes in v2: None

 common/board_r.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/common/board_r.c b/common/board_r.c
index 1bdd5a35366..ddfb1e1fcad 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -974,6 +974,16 @@ static init_fnc_t init_sequence_r[] = {
 
 void board_init_r(gd_t *new_gd, ulong dest_addr)
 {
+	/*
+	 * Set up the new global data pointer. So far only x86 does this
+	 * here.
+	 * TODO(sjg at chromium.org): Consider doing this for all archs, or
+	 * dropping the new_gd parameter.
+	 */
+#if CONFIG_IS_ENABLED(X86_64)
+	arch_setup_gd(new_gd);
+#endif
+
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
 	int i;
 #endif
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 27/62] x86: Do relocation before clearing BSS

[Simon Glass]

The BSS region may overlap with relocations. If we clear BSS we will
overwrite the start of the relocation area. This doesn't matter when running
from SPI flash, since it is read-only. But when relocating 64-bit U-Boot
from one place in RAM to another, relocation will fail because some of its
relocations have been zeroed.

To fix this, put the ELF fixup call before the BSS clearing call.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 common/board_f.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/board_f.c b/common/board_f.c
index 0b135e4fe1b..d70aa88a4af 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -1043,8 +1043,8 @@ static const init_fnc_t init_sequence_f[] = {
 	setup_reloc,
 #if defined(CONFIG_X86) || defined(CONFIG_ARC)
 	copy_uboot_to_ram,
-	clear_bss,
 	do_elf_reloc_fixups,
+	clear_bss,
 #endif
 #if defined(CONFIG_XTENSA)
 	clear_bss,
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 28/62] x86: Refactor relocation to prepare for 64-bit

[Simon Glass]

Move the core relocation code into a separate function so that the checking
code can be used for 64-bit relocation also.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Mention the commit ID containing information about the need for reloc checks
- Drop the pre-panic printf() of the relocation addresses

Changes in v2: None

 arch/x86/lib/relocate.c | 55 ++++++++++++++++++++++++++++---------------------
 1 file changed, 31 insertions(+), 24 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 0d683bfc122..861e6675b3b 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -47,38 +47,18 @@ int clear_bss(void)
 	return 0;
 }
 
-/*
- * This function has more error checking than you might expect. Please see
- * the commit message for more informaiton.
- */
-int do_elf_reloc_fixups(void)
+static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,
+				  Elf32_Rel *re_src, Elf32_Rel *re_end)
 {
-	Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
-	Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
-
 	Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
 	Elf32_Addr *offset_ptr_ram;
-	unsigned int text_base = 0;
-
-	/* The size of the region of u-boot that runs out of RAM. */
-	uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
-
-	if (gd->flags & GD_FLG_SKIP_RELOC)
-		return 0;
-	if (re_src == re_end)
-		panic("No relocation data");
 
-#ifdef CONFIG_SYS_TEXT_BASE
-	text_base = CONFIG_SYS_TEXT_BASE;
-#else
-	panic("No CONFIG_SYS_TEXT_BASE");
-#endif
 	do {
 		/* Get the location from the relocation entry */
-		offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+		offset_ptr_rom = (Elf32_Addr *)(uintptr_t)re_src->r_offset;
 
 		/* Check that the location of the relocation is in .text */
-		if (offset_ptr_rom >= (Elf32_Addr *)text_base &&
+		if (offset_ptr_rom >= (Elf32_Addr *)(uintptr_t)text_base &&
 		    offset_ptr_rom > last_offset) {
 
 			/* Switch to the in-RAM version */
@@ -103,6 +83,33 @@ int do_elf_reloc_fixups(void)
 		last_offset = offset_ptr_rom;
 
 	} while (++re_src < re_end);
+}
+
+/*
+ * This function has more error checking than you might expect. Please see
+ * this commit message for more information:
+ *    62f7970a x86: Add error checking to x86 relocation code
+ */
+int do_elf_reloc_fixups(void)
+{
+	void *re_src = (void *)(&__rel_dyn_start);
+	void *re_end = (void *)(&__rel_dyn_end);
+	uint text_base;
+
+	/* The size of the region of u-boot that runs out of RAM. */
+	uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start;
+
+	if (gd->flags & GD_FLG_SKIP_RELOC)
+		return 0;
+	if (re_src == re_end)
+		panic("No relocation data");
+
+#ifdef CONFIG_SYS_TEXT_BASE
+	text_base = CONFIG_SYS_TEXT_BASE;
+#else
+	panic("No CONFIG_SYS_TEXT_BASE");
+#endif
+	do_elf_reloc_fixups32(text_base, size, re_src, re_end);
 
 	return 0;
 }
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 29/62] x86: Add support for 64-bit relocation

[Simon Glass]

Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed
address and runs it. U-Boot then relocates itself to the top of RAM using
this relocation function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/relocate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index 861e6675b3b..d207fddb756 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -47,6 +47,46 @@ int clear_bss(void)
 	return 0;
 }
 
+#if CONFIG_IS_ENABLED(X86_64)
+static void do_elf_reloc_fixups64(unsigned int text_base, uintptr_t size,
+				  Elf64_Rela *re_src, Elf64_Rela *re_end)
+{
+	Elf64_Addr *offset_ptr_rom, *last_offset = NULL;
+	Elf64_Addr *offset_ptr_ram;
+
+	do {
+		/* Get the location from the relocation entry */
+		offset_ptr_rom = (Elf64_Addr *)(uintptr_t)re_src->r_offset;
+
+		/* Check that the location of the relocation is in .text */
+		if (offset_ptr_rom >= (Elf64_Addr *)(uintptr_t)text_base &&
+		    offset_ptr_rom > last_offset) {
+			/* Switch to the in-RAM version */
+			offset_ptr_ram = (Elf64_Addr *)((ulong)offset_ptr_rom +
+							gd->reloc_off);
+
+			/* Check that the target points into .text */
+			if (*offset_ptr_ram >= text_base &&
+			    *offset_ptr_ram <= text_base + size) {
+				*offset_ptr_ram = gd->reloc_off +
+							re_src->r_addend;
+			} else {
+				debug("   %p: %lx: rom reloc %lx, ram %p, value %lx, limit %"
+				      PRIXPTR "\n",
+				      re_src, (ulong)re_src->r_info,
+				      (ulong)re_src->r_offset, offset_ptr_ram,
+				      (ulong)*offset_ptr_ram, text_base + size);
+			}
+		} else {
+			debug("   %p: %lx: rom reloc %lx, last %p\n", re_src,
+			      (ulong)re_src->r_info, (ulong)re_src->r_offset,
+			      last_offset);
+		}
+		last_offset = offset_ptr_rom;
+
+	} while (++re_src < re_end);
+}
+#else
 static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,
 				  Elf32_Rel *re_src, Elf32_Rel *re_end)
 {
@@ -84,6 +124,7 @@ static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,
 
 	} while (++re_src < re_end);
 }
+#endif
 
 /*
  * This function has more error checking than you might expect. Please see
@@ -109,7 +150,11 @@ int do_elf_reloc_fixups(void)
 #else
 	panic("No CONFIG_SYS_TEXT_BASE");
 #endif
+#if CONFIG_IS_ENABLED(X86_64)
+	do_elf_reloc_fixups64(text_base, size, re_src, re_end);
+#else
 	do_elf_reloc_fixups32(text_base, size, re_src, re_end);
+#endif
 
 	return 0;
 }
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 30/62] x86: Tidy up use of size_t in relocation

[Simon Glass]

Addresses should not be cast to size_t. Use uintptr_t instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/relocate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c
index d207fddb756..1da5210d27b 100644
--- a/arch/x86/lib/relocate.c
+++ b/arch/x86/lib/relocate.c
@@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int copy_uboot_to_ram(void)
 {
-	size_t len = (size_t)&__data_end - (size_t)&__text_start;
+	size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;
 
 	if (gd->flags & GD_FLG_SKIP_RELOC)
 		return 0;
@@ -38,7 +38,7 @@ int copy_uboot_to_ram(void)
 int clear_bss(void)
 {
 	ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
-	size_t len = (size_t)&__bss_end - (size_t)&__bss_start;
+	size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;
 
 	if (gd->flags & GD_FLG_SKIP_RELOC)
 		return 0;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 31/62] x86: Add an SPL implementation

[Simon Glass]

SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping
to it. Call the existing init routines in order to accomplish this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Update copyright year
- Drop duplicate line in header commment
- Add a comment about stack position to x86_spl_init()
- Add a parameter to the use of the SPL_LOAD_IMAGE_METHOD() macro
- Fix printf() warning in spl_board_load_image()

Changes in v2: None

 arch/x86/include/asm/spl.h |   8 +++
 arch/x86/lib/Makefile      |   1 +
 arch/x86/lib/spl.c         | 153 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 162 insertions(+)
 create mode 100644 arch/x86/include/asm/spl.h
 create mode 100644 arch/x86/lib/spl.c

diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h
new file mode 100644
index 00000000000..d48a3fcb741
--- /dev/null
+++ b/arch/x86/include/asm/spl.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright (C) 2017 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file is required for SPL to build, but is empty.
+ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 723288f7b2b..67117c36e83 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -37,6 +37,7 @@ endif
 obj-y	+= tables.o
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
 obj-$(CONFIG_HAVE_FSP) += fsp/
+obj-$(CONFIG_SPL_BUILD) += spl.o
 
 extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a
 
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
new file mode 100644
index 00000000000..7403d152125
--- /dev/null
+++ b/arch/x86/lib/spl.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+#include <asm/cpu.h>
+#include <asm/init_helpers.h>
+#include <asm/mtrr.h>
+#include <asm/processor.h>
+#include <asm-generic/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int x86_spl_init(void)
+{
+	/*
+	 * TODO(sjg at chromium.org): We use this area of RAM for the stack
+	 * and global_data in SPL. Once U-Boot starts up and releocates it
+	 * is not needed. We could make this a CONFIG option or perhaps
+	 * place it immediately below CONFIG_SYS_TEXT_BASE.
+	 */
+	char *ptr = (char *)0x110000;
+	int ret;
+
+	debug("%s starting\n", __func__);
+	ret = spl_init();
+	if (ret) {
+		debug("%s: spl_init() failed\n", __func__);
+		return ret;
+	}
+	preloader_console_init();
+
+	ret = arch_cpu_init();
+	if (ret) {
+		debug("%s: arch_cpu_init() failed\n", __func__);
+		return ret;
+	}
+	ret = arch_cpu_init_dm();
+	if (ret) {
+		debug("%s: arch_cpu_init_dm() failed\n", __func__);
+		return ret;
+	}
+	ret = print_cpuinfo();
+	if (ret) {
+		debug("%s: print_cpuinfo() failed\n", __func__);
+		return ret;
+	}
+	ret = dram_init();
+	if (ret) {
+		debug("%s: dram_init() failed\n", __func__);
+		return ret;
+	}
+	memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
+
+	/* TODO(sjg at chromium.org): Consider calling cpu_init_r() here */
+	ret = interrupt_init();
+	if (ret) {
+		debug("%s: interrupt_init() failed\n", __func__);
+		return ret;
+	}
+
+	/*
+	 * The stack grows down from ptr. Put the global data at ptr. This
+	 * will only be used for SPL. Once SPL loads U-Boot proper it will
+	 * set up its own stack.
+	 */
+	gd->new_gd = (struct global_data *)ptr;
+	memcpy(gd->new_gd, gd, sizeof(*gd));
+	arch_setup_gd(gd->new_gd);
+	gd->start_addr_sp = (ulong)ptr;
+
+	/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
+	ret = mtrr_add_request(MTRR_TYPE_WRBACK,
+			       (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
+			       CONFIG_XIP_ROM_SIZE);
+	if (ret) {
+		debug("%s: SPI cache setup failed\n", __func__);
+		return ret;
+	}
+
+	return 0;
+}
+
+void board_init_f(ulong flags)
+{
+	int ret;
+
+	ret = x86_spl_init();
+	if (ret) {
+		debug("Error %d\n", ret);
+		hang();
+	}
+
+	/* Uninit CAR and jump to board_init_f_r() */
+	board_init_f_r_trampoline(gd->start_addr_sp);
+}
+
+void board_init_f_r(void)
+{
+	init_cache_f_r();
+	gd->flags &= ~GD_FLG_SERIAL_READY;
+	debug("cache status %d\n", dcache_status());
+	board_init_r(gd, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_BOARD;
+}
+
+int spl_start_uboot(void)
+{
+	return 0;
+}
+
+void spl_board_announce_boot_device(void)
+{
+	printf("SPI flash");
+}
+
+static int spl_board_load_image(struct spl_image_info *spl_image,
+				struct spl_boot_device *bootdev)
+{
+	spl_image->size = CONFIG_SYS_MONITOR_LEN;
+	spl_image->entry_point = CONFIG_SYS_TEXT_BASE;
+	spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
+	spl_image->os = IH_OS_U_BOOT;
+	spl_image->name = "U-Boot";
+
+	debug("Loading to %lx\n", spl_image->load_addr);
+
+	return 0;
+}
+SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
+
+int spl_spi_load_image(void)
+{
+	return -EPERM;
+}
+
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
+{
+	int ret;
+
+	printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
+	ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
+	debug("ret=%d\n", ret);
+	while (1);
+}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 32/62] x86: Move the i386 code into its own directory

[Simon Glass]

Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it
into its own directory and build it only in 32-bit mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/Makefile                           |   6 +-
 arch/x86/cpu/cpu.c                              | 504 ----------------------
 arch/x86/cpu/i386/Makefile                      |   7 +
 arch/x86/cpu/i386/cpu.c                         | 534 ++++++++++++++++++++++++
 arch/x86/cpu/{interrupts.c => i386/interrupt.c} |   4 -
 arch/x86/include/asm/mp.h                       |   3 +
 6 files changed, 549 insertions(+), 509 deletions(-)
 create mode 100644 arch/x86/cpu/i386/Makefile
 create mode 100644 arch/x86/cpu/i386/cpu.c
 rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 97b26b0fe76..41ad4818b75 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -14,7 +14,7 @@ else
 extra-y	= start.o
 endif
 extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
-obj-y	+= interrupts.o cpu.o cpu_x86.o call64.o setjmp.o
+obj-y	+= cpu.o cpu_x86.o call64.o setjmp.o
 
 AFLAGS_REMOVE_call32.o := -mregparm=3 \
 	$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
@@ -37,3 +37,7 @@ obj-y += mtrr.o
 obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SMP) += sipi_vector.o
 obj-y += turbo.o
+
+ifeq ($(CONFIG_$(SPL_)X86_64),)
+obj-y += i386/
+endif
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 7c1d6deda9d..8fa6953588b 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -43,55 +43,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Constructor for a conventional segment GDT (or LDT) entry
- * This is a macro so it can be used in initialisers
- */
-#define GDT_ENTRY(flags, base, limit)			\
-	((((base)  & 0xff000000ULL) << (56-24)) |	\
-	 (((flags) & 0x0000f0ffULL) << 40) |		\
-	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
-	 (((base)  & 0x00ffffffULL) << 16) |		\
-	 (((limit) & 0x0000ffffULL)))
-
-struct gdt_ptr {
-	u16 len;
-	u32 ptr;
-} __packed;
-
-struct cpu_device_id {
-	unsigned vendor;
-	unsigned device;
-};
-
-struct cpuinfo_x86 {
-	uint8_t x86;            /* CPU family */
-	uint8_t x86_vendor;     /* CPU vendor */
-	uint8_t x86_model;
-	uint8_t x86_mask;
-};
-
-/*
- * List of cpu vendor strings along with their normalized
- * id values.
- */
-static const struct {
-	int vendor;
-	const char *name;
-} x86_vendors[] = {
-	{ X86_VENDOR_INTEL,     "GenuineIntel", },
-	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
-	{ X86_VENDOR_AMD,       "AuthenticAMD", },
-	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
-	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
-	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
-	{ X86_VENDOR_RISE,      "RiseRiseRise", },
-	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
-	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
-	{ X86_VENDOR_NSC,       "Geode by NSC", },
-	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
-};
-
 static const char *const x86_vendor_name[] = {
 	[X86_VENDOR_INTEL]     = "Intel",
 	[X86_VENDOR_CYRIX]     = "Cyrix",
@@ -105,100 +56,6 @@ static const char *const x86_vendor_name[] = {
 	[X86_VENDOR_SIS]       = "SiS",
 };
 
-static void load_ds(u32 segment)
-{
-	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_es(u32 segment)
-{
-	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_fs(u32 segment)
-{
-	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_gs(u32 segment)
-{
-	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_ss(u32 segment)
-{
-	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
-}
-
-static void load_gdt(const u64 *boot_gdt, u16 num_entries)
-{
-	struct gdt_ptr gdt;
-
-	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
-	gdt.ptr = (ulong)boot_gdt;
-
-	asm volatile("lgdtl %0\n" : : "m" (gdt));
-}
-
-void arch_setup_gd(gd_t *new_gd)
-{
-	u64 *gdt_addr;
-
-	gdt_addr = new_gd->arch.gdt;
-
-	/*
-	 * CS: code, read/execute, 4 GB, base 0
-	 *
-	 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
-	 */
-	gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
-	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
-
-	/* DS: data, read/write, 4 GB, base 0 */
-	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
-
-	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
-	new_gd->arch.gd_addr = new_gd;
-	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
-		     (ulong)&new_gd->arch.gd_addr, 0xfffff);
-
-	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
-	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
-
-	/* 16-bit DS: data, read/write, 64 kB, base 0 */
-	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
-
-	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
-	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
-
-	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
-	load_ds(X86_GDT_ENTRY_32BIT_DS);
-	load_es(X86_GDT_ENTRY_32BIT_DS);
-	load_gs(X86_GDT_ENTRY_32BIT_DS);
-	load_ss(X86_GDT_ENTRY_32BIT_DS);
-	load_fs(X86_GDT_ENTRY_32BIT_FS);
-}
-
-#ifdef CONFIG_HAVE_FSP
-/*
- * Setup FSP execution environment GDT
- *
- * Per Intel FSP external architecture specification, before calling any FSP
- * APIs, we need make sure the system is in flat 32-bit mode and both the code
- * and data selectors should have full 4GB access range. Here we reuse the one
- * we used in arch/x86/cpu/start16.S, and reload the segement registers.
- */
-void setup_fsp_gdt(void)
-{
-	load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
-	load_ds(X86_GDT_ENTRY_32BIT_DS);
-	load_ss(X86_GDT_ENTRY_32BIT_DS);
-	load_es(X86_GDT_ENTRY_32BIT_DS);
-	load_fs(X86_GDT_ENTRY_32BIT_DS);
-	load_gs(X86_GDT_ENTRY_32BIT_DS);
-}
-#endif
-
 int __weak x86_cleanup_before_linux(void)
 {
 #ifdef CONFIG_BOOTSTAGE_STASH
@@ -209,241 +66,6 @@ int __weak x86_cleanup_before_linux(void)
 	return 0;
 }
 
-/*
- * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
- * by the fact that they preserve the flags across the division of 5/2.
- * PII and PPro exhibit this behavior too, but they have cpuid available.
- */
-
-/*
- * Perform the Cyrix 5/2 test. A Cyrix won't change
- * the flags, while other 486 chips will.
- */
-static inline int test_cyrix_52div(void)
-{
-	unsigned int test;
-
-	__asm__ __volatile__(
-	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
-	     "div %b2\n\t"	/* divide 5 by 2 */
-	     "lahf"		/* store flags into %ah */
-	     : "=a" (test)
-	     : "0" (5), "q" (2)
-	     : "cc");
-
-	/* AH is 0x02 on Cyrix after the divide.. */
-	return (unsigned char) (test >> 8) == 0x02;
-}
-
-/*
- *	Detect a NexGen CPU running without BIOS hypercode new enough
- *	to have CPUID. (Thanks to Herbert Oppmann)
- */
-
-static int deep_magic_nexgen_probe(void)
-{
-	int ret;
-
-	__asm__ __volatile__ (
-		"	movw	$0x5555, %%ax\n"
-		"	xorw	%%dx,%%dx\n"
-		"	movw	$2, %%cx\n"
-		"	divw	%%cx\n"
-		"	movl	$0, %%eax\n"
-		"	jnz	1f\n"
-		"	movl	$1, %%eax\n"
-		"1:\n"
-		: "=a" (ret) : : "cx", "dx");
-	return  ret;
-}
-
-static bool has_cpuid(void)
-{
-	return flag_is_changeable_p(X86_EFLAGS_ID);
-}
-
-static bool has_mtrr(void)
-{
-	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
-}
-
-static int build_vendor_name(char *vendor_name)
-{
-	struct cpuid_result result;
-	result = cpuid(0x00000000);
-	unsigned int *name_as_ints = (unsigned int *)vendor_name;
-
-	name_as_ints[0] = result.ebx;
-	name_as_ints[1] = result.edx;
-	name_as_ints[2] = result.ecx;
-
-	return result.eax;
-}
-
-static void identify_cpu(struct cpu_device_id *cpu)
-{
-	char vendor_name[16];
-	int i;
-
-	vendor_name[0] = '\0'; /* Unset */
-	cpu->device = 0; /* fix gcc 4.4.4 warning */
-
-	/* Find the id and vendor_name */
-	if (!has_cpuid()) {
-		/* Its a 486 if we can modify the AC flag */
-		if (flag_is_changeable_p(X86_EFLAGS_AC))
-			cpu->device = 0x00000400; /* 486 */
-		else
-			cpu->device = 0x00000300; /* 386 */
-		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
-			memcpy(vendor_name, "CyrixInstead", 13);
-			/* If we ever care we can enable cpuid here */
-		}
-		/* Detect NexGen with old hypercode */
-		else if (deep_magic_nexgen_probe())
-			memcpy(vendor_name, "NexGenDriven", 13);
-	}
-	if (has_cpuid()) {
-		int  cpuid_level;
-
-		cpuid_level = build_vendor_name(vendor_name);
-		vendor_name[12] = '\0';
-
-		/* Intel-defined flags: level 0x00000001 */
-		if (cpuid_level >= 0x00000001) {
-			cpu->device = cpuid_eax(0x00000001);
-		} else {
-			/* Have CPUID level 0 only unheard of */
-			cpu->device = 0x00000400;
-		}
-	}
-	cpu->vendor = X86_VENDOR_UNKNOWN;
-	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
-		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
-			cpu->vendor = x86_vendors[i].vendor;
-			break;
-		}
-	}
-}
-
-static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
-{
-	c->x86 = (tfms >> 8) & 0xf;
-	c->x86_model = (tfms >> 4) & 0xf;
-	c->x86_mask = tfms & 0xf;
-	if (c->x86 == 0xf)
-		c->x86 += (tfms >> 20) & 0xff;
-	if (c->x86 >= 0x6)
-		c->x86_model += ((tfms >> 16) & 0xF) << 4;
-}
-
-u32 cpu_get_family_model(void)
-{
-	return gd->arch.x86_device & 0x0fff0ff0;
-}
-
-u32 cpu_get_stepping(void)
-{
-	return gd->arch.x86_mask;
-}
-
-int x86_cpu_init_f(void)
-{
-	const u32 em_rst = ~X86_CR0_EM;
-	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
-
-	if (ll_boot_init()) {
-		/* initialize FPU, reset EM, set MP and NE */
-		asm ("fninit\n" \
-		"movl %%cr0, %%eax\n" \
-		"andl %0, %%eax\n" \
-		"orl  %1, %%eax\n" \
-		"movl %%eax, %%cr0\n" \
-		: : "i" (em_rst), "i" (mp_ne_set) : "eax");
-	}
-
-	/* identify CPU via cpuid and store the decoded info into gd->arch */
-	if (has_cpuid()) {
-		struct cpu_device_id cpu;
-		struct cpuinfo_x86 c;
-
-		identify_cpu(&cpu);
-		get_fms(&c, cpu.device);
-		gd->arch.x86 = c.x86;
-		gd->arch.x86_vendor = cpu.vendor;
-		gd->arch.x86_model = c.x86_model;
-		gd->arch.x86_mask = c.x86_mask;
-		gd->arch.x86_device = cpu.device;
-
-		gd->arch.has_mtrr = has_mtrr();
-	}
-	/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
-	gd->pci_ram_top = 0x80000000U;
-
-	/* Configure fixed range MTRRs for some legacy regions */
-	if (gd->arch.has_mtrr) {
-		u64 mtrr_cap;
-
-		mtrr_cap = native_read_msr(MTRR_CAP_MSR);
-		if (mtrr_cap & MTRR_CAP_FIX) {
-			/* Mark the VGA RAM area as uncacheable */
-			native_write_msr(MTRR_FIX_16K_A0000_MSR,
-					 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
-					 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
-
-			/*
-			 * Mark the PCI ROM area as cacheable to improve ROM
-			 * execution performance.
-			 */
-			native_write_msr(MTRR_FIX_4K_C0000_MSR,
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
-			native_write_msr(MTRR_FIX_4K_C8000_MSR,
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
-			native_write_msr(MTRR_FIX_4K_D0000_MSR,
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
-			native_write_msr(MTRR_FIX_4K_D8000_MSR,
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
-					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
-
-			/* Enable the fixed range MTRRs */
-			msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
-		}
-	}
-
-#ifdef CONFIG_I8254_TIMER
-	/* Set up the i8254 timer if required */
-	i8254_init();
-#endif
-
-	return 0;
-}
-
-void x86_enable_caches(void)
-{
-	unsigned long cr0;
-
-	cr0 = read_cr0();
-	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
-	write_cr0(cr0);
-	wbinvd();
-}
-void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
-
-void x86_disable_caches(void)
-{
-	unsigned long cr0;
-
-	cr0 = read_cr0();
-	cr0 |= X86_CR0_NW | X86_CR0_CD;
-	wbinvd();
-	write_cr0(cr0);
-	wbinvd();
-}
-void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
-
 int x86_init_cache(void)
 {
 	enable_caches();
@@ -483,11 +105,6 @@ void x86_full_reset(void)
 	outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
 }
 
-int dcache_status(void)
-{
-	return !(read_cr0() & X86_CR0_CD);
-}
-
 /* Define these functions to allow ehch-hcd to function */
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
@@ -520,57 +137,6 @@ int icache_status(void)
 	return 1;
 }
 
-void cpu_enable_paging_pae(ulong cr3)
-{
-	__asm__ __volatile__(
-		/* Load the page table address */
-		"movl	%0, %%cr3\n"
-		/* Enable pae */
-		"movl	%%cr4, %%eax\n"
-		"orl	$0x00000020, %%eax\n"
-		"movl	%%eax, %%cr4\n"
-		/* Enable paging */
-		"movl	%%cr0, %%eax\n"
-		"orl	$0x80000000, %%eax\n"
-		"movl	%%eax, %%cr0\n"
-		:
-		: "r" (cr3)
-		: "eax");
-}
-
-void cpu_disable_paging_pae(void)
-{
-	/* Turn off paging */
-	__asm__ __volatile__ (
-		/* Disable paging */
-		"movl	%%cr0, %%eax\n"
-		"andl	$0x7fffffff, %%eax\n"
-		"movl	%%eax, %%cr0\n"
-		/* Disable pae */
-		"movl	%%cr4, %%eax\n"
-		"andl	$0xffffffdf, %%eax\n"
-		"movl	%%eax, %%cr4\n"
-		:
-		:
-		: "eax");
-}
-
-static bool can_detect_long_mode(void)
-{
-	return cpuid_eax(0x80000000) > 0x80000000UL;
-}
-
-static bool has_long_mode(void)
-{
-	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
-}
-
-int cpu_has_64bit(void)
-{
-	return has_cpuid() && can_detect_long_mode() &&
-		has_long_mode();
-}
-
 const char *cpu_vendor_name(int vendor)
 {
 	const char *name;
@@ -616,46 +182,6 @@ int default_print_cpuinfo(void)
 	return 0;
 }
 
-#define PAGETABLE_SIZE		(6 * 4096)
-
-/**
- * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
- *
- * @pgtable: Pointer to a 24iKB block of memory
- */
-static void build_pagetable(uint32_t *pgtable)
-{
-	uint i;
-
-	memset(pgtable, '\0', PAGETABLE_SIZE);
-
-	/* Level 4 needs a single entry */
-	pgtable[0] = (ulong)&pgtable[1024] + 7;
-
-	/* Level 3 has one 64-bit entry for each GiB of memory */
-	for (i = 0; i < 4; i++)
-		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
-
-	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
-	for (i = 0; i < 2048; i++)
-		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
-}
-
-int cpu_jump_to_64bit(ulong setup_base, ulong target)
-{
-	uint32_t *pgtable;
-
-	pgtable = memalign(4096, PAGETABLE_SIZE);
-	if (!pgtable)
-		return -ENOMEM;
-
-	build_pagetable(pgtable);
-	cpu_call64((ulong)pgtable, setup_base, target);
-	free(pgtable);
-
-	return -EFAULT;
-}
-
 void show_boot_progress(int val)
 {
 	outb(val, POST_PORT);
@@ -680,36 +206,6 @@ int last_stage_init(void)
 }
 #endif
 
-#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
-	return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
-	MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
-	/* Wait for APs to finish initialization before proceeding */
-	MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int x86_mp_init(void)
-{
-	struct mp_params mp_params;
-
-	mp_params.parallel_microcode_load = 0,
-	mp_params.flight_plan = &mp_steps[0];
-	mp_params.num_records = ARRAY_SIZE(mp_steps);
-	mp_params.microcode_pointer = 0;
-
-	if (mp_init(&mp_params)) {
-		printf("Warning: MP init failure\n");
-		return -EIO;
-	}
-
-	return 0;
-}
-#endif
-
 static int x86_init_cpus(void)
 {
 #ifdef CONFIG_SMP
diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile
new file mode 100644
index 00000000000..d3364955d8e
--- /dev/null
+++ b/arch/x86/cpu/i386/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+obj-y += cpu.o
+obj-y += interrupt.o
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
new file mode 100644
index 00000000000..09a5b919e07
--- /dev/null
+++ b/arch/x86/cpu/i386/cpu.c
@@ -0,0 +1,534 @@
+/*
+ * (C) Copyright 2008-2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Part of this file is adapted from coreboot
+ * src/arch/x86/lib/cpu.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/control_regs.h>
+#include <asm/cpu.h>
+#include <asm/mp.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/processor-flags.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Constructor for a conventional segment GDT (or LDT) entry
+ * This is a macro so it can be used in initialisers
+ */
+#define GDT_ENTRY(flags, base, limit)			\
+	((((base)  & 0xff000000ULL) << (56-24)) |	\
+	 (((flags) & 0x0000f0ffULL) << 40) |		\
+	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
+	 (((base)  & 0x00ffffffULL) << 16) |		\
+	 (((limit) & 0x0000ffffULL)))
+
+struct gdt_ptr {
+	u16 len;
+	u32 ptr;
+} __packed;
+
+struct cpu_device_id {
+	unsigned vendor;
+	unsigned device;
+};
+
+struct cpuinfo_x86 {
+	uint8_t x86;            /* CPU family */
+	uint8_t x86_vendor;     /* CPU vendor */
+	uint8_t x86_model;
+	uint8_t x86_mask;
+};
+
+/*
+ * List of cpu vendor strings along with their normalized
+ * id values.
+ */
+static const struct {
+	int vendor;
+	const char *name;
+} x86_vendors[] = {
+	{ X86_VENDOR_INTEL,     "GenuineIntel", },
+	{ X86_VENDOR_CYRIX,     "CyrixInstead", },
+	{ X86_VENDOR_AMD,       "AuthenticAMD", },
+	{ X86_VENDOR_UMC,       "UMC UMC UMC ", },
+	{ X86_VENDOR_NEXGEN,    "NexGenDriven", },
+	{ X86_VENDOR_CENTAUR,   "CentaurHauls", },
+	{ X86_VENDOR_RISE,      "RiseRiseRise", },
+	{ X86_VENDOR_TRANSMETA, "GenuineTMx86", },
+	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
+	{ X86_VENDOR_NSC,       "Geode by NSC", },
+	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
+};
+
+static void load_ds(u32 segment)
+{
+	asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_es(u32 segment)
+{
+	asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_fs(u32 segment)
+{
+	asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_gs(u32 segment)
+{
+	asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_ss(u32 segment)
+{
+	asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE));
+}
+
+static void load_gdt(const u64 *boot_gdt, u16 num_entries)
+{
+	struct gdt_ptr gdt;
+
+	gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
+	gdt.ptr = (ulong)boot_gdt;
+
+	asm volatile("lgdtl %0\n" : : "m" (gdt));
+}
+
+void arch_setup_gd(gd_t *new_gd)
+{
+	u64 *gdt_addr;
+
+	gdt_addr = new_gd->arch.gdt;
+
+	/*
+	 * CS: code, read/execute, 4 GB, base 0
+	 *
+	 * Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS
+	 */
+	gdt_addr[X86_GDT_ENTRY_UNUSED] = GDT_ENTRY(0xc09b, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
+
+	/* DS: data, read/write, 4 GB, base 0 */
+	gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
+
+	/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
+	new_gd->arch.gd_addr = new_gd;
+	gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
+		     (ulong)&new_gd->arch.gd_addr, 0xfffff);
+
+	/* 16-bit CS: code, read/execute, 64 kB, base 0 */
+	gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
+
+	/* 16-bit DS: data, read/write, 64 kB, base 0 */
+	gdt_addr[X86_GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x0093, 0, 0x0ffff);
+
+	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_CS] = GDT_ENTRY(0x809b, 0, 0xfffff);
+	gdt_addr[X86_GDT_ENTRY_16BIT_FLAT_DS] = GDT_ENTRY(0x8093, 0, 0xfffff);
+
+	load_gdt(gdt_addr, X86_GDT_NUM_ENTRIES);
+	load_ds(X86_GDT_ENTRY_32BIT_DS);
+	load_es(X86_GDT_ENTRY_32BIT_DS);
+	load_gs(X86_GDT_ENTRY_32BIT_DS);
+	load_ss(X86_GDT_ENTRY_32BIT_DS);
+	load_fs(X86_GDT_ENTRY_32BIT_FS);
+}
+
+#ifdef CONFIG_HAVE_FSP
+/*
+ * Setup FSP execution environment GDT
+ *
+ * Per Intel FSP external architecture specification, before calling any FSP
+ * APIs, we need make sure the system is in flat 32-bit mode and both the code
+ * and data selectors should have full 4GB access range. Here we reuse the one
+ * we used in arch/x86/cpu/start16.S, and reload the segement registers.
+ */
+void setup_fsp_gdt(void)
+{
+	load_gdt((const u64 *)(gdt_rom + CONFIG_RESET_SEG_START), 4);
+	load_ds(X86_GDT_ENTRY_32BIT_DS);
+	load_ss(X86_GDT_ENTRY_32BIT_DS);
+	load_es(X86_GDT_ENTRY_32BIT_DS);
+	load_fs(X86_GDT_ENTRY_32BIT_DS);
+	load_gs(X86_GDT_ENTRY_32BIT_DS);
+}
+#endif
+
+/*
+ * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
+ * by the fact that they preserve the flags across the division of 5/2.
+ * PII and PPro exhibit this behavior too, but they have cpuid available.
+ */
+
+/*
+ * Perform the Cyrix 5/2 test. A Cyrix won't change
+ * the flags, while other 486 chips will.
+ */
+static inline int test_cyrix_52div(void)
+{
+	unsigned int test;
+
+	__asm__ __volatile__(
+	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
+	     "div %b2\n\t"	/* divide 5 by 2 */
+	     "lahf"		/* store flags into %ah */
+	     : "=a" (test)
+	     : "0" (5), "q" (2)
+	     : "cc");
+
+	/* AH is 0x02 on Cyrix after the divide.. */
+	return (unsigned char) (test >> 8) == 0x02;
+}
+
+/*
+ *	Detect a NexGen CPU running without BIOS hypercode new enough
+ *	to have CPUID. (Thanks to Herbert Oppmann)
+ */
+static int deep_magic_nexgen_probe(void)
+{
+	int ret;
+
+	__asm__ __volatile__ (
+		"	movw	$0x5555, %%ax\n"
+		"	xorw	%%dx,%%dx\n"
+		"	movw	$2, %%cx\n"
+		"	divw	%%cx\n"
+		"	movl	$0, %%eax\n"
+		"	jnz	1f\n"
+		"	movl	$1, %%eax\n"
+		"1:\n"
+		: "=a" (ret) : : "cx", "dx");
+	return  ret;
+}
+
+static bool has_cpuid(void)
+{
+	return flag_is_changeable_p(X86_EFLAGS_ID);
+}
+
+static bool has_mtrr(void)
+{
+	return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
+}
+
+static int build_vendor_name(char *vendor_name)
+{
+	struct cpuid_result result;
+	result = cpuid(0x00000000);
+	unsigned int *name_as_ints = (unsigned int *)vendor_name;
+
+	name_as_ints[0] = result.ebx;
+	name_as_ints[1] = result.edx;
+	name_as_ints[2] = result.ecx;
+
+	return result.eax;
+}
+
+static void identify_cpu(struct cpu_device_id *cpu)
+{
+	char vendor_name[16];
+	int i;
+
+	vendor_name[0] = '\0'; /* Unset */
+	cpu->device = 0; /* fix gcc 4.4.4 warning */
+
+	/* Find the id and vendor_name */
+	if (!has_cpuid()) {
+		/* Its a 486 if we can modify the AC flag */
+		if (flag_is_changeable_p(X86_EFLAGS_AC))
+			cpu->device = 0x00000400; /* 486 */
+		else
+			cpu->device = 0x00000300; /* 386 */
+		if ((cpu->device == 0x00000400) && test_cyrix_52div()) {
+			memcpy(vendor_name, "CyrixInstead", 13);
+			/* If we ever care we can enable cpuid here */
+		}
+		/* Detect NexGen with old hypercode */
+		else if (deep_magic_nexgen_probe())
+			memcpy(vendor_name, "NexGenDriven", 13);
+	}
+	if (has_cpuid()) {
+		int  cpuid_level;
+
+		cpuid_level = build_vendor_name(vendor_name);
+		vendor_name[12] = '\0';
+
+		/* Intel-defined flags: level 0x00000001 */
+		if (cpuid_level >= 0x00000001) {
+			cpu->device = cpuid_eax(0x00000001);
+		} else {
+			/* Have CPUID level 0 only unheard of */
+			cpu->device = 0x00000400;
+		}
+	}
+	cpu->vendor = X86_VENDOR_UNKNOWN;
+	for (i = 0; i < ARRAY_SIZE(x86_vendors); i++) {
+		if (memcmp(vendor_name, x86_vendors[i].name, 12) == 0) {
+			cpu->vendor = x86_vendors[i].vendor;
+			break;
+		}
+	}
+}
+
+static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
+{
+	c->x86 = (tfms >> 8) & 0xf;
+	c->x86_model = (tfms >> 4) & 0xf;
+	c->x86_mask = tfms & 0xf;
+	if (c->x86 == 0xf)
+		c->x86 += (tfms >> 20) & 0xff;
+	if (c->x86 >= 0x6)
+		c->x86_model += ((tfms >> 16) & 0xF) << 4;
+}
+
+u32 cpu_get_family_model(void)
+{
+	return gd->arch.x86_device & 0x0fff0ff0;
+}
+
+u32 cpu_get_stepping(void)
+{
+	return gd->arch.x86_mask;
+}
+
+int x86_cpu_init_f(void)
+{
+	const u32 em_rst = ~X86_CR0_EM;
+	const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
+	if (ll_boot_init()) {
+		/* initialize FPU, reset EM, set MP and NE */
+		asm ("fninit\n" \
+		"movl %%cr0, %%eax\n" \
+		"andl %0, %%eax\n" \
+		"orl  %1, %%eax\n" \
+		"movl %%eax, %%cr0\n" \
+		: : "i" (em_rst), "i" (mp_ne_set) : "eax");
+	}
+
+	/* identify CPU via cpuid and store the decoded info into gd->arch */
+	if (has_cpuid()) {
+		struct cpu_device_id cpu;
+		struct cpuinfo_x86 c;
+
+		identify_cpu(&cpu);
+		get_fms(&c, cpu.device);
+		gd->arch.x86 = c.x86;
+		gd->arch.x86_vendor = cpu.vendor;
+		gd->arch.x86_model = c.x86_model;
+		gd->arch.x86_mask = c.x86_mask;
+		gd->arch.x86_device = cpu.device;
+
+		gd->arch.has_mtrr = has_mtrr();
+	}
+	/* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+	gd->pci_ram_top = 0x80000000U;
+
+	/* Configure fixed range MTRRs for some legacy regions */
+	if (gd->arch.has_mtrr) {
+		u64 mtrr_cap;
+
+		mtrr_cap = native_read_msr(MTRR_CAP_MSR);
+		if (mtrr_cap & MTRR_CAP_FIX) {
+			/* Mark the VGA RAM area as uncacheable */
+			native_write_msr(MTRR_FIX_16K_A0000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
+					 MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+			/*
+			 * Mark the PCI ROM area as cacheable to improve ROM
+			 * execution performance.
+			 */
+			native_write_msr(MTRR_FIX_4K_C0000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+			native_write_msr(MTRR_FIX_4K_C8000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+			native_write_msr(MTRR_FIX_4K_D0000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+			native_write_msr(MTRR_FIX_4K_D8000_MSR,
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+					 MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+			/* Enable the fixed range MTRRs */
+			msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
+		}
+	}
+
+#ifdef CONFIG_I8254_TIMER
+	/* Set up the i8254 timer if required */
+	i8254_init();
+#endif
+
+	return 0;
+}
+
+void x86_enable_caches(void)
+{
+	unsigned long cr0;
+
+	cr0 = read_cr0();
+	cr0 &= ~(X86_CR0_NW | X86_CR0_CD);
+	write_cr0(cr0);
+	wbinvd();
+}
+void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
+
+void x86_disable_caches(void)
+{
+	unsigned long cr0;
+
+	cr0 = read_cr0();
+	cr0 |= X86_CR0_NW | X86_CR0_CD;
+	wbinvd();
+	write_cr0(cr0);
+	wbinvd();
+}
+void disable_caches(void) __attribute__((weak, alias("x86_disable_caches")));
+
+int dcache_status(void)
+{
+	return !(read_cr0() & X86_CR0_CD);
+}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+	__asm__ __volatile__(
+		/* Load the page table address */
+		"movl	%0, %%cr3\n"
+		/* Enable pae */
+		"movl	%%cr4, %%eax\n"
+		"orl	$0x00000020, %%eax\n"
+		"movl	%%eax, %%cr4\n"
+		/* Enable paging */
+		"movl	%%cr0, %%eax\n"
+		"orl	$0x80000000, %%eax\n"
+		"movl	%%eax, %%cr0\n"
+		:
+		: "r" (cr3)
+		: "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+	/* Turn off paging */
+	__asm__ __volatile__ (
+		/* Disable paging */
+		"movl	%%cr0, %%eax\n"
+		"andl	$0x7fffffff, %%eax\n"
+		"movl	%%eax, %%cr0\n"
+		/* Disable pae */
+		"movl	%%cr4, %%eax\n"
+		"andl	$0xffffffdf, %%eax\n"
+		"movl	%%eax, %%cr4\n"
+		:
+		:
+		: "eax");
+}
+
+static bool can_detect_long_mode(void)
+{
+	return cpuid_eax(0x80000000) > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+	return cpuid_edx(0x80000001) & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+	return has_cpuid() && can_detect_long_mode() &&
+		has_long_mode();
+}
+
+#define PAGETABLE_SIZE		(6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+	uint i;
+
+	memset(pgtable, '\0', PAGETABLE_SIZE);
+
+	/* Level 4 needs a single entry */
+	pgtable[0] = (ulong)&pgtable[1024] + 7;
+
+	/* Level 3 has one 64-bit entry for each GiB of memory */
+	for (i = 0; i < 4; i++)
+		pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
+
+	/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+	for (i = 0; i < 2048; i++)
+		pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+	uint32_t *pgtable;
+
+	pgtable = memalign(4096, PAGETABLE_SIZE);
+	if (!pgtable)
+		return -ENOMEM;
+
+	build_pagetable(pgtable);
+	cpu_call64((ulong)pgtable, setup_base, target);
+	free(pgtable);
+
+	return -EFAULT;
+}
+
+#ifdef CONFIG_SMP
+static int enable_smis(struct udevice *cpu, void *unused)
+{
+	return 0;
+}
+
+static struct mp_flight_record mp_steps[] = {
+	MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
+	/* Wait for APs to finish initialization before proceeding */
+	MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
+};
+
+int x86_mp_init(void)
+{
+	struct mp_params mp_params;
+
+	mp_params.parallel_microcode_load = 0,
+	mp_params.flight_plan = &mp_steps[0];
+	mp_params.num_records = ARRAY_SIZE(mp_steps);
+	mp_params.microcode_pointer = 0;
+
+	if (mp_init(&mp_params)) {
+		printf("Warning: MP init failure\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/i386/interrupt.c
similarity index 99%
rename from arch/x86/cpu/interrupts.c
rename to arch/x86/cpu/i386/interrupt.c
index 5f6cdd36ac1..8dfbb4880fd 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -13,16 +13,12 @@
 
 #include <common.h>
 #include <dm.h>
-#include <asm/cache.h>
 #include <asm/control_regs.h>
 #include <asm/i8259.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
-#include <asm/msr.h>
 #include <asm/processor-flags.h>
-#include <asm/processor.h>
-#include <asm/u-boot-x86.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h
index 2e6c3120c77..83b99dcd192 100644
--- a/arch/x86/include/asm/mp.h
+++ b/arch/x86/include/asm/mp.h
@@ -90,4 +90,7 @@ int mp_init(struct mp_params *params);
 /* Probes the CPU device */
 int mp_init_cpu(struct udevice *cpu, void *unused);
 
+/* Set up additional CPUs */
+int x86_mp_init(void);
+
 #endif /* _X86_MP_H_ */
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 33/62] x86: Add cpu code for x86_64

[Simon Glass]

There is not much needed at present, but set up a separate directory to put
this code as it grows.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Drop blank line at end of arch/x86/cpu/x86_64/interrupts.c
- Drop #include of debug_uart.h

Changes in v2: None

 arch/x86/cpu/Makefile            |  4 +++-
 arch/x86/cpu/x86_64/Makefile     |  6 ++++++
 arch/x86/cpu/x86_64/cpu.c        | 34 ++++++++++++++++++++++++++++++++++
 arch/x86/cpu/x86_64/interrupts.c | 29 +++++++++++++++++++++++++++++
 4 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/x86_64/Makefile
 create mode 100644 arch/x86/cpu/x86_64/cpu.c
 create mode 100644 arch/x86/cpu/x86_64/interrupts.c

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 41ad4818b75..7f89ff047fa 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -38,6 +38,8 @@ obj-$(CONFIG_PCI) += pci.o
 obj-$(CONFIG_SMP) += sipi_vector.o
 obj-y += turbo.o
 
-ifeq ($(CONFIG_$(SPL_)X86_64),)
+ifeq ($(CONFIG_$(SPL_)X86_64),y)
+obj-y += x86_64/
+else
 obj-y += i386/
 endif
diff --git a/arch/x86/cpu/x86_64/Makefile b/arch/x86/cpu/x86_64/Makefile
new file mode 100644
index 00000000000..4b063862e17
--- /dev/null
+++ b/arch/x86/cpu/x86_64/Makefile
@@ -0,0 +1,6 @@
+#
+# (C) Copyright 2016 Google, Inc
+# Written by Simon Glass <sjg@chromium.org>
+#
+
+obj-y += cpu.o interrupts.o
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
new file mode 100644
index 00000000000..b12eab1cb69
--- /dev/null
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int cpu_has_64bit(void)
+{
+	return true;
+}
+
+void enable_caches(void)
+{
+	/* Not implemented */
+}
+
+void disable_caches(void)
+{
+	/* Not implemented */
+}
+
+int dcache_status(void)
+{
+	return true;
+}
+
+int x86_mp_init(void)
+{
+	/* Not implemented */
+	return 0;
+}
diff --git a/arch/x86/cpu/x86_64/interrupts.c b/arch/x86/cpu/x86_64/interrupts.c
new file mode 100644
index 00000000000..3e061731865
--- /dev/null
+++ b/arch/x86/cpu/x86_64/interrupts.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/processor-flags.h>
+
+void enable_interrupts(void)
+{
+	asm("sti\n");
+}
+
+int disable_interrupts(void)
+{
+	long flags;
+
+	asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
+
+	return flags & X86_EFLAGS_IF;
+}
+
+int interrupt_init(void)
+{
+	/* Nothing to do - this was already done in SPL */
+	return 0;
+}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 34/62] x86: Support global_data on x86_64

[Simon Glass]

At present this is just an ordinary variable. We may consider making it a
fixed register in the future.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Add a TODO to look at using a fixed register for gd on x86_64
- Expand the TODO about the necessary printch() call
- Add a required debug_uart.h #include in this patch

Changes in v2: None

 arch/x86/cpu/x86_64/cpu.c          | 27 +++++++++++++++++++++++++++
 arch/x86/include/asm/global_data.h |  7 ++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index b12eab1cb69..36272296e63 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -6,6 +6,33 @@
  */
 
 #include <common.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Global declaration of gd */
+struct global_data *global_data_ptr;
+
+void arch_setup_gd(gd_t *new_gd)
+{
+	global_data_ptr = new_gd;
+
+	/*
+	 * TODO(sjg at chromium.org): For some reason U-Boot does not boot
+	 * without this line. It fails to start up U-Boot proper and instead
+	 * restarts SPL. Need to figure out why:
+	 *
+	 * U-Boot SPL 2017.01
+	 *
+	 * U-Boot SPL 2017.01
+	 * CPU:   Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz
+	 * Trying to boot from SPIJumping to 64-bit U-Boot: Note many
+	 * features are missing
+	 *
+	 * U-Boot SPL 2017.01
+	 */
+	printch(' ');
+}
 
 int cpu_has_64bit(void)
 {
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 7434f779b66..34e19efd145 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -104,8 +104,9 @@ struct arch_global_data {
 #include <asm-generic/global_data.h>
 
 #ifndef __ASSEMBLY__
-# ifdef CONFIG_EFI_APP
+# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
 
+/* TODO(sjg at chromium.org): Consider using a fixed register for gd on x86_64 */
 #define gd global_data_ptr
 
 #define DECLARE_GLOBAL_DATA_PTR   extern struct global_data *global_data_ptr
@@ -114,7 +115,11 @@ static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
 {
 	gd_t *gd_ptr;
 
+#if CONFIG_IS_ENABLED(X86_64)
+	asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
+#else
 	asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
+#endif
 
 	return gd_ptr;
 }
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 35/62] x86: Fix up CONFIG_X86_64 check

[Simon Glass]

When SPL and U-Boot proper have different settings for this flag, we need to
use the correct one. Fix this up in the interrupt code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/i386/interrupt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c
index 8dfbb4880fd..a05830326b5 100644
--- a/arch/x86/cpu/i386/interrupt.c
+++ b/arch/x86/cpu/i386/interrupt.c
@@ -234,7 +234,7 @@ int disable_interrupts(void)
 {
 	long flags;
 
-#ifdef CONFIG_X86_64
+#if CONFIG_IS_ENABLED(X86_64)
 	asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
 #else
 	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 36/62] x86: Add a link script for 64-bit x86

[Simon Glass]

This needs a different image format from 32-bit x86, so add a new link
script.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/config.mk     |  6 ++++
 arch/x86/cpu/u-boot-64.lds | 76 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)
 create mode 100644 arch/x86/cpu/u-boot-64.lds

diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk
index 1263221e699..4c99a35621d 100644
--- a/arch/x86/cpu/config.mk
+++ b/arch/x86/cpu/config.mk
@@ -15,3 +15,9 @@ LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE)
 LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC)
 LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
 LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)"
+
+ifdef CONFIG_X86_64
+ifndef CONFIG_SPL_BUILD
+LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds
+endif
+endif
diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds
new file mode 100644
index 00000000000..718790c79a9
--- /dev/null
+++ b/arch/x86/cpu/u-boot-64.lds
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel at omicron.se.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64")
+OUTPUT_ARCH(i386:x86-64)
+ENTRY(_start)
+
+SECTIONS
+{
+#ifndef CONFIG_CMDLINE
+	/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
+#endif
+
+	. = CONFIG_SYS_TEXT_BASE;	/* Location of bootcode in flash */
+	__text_start = .;
+	.text  : { *(.text*); }
+
+	. = ALIGN(4);
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data*) }
+
+	. = ALIGN(4);
+	.hash : { *(.hash*) }
+
+	. = ALIGN(4);
+	.got : { *(.got*) }
+
+	. = ALIGN(4);
+	__data_end = .;
+	__init_end = .;
+
+	. = ALIGN(4);
+	.dynsym : { *(.dynsym*) }
+
+	. = ALIGN(4);
+	__rel_dyn_start = .;
+	.rela.dyn : {
+		*(.rela*)
+	}
+	__rel_dyn_end = .;
+	. = ALIGN(4);
+
+	.dynamic : { *(.dynamic) }
+
+	. = ALIGN(4);
+	_end = .;
+
+	.bss __rel_dyn_start (OVERLAY) : {
+		__bss_start = .;
+		*(.bss)
+		*(COM*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 37/62] x86: Add a link script for SPL

[Simon Glass]

If SPL is used it is always build in 32-bit mode. Add a link script to
handle the correct placement of the sections.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/u-boot-spl.lds | 74 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 arch/x86/cpu/u-boot-spl.lds

diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds
new file mode 100644
index 00000000000..8a38d58f123
--- /dev/null
+++ b/arch/x86/cpu/u-boot-spl.lds
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB, daniel at omicron.se.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+#ifndef CONFIG_CMDLINE
+	/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
+#endif
+
+	. = CONFIG_SPL_TEXT_BASE;	/* Location of bootcode in flash */
+	__text_start = .;
+	.text  : { *(.text*); }
+
+	. = ALIGN(4);
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : { *(.data*) }
+
+	. = ALIGN(4);
+	__data_end = .;
+	__init_end = .;
+
+        _image_binary_end = .;
+
+	. = 0x120000;
+	.bss (OVERLAY) : {
+		__bss_start = .;
+		*(.bss*)
+		*(COM*)
+		. = ALIGN(4);
+		__bss_end = .;
+	}
+	__bss_size = __bss_end - __bss_start;
+
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+
+#ifdef CONFIG_SPL_X86_16BIT_INIT
+	/*
+	 * The following expressions place the 16-bit Real-Mode code and
+	 * Reset Vector at the end of the Flash ROM
+	 */
+	. = START_16 - RESET_SEG_START;
+	.start16 : AT (START_16) {
+		KEEP(*(.start16));
+	}
+
+	. = RESET_VEC_LOC - RESET_SEG_START;
+	.resetvec : AT (RESET_VEC_LOC) {
+		KEEP(*(.resetvec));
+	}
+#endif
+
+}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 38/62] x86: Add SPL build rules for start-up code

[Simon Glass]

When SPL is used we need to build the 16-bit start-up code. Add Makefile
rules to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 scripts/Makefile.spl | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 82cfc601b29..b52f9963f7d 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -179,6 +179,8 @@ ifeq ($(CONFIG_SYS_SOC),"at91")
 ALL-y	+= boot.bin
 endif
 
+ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin
+
 ALL-$(CONFIG_ARCH_ZYNQ)		+= $(obj)/boot.bin
 ALL-$(CONFIG_ARCH_ZYNQMP)	+= $(obj)/boot.bin
 
@@ -263,11 +265,16 @@ endif
 quiet_cmd_objcopy = OBJCOPY $@
 cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@
 
-OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary
+OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \
+		$(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec)
 
 $(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE
 	$(call if_changed,objcopy)
 
+OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j .start16 -j .resetvec
+$(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE
+	$(call if_changed,objcopy)
+
 LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
 ifneq ($(CONFIG_SPL_TEXT_BASE),)
 LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 39/62] x86: Fix up byteorder.h for x86_64

[Simon Glass]

Remove the very old x86 code and add support for 64-bit.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/byteorder.h | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h
index 7dfeb8bbed2..a2d1fd8703b 100644
--- a/arch/x86/include/asm/byteorder.h
+++ b/arch/x86/include/asm/byteorder.h
@@ -8,24 +8,25 @@
 
 static __inline__ __u32 ___arch__swab32(__u32 x)
 {
-#ifdef CONFIG_X86_BSWAP
 	__asm__("bswap %0" : "=r" (x) : "0" (x));
-#else
-	__asm__("xchgb %b0,%h0\n\t"	/* swap lower bytes	*/
-		"rorl $16,%0\n\t"	/* swap words		*/
-		"xchgb %b0,%h0"		/* swap higher bytes	*/
-		:"=q" (x)
-		: "0" (x));
-#endif
+
 	return x;
 }
 
+#define _constant_swab16(x) ((__u16)(				\
+	(((__u16)(x) & (__u16)0x00ffU) << 8) |			\
+	(((__u16)(x) & (__u16)0xff00U) >> 8)))
+
 static __inline__ __u16 ___arch__swab16(__u16 x)
 {
+#if CONFIG_IS_ENABLED(X86_64)
+	return _constant_swab16(x);
+#else
 	__asm__("xchgb %b0,%h0"		/* swap bytes		*/ \
 		: "=q" (x) \
 		:  "0" (x)); \
 		return x;
+#endif
 }
 
 #define __arch__swab32(x) ___arch__swab32(x)
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 40/62] x86: Drop flag_is_changable() on x86_64

[Simon Glass]

This doesn't build at present and is not used in a 64-bit build. Disable it
for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/cpu.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 540024a8592..b408515582c 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -159,6 +159,8 @@ static inline unsigned int cpuid_edx(unsigned int op)
 	return edx;
 }
 
+#if !CONFIG_IS_ENABLED(X86_64)
+
 /* Standard macro to see if a specific flag is changeable */
 static inline int flag_is_changeable_p(uint32_t flag)
 {
@@ -179,6 +181,7 @@ static inline int flag_is_changeable_p(uint32_t flag)
 		: "ir" (flag));
 	return ((f1^f2) & flag) != 0;
 }
+#endif
 
 static inline void mfence(void)
 {
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 41/62] x86: Fix up type sizes for 64-bit

[Simon Glass]

Adjust types as needed to support 64-bit compilation.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/posix_types.h | 5 +++++
 arch/x86/include/asm/types.h       | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index 5529f32702c..717f6cb8e01 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -16,8 +16,13 @@ typedef int		__kernel_pid_t;
 typedef unsigned short	__kernel_ipc_pid_t;
 typedef unsigned short	__kernel_uid_t;
 typedef unsigned short	__kernel_gid_t;
+#if CONFIG_IS_ENABLED(X86_64)
+typedef unsigned long	__kernel_size_t;
+typedef long		__kernel_ssize_t;
+#else
 typedef unsigned int	__kernel_size_t;
 typedef int		__kernel_ssize_t;
+#endif
 typedef int		__kernel_ptrdiff_t;
 typedef long		__kernel_time_t;
 typedef long		__kernel_suseconds_t;
diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h
index 880dcb488a5..a47e581fe3a 100644
--- a/arch/x86/include/asm/types.h
+++ b/arch/x86/include/asm/types.h
@@ -44,7 +44,12 @@ typedef __INT64_TYPE__ s64;
 typedef __UINT64_TYPE__ u64;
 #endif
 
+#if CONFIG_IS_ENABLED(X86_64)
+#define BITS_PER_LONG 64
+#else
 #define BITS_PER_LONG 32
+#endif
+
 /* Dma addresses are 32-bits wide.  */
 
 typedef u32 dma_addr_t;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 42/62] x86: ivybridge: Skip SATA init in SPL

[Simon Glass]

This doesn't work at present. Disable it for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Fix 'skipt' typo in the subject

Changes in v2: None

 arch/x86/cpu/ivybridge/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index d13d0d3f694..1a526c8f0f5 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -12,7 +12,9 @@ obj-y += early_me.o
 obj-y += lpc.o
 obj-y += model_206ax.o
 obj-y += northbridge.o
+ifndef CONFIG_SPL_BUILD
 obj-y += sata.o
+endif
 obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o
 endif
 obj-y += bd82x6x.o
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 43/62] x86: ivybridge: Provide a dummy SDRAM init for 64-bit

[Simon Glass]

We don't support SDRAM init in 64-bit mode since it is essentially
impossible to get into that mode before SDRAM set up. Provide dummy functions
for now. At some point we will need to pass the SDRAM parameters through from
SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Put dummy misc_init_r() and print_cpuinfo() functions into cpu.c
- Drop duplicate comment line in header

Changes in v2: None

 arch/x86/cpu/ivybridge/Makefile    |  3 +++
 arch/x86/cpu/ivybridge/sdram_nop.c | 18 ++++++++++++++++++
 arch/x86/cpu/x86_64/cpu.c          | 10 ++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 1a526c8f0f5..25fbd599db0 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -16,5 +16,8 @@ ifndef CONFIG_SPL_BUILD
 obj-y += sata.o
 endif
 obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o
+ifndef CONFIG_$(SPL_)X86_32BIT_INIT
+obj-y += sdram_nop.o
+endif
 endif
 obj-y += bd82x6x.o
diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c
new file mode 100644
index 00000000000..bd1189e4471
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/sdram_nop.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = 1ULL << 31;
+	gd->bd->bi_dram[0].start = 0;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 36272296e63..77cbb567c45 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -59,3 +59,13 @@ int x86_mp_init(void)
 	/* Not implemented */
 	return 0;
 }
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	return 0;
+}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 44/62] x86: Don't try to run the VGA BIOS in 64-bit mode

[Simon Glass]

This is not supported, so disable it for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/Makefile | 2 ++
 drivers/pci/pci_rom.c | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 67117c36e83..f737b7ecc2e 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -5,9 +5,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifndef CONFIG_X86_64
 obj-y += bios.o
 obj-y += bios_asm.o
 obj-y += bios_interrupts.o
+endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cmd_boot.o
 obj-$(CONFIG_SEABIOS) += coreboot_table.o
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index cd083f7dde8..57204c4f3f1 100644
--- a/drivers/pci/pci_rom.c
+++ b/drivers/pci/pci_rom.c
@@ -334,7 +334,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
 			goto err;
 #endif
 	} else {
-#ifdef CONFIG_X86
+#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT)
 		bios_set_interrupt_handler(0x15, int15_handler);
 
 		bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 45/62] x86: Don't build call64 and setjmp on 64-bit

[Simon Glass]

These are currently not supported. Calling 64-bit code from 64-bit U-Boot is
much simpler, so this code is not needed. setjmp() is not yet implemented for
64-bit.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Add a TODO indicating that booting 32- and 64-bit kernels should be supported

Changes in v2: None

 arch/x86/cpu/Makefile | 6 +++++-
 arch/x86/lib/bootm.c  | 7 +++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f89ff047fa..f0135a759e9 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -14,7 +14,11 @@ else
 extra-y	= start.o
 endif
 extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
-obj-y	+= cpu.o cpu_x86.o call64.o setjmp.o
+ifndef CONFIG_$(SPL_)X86_64
+obj-y	+= call64.o setjmp.o
+endif
+
+obj-y	+= cpu.o cpu_x86.o
 
 AFLAGS_REMOVE_call32.o := -mregparm=3 \
 	$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index e5e63f6888e..3c3d9e1e800 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -155,7 +155,14 @@ int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit)
 			puts("Cannot boot 64-bit kernel on 32-bit machine\n");
 			return -EFAULT;
 		}
+		/* At present 64-bit U-Boot does not support booting a
+		 * kernel.
+		 * TODO(sjg at chromium.org): Support booting both 32-bit and
+		 * 64-bit kernels from 64-bit U-Boot.
+		 */
+#if !CONFIG_IS_ENABLED(X86_64)
 		return cpu_jump_to_64bit(setup_base, load_address);
+#endif
 	} else {
 		/*
 		* Set %ebx, %ebp, and %edi to 0, %esi to point to the
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 46/62] x86: Don't build cpu files which are not supported on 64-bit

[Simon Glass]

Some files cannot be built with 64-bit and mostly don't make sense in that
context. Disable them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/Makefile | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index f0135a759e9..6889df34c45 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -20,11 +20,13 @@ endif
 
 obj-y	+= cpu.o cpu_x86.o
 
+ifndef CONFIG_$(SPL_)X86_64
 AFLAGS_REMOVE_call32.o := -mregparm=3 \
 	$(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32)
 AFLAGS_call32.o := -fpic -fshort-wchar
 
 extra-y += call32.o
+endif
 
 obj-y += intel_common/
 obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
@@ -35,11 +37,16 @@ obj-$(CONFIG_QEMU) += qemu/
 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
 obj-$(CONFIG_INTEL_QUARK) += quark/
 obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
-obj-y += irq.o lapic.o ioapic.o
+obj-y += lapic.o ioapic.o
+ifndef CONFIG_$(SPL_)X86_64
+obj-y += irq.o
 obj-$(CONFIG_SMP) += mp_init.o
+endif
 obj-y += mtrr.o
 obj-$(CONFIG_PCI) += pci.o
+ifndef CONFIG_$(SPL_)X86_64
 obj-$(CONFIG_SMP) += sipi_vector.o
+endif
 obj-y += turbo.o
 
 ifeq ($(CONFIG_$(SPL_)X86_64),y)
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 47/62] x86: Don't build 32-bit efi files on x86_64

[Simon Glass]

These cannot be built in this mode, so drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f737b7ecc2e..05e212f9bf3 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -48,7 +48,9 @@ OBJCOPYFLAGS := --prefix-symbols=__normal_
 $(obj)/lib.a: $(NORMAL_LIBGCC) FORCE
 	$(call if_changed,objcopy)
 
+ifeq ($(CONFIG_$(SPL_)X86_64),)
 obj-$(CONFIG_EFI_APP) += crt0_ia32_efi.o reloc_ia32_efi.o
+endif
 
 ifneq ($(CONFIG_EFI_STUB),)
 
@@ -68,5 +70,7 @@ extra-$(CONFIG_EFI_STUB_64BIT) += crt0_x86_64_efi.o reloc_x86_64_efi.o
 endif
 
 ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
+ifeq ($(CONFIG_$(SPL_)X86_64),)
 extra-y += $(EFI_CRT0) $(EFI_RELOC)
 endif
+endif
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 48/62] x86: Don't try to boot Linux from SPL

[Simon Glass]

Booting into linux from 64-bit U-Boot is not yet supported. Avoid bringing
in the bootm code until it is implemented.

Of course 32-bit U-Boot still supports booting into both 32- and 64-bit
kernels.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 05e212f9bf3..1c2c0851790 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,7 +10,9 @@ obj-y += bios.o
 obj-y += bios_asm.o
 obj-y += bios_interrupts.o
 endif
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
+endif
 obj-y	+= cmd_boot.o
 obj-$(CONFIG_SEABIOS) += coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
@@ -37,7 +39,9 @@ ifndef CONFIG_QEMU
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CMD_ZBOOT)	+= zimage.o
+endif
 obj-$(CONFIG_HAVE_FSP) += fsp/
 obj-$(CONFIG_SPL_BUILD) += spl.o
 
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 49/62] x86: Drop interrupt support in 64-bit mode

[Simon Glass]

This is not currently supported, so drop the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/interrupts.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/lib/interrupts.c b/arch/x86/lib/interrupts.c
index dd084026655..d3ae6d9694a 100644
--- a/arch/x86/lib/interrupts.c
+++ b/arch/x86/lib/interrupts.c
@@ -33,6 +33,8 @@
 #include <common.h>
 #include <asm/interrupt.h>
 
+#if !CONFIG_IS_ENABLED(X86_64)
+
 struct irq_action {
 	interrupt_handler_t *handler;
 	void *arg;
@@ -118,10 +120,12 @@ void do_irq(int hw_irq)
 		}
 	}
 }
+#endif
 
 #if defined(CONFIG_CMD_IRQ)
 int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
+#if !CONFIG_IS_ENABLED(X86_64)
 	int irq;
 
 	printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
@@ -139,6 +143,7 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 					irq_handlers[irq].count);
 		}
 	}
+#endif
 
 	return 0;
 }
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 50/62] x86: Support jumping from SPL to U-Boot

[Simon Glass]

Add a rough function to handle jumping from 32-bit SPL to 64-bit U-Boot.
This still needs work to clean it up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/call64.S      |  3 +++
 arch/x86/cpu/i386/cpu.c    | 65 ++++++++++++++++++++++++++++++++++++++++++++++
 arch/x86/include/asm/cpu.h |  9 +++++++
 3 files changed, 77 insertions(+)

diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S
index 08dc473d6af..970c4615083 100644
--- a/arch/x86/cpu/call64.S
+++ b/arch/x86/cpu/call64.S
@@ -81,6 +81,9 @@ lret_target:
 	jmp	*%eax			/* Jump to the 64-bit target */
 
 	.data
+	.align	16
+	.globl	gdt64
+gdt64:
 gdt:
 	.word	gdt_end - gdt - 1
 	.long	gdt			/* Fixed up by code above */
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 09a5b919e07..ddbf3673fbd 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -503,6 +503,71 @@ int cpu_jump_to_64bit(ulong setup_base, ulong target)
 	return -EFAULT;
 }
 
+/*
+ * Jump from SPL to U-Boot
+ *
+ * This function is work-in-progress with many issues to resolve.
+ *
+ * It works by setting up several regions:
+ *   ptr      - a place to put the code that jumps into 64-bit mode
+ *   gdt      - a place to put the global descriptor table
+ *   pgtable  - a place to put the page tables
+ *
+ * The cpu_call64() code is copied from ROM and then manually patched so that
+ * it has the correct GDT address in RAM. U-Boot is copied from ROM into
+ * its pre-relocation address. Then we jump to the cpu_call64() code in RAM,
+ * which changes to 64-bit mode and starts U-Boot.
+ */
+int cpu_jump_to_64bit_uboot(ulong target)
+{
+	typedef void (*func_t)(ulong pgtable, ulong setup_base, ulong target);
+	void target64(void);
+	uint32_t *pgtable;
+	func_t func;
+
+	/* TODO(sjg at chromium.org): Find a better place for this */
+	pgtable = (uint32_t *)0x1000000;
+	if (!pgtable)
+		return -ENOMEM;
+
+	build_pagetable(pgtable);
+
+	/* TODO(sjg at chromium.org): Find a better place for this */
+	char *ptr = (char *)0x3000000;
+	char *gdt = (char *)0x3100000;
+
+	extern char gdt64[];
+
+	memcpy(ptr, cpu_call64, 0x1000);
+	memcpy(gdt, gdt64, 0x100);
+
+	/*
+	 * TODO(sjg at chromium.org): This manually inserts the pointers into
+	 * the code. Tidy this up to avoid this.
+	 */
+	func = (func_t)ptr;
+	ulong ofs = (ulong)cpu_call64 - (ulong)ptr;
+	*(ulong *)(ptr + 7) = (ulong)gdt;
+	*(ulong *)(ptr + 0xc) = (ulong)gdt + 2;
+	*(ulong *)(ptr + 0x13) = (ulong)gdt;
+	*(ulong *)(ptr + 0x117 - 0xd4) -= ofs;
+
+	/*
+	 * Copy U-Boot from ROM
+	 * TODO(sjg at chromium.org): Figure out a way to get the text base
+	 * correctly here, and in the device-tree binman definition.
+	 *
+	 * Also consider using FIT so we get the correct image length and
+	 * parameters.
+	 */
+	memcpy((char *)target, (char *)0xfff00000, 0x100000);
+
+	/* Jump to U-Boot */
+	func((ulong)pgtable, 0, (ulong)target);
+
+	return -EFAULT;
+}
+
 #ifdef CONFIG_SMP
 static int enable_smis(struct udevice *cpu, void *unused)
 {
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index b408515582c..c651f2f5945 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -264,6 +264,15 @@ void cpu_call32(ulong code_seg32, ulong target, ulong table);
 int cpu_jump_to_64bit(ulong setup_base, ulong target);
 
 /**
+ * cpu_jump_to_64bit_uboot() - special function to jump from SPL to U-Boot
+ *
+ * This handles calling from 32-bit SPL to 64-bit U-Boot.
+ *
+ * @target:	Address of U-Boot in RAM
+ */
+int cpu_jump_to_64bit_uboot(ulong target);
+
+/**
  * cpu_get_family_model() - Get the family and model for the CPU
  *
  * @return the CPU ID masked with 0x0fff0ff0
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 51/62] x86: Move pirq_routing_table to global_data

[Simon Glass]

To avoid using BSS in SPL before SDRAM is set up, move this field to
global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/irq.c                 | 12 +++++-------
 arch/x86/include/asm/global_data.h |  1 +
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index e3e928bb79b..442d373e095 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -17,8 +17,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct irq_routing_table *pirq_routing_table;
-
 bool pirq_check_irq_routed(struct udevice *dev, int link, u8 irq)
 {
 	struct irq_router *priv = dev_get_priv(dev);
@@ -219,7 +217,7 @@ static int create_pirq_routing_table(struct udevice *dev)
 	/* Fix up the table checksum */
 	rt->checksum = table_compute_checksum(rt, rt->size);
 
-	pirq_routing_table = rt;
+	gd->arch.pirq_routing_table = rt;
 
 	return 0;
 }
@@ -250,8 +248,8 @@ int irq_router_common_init(struct udevice *dev)
 		return ret;
 	}
 	/* Route PIRQ */
-	pirq_route_irqs(dev, pirq_routing_table->slots,
-			get_irq_slot_count(pirq_routing_table));
+	pirq_route_irqs(dev, gd->arch.pirq_routing_table->slots,
+			get_irq_slot_count(gd->arch.pirq_routing_table));
 
 	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
 		irq_enable_sci(dev);
@@ -266,10 +264,10 @@ int irq_router_probe(struct udevice *dev)
 
 ulong write_pirq_routing_table(ulong addr)
 {
-	if (!pirq_routing_table)
+	if (!gd->arch.pirq_routing_table)
 		return addr;
 
-	return copy_pirq_routing_table(addr, pirq_routing_table);
+	return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
 }
 
 static const struct udevice_id irq_router_ids[] = {
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 34e19efd145..43a59a3b0c9 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,7 @@ struct arch_global_data {
 	char *mrc_output;
 	unsigned int mrc_output_len;
 	ulong table;			/* Table pointer from previous loader */
+	struct irq_routing_table *pirq_routing_table;
 #ifdef CONFIG_SEABIOS
 	u32 high_table_ptr;
 	u32 high_table_limit;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 52/62] x86: Move turbo_state to global_data

[Simon Glass]

To avoid using BSS in SPL before SDRAM is set up, move this field to
global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/turbo.c               | 8 ++++----
 arch/x86/include/asm/global_data.h | 1 +
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c
index 254d0de0e4b..bbd255efc0a 100644
--- a/arch/x86/cpu/turbo.c
+++ b/arch/x86/cpu/turbo.c
@@ -12,6 +12,8 @@
 #include <asm/processor.h>
 #include <asm/turbo.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
 static inline int get_global_turbo_state(void)
 {
@@ -22,16 +24,14 @@ static inline void set_global_turbo_state(int state)
 {
 }
 #else
-static int g_turbo_state = TURBO_UNKNOWN;
-
 static inline int get_global_turbo_state(void)
 {
-	return g_turbo_state;
+	return gd->arch.turbo_state;
 }
 
 static inline void set_global_turbo_state(int state)
 {
-	g_turbo_state = state;
+	gd->arch.turbo_state = state;
 }
 #endif
 
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 43a59a3b0c9..4570bc7a4ad 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,7 @@ struct arch_global_data {
 	char *mrc_output;
 	unsigned int mrc_output_len;
 	ulong table;			/* Table pointer from previous loader */
+	int turbo_state;		/* Current turbo state */
 	struct irq_routing_table *pirq_routing_table;
 #ifdef CONFIG_SEABIOS
 	u32 high_table_ptr;
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 53/62] x86: Change irq_already_routed to a local variable

[Simon Glass]

This avoids using BSS before SDRAM is set up in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/lib/pirq_routing.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index c98526d6aa8..5df3cab6c9c 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -11,9 +11,8 @@
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
 
-static bool irq_already_routed[16];
-
-static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap)
+static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap,
+				 bool irq_already_routed[])
 {
 	int i, link;
 	u8 irq = 0;
@@ -55,9 +54,11 @@ void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num)
 {
 	unsigned char irq_slot[MAX_INTX_ENTRIES];
 	unsigned char pirq[CONFIG_MAX_PIRQ_LINKS];
+	bool irq_already_routed[16];
 	int i, intx;
 
 	memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS);
+	memset(irq_already_routed, '\0', sizeof(irq_already_routed));
 
 	/* Set PCI IRQs */
 	for (i = 0; i < num; i++) {
@@ -83,7 +84,8 @@ void pirq_route_irqs(struct udevice *dev, struct irq_info *irq, int num)
 
 			/* yet not routed */
 			if (!pirq[link]) {
-				irq = pirq_get_next_free_irq(dev, pirq, bitmap);
+				irq = pirq_get_next_free_irq(dev, pirq, bitmap,
+						irq_already_routed);
 				pirq[link] = irq;
 			} else {
 				irq = pirq[link];
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 54/62] x86: Move call64 to the i386 directory

[Simon Glass]

This code is only used in 32-bit mode. Move it so that it does not get
built with 64-bit U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/Makefile            | 2 +-
 arch/x86/cpu/i386/Makefile       | 1 +
 arch/x86/cpu/{ => i386}/call64.S | 0
 3 files changed, 2 insertions(+), 1 deletion(-)
 rename arch/x86/cpu/{ => i386}/call64.S (100%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 6889df34c45..2fda32d29f4 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -15,7 +15,7 @@ extra-y	= start.o
 endif
 extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
 ifndef CONFIG_$(SPL_)X86_64
-obj-y	+= call64.o setjmp.o
+obj-y	+= setjmp.o
 endif
 
 obj-y	+= cpu.o cpu_x86.o
diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile
index d3364955d8e..2547bbaa635 100644
--- a/arch/x86/cpu/i386/Makefile
+++ b/arch/x86/cpu/i386/Makefile
@@ -3,5 +3,6 @@
 # Written by Simon Glass <sjg@chromium.org>
 #
 
+obj-y += call64.o
 obj-y += cpu.o
 obj-y += interrupt.o
diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/i386/call64.S
similarity index 100%
rename from arch/x86/cpu/call64.S
rename to arch/x86/cpu/i386/call64.S
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 55/62] x86: Move setjmp to the i386 directory

[Simon Glass]

This code is only used in 32-bit mode. Move it so that it does not get
built with 64-bit U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/Makefile            | 3 ---
 arch/x86/cpu/i386/Makefile       | 1 +
 arch/x86/cpu/{ => i386}/setjmp.S | 0
 3 files changed, 1 insertion(+), 3 deletions(-)
 rename arch/x86/cpu/{ => i386}/setjmp.S (100%)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 2fda32d29f4..45f95ab0349 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -14,9 +14,6 @@ else
 extra-y	= start.o
 endif
 extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o
-ifndef CONFIG_$(SPL_)X86_64
-obj-y	+= setjmp.o
-endif
 
 obj-y	+= cpu.o cpu_x86.o
 
diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile
index 2547bbaa635..0c47252610d 100644
--- a/arch/x86/cpu/i386/Makefile
+++ b/arch/x86/cpu/i386/Makefile
@@ -6,3 +6,4 @@
 obj-y += call64.o
 obj-y += cpu.o
 obj-y += interrupt.o
+obj-y += setjmp.o
diff --git a/arch/x86/cpu/setjmp.S b/arch/x86/cpu/i386/setjmp.S
similarity index 100%
rename from arch/x86/cpu/setjmp.S
rename to arch/x86/cpu/i386/setjmp.S
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 56/62] x86: Add a dummy setjmp implementation for x86_64

[Simon Glass]

We don't have the code for this yet. Add a dummy version for now, so that
EFI builds correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2:
- Add the 'val' parameter to longjmp()

 arch/x86/cpu/x86_64/Makefile |  2 +-
 arch/x86/cpu/x86_64/setjmp.c | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/x86_64/setjmp.c

diff --git a/arch/x86/cpu/x86_64/Makefile b/arch/x86/cpu/x86_64/Makefile
index 4b063862e17..400f0ffe397 100644
--- a/arch/x86/cpu/x86_64/Makefile
+++ b/arch/x86/cpu/x86_64/Makefile
@@ -3,4 +3,4 @@
 # Written by Simon Glass <sjg@chromium.org>
 #
 
-obj-y += cpu.o interrupts.o
+obj-y += cpu.o interrupts.o setjmp.o
diff --git a/arch/x86/cpu/x86_64/setjmp.c b/arch/x86/cpu/x86_64/setjmp.c
new file mode 100644
index 00000000000..25f8d2804be
--- /dev/null
+++ b/arch/x86/cpu/x86_64/setjmp.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/setjmp.h>
+
+int setjmp(struct jmp_buf_data *jmp_buf)
+{
+	printf("WARNING: setjmp() is not supported\n");
+
+	return 0;
+}
+
+void longjmp(struct jmp_buf_data *jmp_buf, int val)
+{
+	printf("WARNING: longjmp() is not supported\n");
+}
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 57/62] x86: link: Add a text base for 64-bit U-Boot

[Simon Glass]

Set up the 64-bit U-Boot text base if building for that target.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 board/google/chromebook_link/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index fa12f338de5..5c57945d77a 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -13,7 +13,8 @@ config SYS_CONFIG_NAME
 	default "chromebook_link"
 
 config SYS_TEXT_BASE
-	default 0xfff00000
+	default 0xfff00000 if !SUPPORT_SPL
+	default 0x10000000 if SUPPORT_SPL
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 58/62] x86: link: Add SPL declarations to the binman image

[Simon Glass]

When building for 64-bit we need to put an SPL binary into the image. Update
the binman image description to reflect this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 31f0b1aa10d..69c1c1d4986 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -21,9 +21,22 @@
 		intel-me {
 		};
 #endif
+#ifdef CONFIG_SPL
+		u-boot-spl-with-ucode-ptr {
+			pos = <CONFIG_SPL_TEXT_BASE>;
+		};
+
+		u-boot-dtb-with-ucode2 {
+			type = "u-boot-dtb-with-ucode";
+		};
+		u-boot {
+			pos = <0xfff00000>;
+		};
+#else
 		u-boot-with-ucode-ptr {
 			pos = <CONFIG_SYS_TEXT_BASE>;
 		};
+#endif
 		u-boot-dtb-with-ucode {
 		};
 		u-boot-ucode {
@@ -57,9 +70,15 @@
 			pos = <CONFIG_X86_REFCODE_ADDR>;
 		};
 #endif
+#ifdef CONFIG_SPL
+		x86-start16-spl {
+			pos = <CONFIG_SYS_X86_START16>;
+		};
+#else
 		x86-start16 {
 			pos = <CONFIG_SYS_X86_START16>;
 		};
+#endif
 	};
 };
 #endif
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 59/62] x86: link: Set up device tree for SPL

[Simon Glass]

Add the correct pre-relocation tag so that the required device tree nodes
are present in the SPL device tree.

On x86 it doesn't make a lot of sense to have a separate SPL device tree.
Since everything is in the same ROM we might as well just use the main
device tree in both SPL and U-Boot proper. But we haven't implemented that,
so this is a good first step.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3:
- Expand pre-reloc malloc() size in this patch to prevent boot failure

Changes in v2: None

 arch/x86/dts/chromebook_link.dts  | 15 ++++++++++++++-
 configs/chromebook_link_defconfig |  4 ++--
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index b93234046e0..fab919a3589 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -26,12 +26,14 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
 
 		cpu at 0 {
 			device_type = "cpu";
 			compatible = "intel,core-gen3";
 			reg = <0>;
 			intel,apic-id = <0>;
+			u-boot,dm-pre-reloc;
 		};
 
 		cpu at 1 {
@@ -39,6 +41,7 @@
 			compatible = "intel,core-gen3";
 			reg = <1>;
 			intel,apic-id = <1>;
+			u-boot,dm-pre-reloc;
 		};
 
 		cpu at 2 {
@@ -46,6 +49,7 @@
 			compatible = "intel,core-gen3";
 			reg = <2>;
 			intel,apic-id = <2>;
+			u-boot,dm-pre-reloc;
 		};
 
 		cpu at 3 {
@@ -53,6 +57,7 @@
 			compatible = "intel,core-gen3";
 			reg = <3>;
 			intel,apic-id = <3>;
+			u-boot,dm-pre-reloc;
 		};
 
 	};
@@ -229,14 +234,16 @@
 
 		northbridge at 0,0 {
 			reg = <0x00000000 0 0 0 0>;
+			u-boot,dm-pre-reloc;
 			compatible = "intel,bd82x6x-northbridge";
 			board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
 					<&gpio_b 11 0>, <&gpio_a 10 0>;
-			u-boot,dm-pre-reloc;
 			spd {
+				u-boot,dm-pre-reloc;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				elpida_4Gb_1600_x16 {
+					u-boot,dm-pre-reloc;
 					reg = <0>;
 					data = [92 10 0b 03 04 19 02 02
 						03 52 01 08 0a 00 fe 00
@@ -272,6 +279,7 @@
 						00 00 00 00 00 00 00 00];
 				};
 				samsung_4Gb_1600_1.35v_x16 {
+					u-boot,dm-pre-reloc;
 					reg = <1>;
 					data = [92 11 0b 03 04 19 02 02
 						03 11 01 08 0a 00 fe 00
@@ -391,9 +399,11 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
+				u-boot,dm-pre-reloc;
 				spi-flash at 0 {
 					#size-cells = <1>;
 					#address-cells = <1>;
+					u-boot,dm-pre-reloc;
 					reg = <0>;
 					compatible = "winbond,w25q64",
 							"spi-flash";
@@ -401,6 +411,7 @@
 					rw-mrc-cache {
 						label = "rw-mrc-cache";
 						reg = <0x003e0000 0x00010000>;
+						u-boot,dm-pre-reloc;
 					};
 				};
 			};
@@ -478,7 +489,9 @@
 	};
 
 	microcode {
+		u-boot,dm-pre-reloc;
 		update at 0 {
+			u-boot,dm-pre-reloc;
 #include "microcode/m12306a9_0000001b.dtsi"
 		};
 	};
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 84077312c37..bf3795f13ce 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -1,5 +1,5 @@
 CONFIG_X86=y
-CONFIG_SYS_MALLOC_F_LEN=0x1800
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_VENDOR_GOOGLE=y
 CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
 CONFIG_TARGET_CHROMEBOOK_LINK=y
@@ -57,8 +57,8 @@ CONFIG_TPM_TIS_LPC=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_USB_KEYBOARD=y
 CONFIG_DM_VIDEO=y
+CONFIG_USB_KEYBOARD=y
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 60/62] x86: link: Add build options for SPL

[Simon Glass]

If SPL is used we want to use the generic SPL framework and boot from SPI
via a board-specific means. Add these options to the board config file.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Remove duplicate CONFIG_VIDEO_IVYBRIDGE_IGD in defconfig file
- Drop the unnecessary defconfig changes for chromebook_link

Changes in v2: None

 include/configs/chromebook_link.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index f2d798a52f0..b116a27869a 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -19,4 +19,13 @@
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x003f8000
 
+#define CONFIG_SPL_FRAMEWORK
+
+#define CONFIG_SPL_TEXT_BASE		0xfffd0000
+
+#define BOOT_DEVICE_SPI			10
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#define BOOT_DEVICE_BOARD		11
+
 #endif	/* __CONFIG_H */
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 61/62] x86: Update compile/link flags to support 64-bit U-Boot

[Simon Glass]

Update config.mk settings to support both 32-bit and 64-bit U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v3: None
Changes in v2: None

 arch/x86/config.mk     | 30 ++++++++++++++++++++++++++++--
 arch/x86/cpu/config.mk |  2 --
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 1697dca47fb..74b87ceac54 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -15,11 +15,25 @@ PF_CPPFLAGS_X86   := $(call cc-option, -fno-toplevel-reorder, \
 
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
 PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+
+ifdef CONFIG_SPL_BUILD
+IS_32BIT := y
+else
+ifndef CONFIG_X86_64
+IS_32BIT := y
+endif
+endif
+
+ifeq ($(IS_32BIT),y)
 PLATFORM_CPPFLAGS += -march=i386 -m32
+else
+PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common
+endif
 
 PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
 
-PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions -m elf_i386
+PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions
+PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)
 
 LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
@@ -31,7 +45,9 @@ LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined
 OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \
 	-j .rel -j .rela -j .reloc
 
+ifeq ($(IS_32BIT),y)
 CFLAGS_NON_EFI := -mregparm=3
+endif
 CFLAGS_EFI := -fpic -fshort-wchar
 
 ifeq ($(CONFIG_EFI_STUB_64BIT),)
@@ -62,8 +78,18 @@ else
 
 PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI)
 PLATFORM_LDFLAGS += --emit-relocs
-LDFLAGS_FINAL += --gc-sections -pie
+LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie)
+
+endif
 
+ifdef CONFIG_X86_64
+ifndef CONFIG_SPL_BUILD
+PLATFORM_CPPFLAGS += -D__x86_64__
+else
+PLATFORM_CPPFLAGS += -D__I386__
+endif
+else
+PLATFORM_CPPFLAGS += -D__I386__
 endif
 
 ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk
index 4c99a35621d..b519f433acf 100644
--- a/arch/x86/cpu/config.mk
+++ b/arch/x86/cpu/config.mk
@@ -7,8 +7,6 @@
 
 CROSS_COMPILE ?= i386-linux-
 
-PLATFORM_CPPFLAGS += -D__I386__
-
 # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
 LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START)
 LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE)
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 62/62] x86: link: Add a config for 64-bit U-Boot

[Simon Glass]

Add a new link config which uses 64-bit U-Boot. This is not fully
functional but is it a start. Missing features:

- SDRAM sizing
- Booting linux
- EFI support
- SCSI device init
(and others)

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v3:
- Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application'
- Drop patch 'Mention the MRC region in the README'
- Drop patch 'x86: link: Add build options for SPL'
- Drop unnecessary defconfig options for chromebook_link64
- Avoid including helloworld.efi in the 64-bit U-Boot

Changes in v2:
- Drop patch 'video: Use ulong for video frame buffer address'
- Add a new 64-bit link config instead of changing the existing one

 board/google/Kconfig                     |  7 +++
 board/google/chromebook_link/Kconfig     |  2 +-
 board/google/chromebook_link/MAINTAINERS |  7 +++
 configs/chromebook_link64_defconfig      | 89 ++++++++++++++++++++++++++++++++
 4 files changed, 104 insertions(+), 1 deletion(-)
 create mode 100644 configs/chromebook_link64_defconfig

diff --git a/board/google/Kconfig b/board/google/Kconfig
index 7ba73a2461d..e56c026ef6d 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -22,6 +22,13 @@ config TARGET_CHROMEBOOK_LINK
 	  and it provides a 2560x1700 high resolution touch-enabled LCD
 	  display.
 
+config TARGET_CHROMEBOOK_LINK64
+	bool "Chromebook link 64-bit"
+	help
+	  This is the Chromebook Pixel released in 2013. With this config
+	  U-Boot is built as a 64-bit binary. This allows testing while this
+	  feature is being completed.
+
 config TARGET_CHROMEBOX_PANTHER
 	bool "Chromebox panther (not available)"
 	select n
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 5c57945d77a..8999b582943 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CHROMEBOOK_LINK
+if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
 
 config SYS_BOARD
 	default "chromebook_link"
diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
index bc253a2ba7b..e7aef53390c 100644
--- a/board/google/chromebook_link/MAINTAINERS
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/google/chromebook_link/
 F:	include/configs/chromebook_link.h
 F:	configs/chromebook_link_defconfig
+
+CHROMEBOOK LINK 64-bit BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_link/
+F:	include/configs/chromebook_link.h
+F:	configs/chromebook_link64_defconfig
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
new file mode 100644
index 00000000000..dd8175ec767
--- /dev/null
+++ b/configs/chromebook_link64_defconfig
@@ -0,0 +1,89 @@
+CONFIG_X86=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_X86_RUN_64BIT=y
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
+CONFIG_TARGET_CHROMEBOOK_LINK=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_HAVE_MRC=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_CPU_SUPPORT=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_PCI_SUPPORT=y
+CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_TIMER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_INTEL=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_VIDEO_IVYBRIDGE_IGD=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_USE_PRIVATE_LIBGCC=y
+CONFIG_TPM=y
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
-- 
2.11.0.483.g087da7b7c-goog

[U-Boot] [PATCH v3 01/62] console: Don't enable CONFIG-CONSOLE_MUX, etc. in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable
> for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these
> options will be inactive in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - update iomux.c and usb_kbd.c also
>
> Changes in v2: None
>
>  common/console.c | 30 +++++++++++++++---------------
>  common/iomux.c   |  4 ++--
>  common/usb_kbd.c |  6 +++---
>  3 files changed, 20 insertions(+), 20 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 02/62] spl: spi: Add a debug message if loading fails

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> This currently fails silently. Add a debug message to aid debugging.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Show the error value in spl_spi_load_image()
>
>  common/spl/spl_spi.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 03/62] spl: Makefile: Define SPL_ earlier

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> This Makefile variable can be used in the architecture's main Makefile but
> at present it is not set up until later. Set it just before this Makefile is
> included.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  scripts/Makefile.spl | 6 ++++++
>  1 file changed, 6 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 04/62] spl: Allow CPU drivers to be used in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new Kconfig option to allow CPU drivers to be used in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  common/spl/Kconfig | 10 ++++++++++
>  drivers/Makefile   |  1 +
>  2 files changed, 11 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 05/62] spl: Allow PCI drivers to be used in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new Kconfig option to allow PCI drivers to be used in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +++++++++
>  drivers/Makefile   | 1 +
>  2 files changed, 10 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 06/62] spl: Allow RTC drivers to be used in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new Kconfig option to allow RTC drivers to be used in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  common/spl/Kconfig | 10 ++++++++++
>  drivers/Makefile   |  1 +
>  2 files changed, 11 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 07/62] spl: Allow timer drivers to be used in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new Kconfig option to allow timer drivers to be used in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +++++++++
>  drivers/Makefile   | 1 +
>  2 files changed, 10 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 08/62] spl: Allow PCH drivers to be used in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add an option for building Platorm Controller Hub drivers in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +++++++++
>  drivers/Makefile   | 1 +
>  2 files changed, 10 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 09/62] spl: Don't create a BSS padding when it is separate

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> When BSS does not immediate follow the SPL image we don't need padding
> before the device tree. Remove it in this case.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  scripts/Makefile.spl | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 10/62] x86: Use unsigned long for address in table generation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> We should use unsigned long rather than u32 for addresses. Update this so
> that the table-generation code builds correctly on 64-bit machines.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Move table-related changes from a later patch
> - Rebase to mainline
> - Drop the write_smbios_table_wrapper() function
>
>  arch/x86/cpu/irq.c                |  2 +-
>  arch/x86/include/asm/acpi_table.h |  2 +-
>  arch/x86/include/asm/mpspec.h     |  2 +-
>  arch/x86/include/asm/sfi.h        |  2 +-
>  arch/x86/include/asm/tables.h     |  2 +-
>  arch/x86/lib/acpi_table.c         |  4 ++--
>  arch/x86/lib/mpspec.c             |  2 +-
>  arch/x86/lib/sfi.c                |  6 +++---
>  arch/x86/lib/tables.c             | 11 ++---------
>  arch/x86/lib/zimage.c             |  2 +-
>  drivers/misc/qfw.c                |  4 ++--
>  include/smbios.h                  |  4 ++--
>  lib/smbios.c                      | 22 +++++++++++-----------
>  13 files changed, 29 insertions(+), 36 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 11/62] x86: Update mpspec to build on 64-bit machines

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> At present this uses u32 to store an address. We should use unsigned long
> and avoid special types in function return values and parameters unless
> necessary. This makes the code more portable.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Drop WIP tag as this patch is actually needed
>
> Changes in v2: None
>
>  arch/x86/include/asm/mpspec.h |  8 ++++----
>  arch/x86/lib/mpspec.c         | 12 ++++++------
>  2 files changed, 10 insertions(+), 10 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 12/62] x86: ivybridge: Declare global data where it is used

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Some files are missing this declaration. Add it to avoid build errors when
> we actually need the declaration.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Drop change to gma.c
>
>  arch/x86/cpu/ivybridge/bd82x6x.c     | 2 ++
>  arch/x86/cpu/ivybridge/lpc.c         | 2 ++
>  arch/x86/cpu/ivybridge/model_206ax.c | 2 ++
>  arch/x86/cpu/ivybridge/northbridge.c | 2 ++
>  drivers/video/ivybridge_igd.c        | 2 ++
>  5 files changed, 10 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 13/62] x86: ivybridge: Add more debugging for failures

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add various debug() messages in places where errors occur. This aids with
> debugging.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Output error code values in debug() statements
>
>  arch/x86/cpu/ivybridge/cpu.c   |  4 +++-
>  arch/x86/cpu/ivybridge/sdram.c | 37 ++++++++++++++++++++++++++++---------
>  2 files changed, 31 insertions(+), 10 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 14/62] x86: ivybridge: Fix types for 64-bit compilation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Fix a few types that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Fix cast in bd82x6x_video_probe() also
>
>  arch/x86/cpu/ivybridge/sata.c | 4 ++--
>  drivers/video/ivybridge_igd.c | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 15/62] x86: dts: Mark serial as needed before relocation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> We almost always need the serial port before relocation, so mark it as such.
> This will ensure that it appears in the device tree for SPL, if used.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/serial.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 16/62] x86: fsp: Fix cast for 64-bit compilation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Fix a cast in get_next_hob() that causes warnings on 64-bit machines.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Fix cast in get_guid_hob_data() also
>
>  arch/x86/include/asm/fsp/fsp_hob.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 17/62] x86: lib: Fix types and casts for 64-bit compilation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Fix various compiler warnings in the x86 library code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Move table-related changes to an earlier patch
>
>  arch/x86/lib/bios.c         | 4 ++--
>  arch/x86/lib/pinctrl_ich6.c | 2 +-
>  arch/x86/lib/pirq_routing.c | 4 ++--
>  3 files changed, 5 insertions(+), 5 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 18/62] x86: Add Kconfig options to build 64-bit U-Boot

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be
> built as a 64-bit application, with SPL doing the 16/32-bit init.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Use tab instead of space in Kconfig help line
>
> Changes in v2: None
>
>  arch/x86/Kconfig | 46 ++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 19/62] x86: Kconfig: Add location options for 16/32-bit init

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If
> this is enabled, then U-Boot is the 'first' boot loader and handles execution
> from the reset vector through to U-Boot's command prompt. If it is not
> enabled then U-Boot starts at the 32-bit entry and skips most of its init,
> assuming that the previous boot loader has done this already.
>
> With the move to suport 64-bit operation, we have more cases to consider.
> The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper.
>
> Add Kconfig options which control the location of the 16-bit and the 32-bit
> init. These are not intended to be user-setting except for experimentation.
> Their values should be determined by whether 64-bit U-Boot is used.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Fix s/32-bit init/16-bit init/ and expand the comment
>
> Changes in v2: None
>
>  arch/x86/Kconfig | 40 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 20/62] x86: Use X86_16BIT_INIT instead of X86_RESET_VECTOR

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Use this new option to control the location of 16-bit init. This will allow
> us to place this in SPL if needed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  Makefile                | 7 ++++---
>  arch/x86/Makefile       | 6 ++----
>  arch/x86/cpu/Makefile   | 2 +-
>  arch/x86/cpu/u-boot.lds | 2 +-
>  4 files changed, 8 insertions(+), 9 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 23/62] x86: Add 64-bit start-up code

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are
> running from RAM and SPL has done the low-level init.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop unused headers
> - Drop unused board_debug_uart_init function
> - Use call instead of callq
>
> Changes in v2: None
>
>  arch/x86/Makefile      |  5 +++++
>  arch/x86/cpu/Makefile  |  4 ++++
>  arch/x86/cpu/start64.S | 28 ++++++++++++++++++++++++++++
>  3 files changed, 37 insertions(+)
>  create mode 100644 arch/x86/cpu/start64.S
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 25/62] board_f/r: Use static const for the init sequences

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> These tables should be declared static const. Unfortunately the table in
> board_r is updated on machines with manual relocation.
>
> Update them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Add new patch to use static const for the board_f/r init sequences
>
> Changes in v2: None
>
>  common/board_f.c | 4 ++--
>  common/board_r.c | 2 +-
>  2 files changed, 3 insertions(+), 3 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 26/62] x86: board_r: Set the global data pointer after relocation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the
> time we get to board_init_r(). The old 'gd' variable is passed in as
> parameter to board_init_r(), presumably for this situation.
>
> Assign it on 64-bit x86 so that gd points to the correct data.
>
> Options to improve this:
> - Make gd a fixed register and remove the board_init_r() parameter
> - Make all archs use this board_init_r() parameter
>
> The second has a TODO in the code. The first has a TODO in a future commit
> ('x86: Support global_data on x86_64')
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Add a TODO to board_init_r() regarding the use of the new_gd parameter
>
> Changes in v2: None
>
>  common/board_r.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 28/62] x86: Refactor relocation to prepare for 64-bit

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Move the core relocation code into a separate function so that the checking
> code can be used for 64-bit relocation also.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Mention the commit ID containing information about the need for reloc checks
> - Drop the pre-panic printf() of the relocation addresses
>
> Changes in v2: None
>
>  arch/x86/lib/relocate.c | 55 ++++++++++++++++++++++++++++---------------------
>  1 file changed, 31 insertions(+), 24 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 21/62] x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Use this new option to control the location of 32-bit init. This will allow
> us to place this in SPL if needed.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/intel_common/Makefile | 10 ++++++----
>  arch/x86/lib/init_helpers.c        |  2 +-
>  2 files changed, 7 insertions(+), 5 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 22/62] x86: ivybridge: Allow 32-bit init to move to SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Update the Makefile so that some 32-bit init can be built into SPL rather
> than U-Boot proper.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/ivybridge/Makefile | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 23/62] x86: Add 64-bit start-up code

[Bin Meng]

On Tue, Jan 17, 2017 at 10:25 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
>> Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are
>> running from RAM and SPL has done the low-level init.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Drop unused headers
>> - Drop unused board_debug_uart_init function
>> - Use call instead of callq
>>
>> Changes in v2: None
>>
>>  arch/x86/Makefile      |  5 +++++
>>  arch/x86/cpu/Makefile  |  4 ++++
>>  arch/x86/cpu/start64.S | 28 ++++++++++++++++++++++++++++
>>  3 files changed, 37 insertions(+)
>>  create mode 100644 arch/x86/cpu/start64.S
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 24/62] x86: board_f: Update init sequence for 64-bit startup

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Adjust the code so that 64-bit startup works. Since we don't need to do CAR
> changes in U-Boot proper anymore (they are done in SPL) we can simplify the
> flow and return normally from board_init_f().
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Move 'const' change into its own patch
>
> Changes in v2: None
>
>  common/board_f.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 25/62] board_f/r: Use static const for the init sequences

[Bin Meng]

On Tue, Jan 17, 2017 at 10:27 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
>> These tables should be declared static const. Unfortunately the table in
>> board_r is updated on machines with manual relocation.
>>
>> Update them.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Add new patch to use static const for the board_f/r init sequences
>>
>> Changes in v2: None
>>
>>  common/board_f.c | 4 ++--
>>  common/board_r.c | 2 +-
>>  2 files changed, 3 insertions(+), 3 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 26/62] x86: board_r: Set the global data pointer after relocation

[Bin Meng]

On Tue, Jan 17, 2017 at 10:29 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
>> Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the
>> time we get to board_init_r(). The old 'gd' variable is passed in as
>> parameter to board_init_r(), presumably for this situation.
>>
>> Assign it on 64-bit x86 so that gd points to the correct data.
>>
>> Options to improve this:
>> - Make gd a fixed register and remove the board_init_r() parameter
>> - Make all archs use this board_init_r() parameter
>>
>> The second has a TODO in the code. The first has a TODO in a future commit
>> ('x86: Support global_data on x86_64')
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Add a TODO to board_init_r() regarding the use of the new_gd parameter
>>
>> Changes in v2: None
>>
>>  common/board_r.c | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 27/62] x86: Do relocation before clearing BSS

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> The BSS region may overlap with relocations. If we clear BSS we will
> overwrite the start of the relocation area. This doesn't matter when running
> from SPI flash, since it is read-only. But when relocating 64-bit U-Boot
> from one place in RAM to another, relocation will fail because some of its
> relocations have been zeroed.
>
> To fix this, put the ELF fixup call before the BSS clearing call.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  common/board_f.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 28/62] x86: Refactor relocation to prepare for 64-bit

[Bin Meng]

On Tue, Jan 17, 2017 at 10:33 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
>> Move the core relocation code into a separate function so that the checking
>> code can be used for 64-bit relocation also.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Mention the commit ID containing information about the need for reloc checks
>> - Drop the pre-panic printf() of the relocation addresses
>>
>> Changes in v2: None
>>
>>  arch/x86/lib/relocate.c | 55 ++++++++++++++++++++++++++++---------------------
>>  1 file changed, 31 insertions(+), 24 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 29/62] x86: Add support for 64-bit relocation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed
> address and runs it. U-Boot then relocates itself to the top of RAM using
> this relocation function.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/relocate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 30/62] x86: Tidy up use of size_t in relocation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Addresses should not be cast to size_t. Use uintptr_t instead.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/relocate.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 31/62] x86: Add an SPL implementation

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping
> to it. Call the existing init routines in order to accomplish this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Update copyright year
> - Drop duplicate line in header commment
> - Add a comment about stack position to x86_spl_init()
> - Add a parameter to the use of the SPL_LOAD_IMAGE_METHOD() macro
> - Fix printf() warning in spl_board_load_image()
>
> Changes in v2: None
>
>  arch/x86/include/asm/spl.h |   8 +++
>  arch/x86/lib/Makefile      |   1 +
>  arch/x86/lib/spl.c         | 153 +++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 162 insertions(+)
>  create mode 100644 arch/x86/include/asm/spl.h
>  create mode 100644 arch/x86/lib/spl.c
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 34/62] x86: Support global_data on x86_64

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> At present this is just an ordinary variable. We may consider making it a
> fixed register in the future.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Add a TODO to look at using a fixed register for gd on x86_64
> - Expand the TODO about the necessary printch() call
> - Add a required debug_uart.h #include in this patch
>
> Changes in v2: None
>
>  arch/x86/cpu/x86_64/cpu.c          | 27 +++++++++++++++++++++++++++
>  arch/x86/include/asm/global_data.h |  7 ++++++-
>  2 files changed, 33 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 31/62] x86: Add an SPL implementation

[Bin Meng]

On Tue, Jan 17, 2017 at 11:24 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
>> SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping
>> to it. Call the existing init routines in order to accomplish this.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Update copyright year
>> - Drop duplicate line in header commment
>> - Add a comment about stack position to x86_spl_init()
>> - Add a parameter to the use of the SPL_LOAD_IMAGE_METHOD() macro
>> - Fix printf() warning in spl_board_load_image()
>>
>> Changes in v2: None
>>
>>  arch/x86/include/asm/spl.h |   8 +++
>>  arch/x86/lib/Makefile      |   1 +
>>  arch/x86/lib/spl.c         | 153 +++++++++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 162 insertions(+)
>>  create mode 100644 arch/x86/include/asm/spl.h
>>  create mode 100644 arch/x86/lib/spl.c
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Fixed the style error reported by checkpatch,

ERROR: trailing statements should be on next line
#219: FILE: arch/x86/lib/spl.c:152:
+       while (1);

and applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 32/62] x86: Move the i386 code into its own directory

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> Much of the cpu and interrupt code cannot be compiled on 64-bit x86. Move it
> into its own directory and build it only in 32-bit mode.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/Makefile                           |   6 +-
>  arch/x86/cpu/cpu.c                              | 504 ----------------------
>  arch/x86/cpu/i386/Makefile                      |   7 +
>  arch/x86/cpu/i386/cpu.c                         | 534 ++++++++++++++++++++++++
>  arch/x86/cpu/{interrupts.c => i386/interrupt.c} |   4 -
>  arch/x86/include/asm/mp.h                       |   3 +
>  6 files changed, 549 insertions(+), 509 deletions(-)
>  create mode 100644 arch/x86/cpu/i386/Makefile
>  create mode 100644 arch/x86/cpu/i386/cpu.c
>  rename arch/x86/cpu/{interrupts.c => i386/interrupt.c} (99%)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 33/62] x86: Add cpu code for x86_64

[Bin Meng]

On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
> There is not much needed at present, but set up a separate directory to put
> this code as it grows.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Drop blank line at end of arch/x86/cpu/x86_64/interrupts.c
> - Drop #include of debug_uart.h
>
> Changes in v2: None
>
>  arch/x86/cpu/Makefile            |  4 +++-
>  arch/x86/cpu/x86_64/Makefile     |  6 ++++++
>  arch/x86/cpu/x86_64/cpu.c        | 34 ++++++++++++++++++++++++++++++++++
>  arch/x86/cpu/x86_64/interrupts.c | 29 +++++++++++++++++++++++++++++
>  4 files changed, 72 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/cpu/x86_64/Makefile
>  create mode 100644 arch/x86/cpu/x86_64/cpu.c
>  create mode 100644 arch/x86/cpu/x86_64/interrupts.c
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 34/62] x86: Support global_data on x86_64

[Bin Meng]

On Tue, Jan 17, 2017 at 11:26 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:03 PM, Simon Glass <sjg@chromium.org> wrote:
>> At present this is just an ordinary variable. We may consider making it a
>> fixed register in the future.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Add a TODO to look at using a fixed register for gd on x86_64
>> - Expand the TODO about the necessary printch() call
>> - Add a required debug_uart.h #include in this patch
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/x86_64/cpu.c          | 27 +++++++++++++++++++++++++++
>>  arch/x86/include/asm/global_data.h |  7 ++++++-
>>  2 files changed, 33 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 35/62] x86: Fix up CONFIG_X86_64 check

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> When SPL and U-Boot proper have different settings for this flag, we need to
> use the correct one. Fix this up in the interrupt code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/i386/interrupt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 36/62] x86: Add a link script for 64-bit x86

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This needs a different image format from 32-bit x86, so add a new link
> script.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/config.mk     |  6 ++++
>  arch/x86/cpu/u-boot-64.lds | 76 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 82 insertions(+)
>  create mode 100644 arch/x86/cpu/u-boot-64.lds
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 37/62] x86: Add a link script for SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> If SPL is used it is always build in 32-bit mode. Add a link script to
> handle the correct placement of the sections.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/u-boot-spl.lds | 74 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
>  create mode 100644 arch/x86/cpu/u-boot-spl.lds
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 38/62] x86: Add SPL build rules for start-up code

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> When SPL is used we need to build the 16-bit start-up code. Add Makefile
> rules to handle this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  scripts/Makefile.spl | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 39/62] x86: Fix up byteorder.h for x86_64

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Remove the very old x86 code and add support for 64-bit.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/include/asm/byteorder.h | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 40/62] x86: Drop flag_is_changable() on x86_64

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This doesn't build at present and is not used in a 64-bit build. Disable it
> for now.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/include/asm/cpu.h | 3 +++
>  1 file changed, 3 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 41/62] x86: Fix up type sizes for 64-bit

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Adjust types as needed to support 64-bit compilation.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/include/asm/posix_types.h | 5 +++++
>  arch/x86/include/asm/types.h       | 5 +++++
>  2 files changed, 10 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 43/62] x86: ivybridge: Provide a dummy SDRAM init for 64-bit

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> We don't support SDRAM init in 64-bit mode since it is essentially
> impossible to get into that mode before SDRAM set up. Provide dummy functions
> for now. At some point we will need to pass the SDRAM parameters through from
> SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Put dummy misc_init_r() and print_cpuinfo() functions into cpu.c
> - Drop duplicate comment line in header
>
> Changes in v2: None
>
>  arch/x86/cpu/ivybridge/Makefile    |  3 +++
>  arch/x86/cpu/ivybridge/sdram_nop.c | 18 ++++++++++++++++++
>  arch/x86/cpu/x86_64/cpu.c          | 10 ++++++++++
>  3 files changed, 31 insertions(+)
>  create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 45/62] x86: Don't build call64 and setjmp on 64-bit

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> These are currently not supported. Calling 64-bit code from 64-bit U-Boot is
> much simpler, so this code is not needed. setjmp() is not yet implemented for
> 64-bit.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Add a TODO indicating that booting 32- and 64-bit kernels should be supported
>
> Changes in v2: None
>
>  arch/x86/cpu/Makefile | 6 +++++-
>  arch/x86/lib/bootm.c  | 7 +++++++
>  2 files changed, 12 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 41/62] x86: Fix up type sizes for 64-bit

[Bin Meng]

On Tue, Jan 17, 2017 at 12:03 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> Adjust types as needed to support 64-bit compilation.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  arch/x86/include/asm/posix_types.h | 5 +++++
>>  arch/x86/include/asm/types.h       | 5 +++++
>>  2 files changed, 10 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 42/62] x86: ivybridge: Skip SATA init in SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This doesn't work at present. Disable it for now.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Fix 'skipt' typo in the subject
>
> Changes in v2: None
>
>  arch/x86/cpu/ivybridge/Makefile | 2 ++
>  1 file changed, 2 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 43/62] x86: ivybridge: Provide a dummy SDRAM init for 64-bit

[Bin Meng]

On Tue, Jan 17, 2017 at 12:04 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> We don't support SDRAM init in 64-bit mode since it is essentially
>> impossible to get into that mode before SDRAM set up. Provide dummy functions
>> for now. At some point we will need to pass the SDRAM parameters through from
>> SPL.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Put dummy misc_init_r() and print_cpuinfo() functions into cpu.c
>> - Drop duplicate comment line in header
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/ivybridge/Makefile    |  3 +++
>>  arch/x86/cpu/ivybridge/sdram_nop.c | 18 ++++++++++++++++++
>>  arch/x86/cpu/x86_64/cpu.c          | 10 ++++++++++
>>  3 files changed, 31 insertions(+)
>>  create mode 100644 arch/x86/cpu/ivybridge/sdram_nop.c
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 44/62] x86: Don't try to run the VGA BIOS in 64-bit mode

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This is not supported, so disable it for now.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/Makefile | 2 ++
>  drivers/pci/pci_rom.c | 2 +-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 45/62] x86: Don't build call64 and setjmp on 64-bit

[Bin Meng]

On Tue, Jan 17, 2017 at 12:04 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> These are currently not supported. Calling 64-bit code from 64-bit U-Boot is
>> much simpler, so this code is not needed. setjmp() is not yet implemented for
>> 64-bit.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Add a TODO indicating that booting 32- and 64-bit kernels should be supported
>>
>> Changes in v2: None
>>
>>  arch/x86/cpu/Makefile | 6 +++++-
>>  arch/x86/lib/bootm.c  | 7 +++++++
>>  2 files changed, 12 insertions(+), 1 deletion(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 46/62] x86: Don't build cpu files which are not supported on 64-bit

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Some files cannot be built with 64-bit and mostly don't make sense in that
> context. Disable them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/Makefile | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 47/62] x86: Don't build 32-bit efi files on x86_64

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> These cannot be built in this mode, so drop them.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/Makefile | 4 ++++
>  1 file changed, 4 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 48/62] x86: Don't try to boot Linux from SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Booting into linux from 64-bit U-Boot is not yet supported. Avoid bringing
> in the bootm code until it is implemented.
>
> Of course 32-bit U-Boot still supports booting into both 32- and 64-bit
> kernels.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/Makefile | 4 ++++
>  1 file changed, 4 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 49/62] x86: Drop interrupt support in 64-bit mode

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This is not currently supported, so drop the code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/interrupts.c | 5 +++++
>  1 file changed, 5 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 50/62] x86: Support jumping from SPL to U-Boot

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a rough function to handle jumping from 32-bit SPL to 64-bit U-Boot.
> This still needs work to clean it up.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/call64.S      |  3 +++
>  arch/x86/cpu/i386/cpu.c    | 65 ++++++++++++++++++++++++++++++++++++++++++++++
>  arch/x86/include/asm/cpu.h |  9 +++++++
>  3 files changed, 77 insertions(+)
>

Fixed the first style issue by removing target64() as it is not needed:

WARNING: externs should be avoided in .c files
#68: FILE: arch/x86/cpu/i386/cpu.c:524:
+       void target64(void);

WARNING: externs should be avoided in .c files
#83: FILE: arch/x86/cpu/i386/cpu.c:539:
+       extern char gdt64[];

Leave the 2nd one in the codes, and

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 60/62] x86: link: Add build options for SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> If SPL is used we want to use the generic SPL framework and boot from SPI
> via a board-specific means. Add these options to the board config file.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Remove duplicate CONFIG_VIDEO_IVYBRIDGE_IGD in defconfig file
> - Drop the unnecessary defconfig changes for chromebook_link
>
> Changes in v2: None
>
>  include/configs/chromebook_link.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 62/62] x86: link: Add a config for 64-bit U-Boot

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new link config which uses 64-bit U-Boot. This is not fully
> functional but is it a start. Missing features:
>
> - SDRAM sizing
> - Booting linux
> - EFI support
> - SCSI device init
> (and others)
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application'
> - Drop patch 'Mention the MRC region in the README'
> - Drop patch 'x86: link: Add build options for SPL'
> - Drop unnecessary defconfig options for chromebook_link64
> - Avoid including helloworld.efi in the 64-bit U-Boot
>
> Changes in v2:
> - Drop patch 'video: Use ulong for video frame buffer address'
> - Add a new 64-bit link config instead of changing the existing one
>
>  board/google/Kconfig                     |  7 +++
>  board/google/chromebook_link/Kconfig     |  2 +-
>  board/google/chromebook_link/MAINTAINERS |  7 +++
>  configs/chromebook_link64_defconfig      | 89 ++++++++++++++++++++++++++++++++
>  4 files changed, 104 insertions(+), 1 deletion(-)
>  create mode 100644 configs/chromebook_link64_defconfig
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 62/62] x86: link: Add a config for 64-bit U-Boot

[Bin Meng]

Hi Simon,

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Add a new link config which uses 64-bit U-Boot. This is not fully

I guess you want to say: a new "board" config instead of "link" config?

> functional but is it a start. Missing features:
>
> - SDRAM sizing
> - Booting linux
> - EFI support
> - SCSI device init
> (and others)
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3:
> - Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application'
> - Drop patch 'Mention the MRC region in the README'
> - Drop patch 'x86: link: Add build options for SPL'
> - Drop unnecessary defconfig options for chromebook_link64
> - Avoid including helloworld.efi in the 64-bit U-Boot
>
> Changes in v2:
> - Drop patch 'video: Use ulong for video frame buffer address'
> - Add a new 64-bit link config instead of changing the existing one
>
>  board/google/Kconfig                     |  7 +++
>  board/google/chromebook_link/Kconfig     |  2 +-
>  board/google/chromebook_link/MAINTAINERS |  7 +++
>  configs/chromebook_link64_defconfig      | 89 ++++++++++++++++++++++++++++++++
>  4 files changed, 104 insertions(+), 1 deletion(-)
>  create mode 100644 configs/chromebook_link64_defconfig
>
> diff --git a/board/google/Kconfig b/board/google/Kconfig
> index 7ba73a2461d..e56c026ef6d 100644
> --- a/board/google/Kconfig
> +++ b/board/google/Kconfig
> @@ -22,6 +22,13 @@ config TARGET_CHROMEBOOK_LINK
>           and it provides a 2560x1700 high resolution touch-enabled LCD
>           display.
>
> +config TARGET_CHROMEBOOK_LINK64
> +       bool "Chromebook link 64-bit"
> +       help
> +         This is the Chromebook Pixel released in 2013. With this config
> +         U-Boot is built as a 64-bit binary. This allows testing while this
> +         feature is being completed.
> +
>  config TARGET_CHROMEBOX_PANTHER
>         bool "Chromebox panther (not available)"
>         select n
> diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
> index 5c57945d77a..8999b582943 100644
> --- a/board/google/chromebook_link/Kconfig
> +++ b/board/google/chromebook_link/Kconfig
> @@ -1,4 +1,4 @@
> -if TARGET_CHROMEBOOK_LINK
> +if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
>
>  config SYS_BOARD
>         default "chromebook_link"
> diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
> index bc253a2ba7b..e7aef53390c 100644
> --- a/board/google/chromebook_link/MAINTAINERS
> +++ b/board/google/chromebook_link/MAINTAINERS
> @@ -4,3 +4,10 @@ S:     Maintained
>  F:     board/google/chromebook_link/
>  F:     include/configs/chromebook_link.h
>  F:     configs/chromebook_link_defconfig
> +
> +CHROMEBOOK LINK 64-bit BOARD
> +M:     Simon Glass <sjg@chromium.org>
> +S:     Maintained
> +F:     board/google/chromebook_link/
> +F:     include/configs/chromebook_link.h
> +F:     configs/chromebook_link64_defconfig
> diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
> new file mode 100644
> index 00000000000..dd8175ec767
> --- /dev/null
> +++ b/configs/chromebook_link64_defconfig
> @@ -0,0 +1,89 @@
> +CONFIG_X86=y
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_X86_RUN_64BIT=y
> +CONFIG_VENDOR_GOOGLE=y
> +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
> +CONFIG_TARGET_CHROMEBOOK_LINK=y

I think this should be:
CONFIG_TARGET_CHROMEBOOK_LINK64=y

[snip]

I can fix these two when applying if you don't have different thoughts.

Regards,
Bin

[U-Boot] [PATCH v3 62/62] x86: link: Add a config for 64-bit U-Boot

[Simon Glass]

Hi Bin,

On 18 January 2017 at 02:04, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> Add a new link config which uses 64-bit U-Boot. This is not fully
>
> I guess you want to say: a new "board" config instead of "link" config?

Yes that's OK.

>
>> functional but is it a start. Missing features:
>>
>> - SDRAM sizing
>> - Booting linux
>> - EFI support
>> - SCSI device init
>> (and others)
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application'
>> - Drop patch 'Mention the MRC region in the README'
>> - Drop patch 'x86: link: Add build options for SPL'
>> - Drop unnecessary defconfig options for chromebook_link64
>> - Avoid including helloworld.efi in the 64-bit U-Boot
>>
>> Changes in v2:
>> - Drop patch 'video: Use ulong for video frame buffer address'
>> - Add a new 64-bit link config instead of changing the existing one
>>
>>  board/google/Kconfig                     |  7 +++
>>  board/google/chromebook_link/Kconfig     |  2 +-
>>  board/google/chromebook_link/MAINTAINERS |  7 +++
>>  configs/chromebook_link64_defconfig      | 89 ++++++++++++++++++++++++++++++++
>>  4 files changed, 104 insertions(+), 1 deletion(-)
>>  create mode 100644 configs/chromebook_link64_defconfig
>>
>> diff --git a/board/google/Kconfig b/board/google/Kconfig
>> index 7ba73a2461d..e56c026ef6d 100644
>> --- a/board/google/Kconfig
>> +++ b/board/google/Kconfig
>> @@ -22,6 +22,13 @@ config TARGET_CHROMEBOOK_LINK
>>           and it provides a 2560x1700 high resolution touch-enabled LCD
>>           display.
>>
>> +config TARGET_CHROMEBOOK_LINK64
>> +       bool "Chromebook link 64-bit"
>> +       help
>> +         This is the Chromebook Pixel released in 2013. With this config
>> +         U-Boot is built as a 64-bit binary. This allows testing while this
>> +         feature is being completed.
>> +
>>  config TARGET_CHROMEBOX_PANTHER
>>         bool "Chromebox panther (not available)"
>>         select n
>> diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
>> index 5c57945d77a..8999b582943 100644
>> --- a/board/google/chromebook_link/Kconfig
>> +++ b/board/google/chromebook_link/Kconfig
>> @@ -1,4 +1,4 @@
>> -if TARGET_CHROMEBOOK_LINK
>> +if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64
>>
>>  config SYS_BOARD
>>         default "chromebook_link"
>> diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
>> index bc253a2ba7b..e7aef53390c 100644
>> --- a/board/google/chromebook_link/MAINTAINERS
>> +++ b/board/google/chromebook_link/MAINTAINERS
>> @@ -4,3 +4,10 @@ S:     Maintained
>>  F:     board/google/chromebook_link/
>>  F:     include/configs/chromebook_link.h
>>  F:     configs/chromebook_link_defconfig
>> +
>> +CHROMEBOOK LINK 64-bit BOARD
>> +M:     Simon Glass <sjg@chromium.org>
>> +S:     Maintained
>> +F:     board/google/chromebook_link/
>> +F:     include/configs/chromebook_link.h
>> +F:     configs/chromebook_link64_defconfig
>> diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
>> new file mode 100644
>> index 00000000000..dd8175ec767
>> --- /dev/null
>> +++ b/configs/chromebook_link64_defconfig
>> @@ -0,0 +1,89 @@
>> +CONFIG_X86=y
>> +CONFIG_SPL_GPIO_SUPPORT=y
>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>> +CONFIG_SPL_I2C_SUPPORT=y
>> +CONFIG_SPL_SERIAL_SUPPORT=y
>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
>> +CONFIG_SPL_SPI_SUPPORT=y
>> +CONFIG_X86_RUN_64BIT=y
>> +CONFIG_VENDOR_GOOGLE=y
>> +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
>> +CONFIG_TARGET_CHROMEBOOK_LINK=y
>
> I think this should be:
> CONFIG_TARGET_CHROMEBOOK_LINK64=y

Yes that's right.

>
> [snip]
>
> I can fix these two when applying if you don't have different thoughts.

OK, thanks.

Regards,
SImon

[U-Boot] [PATCH v3 52/62] x86: Move turbo_state to global_data

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> To avoid using BSS in SPL before SDRAM is set up, move this field to
> global_data.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/turbo.c               | 8 ++++----
>  arch/x86/include/asm/global_data.h | 1 +
>  2 files changed, 5 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 51/62] x86: Move pirq_routing_table to global_data

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> To avoid using BSS in SPL before SDRAM is set up, move this field to
> global_data.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/irq.c                 | 12 +++++-------
>  arch/x86/include/asm/global_data.h |  1 +
>  2 files changed, 6 insertions(+), 7 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v3 51/62] x86: Move pirq_routing_table to global_data

[Bin Meng]

On Tue, Feb 7, 2017 at 1:03 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> To avoid using BSS in SPL before SDRAM is set up, move this field to
>> global_data.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  arch/x86/cpu/irq.c                 | 12 +++++-------
>>  arch/x86/include/asm/global_data.h |  1 +
>>  2 files changed, 6 insertions(+), 7 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 52/62] x86: Move turbo_state to global_data

[Bin Meng]

On Tue, Feb 7, 2017 at 1:02 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> To avoid using BSS in SPL before SDRAM is set up, move this field to
>> global_data.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3: None
>> Changes in v2: None
>>
>>  arch/x86/cpu/turbo.c               | 8 ++++----
>>  arch/x86/include/asm/global_data.h | 1 +
>>  2 files changed, 5 insertions(+), 4 deletions(-)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 53/62] x86: Change irq_already_routed to a local variable

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This avoids using BSS before SDRAM is set up in SPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/lib/pirq_routing.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 54/62] x86: Move call64 to the i386 directory

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This code is only used in 32-bit mode. Move it so that it does not get
> built with 64-bit U-Boot.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/Makefile            | 2 +-
>  arch/x86/cpu/i386/Makefile       | 1 +
>  arch/x86/cpu/{ => i386}/call64.S | 0
>  3 files changed, 2 insertions(+), 1 deletion(-)
>  rename arch/x86/cpu/{ => i386}/call64.S (100%)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 55/62] x86: Move setjmp to the i386 directory

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> This code is only used in 32-bit mode. Move it so that it does not get
> built with 64-bit U-Boot.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/cpu/Makefile            | 3 ---
>  arch/x86/cpu/i386/Makefile       | 1 +
>  arch/x86/cpu/{ => i386}/setjmp.S | 0
>  3 files changed, 1 insertion(+), 3 deletions(-)
>  rename arch/x86/cpu/{ => i386}/setjmp.S (100%)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 56/62] x86: Add a dummy setjmp implementation for x86_64

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> We don't have the code for this yet. Add a dummy version for now, so that
> EFI builds correctly.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2:
> - Add the 'val' parameter to longjmp()
>
>  arch/x86/cpu/x86_64/Makefile |  2 +-
>  arch/x86/cpu/x86_64/setjmp.c | 20 ++++++++++++++++++++
>  2 files changed, 21 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/cpu/x86_64/setjmp.c
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 57/62] x86: link: Add a text base for 64-bit U-Boot

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Set up the 64-bit U-Boot text base if building for that target.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  board/google/chromebook_link/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 58/62] x86: link: Add SPL declarations to the binman image

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> When building for 64-bit we need to put an SPL binary into the image. Update
> the binman image description to reflect this.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/u-boot.dtsi | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 59/62] x86: link: Set up device tree for SPL

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Add the correct pre-relocation tag so that the required device tree nodes
> are present in the SPL device tree.
>
> On x86 it doesn't make a lot of sense to have a separate SPL device tree.
> Since everything is in the same ROM we might as well just use the main
> device tree in both SPL and U-Boot proper. But we haven't implemented that,
> so this is a good first step.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3:
> - Expand pre-reloc malloc() size in this patch to prevent boot failure
>
> Changes in v2: None
>
>  arch/x86/dts/chromebook_link.dts  | 15 ++++++++++++++-
>  configs/chromebook_link_defconfig |  4 ++--
>  2 files changed, 16 insertions(+), 3 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 60/62] x86: link: Add build options for SPL

[Bin Meng]

On Tue, Jan 17, 2017 at 12:35 PM, Bin Meng <bmeng.cn@gmail.com> wrote:
> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> If SPL is used we want to use the generic SPL framework and boot from SPI
>> via a board-specific means. Add these options to the board config file.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> Changes in v3:
>> - Remove duplicate CONFIG_VIDEO_IVYBRIDGE_IGD in defconfig file
>> - Drop the unnecessary defconfig changes for chromebook_link
>>
>> Changes in v2: None
>>
>>  include/configs/chromebook_link.h | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 61/62] x86: Update compile/link flags to support 64-bit U-Boot

[Bin Meng]

On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Update config.mk settings to support both 32-bit and 64-bit U-Boot.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/config.mk     | 30 ++++++++++++++++++++++++++++--
>  arch/x86/cpu/config.mk |  2 --
>  2 files changed, 28 insertions(+), 4 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v3 62/62] x86: link: Add a config for 64-bit U-Boot

[Bin Meng]

On Wed, Jan 25, 2017 at 12:07 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 18 January 2017 at 02:04, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Mon, Jan 16, 2017 at 10:04 PM, Simon Glass <sjg@chromium.org> wrote:
>>> Add a new link config which uses 64-bit U-Boot. This is not fully
>>
>> I guess you want to say: a new "board" config instead of "link" config?
>
> Yes that's OK.
>

[snip]

>>> diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
>>> new file mode 100644
>>> index 00000000000..dd8175ec767
>>> --- /dev/null
>>> +++ b/configs/chromebook_link64_defconfig
>>> @@ -0,0 +1,89 @@
>>> +CONFIG_X86=y
>>> +CONFIG_SPL_GPIO_SUPPORT=y
>>> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
>>> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
>>> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>>> +CONFIG_SPL_I2C_SUPPORT=y
>>> +CONFIG_SPL_SERIAL_SUPPORT=y
>>> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
>>> +CONFIG_SPL_SPI_SUPPORT=y
>>> +CONFIG_X86_RUN_64BIT=y
>>> +CONFIG_VENDOR_GOOGLE=y
>>> +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
>>> +CONFIG_TARGET_CHROMEBOOK_LINK=y
>>
>> I think this should be:
>> CONFIG_TARGET_CHROMEBOOK_LINK64=y
>
> Yes that's right.
>
>>
>> [snip]
>>
>> I can fix these two when applying if you don't have different thoughts.
>
> OK, thanks.
>

Fixed above two nits, and

applied to u-boot-x86, thanks!