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* [PATCH] target/riscv: csr: Implement mconfigptr CSR
@ 2021-10-03 11:28 Rahul Pathak
  2021-10-07  5:37   ` Bin Meng
  0 siblings, 1 reply; 7+ messages in thread
From: Rahul Pathak @ 2021-10-03 11:28 UTC (permalink / raw)
  To: Alistair.Francis, bmeng.cn, qemu-devel, qemu-riscv
  Cc: pathakraul, Rahul Pathak

mconfigptr is an mandatory CSR as per the priv spec.
This csr holds the physical address of the configuration
data structure if this data structure is implemented
Its an readonly csr set to zero making configuration
data structure not supported.

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
---
 target/riscv/cpu_bits.h | 1 +
 target/riscv/csr.c      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..5dc4729ed5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -140,6 +140,7 @@
 #define CSR_MARCHID         0xf12
 #define CSR_MIMPID          0xf13
 #define CSR_MHARTID         0xf14
+#define CSR_MCONFIGPTR      0xf15 
 
 /* Machine Trap Setup */
 #define CSR_MSTATUS         0x300
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd3216..2182943f54 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
+    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },
 
     /* Machine Trap Setup */
     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
  2021-10-03 11:28 [PATCH] target/riscv: csr: Implement mconfigptr CSR Rahul Pathak
@ 2021-10-07  5:37   ` Bin Meng
  0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-10-07  5:37 UTC (permalink / raw)
  To: Rahul Pathak
  Cc: open list:RISC-V, pathakraul, Alistair Francis,
	qemu-devel@nongnu.org Developers

On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
>
> mconfigptr is an mandatory CSR as per the priv spec.

%s/an/a

as per the priv spec v1.12

> This csr holds the physical address of the configuration
> data structure if this data structure is implemented
> Its an readonly csr set to zero making configuration
> data structure not supported.
>
> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..5dc4729ed5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -140,6 +140,7 @@
>  #define CSR_MARCHID         0xf12
>  #define CSR_MIMPID          0xf13
>  #define CSR_MHARTID         0xf14
> +#define CSR_MCONFIGPTR      0xf15
>
>  /* Machine Trap Setup */
>  #define CSR_MSTATUS         0x300
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd3216..2182943f54 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
>      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
>      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> +    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },

Not any, as we need to check the priv version >= 1.12

>
>      /* Machine Trap Setup */
>      [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
> --

Regards,
Bin


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
@ 2021-10-07  5:37   ` Bin Meng
  0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-10-07  5:37 UTC (permalink / raw)
  To: Rahul Pathak
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, pathakraul

On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
>
> mconfigptr is an mandatory CSR as per the priv spec.

%s/an/a

as per the priv spec v1.12

> This csr holds the physical address of the configuration
> data structure if this data structure is implemented
> Its an readonly csr set to zero making configuration
> data structure not supported.
>
> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..5dc4729ed5 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -140,6 +140,7 @@
>  #define CSR_MARCHID         0xf12
>  #define CSR_MIMPID          0xf13
>  #define CSR_MHARTID         0xf14
> +#define CSR_MCONFIGPTR      0xf15
>
>  /* Machine Trap Setup */
>  #define CSR_MSTATUS         0x300
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 23fbbd3216..2182943f54 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
>      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
>      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> +    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },

Not any, as we need to check the priv version >= 1.12

>
>      /* Machine Trap Setup */
>      [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
> --

Regards,
Bin


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
  2021-10-07  5:37   ` Bin Meng
@ 2021-10-08  9:47     ` Rahul Pathak
  -1 siblings, 0 replies; 7+ messages in thread
From: Rahul Pathak @ 2021-10-08  9:47 UTC (permalink / raw)
  To: Bin Meng
  Cc: open list:RISC-V, pathakraul, Alistair Francis,
	qemu-devel@nongnu.org Developers

Hi Bin


On Thu, Oct 7, 2021 at 11:07 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
> >
> > mconfigptr is an mandatory CSR as per the priv spec.
>
> %s/an/a
>

Done

>
> as per the priv spec v1.12
>
> > This csr holds the physical address of the configuration
> > data structure if this data structure is implemented
> > Its an readonly csr set to zero making configuration
> > data structure not supported.
> >
> > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> > ---
> >  target/riscv/cpu_bits.h | 1 +
> >  target/riscv/csr.c      | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 999187a9ee..5dc4729ed5 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -140,6 +140,7 @@
> >  #define CSR_MARCHID         0xf12
> >  #define CSR_MIMPID          0xf13
> >  #define CSR_MHARTID         0xf14
> > +#define CSR_MCONFIGPTR      0xf15
> >
> >  /* Machine Trap Setup */
> >  #define CSR_MSTATUS         0x300
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 23fbbd3216..2182943f54 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >      [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
> >      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
> >      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> > +    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },
>
> Not any, as we need to check the priv version >= 1.12


To check the priv version, I am thinking of creating a generic
predicate function
which checks the env->priv_ver.?
Generic predicate function for the priv version can be reused in other such
scenarios also.


>
> >
> >      /* Machine Trap Setup */
> >      [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
> > --
>
> Regards,
> Bin


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
@ 2021-10-08  9:47     ` Rahul Pathak
  0 siblings, 0 replies; 7+ messages in thread
From: Rahul Pathak @ 2021-10-08  9:47 UTC (permalink / raw)
  To: Bin Meng
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, pathakraul

Hi Bin


On Thu, Oct 7, 2021 at 11:07 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
> >
> > mconfigptr is an mandatory CSR as per the priv spec.
>
> %s/an/a
>

Done

>
> as per the priv spec v1.12
>
> > This csr holds the physical address of the configuration
> > data structure if this data structure is implemented
> > Its an readonly csr set to zero making configuration
> > data structure not supported.
> >
> > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> > ---
> >  target/riscv/cpu_bits.h | 1 +
> >  target/riscv/csr.c      | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 999187a9ee..5dc4729ed5 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -140,6 +140,7 @@
> >  #define CSR_MARCHID         0xf12
> >  #define CSR_MIMPID          0xf13
> >  #define CSR_MHARTID         0xf14
> > +#define CSR_MCONFIGPTR      0xf15
> >
> >  /* Machine Trap Setup */
> >  #define CSR_MSTATUS         0x300
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 23fbbd3216..2182943f54 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >      [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
> >      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
> >      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> > +    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },
>
> Not any, as we need to check the priv version >= 1.12


To check the priv version, I am thinking of creating a generic
predicate function
which checks the env->priv_ver.?
Generic predicate function for the priv version can be reused in other such
scenarios also.


>
> >
> >      /* Machine Trap Setup */
> >      [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus     },
> > --
>
> Regards,
> Bin


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
  2021-10-08  9:47     ` Rahul Pathak
@ 2021-10-13  9:36       ` Bin Meng
  -1 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-10-13  9:36 UTC (permalink / raw)
  To: Rahul Pathak
  Cc: open list:RISC-V, pathakraul, Alistair Francis,
	qemu-devel@nongnu.org Developers

HI Rahul,

On Fri, Oct 8, 2021 at 5:47 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
>
> Hi Bin
>
>
> On Thu, Oct 7, 2021 at 11:07 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
> > >
> > > mconfigptr is an mandatory CSR as per the priv spec.
> >
> > %s/an/a
> >
>
> Done
>
> >
> > as per the priv spec v1.12
> >
> > > This csr holds the physical address of the configuration
> > > data structure if this data structure is implemented
> > > Its an readonly csr set to zero making configuration
> > > data structure not supported.
> > >
> > > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> > > ---
> > >  target/riscv/cpu_bits.h | 1 +
> > >  target/riscv/csr.c      | 1 +
> > >  2 files changed, 2 insertions(+)
> > >
> > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > index 999187a9ee..5dc4729ed5 100644
> > > --- a/target/riscv/cpu_bits.h
> > > +++ b/target/riscv/cpu_bits.h
> > > @@ -140,6 +140,7 @@
> > >  #define CSR_MARCHID         0xf12
> > >  #define CSR_MIMPID          0xf13
> > >  #define CSR_MHARTID         0xf14
> > > +#define CSR_MCONFIGPTR      0xf15
> > >
> > >  /* Machine Trap Setup */
> > >  #define CSR_MSTATUS         0x300
> > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > > index 23fbbd3216..2182943f54 100644
> > > --- a/target/riscv/csr.c
> > > +++ b/target/riscv/csr.c
> > > @@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > >      [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
> > >      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
> > >      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> > > +    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },
> >
> > Not any, as we need to check the priv version >= 1.12
>
>
> To check the priv version, I am thinking of creating a generic
> predicate function
> which checks the env->priv_ver.?
> Generic predicate function for the priv version can be reused in other such
> scenarios also.

Sounds good to me. Thanks!

Regards,
Bin


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] target/riscv: csr: Implement mconfigptr CSR
@ 2021-10-13  9:36       ` Bin Meng
  0 siblings, 0 replies; 7+ messages in thread
From: Bin Meng @ 2021-10-13  9:36 UTC (permalink / raw)
  To: Rahul Pathak
  Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
	open list:RISC-V, pathakraul

HI Rahul,

On Fri, Oct 8, 2021 at 5:47 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
>
> Hi Bin
>
>
> On Thu, Oct 7, 2021 at 11:07 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Sun, Oct 3, 2021 at 7:29 PM Rahul Pathak <rpathak@ventanamicro.com> wrote:
> > >
> > > mconfigptr is an mandatory CSR as per the priv spec.
> >
> > %s/an/a
> >
>
> Done
>
> >
> > as per the priv spec v1.12
> >
> > > This csr holds the physical address of the configuration
> > > data structure if this data structure is implemented
> > > Its an readonly csr set to zero making configuration
> > > data structure not supported.
> > >
> > > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
> > > ---
> > >  target/riscv/cpu_bits.h | 1 +
> > >  target/riscv/csr.c      | 1 +
> > >  2 files changed, 2 insertions(+)
> > >
> > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > index 999187a9ee..5dc4729ed5 100644
> > > --- a/target/riscv/cpu_bits.h
> > > +++ b/target/riscv/cpu_bits.h
> > > @@ -140,6 +140,7 @@
> > >  #define CSR_MARCHID         0xf12
> > >  #define CSR_MIMPID          0xf13
> > >  #define CSR_MHARTID         0xf14
> > > +#define CSR_MCONFIGPTR      0xf15
> > >
> > >  /* Machine Trap Setup */
> > >  #define CSR_MSTATUS         0x300
> > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > > index 23fbbd3216..2182943f54 100644
> > > --- a/target/riscv/csr.c
> > > +++ b/target/riscv/csr.c
> > > @@ -1549,6 +1549,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > >      [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
> > >      [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
> > >      [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
> > > +    [CSR_MCONFIGPTR] = {"mconfigptr", any,  read_zero    },
> >
> > Not any, as we need to check the priv version >= 1.12
>
>
> To check the priv version, I am thinking of creating a generic
> predicate function
> which checks the env->priv_ver.?
> Generic predicate function for the priv version can be reused in other such
> scenarios also.

Sounds good to me. Thanks!

Regards,
Bin


^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2021-10-13  9:53 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-03 11:28 [PATCH] target/riscv: csr: Implement mconfigptr CSR Rahul Pathak
2021-10-07  5:37 ` Bin Meng
2021-10-07  5:37   ` Bin Meng
2021-10-08  9:47   ` Rahul Pathak
2021-10-08  9:47     ` Rahul Pathak
2021-10-13  9:36     ` Bin Meng
2021-10-13  9:36       ` Bin Meng

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