[RFC PATCH v1 00/10] RISC-V ACLINT Support

[RFC PATCH v1 00/10] RISC-V ACLINT Support

[Anup Patel]

Most of the existing RISC-V platforms use SiFive CLINT to provide M-level
timer and IPI support whereas S-level uses SBI calls for timer and IPI
support. Also, the SiFive CLINT device is a single device providing both
timer and IPI functionality so RISC-V platforms can't partially implement
SiFive CLINT device and provide alternate mechanism for timer and IPI.

The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the
limitations of SiFive CLINT by:
1) Taking modular approach and defining timer and IPI functionality as
   separate devices so that RISC-V platforms can include only required
   devices
2) Providing dedicated MMIO device for S-level IPIs so that SBI calls
   can be avoided for IPIs in Linux RISC-V
3) Allowing multiple instances of timer and IPI devices for a
   multi-socket (or multi-die) NUMA systems
4) Being backward compatible to SiFive CLINT so that existing RISC-V
   platforms stay compliant with RISC-V ACLINT specification

Latest RISC-V ACLINT specification (will be frozen in a month) can be
found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

This series adds RISC-V ACLINT support and can be found in riscv_aclint_v1
branch at:
https://github.com/avpatel/linux

To test this series, the RISC-V ACLINT support for QEMU and OpenSBI
can be found in the riscv_aclint_v1 branch at:
https://github.com/avpatel/qemu
https://github.com/avpatel/opensbi

Anup Patel (10):
  RISC-V: Clear SIP bit only when using SBI IPI operations
  RISC-V: Use common print prefix in smp.c
  RISC-V: Allow more details in IPI operations
  RISC-V: Use IPIs for remote TLB flush when possible
  irqchip: Add ACLINT software interrupt driver
  RISC-V: Select ACLINT SWI driver for virt machine
  clocksource: clint: Add support for ACLINT MTIMER device
  dt-bindings: timer: Add ACLINT MTIMER bindings
  dt-bindings: timer: Add ACLINT MSWI and SSWI bindings
  MAINTAINERS: Add entry for RISC-V ACLINT drivers

 .../riscv,aclint-swi.yaml                     |  82 ++++++++++++
 .../bindings/timer/riscv,aclint-mtimer.yaml   |  55 ++++++++
 MAINTAINERS                                   |   9 ++
 arch/riscv/Kconfig.socs                       |   1 +
 arch/riscv/include/asm/smp.h                  |  15 +++
 arch/riscv/kernel/sbi.c                       |  10 +-
 arch/riscv/kernel/smp.c                       |  36 +++++-
 arch/riscv/mm/cacheflush.c                    |   2 +-
 arch/riscv/mm/tlbflush.c                      |  62 +++++++--
 drivers/clocksource/timer-clint.c             |  45 +++++--
 drivers/irqchip/Kconfig                       |  11 ++
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-aclint-swi.c              | 122 ++++++++++++++++++
 13 files changed, 415 insertions(+), 36 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 create mode 100644 drivers/irqchip/irq-aclint-swi.c

-- 
2.25.1

[RFC PATCH v1 00/10] RISC-V ACLINT Support

[Anup Patel]

Most of the existing RISC-V platforms use SiFive CLINT to provide M-level
timer and IPI support whereas S-level uses SBI calls for timer and IPI
support. Also, the SiFive CLINT device is a single device providing both
timer and IPI functionality so RISC-V platforms can't partially implement
SiFive CLINT device and provide alternate mechanism for timer and IPI.

The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the
limitations of SiFive CLINT by:
1) Taking modular approach and defining timer and IPI functionality as
   separate devices so that RISC-V platforms can include only required
   devices
2) Providing dedicated MMIO device for S-level IPIs so that SBI calls
   can be avoided for IPIs in Linux RISC-V
3) Allowing multiple instances of timer and IPI devices for a
   multi-socket (or multi-die) NUMA systems
4) Being backward compatible to SiFive CLINT so that existing RISC-V
   platforms stay compliant with RISC-V ACLINT specification

Latest RISC-V ACLINT specification (will be frozen in a month) can be
found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

This series adds RISC-V ACLINT support and can be found in riscv_aclint_v1
branch at:
https://github.com/avpatel/linux

To test this series, the RISC-V ACLINT support for QEMU and OpenSBI
can be found in the riscv_aclint_v1 branch at:
https://github.com/avpatel/qemu
https://github.com/avpatel/opensbi

Anup Patel (10):
  RISC-V: Clear SIP bit only when using SBI IPI operations
  RISC-V: Use common print prefix in smp.c
  RISC-V: Allow more details in IPI operations
  RISC-V: Use IPIs for remote TLB flush when possible
  irqchip: Add ACLINT software interrupt driver
  RISC-V: Select ACLINT SWI driver for virt machine
  clocksource: clint: Add support for ACLINT MTIMER device
  dt-bindings: timer: Add ACLINT MTIMER bindings
  dt-bindings: timer: Add ACLINT MSWI and SSWI bindings
  MAINTAINERS: Add entry for RISC-V ACLINT drivers

 .../riscv,aclint-swi.yaml                     |  82 ++++++++++++
 .../bindings/timer/riscv,aclint-mtimer.yaml   |  55 ++++++++
 MAINTAINERS                                   |   9 ++
 arch/riscv/Kconfig.socs                       |   1 +
 arch/riscv/include/asm/smp.h                  |  15 +++
 arch/riscv/kernel/sbi.c                       |  10 +-
 arch/riscv/kernel/smp.c                       |  36 +++++-
 arch/riscv/mm/cacheflush.c                    |   2 +-
 arch/riscv/mm/tlbflush.c                      |  62 +++++++--
 drivers/clocksource/timer-clint.c             |  45 +++++--
 drivers/irqchip/Kconfig                       |  11 ++
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-aclint-swi.c              | 122 ++++++++++++++++++
 13 files changed, 415 insertions(+), 36 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
 create mode 100644 drivers/irqchip/irq-aclint-swi.c

-- 
2.25.1


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[RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations

[Anup Patel]

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but readonly for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/kernel/sbi.c | 8 +++++++-
 arch/riscv/kernel/smp.c | 2 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 9a84f0cb5175..8aeca26198f2 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -598,8 +598,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
 	sbi_send_ipi(cpumask_bits(&hartid_mask));
 }
 
+static void sbi_ipi_clear(void)
+{
+	csr_clear(CSR_IP, IE_SIE);
+}
+
 static const struct riscv_ipi_ops sbi_ipi_ops = {
-	.ipi_inject = sbi_send_cpumask_ipi
+	.ipi_inject = sbi_send_cpumask_ipi,
+	.ipi_clear = sbi_ipi_clear
 };
 
 void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 921d9d7df400..547dc508f7d1 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -99,8 +99,6 @@ void riscv_clear_ipi(void)
 {
 	if (ipi_ops && ipi_ops->ipi_clear)
 		ipi_ops->ipi_clear();
-
-	csr_clear(CSR_IP, IE_SIE);
 }
 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
 
-- 
2.25.1

[RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations

[Anup Patel]

The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
S-mode but readonly for M-mode so we clear this bit only when using
SBI IPI operations.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/kernel/sbi.c | 8 +++++++-
 arch/riscv/kernel/smp.c | 2 --
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 9a84f0cb5175..8aeca26198f2 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -598,8 +598,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
 	sbi_send_ipi(cpumask_bits(&hartid_mask));
 }
 
+static void sbi_ipi_clear(void)
+{
+	csr_clear(CSR_IP, IE_SIE);
+}
+
 static const struct riscv_ipi_ops sbi_ipi_ops = {
-	.ipi_inject = sbi_send_cpumask_ipi
+	.ipi_inject = sbi_send_cpumask_ipi,
+	.ipi_clear = sbi_ipi_clear
 };
 
 void __init sbi_init(void)
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 921d9d7df400..547dc508f7d1 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -99,8 +99,6 @@ void riscv_clear_ipi(void)
 {
 	if (ipi_ops && ipi_ops->ipi_clear)
 		ipi_ops->ipi_clear();
-
-	csr_clear(CSR_IP, IE_SIE);
 }
 EXPORT_SYMBOL_GPL(riscv_clear_ipi);
 
-- 
2.25.1


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Re: [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations

[Bin Meng]

On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
> S-mode but readonly for M-mode so we clear this bit only when using

nits: read-only

> SBI IPI operations.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/kernel/sbi.c | 8 +++++++-
>  arch/riscv/kernel/smp.c | 2 --
>  2 files changed, 7 insertions(+), 3 deletions(-)
>

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 01/10] RISC-V: Clear SIP bit only when using SBI IPI operations

[Bin Meng]

On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
> S-mode but readonly for M-mode so we clear this bit only when using

nits: read-only

> SBI IPI operations.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/kernel/sbi.c | 8 +++++++-
>  arch/riscv/kernel/smp.c | 2 --
>  2 files changed, 7 insertions(+), 3 deletions(-)
>

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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[RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c

[Anup Patel]

We add "#define pr_fmt()" in smp.c to use "riscv:" as common
print prefix for all pr_xyz() statements in this file.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/kernel/smp.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 547dc508f7d1..eea0c9d11d9f 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -8,6 +8,7 @@
  * Copyright (C) 2017 SiFive
  */
 
+#define pr_fmt(fmt) "riscv: " fmt
 #include <linux/cpu.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -114,7 +115,7 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
 	if (ipi_ops && ipi_ops->ipi_inject)
 		ipi_ops->ipi_inject(mask);
 	else
-		pr_warn("SMP: IPI inject method not available\n");
+		pr_warn("IPI inject method not available\n");
 }
 
 static void send_ipi_single(int cpu, enum ipi_message_type op)
@@ -126,7 +127,7 @@ static void send_ipi_single(int cpu, enum ipi_message_type op)
 	if (ipi_ops && ipi_ops->ipi_inject)
 		ipi_ops->ipi_inject(cpumask_of(cpu));
 	else
-		pr_warn("SMP: IPI inject method not available\n");
+		pr_warn("IPI inject method not available\n");
 }
 
 #ifdef CONFIG_IRQ_WORK
@@ -242,7 +243,7 @@ void smp_send_stop(void)
 		cpumask_clear_cpu(smp_processor_id(), &mask);
 
 		if (system_state <= SYSTEM_RUNNING)
-			pr_crit("SMP: stopping secondary CPUs\n");
+			pr_crit("stopping secondary CPUs\n");
 		send_ipi_mask(&mask, IPI_CPU_STOP);
 	}
 
@@ -252,7 +253,7 @@ void smp_send_stop(void)
 		udelay(1);
 
 	if (num_online_cpus() > 1)
-		pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
+		pr_warn("failed to stop secondary CPUs %*pbl\n",
 			   cpumask_pr_args(cpu_online_mask));
 }
 
-- 
2.25.1

[RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c

[Anup Patel]

We add "#define pr_fmt()" in smp.c to use "riscv:" as common
print prefix for all pr_xyz() statements in this file.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/kernel/smp.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index 547dc508f7d1..eea0c9d11d9f 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -8,6 +8,7 @@
  * Copyright (C) 2017 SiFive
  */
 
+#define pr_fmt(fmt) "riscv: " fmt
 #include <linux/cpu.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -114,7 +115,7 @@ static void send_ipi_mask(const struct cpumask *mask, enum ipi_message_type op)
 	if (ipi_ops && ipi_ops->ipi_inject)
 		ipi_ops->ipi_inject(mask);
 	else
-		pr_warn("SMP: IPI inject method not available\n");
+		pr_warn("IPI inject method not available\n");
 }
 
 static void send_ipi_single(int cpu, enum ipi_message_type op)
@@ -126,7 +127,7 @@ static void send_ipi_single(int cpu, enum ipi_message_type op)
 	if (ipi_ops && ipi_ops->ipi_inject)
 		ipi_ops->ipi_inject(cpumask_of(cpu));
 	else
-		pr_warn("SMP: IPI inject method not available\n");
+		pr_warn("IPI inject method not available\n");
 }
 
 #ifdef CONFIG_IRQ_WORK
@@ -242,7 +243,7 @@ void smp_send_stop(void)
 		cpumask_clear_cpu(smp_processor_id(), &mask);
 
 		if (system_state <= SYSTEM_RUNNING)
-			pr_crit("SMP: stopping secondary CPUs\n");
+			pr_crit("stopping secondary CPUs\n");
 		send_ipi_mask(&mask, IPI_CPU_STOP);
 	}
 
@@ -252,7 +253,7 @@ void smp_send_stop(void)
 		udelay(1);
 
 	if (num_online_cpus() > 1)
-		pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
+		pr_warn("failed to stop secondary CPUs %*pbl\n",
 			   cpumask_pr_args(cpu_online_mask));
 }
 
-- 
2.25.1


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Re: [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c

[Bin Meng]

On Sun, Jun 13, 2021 at 12:06 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add "#define pr_fmt()" in smp.c to use "riscv:" as common
> print prefix for all pr_xyz() statements in this file.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/kernel/smp.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 02/10] RISC-V: Use common print prefix in smp.c

[Bin Meng]

On Sun, Jun 13, 2021 at 12:06 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add "#define pr_fmt()" in smp.c to use "riscv:" as common
> print prefix for all pr_xyz() statements in this file.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/kernel/smp.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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[RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations

[Anup Patel]

We extend struct riscv_ipi_ops so that the IPI providers (such as
SBI, CLINT driver, ACLINT SWI driver etc) can specify:
1) Name of the IPI operations
2) Whether IPIs are suitable for doing remote FENCEs

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/include/asm/smp.h      | 15 +++++++++++++++
 arch/riscv/kernel/sbi.c           |  2 ++
 arch/riscv/kernel/smp.c           | 25 ++++++++++++++++++++++++-
 arch/riscv/mm/cacheflush.c        |  2 +-
 drivers/clocksource/timer-clint.c |  2 ++
 5 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index a7d2811f3536..4c4f0dde1164 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -16,11 +16,16 @@ struct seq_file;
 extern unsigned long boot_cpu_hartid;
 
 struct riscv_ipi_ops {
+	const char *name;
+	bool use_for_rfence;
 	void (*ipi_inject)(const struct cpumask *target);
 	void (*ipi_clear)(void);
 };
 
 #ifdef CONFIG_SMP
+
+#include <linux/jump_label.h>
+
 /*
  * Mapping between linux logical cpu index and hartid.
  */
@@ -45,6 +50,11 @@ void arch_send_call_function_single_ipi(int cpu);
 int riscv_hartid_to_cpuid(int hartid);
 void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
 
+/* Check if we can use IPIs for remote FENCE */
+extern struct static_key_false riscv_ipi_for_rfence;
+#define riscv_use_ipi_for_rfence() \
+	static_branch_unlikely(&riscv_ipi_for_rfence)
+
 /* Set custom IPI operations */
 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops);
 
@@ -92,6 +102,11 @@ static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,
 	cpumask_set_cpu(boot_cpu_hartid, out);
 }
 
+static inline bool riscv_use_ipi_for_rfence(void)
+{
+	return false;
+}
+
 static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
 {
 }
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 8aeca26198f2..be2b7a89ce49 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -604,6 +604,8 @@ static void sbi_ipi_clear(void)
 }
 
 static const struct riscv_ipi_ops sbi_ipi_ops = {
+	.name = "SBI",
+	.use_for_rfence = false,
 	.ipi_inject = sbi_send_cpumask_ipi,
 	.ipi_clear = sbi_ipi_clear
 };
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index eea0c9d11d9f..cffe3247b132 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -90,9 +90,32 @@ static void ipi_stop(void)
 
 static const struct riscv_ipi_ops *ipi_ops __ro_after_init;
 
+DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence);
+EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence);
+
 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
 {
-	ipi_ops = ops;
+	bool updated = true;
+
+	if (!ops)
+		return;
+
+	if (!ipi_ops) {
+		ipi_ops = ops;
+	} else {
+		if (!ipi_ops->use_for_rfence && ops->use_for_rfence)
+			ipi_ops = ops;
+		else
+			updated = false;
+	}
+
+	if (updated) {
+		if (ipi_ops->use_for_rfence)
+			static_branch_enable(&riscv_ipi_for_rfence);
+		else
+			static_branch_disable(&riscv_ipi_for_rfence);
+		pr_info("switched IPI operations to %s\n", ipi_ops->name);
+	}
 }
 EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
 
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 094118663285..0ffe7d560dc8 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -16,7 +16,7 @@ static void ipi_remote_fence_i(void *info)
 
 void flush_icache_all(void)
 {
-	if (IS_ENABLED(CONFIG_RISCV_SBI))
+	if (!riscv_use_ipi_for_rfence())
 		sbi_remote_fence_i(NULL);
 	else
 		on_each_cpu(ipi_remote_fence_i, NULL, 1);
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 6cfe2ab73eb0..dfdcd94c1fd5 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -55,6 +55,8 @@ static void clint_clear_ipi(void)
 }
 
 static struct riscv_ipi_ops clint_ipi_ops = {
+	.name = "CLINT",
+	.use_for_rfence = true,
 	.ipi_inject = clint_send_ipi,
 	.ipi_clear = clint_clear_ipi,
 };
-- 
2.25.1

[RFC PATCH v1 03/10] RISC-V: Allow more details in IPI operations

[Anup Patel]

We extend struct riscv_ipi_ops so that the IPI providers (such as
SBI, CLINT driver, ACLINT SWI driver etc) can specify:
1) Name of the IPI operations
2) Whether IPIs are suitable for doing remote FENCEs

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/include/asm/smp.h      | 15 +++++++++++++++
 arch/riscv/kernel/sbi.c           |  2 ++
 arch/riscv/kernel/smp.c           | 25 ++++++++++++++++++++++++-
 arch/riscv/mm/cacheflush.c        |  2 +-
 drivers/clocksource/timer-clint.c |  2 ++
 5 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
index a7d2811f3536..4c4f0dde1164 100644
--- a/arch/riscv/include/asm/smp.h
+++ b/arch/riscv/include/asm/smp.h
@@ -16,11 +16,16 @@ struct seq_file;
 extern unsigned long boot_cpu_hartid;
 
 struct riscv_ipi_ops {
+	const char *name;
+	bool use_for_rfence;
 	void (*ipi_inject)(const struct cpumask *target);
 	void (*ipi_clear)(void);
 };
 
 #ifdef CONFIG_SMP
+
+#include <linux/jump_label.h>
+
 /*
  * Mapping between linux logical cpu index and hartid.
  */
@@ -45,6 +50,11 @@ void arch_send_call_function_single_ipi(int cpu);
 int riscv_hartid_to_cpuid(int hartid);
 void riscv_cpuid_to_hartid_mask(const struct cpumask *in, struct cpumask *out);
 
+/* Check if we can use IPIs for remote FENCE */
+extern struct static_key_false riscv_ipi_for_rfence;
+#define riscv_use_ipi_for_rfence() \
+	static_branch_unlikely(&riscv_ipi_for_rfence)
+
 /* Set custom IPI operations */
 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops);
 
@@ -92,6 +102,11 @@ static inline void riscv_cpuid_to_hartid_mask(const struct cpumask *in,
 	cpumask_set_cpu(boot_cpu_hartid, out);
 }
 
+static inline bool riscv_use_ipi_for_rfence(void)
+{
+	return false;
+}
+
 static inline void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
 {
 }
diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
index 8aeca26198f2..be2b7a89ce49 100644
--- a/arch/riscv/kernel/sbi.c
+++ b/arch/riscv/kernel/sbi.c
@@ -604,6 +604,8 @@ static void sbi_ipi_clear(void)
 }
 
 static const struct riscv_ipi_ops sbi_ipi_ops = {
+	.name = "SBI",
+	.use_for_rfence = false,
 	.ipi_inject = sbi_send_cpumask_ipi,
 	.ipi_clear = sbi_ipi_clear
 };
diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
index eea0c9d11d9f..cffe3247b132 100644
--- a/arch/riscv/kernel/smp.c
+++ b/arch/riscv/kernel/smp.c
@@ -90,9 +90,32 @@ static void ipi_stop(void)
 
 static const struct riscv_ipi_ops *ipi_ops __ro_after_init;
 
+DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence);
+EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence);
+
 void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops)
 {
-	ipi_ops = ops;
+	bool updated = true;
+
+	if (!ops)
+		return;
+
+	if (!ipi_ops) {
+		ipi_ops = ops;
+	} else {
+		if (!ipi_ops->use_for_rfence && ops->use_for_rfence)
+			ipi_ops = ops;
+		else
+			updated = false;
+	}
+
+	if (updated) {
+		if (ipi_ops->use_for_rfence)
+			static_branch_enable(&riscv_ipi_for_rfence);
+		else
+			static_branch_disable(&riscv_ipi_for_rfence);
+		pr_info("switched IPI operations to %s\n", ipi_ops->name);
+	}
 }
 EXPORT_SYMBOL_GPL(riscv_set_ipi_ops);
 
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 094118663285..0ffe7d560dc8 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -16,7 +16,7 @@ static void ipi_remote_fence_i(void *info)
 
 void flush_icache_all(void)
 {
-	if (IS_ENABLED(CONFIG_RISCV_SBI))
+	if (!riscv_use_ipi_for_rfence())
 		sbi_remote_fence_i(NULL);
 	else
 		on_each_cpu(ipi_remote_fence_i, NULL, 1);
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index 6cfe2ab73eb0..dfdcd94c1fd5 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -55,6 +55,8 @@ static void clint_clear_ipi(void)
 }
 
 static struct riscv_ipi_ops clint_ipi_ops = {
+	.name = "CLINT",
+	.use_for_rfence = true,
 	.ipi_inject = clint_send_ipi,
 	.ipi_clear = clint_clear_ipi,
 };
-- 
2.25.1


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[RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible

[Anup Patel]

If IPI calls are injected using SBI IPI calls then remote TLB flush
using SBI RFENCE calls is much faster because using IPIs for remote
TLB flush would still endup as SBI IPI calls with extra processing
on kernel side.

It is now possible to have specialized hardware (such as RISC-V AIA)
which allows S-mode software to directly inject IPIs without any
assistance from M-mode runtime firmware.

This patch extends remote TLB flush functions to use IPIs whenever
underlying IPI operations are suitable for remote FENCEs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++---------
 1 file changed, 48 insertions(+), 14 deletions(-)

diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 720b443c4528..009c56fa102d 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -1,39 +1,73 @@
 // SPDX-License-Identifier: GPL-2.0
+/*
+ * TLB flush implementation.
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ */
 
 #include <linux/mm.h>
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <asm/sbi.h>
 
+static void ipi_flush_tlb_all(void *info)
+{
+	local_flush_tlb_all();
+}
+
 void flush_tlb_all(void)
 {
-	sbi_remote_sfence_vma(NULL, 0, -1);
+	if (!riscv_use_ipi_for_rfence())
+		sbi_remote_sfence_vma(NULL, 0, -1);
+	else
+		on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
+
+struct flush_range_data {
+	unsigned long start;
+	unsigned long size;
+};
+
+static void ipi_flush_range(void *info)
+{
+	struct flush_range_data *data = info;
+
+	/* local cpu is the only cpu present in cpumask */
+	if (data->size <= PAGE_SIZE)
+		local_flush_tlb_page(data->start);
+	else
+		local_flush_tlb_all();
 }
 
 /*
- * This function must not be called with cmask being null.
+ * This function must not be called with NULL cpumask.
  * Kernel may panic if cmask is NULL.
  */
-static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
-				  unsigned long size)
+static void flush_range(struct cpumask *cmask, unsigned long start,
+			unsigned long size)
 {
+	struct flush_range_data info;
 	struct cpumask hmask;
 	unsigned int cpuid;
 
 	if (cpumask_empty(cmask))
 		return;
 
+	info.start = start;
+	info.size = size;
+
 	cpuid = get_cpu();
 
 	if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) {
-		/* local cpu is the only cpu present in cpumask */
-		if (size <= PAGE_SIZE)
-			local_flush_tlb_page(start);
-		else
-			local_flush_tlb_all();
+		ipi_flush_range(&info);
 	} else {
-		riscv_cpuid_to_hartid_mask(cmask, &hmask);
-		sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size);
+		if (!riscv_use_ipi_for_rfence()) {
+			riscv_cpuid_to_hartid_mask(cmask, &hmask);
+			sbi_remote_sfence_vma(cpumask_bits(&hmask),
+					      start, size);
+		} else {
+			on_each_cpu_mask(cmask, ipi_flush_range, &info, 1);
+		}
 	}
 
 	put_cpu();
@@ -41,16 +75,16 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
 
 void flush_tlb_mm(struct mm_struct *mm)
 {
-	__sbi_tlb_flush_range(mm_cpumask(mm), 0, -1);
+	flush_range(mm_cpumask(mm), 0, -1);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE);
+	flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE);
 }
 
 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 		     unsigned long end)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start);
+	flush_range(mm_cpumask(vma->vm_mm), start, end - start);
 }
-- 
2.25.1

[RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible

[Anup Patel]

If IPI calls are injected using SBI IPI calls then remote TLB flush
using SBI RFENCE calls is much faster because using IPIs for remote
TLB flush would still endup as SBI IPI calls with extra processing
on kernel side.

It is now possible to have specialized hardware (such as RISC-V AIA)
which allows S-mode software to directly inject IPIs without any
assistance from M-mode runtime firmware.

This patch extends remote TLB flush functions to use IPIs whenever
underlying IPI operations are suitable for remote FENCEs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++---------
 1 file changed, 48 insertions(+), 14 deletions(-)

diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 720b443c4528..009c56fa102d 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -1,39 +1,73 @@
 // SPDX-License-Identifier: GPL-2.0
+/*
+ * TLB flush implementation.
+ *
+ * Copyright (c) 2021 Western Digital Corporation or its affiliates.
+ */
 
 #include <linux/mm.h>
 #include <linux/smp.h>
 #include <linux/sched.h>
 #include <asm/sbi.h>
 
+static void ipi_flush_tlb_all(void *info)
+{
+	local_flush_tlb_all();
+}
+
 void flush_tlb_all(void)
 {
-	sbi_remote_sfence_vma(NULL, 0, -1);
+	if (!riscv_use_ipi_for_rfence())
+		sbi_remote_sfence_vma(NULL, 0, -1);
+	else
+		on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
+
+struct flush_range_data {
+	unsigned long start;
+	unsigned long size;
+};
+
+static void ipi_flush_range(void *info)
+{
+	struct flush_range_data *data = info;
+
+	/* local cpu is the only cpu present in cpumask */
+	if (data->size <= PAGE_SIZE)
+		local_flush_tlb_page(data->start);
+	else
+		local_flush_tlb_all();
 }
 
 /*
- * This function must not be called with cmask being null.
+ * This function must not be called with NULL cpumask.
  * Kernel may panic if cmask is NULL.
  */
-static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
-				  unsigned long size)
+static void flush_range(struct cpumask *cmask, unsigned long start,
+			unsigned long size)
 {
+	struct flush_range_data info;
 	struct cpumask hmask;
 	unsigned int cpuid;
 
 	if (cpumask_empty(cmask))
 		return;
 
+	info.start = start;
+	info.size = size;
+
 	cpuid = get_cpu();
 
 	if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) {
-		/* local cpu is the only cpu present in cpumask */
-		if (size <= PAGE_SIZE)
-			local_flush_tlb_page(start);
-		else
-			local_flush_tlb_all();
+		ipi_flush_range(&info);
 	} else {
-		riscv_cpuid_to_hartid_mask(cmask, &hmask);
-		sbi_remote_sfence_vma(cpumask_bits(&hmask), start, size);
+		if (!riscv_use_ipi_for_rfence()) {
+			riscv_cpuid_to_hartid_mask(cmask, &hmask);
+			sbi_remote_sfence_vma(cpumask_bits(&hmask),
+					      start, size);
+		} else {
+			on_each_cpu_mask(cmask, ipi_flush_range, &info, 1);
+		}
 	}
 
 	put_cpu();
@@ -41,16 +75,16 @@ static void __sbi_tlb_flush_range(struct cpumask *cmask, unsigned long start,
 
 void flush_tlb_mm(struct mm_struct *mm)
 {
-	__sbi_tlb_flush_range(mm_cpumask(mm), 0, -1);
+	flush_range(mm_cpumask(mm), 0, -1);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE);
+	flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE);
 }
 
 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 		     unsigned long end)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), start, end - start);
+	flush_range(mm_cpumask(vma->vm_mm), start, end - start);
 }
-- 
2.25.1


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Re: [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible

[Marc Zyngier]

On Sat, 12 Jun 2021 17:04:16 +0100,
Anup Patel <anup.patel@wdc.com> wrote:
> 
> If IPI calls are injected using SBI IPI calls then remote TLB flush
> using SBI RFENCE calls is much faster because using IPIs for remote
> TLB flush would still endup as SBI IPI calls with extra processing
> on kernel side.
> 
> It is now possible to have specialized hardware (such as RISC-V AIA)
> which allows S-mode software to directly inject IPIs without any
> assistance from M-mode runtime firmware.
> 
> This patch extends remote TLB flush functions to use IPIs whenever
> underlying IPI operations are suitable for remote FENCEs.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++---------
>  1 file changed, 48 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 720b443c4528..009c56fa102d 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -1,39 +1,73 @@
>  // SPDX-License-Identifier: GPL-2.0
> +/*
> + * TLB flush implementation.
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + */

I find this a bit odd. You don't mention this addition in the commit
message, and a quick look at the commits touching tlbflush.[ch]
doesn't make the copyright assignment obvious (most commits originate
from either SiFive or Christoph).

In any way, please keep this kind of changes out of this series if
possible, and have a separate discussion on who gets to brag about
this code.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible

[Marc Zyngier]

On Sat, 12 Jun 2021 17:04:16 +0100,
Anup Patel <anup.patel@wdc.com> wrote:
> 
> If IPI calls are injected using SBI IPI calls then remote TLB flush
> using SBI RFENCE calls is much faster because using IPIs for remote
> TLB flush would still endup as SBI IPI calls with extra processing
> on kernel side.
> 
> It is now possible to have specialized hardware (such as RISC-V AIA)
> which allows S-mode software to directly inject IPIs without any
> assistance from M-mode runtime firmware.
> 
> This patch extends remote TLB flush functions to use IPIs whenever
> underlying IPI operations are suitable for remote FENCEs.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++---------
>  1 file changed, 48 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 720b443c4528..009c56fa102d 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -1,39 +1,73 @@
>  // SPDX-License-Identifier: GPL-2.0
> +/*
> + * TLB flush implementation.
> + *
> + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> + */

I find this a bit odd. You don't mention this addition in the commit
message, and a quick look at the commits touching tlbflush.[ch]
doesn't make the copyright assignment obvious (most commits originate
from either SiFive or Christoph).

In any way, please keep this kind of changes out of this series if
possible, and have a separate discussion on who gets to brag about
this code.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible

[Anup Patel]

On Sun, Jun 13, 2021 at 3:03 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sat, 12 Jun 2021 17:04:16 +0100,
> Anup Patel <anup.patel@wdc.com> wrote:
> >
> > If IPI calls are injected using SBI IPI calls then remote TLB flush
> > using SBI RFENCE calls is much faster because using IPIs for remote
> > TLB flush would still endup as SBI IPI calls with extra processing
> > on kernel side.
> >
> > It is now possible to have specialized hardware (such as RISC-V AIA)
> > which allows S-mode software to directly inject IPIs without any
> > assistance from M-mode runtime firmware.
> >
> > This patch extends remote TLB flush functions to use IPIs whenever
> > underlying IPI operations are suitable for remote FENCEs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> >  arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++---------
> >  1 file changed, 48 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> > index 720b443c4528..009c56fa102d 100644
> > --- a/arch/riscv/mm/tlbflush.c
> > +++ b/arch/riscv/mm/tlbflush.c
> > @@ -1,39 +1,73 @@
> >  // SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * TLB flush implementation.
> > + *
> > + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> > + */
>
> I find this a bit odd. You don't mention this addition in the commit
> message, and a quick look at the commits touching tlbflush.[ch]
> doesn't make the copyright assignment obvious (most commits originate
> from either SiFive or Christoph).
>
> In any way, please keep this kind of changes out of this series if
> possible, and have a separate discussion on who gets to brag about
> this code.

I agree it's unrelated change.

The commit history suggest mm/tlbflush.c was added by Christoph
and other commits after that are from Atish (Western Digital).

I will sort this out separately.

Regards,
Anup

>
> Thanks,
>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

Re: [RFC PATCH v1 04/10] RISC-V: Use IPIs for remote TLB flush when possible

[Anup Patel]

On Sun, Jun 13, 2021 at 3:03 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sat, 12 Jun 2021 17:04:16 +0100,
> Anup Patel <anup.patel@wdc.com> wrote:
> >
> > If IPI calls are injected using SBI IPI calls then remote TLB flush
> > using SBI RFENCE calls is much faster because using IPIs for remote
> > TLB flush would still endup as SBI IPI calls with extra processing
> > on kernel side.
> >
> > It is now possible to have specialized hardware (such as RISC-V AIA)
> > which allows S-mode software to directly inject IPIs without any
> > assistance from M-mode runtime firmware.
> >
> > This patch extends remote TLB flush functions to use IPIs whenever
> > underlying IPI operations are suitable for remote FENCEs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> >  arch/riscv/mm/tlbflush.c | 62 +++++++++++++++++++++++++++++++---------
> >  1 file changed, 48 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> > index 720b443c4528..009c56fa102d 100644
> > --- a/arch/riscv/mm/tlbflush.c
> > +++ b/arch/riscv/mm/tlbflush.c
> > @@ -1,39 +1,73 @@
> >  // SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * TLB flush implementation.
> > + *
> > + * Copyright (c) 2021 Western Digital Corporation or its affiliates.
> > + */
>
> I find this a bit odd. You don't mention this addition in the commit
> message, and a quick look at the commits touching tlbflush.[ch]
> doesn't make the copyright assignment obvious (most commits originate
> from either SiFive or Christoph).
>
> In any way, please keep this kind of changes out of this series if
> possible, and have a separate discussion on who gets to brag about
> this code.

I agree it's unrelated change.

The commit history suggest mm/tlbflush.c was added by Christoph
and other commits after that are from Atish (Western Digital).

I will sort this out separately.

Regards,
Anup

>
> Thanks,
>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

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[RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Anup Patel]

The RISC-V ACLINT provides MSWI and SSWI devices for M-mode and
S-mode software interrupts respectively. We add irqchip driver
which provide IPI operations based on ACLINT [M|S]SWI devices
to the Linux RISC-V kernel.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 drivers/irqchip/Kconfig          |  11 +++
 drivers/irqchip/Makefile         |   1 +
 drivers/irqchip/irq-aclint-swi.c | 122 +++++++++++++++++++++++++++++++
 3 files changed, 134 insertions(+)
 create mode 100644 drivers/irqchip/irq-aclint-swi.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 62543a4eccc0..2010d493b03b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -508,6 +508,17 @@ config RISCV_INTC
 
 	   If you don't know what to do here, say Y.
 
+config RISCV_ACLINT_SWI
+	bool "RISC-V Advanced Core Local Interruptor Software Interrupts"
+	depends on RISCV
+	help
+	   This enables support for software interrupts using the Advanced
+	   Core Local Interruptor (ACLINT) found in RISC-V systems.  The
+	   RISC-V ACLINT provides devices for inter-process interrupt and
+	   timer functionality.
+
+	   If you don't know what to do here, say Y.
+
 config SIFIVE_PLIC
 	bool "SiFive Platform-Level Interrupt Controller"
 	depends on RISCV
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index f88cbf36a9d2..a6edf6733c1d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
 obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
 obj-$(CONFIG_CSKY_APB_INTC)		+= irq-csky-apb-intc.o
 obj-$(CONFIG_RISCV_INTC)		+= irq-riscv-intc.o
+obj-$(CONFIG_RISCV_ACLINT_SWI)		+= irq-aclint-swi.o
 obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
 obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
 obj-$(CONFIG_IMX_INTMUX)		+= irq-imx-intmux.o
diff --git a/drivers/irqchip/irq-aclint-swi.c b/drivers/irqchip/irq-aclint-swi.c
new file mode 100644
index 000000000000..f9607072cc7b
--- /dev/null
+++ b/drivers/irqchip/irq-aclint-swi.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#define pr_fmt(fmt) "aclint-swi: " fmt
+#include <linux/cpu.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/smp.h>
+
+struct aclint_swi {
+	void __iomem *sip_reg;
+};
+static DEFINE_PER_CPU(struct aclint_swi, aclint_swis);
+
+static void aclint_swi_send_ipi(const struct cpumask *target)
+{
+	unsigned int cpu;
+	struct aclint_swi *swi;
+
+	for_each_cpu(cpu, target) {
+		swi = per_cpu_ptr(&aclint_swis, cpu);
+		if (!swi->sip_reg) {
+			pr_warn("%s: CPU%d SIP register not available\n",
+				__func__, cpu);
+			continue;
+		}
+
+		writel(1, swi->sip_reg);
+	}
+}
+
+static void aclint_swi_clear_ipi(void)
+{
+	struct aclint_swi *swi = this_cpu_ptr(&aclint_swis);
+
+	if (!swi->sip_reg) {
+		pr_warn("%s: CPU%d SIP register not available\n",
+			__func__, smp_processor_id());
+		return;
+	}
+
+	writel(0, swi->sip_reg);
+}
+
+static struct riscv_ipi_ops aclint_swi_ipi_ops = {
+	.name = "ACLINT-SWI",
+	.use_for_rfence = true,
+	.ipi_inject = aclint_swi_send_ipi,
+	.ipi_clear = aclint_swi_clear_ipi,
+};
+
+static int __init aclint_swi_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	void __iomem *base;
+	struct aclint_swi *swi;
+	u32 i, nr_irqs, nr_cpus = 0;
+
+	/* Map the registers */
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%pOFP: could not map registers\n", node);
+		return -ENODEV;
+	}
+
+	/* Iterarte over each target CPU connected with this ACLINT */
+	nr_irqs = of_irq_count(node);
+	for (i = 0; i < nr_irqs; i++) {
+		struct of_phandle_args parent;
+		int cpu, hartid;
+
+		if (of_irq_parse_one(node, i, &parent)) {
+			pr_err("%pOFP: failed to parse irq %d.\n",
+			       node, i);
+			continue;
+		}
+
+		if (parent.args[0] != RV_IRQ_SOFT) {
+			pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
+			       node, i, parent.args[0]);
+			continue;
+		}
+
+		hartid = riscv_of_parent_hartid(parent.np);
+		if (hartid < 0) {
+			pr_warn("failed to parse hart ID for irq %d.\n", i);
+			continue;
+		}
+
+		cpu = riscv_hartid_to_cpuid(hartid);
+		if (cpu < 0) {
+			pr_warn("Invalid cpuid for irq %d\n", i);
+			continue;
+		}
+
+		swi = per_cpu_ptr(&aclint_swis, cpu);
+		swi->sip_reg = base + i * sizeof(u32);
+		nr_cpus++;
+	}
+
+	/* Announce the ACLINT SWI device */
+	pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
+
+	/* Register the IPI operations */
+	riscv_set_ipi_ops(&aclint_swi_ipi_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_RISCV_M_MODE
+IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-mswi", aclint_swi_init);
+#else
+IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-sswi", aclint_swi_init);
+#endif
-- 
2.25.1

[RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Anup Patel]

The RISC-V ACLINT provides MSWI and SSWI devices for M-mode and
S-mode software interrupts respectively. We add irqchip driver
which provide IPI operations based on ACLINT [M|S]SWI devices
to the Linux RISC-V kernel.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 drivers/irqchip/Kconfig          |  11 +++
 drivers/irqchip/Makefile         |   1 +
 drivers/irqchip/irq-aclint-swi.c | 122 +++++++++++++++++++++++++++++++
 3 files changed, 134 insertions(+)
 create mode 100644 drivers/irqchip/irq-aclint-swi.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 62543a4eccc0..2010d493b03b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -508,6 +508,17 @@ config RISCV_INTC
 
 	   If you don't know what to do here, say Y.
 
+config RISCV_ACLINT_SWI
+	bool "RISC-V Advanced Core Local Interruptor Software Interrupts"
+	depends on RISCV
+	help
+	   This enables support for software interrupts using the Advanced
+	   Core Local Interruptor (ACLINT) found in RISC-V systems.  The
+	   RISC-V ACLINT provides devices for inter-process interrupt and
+	   timer functionality.
+
+	   If you don't know what to do here, say Y.
+
 config SIFIVE_PLIC
 	bool "SiFive Platform-Level Interrupt Controller"
 	depends on RISCV
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index f88cbf36a9d2..a6edf6733c1d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
 obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
 obj-$(CONFIG_CSKY_APB_INTC)		+= irq-csky-apb-intc.o
 obj-$(CONFIG_RISCV_INTC)		+= irq-riscv-intc.o
+obj-$(CONFIG_RISCV_ACLINT_SWI)		+= irq-aclint-swi.o
 obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
 obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
 obj-$(CONFIG_IMX_INTMUX)		+= irq-imx-intmux.o
diff --git a/drivers/irqchip/irq-aclint-swi.c b/drivers/irqchip/irq-aclint-swi.c
new file mode 100644
index 000000000000..f9607072cc7b
--- /dev/null
+++ b/drivers/irqchip/irq-aclint-swi.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Western Digital Corporation or its affiliates.
+ */
+
+#define pr_fmt(fmt) "aclint-swi: " fmt
+#include <linux/cpu.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/smp.h>
+
+struct aclint_swi {
+	void __iomem *sip_reg;
+};
+static DEFINE_PER_CPU(struct aclint_swi, aclint_swis);
+
+static void aclint_swi_send_ipi(const struct cpumask *target)
+{
+	unsigned int cpu;
+	struct aclint_swi *swi;
+
+	for_each_cpu(cpu, target) {
+		swi = per_cpu_ptr(&aclint_swis, cpu);
+		if (!swi->sip_reg) {
+			pr_warn("%s: CPU%d SIP register not available\n",
+				__func__, cpu);
+			continue;
+		}
+
+		writel(1, swi->sip_reg);
+	}
+}
+
+static void aclint_swi_clear_ipi(void)
+{
+	struct aclint_swi *swi = this_cpu_ptr(&aclint_swis);
+
+	if (!swi->sip_reg) {
+		pr_warn("%s: CPU%d SIP register not available\n",
+			__func__, smp_processor_id());
+		return;
+	}
+
+	writel(0, swi->sip_reg);
+}
+
+static struct riscv_ipi_ops aclint_swi_ipi_ops = {
+	.name = "ACLINT-SWI",
+	.use_for_rfence = true,
+	.ipi_inject = aclint_swi_send_ipi,
+	.ipi_clear = aclint_swi_clear_ipi,
+};
+
+static int __init aclint_swi_init(struct device_node *node,
+				  struct device_node *parent)
+{
+	void __iomem *base;
+	struct aclint_swi *swi;
+	u32 i, nr_irqs, nr_cpus = 0;
+
+	/* Map the registers */
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%pOFP: could not map registers\n", node);
+		return -ENODEV;
+	}
+
+	/* Iterarte over each target CPU connected with this ACLINT */
+	nr_irqs = of_irq_count(node);
+	for (i = 0; i < nr_irqs; i++) {
+		struct of_phandle_args parent;
+		int cpu, hartid;
+
+		if (of_irq_parse_one(node, i, &parent)) {
+			pr_err("%pOFP: failed to parse irq %d.\n",
+			       node, i);
+			continue;
+		}
+
+		if (parent.args[0] != RV_IRQ_SOFT) {
+			pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
+			       node, i, parent.args[0]);
+			continue;
+		}
+
+		hartid = riscv_of_parent_hartid(parent.np);
+		if (hartid < 0) {
+			pr_warn("failed to parse hart ID for irq %d.\n", i);
+			continue;
+		}
+
+		cpu = riscv_hartid_to_cpuid(hartid);
+		if (cpu < 0) {
+			pr_warn("Invalid cpuid for irq %d\n", i);
+			continue;
+		}
+
+		swi = per_cpu_ptr(&aclint_swis, cpu);
+		swi->sip_reg = base + i * sizeof(u32);
+		nr_cpus++;
+	}
+
+	/* Announce the ACLINT SWI device */
+	pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
+
+	/* Register the IPI operations */
+	riscv_set_ipi_ops(&aclint_swi_ipi_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_RISCV_M_MODE
+IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-mswi", aclint_swi_init);
+#else
+IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-sswi", aclint_swi_init);
+#endif
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Marc Zyngier]

On Sat, 12 Jun 2021 17:04:17 +0100,
Anup Patel <anup.patel@wdc.com> wrote:
> 
> The RISC-V ACLINT provides MSWI and SSWI devices for M-mode and
> S-mode software interrupts respectively. We add irqchip driver
> which provide IPI operations based on ACLINT [M|S]SWI devices
> to the Linux RISC-V kernel.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  drivers/irqchip/Kconfig          |  11 +++
>  drivers/irqchip/Makefile         |   1 +
>  drivers/irqchip/irq-aclint-swi.c | 122 +++++++++++++++++++++++++++++++
>  3 files changed, 134 insertions(+)
>  create mode 100644 drivers/irqchip/irq-aclint-swi.c
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 62543a4eccc0..2010d493b03b 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -508,6 +508,17 @@ config RISCV_INTC
>  
>  	   If you don't know what to do here, say Y.
>  
> +config RISCV_ACLINT_SWI
> +	bool "RISC-V Advanced Core Local Interruptor Software Interrupts"
> +	depends on RISCV
> +	help
> +	   This enables support for software interrupts using the Advanced
> +	   Core Local Interruptor (ACLINT) found in RISC-V systems.  The
> +	   RISC-V ACLINT provides devices for inter-process interrupt and
> +	   timer functionality.
> +
> +	   If you don't know what to do here, say Y.
> +
>  config SIFIVE_PLIC
>  	bool "SiFive Platform-Level Interrupt Controller"
>  	depends on RISCV
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index f88cbf36a9d2..a6edf6733c1d 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -97,6 +97,7 @@ obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
>  obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
>  obj-$(CONFIG_CSKY_APB_INTC)		+= irq-csky-apb-intc.o
>  obj-$(CONFIG_RISCV_INTC)		+= irq-riscv-intc.o
> +obj-$(CONFIG_RISCV_ACLINT_SWI)		+= irq-aclint-swi.o
>  obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
>  obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
>  obj-$(CONFIG_IMX_INTMUX)		+= irq-imx-intmux.o
> diff --git a/drivers/irqchip/irq-aclint-swi.c b/drivers/irqchip/irq-aclint-swi.c
> new file mode 100644
> index 000000000000..f9607072cc7b
> --- /dev/null
> +++ b/drivers/irqchip/irq-aclint-swi.c
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#define pr_fmt(fmt) "aclint-swi: " fmt
> +#include <linux/cpu.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/smp.h>
> +
> +struct aclint_swi {
> +	void __iomem *sip_reg;
> +};
> +static DEFINE_PER_CPU(struct aclint_swi, aclint_swis);
> +
> +static void aclint_swi_send_ipi(const struct cpumask *target)
> +{
> +	unsigned int cpu;
> +	struct aclint_swi *swi;
> +
> +	for_each_cpu(cpu, target) {
> +		swi = per_cpu_ptr(&aclint_swis, cpu);
> +		if (!swi->sip_reg) {
> +			pr_warn("%s: CPU%d SIP register not available\n",
> +				__func__, cpu);
> +			continue;
> +		}
> +
> +		writel(1, swi->sip_reg);
> +	}
> +}
> +
> +static void aclint_swi_clear_ipi(void)
> +{
> +	struct aclint_swi *swi = this_cpu_ptr(&aclint_swis);
> +
> +	if (!swi->sip_reg) {
> +		pr_warn("%s: CPU%d SIP register not available\n",
> +			__func__, smp_processor_id());
> +		return;
> +	}
> +
> +	writel(0, swi->sip_reg);
> +}
> +
> +static struct riscv_ipi_ops aclint_swi_ipi_ops = {
> +	.name = "ACLINT-SWI",
> +	.use_for_rfence = true,
> +	.ipi_inject = aclint_swi_send_ipi,
> +	.ipi_clear = aclint_swi_clear_ipi,
> +};
> +
> +static int __init aclint_swi_init(struct device_node *node,
> +				  struct device_node *parent)
> +{
> +	void __iomem *base;
> +	struct aclint_swi *swi;
> +	u32 i, nr_irqs, nr_cpus = 0;
> +
> +	/* Map the registers */
> +	base = of_iomap(node, 0);
> +	if (!base) {
> +		pr_err("%pOFP: could not map registers\n", node);
> +		return -ENODEV;
> +	}
> +
> +	/* Iterarte over each target CPU connected with this ACLINT */
> +	nr_irqs = of_irq_count(node);
> +	for (i = 0; i < nr_irqs; i++) {
> +		struct of_phandle_args parent;
> +		int cpu, hartid;
> +
> +		if (of_irq_parse_one(node, i, &parent)) {
> +			pr_err("%pOFP: failed to parse irq %d.\n",
> +			       node, i);
> +			continue;
> +		}
> +
> +		if (parent.args[0] != RV_IRQ_SOFT) {
> +			pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
> +			       node, i, parent.args[0]);
> +			continue;
> +		}
> +
> +		hartid = riscv_of_parent_hartid(parent.np);
> +		if (hartid < 0) {
> +			pr_warn("failed to parse hart ID for irq %d.\n", i);
> +			continue;
> +		}
> +
> +		cpu = riscv_hartid_to_cpuid(hartid);
> +		if (cpu < 0) {
> +			pr_warn("Invalid cpuid for irq %d\n", i);
> +			continue;
> +		}
> +
> +		swi = per_cpu_ptr(&aclint_swis, cpu);
> +		swi->sip_reg = base + i * sizeof(u32);
> +		nr_cpus++;
> +	}
> +
> +	/* Announce the ACLINT SWI device */
> +	pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
> +
> +	/* Register the IPI operations */
> +	riscv_set_ipi_ops(&aclint_swi_ipi_ops);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_RISCV_M_MODE
> +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-mswi", aclint_swi_init);
> +#else
> +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-sswi", aclint_swi_init);
> +#endif

I'm sorry, but this really isn't an irqchip driver. This is a piece of
arch-specific code that uses *none* of the irq subsystem abstractions
apart from the IRQCHIP_DECLARE() macro.

If you implemented it on top of the IPI irq_domain abstraction, making
your IPIs actual IRQs, use the proper interrupt flows and accounting,
then it would make sense to call it an irqchip driver. But as it
stands, it has no place in drivers/irqchip.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Marc Zyngier]

On Sat, 12 Jun 2021 17:04:17 +0100,
Anup Patel <anup.patel@wdc.com> wrote:
> 
> The RISC-V ACLINT provides MSWI and SSWI devices for M-mode and
> S-mode software interrupts respectively. We add irqchip driver
> which provide IPI operations based on ACLINT [M|S]SWI devices
> to the Linux RISC-V kernel.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  drivers/irqchip/Kconfig          |  11 +++
>  drivers/irqchip/Makefile         |   1 +
>  drivers/irqchip/irq-aclint-swi.c | 122 +++++++++++++++++++++++++++++++
>  3 files changed, 134 insertions(+)
>  create mode 100644 drivers/irqchip/irq-aclint-swi.c
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 62543a4eccc0..2010d493b03b 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -508,6 +508,17 @@ config RISCV_INTC
>  
>  	   If you don't know what to do here, say Y.
>  
> +config RISCV_ACLINT_SWI
> +	bool "RISC-V Advanced Core Local Interruptor Software Interrupts"
> +	depends on RISCV
> +	help
> +	   This enables support for software interrupts using the Advanced
> +	   Core Local Interruptor (ACLINT) found in RISC-V systems.  The
> +	   RISC-V ACLINT provides devices for inter-process interrupt and
> +	   timer functionality.
> +
> +	   If you don't know what to do here, say Y.
> +
>  config SIFIVE_PLIC
>  	bool "SiFive Platform-Level Interrupt Controller"
>  	depends on RISCV
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index f88cbf36a9d2..a6edf6733c1d 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -97,6 +97,7 @@ obj-$(CONFIG_QCOM_PDC)			+= qcom-pdc.o
>  obj-$(CONFIG_CSKY_MPINTC)		+= irq-csky-mpintc.o
>  obj-$(CONFIG_CSKY_APB_INTC)		+= irq-csky-apb-intc.o
>  obj-$(CONFIG_RISCV_INTC)		+= irq-riscv-intc.o
> +obj-$(CONFIG_RISCV_ACLINT_SWI)		+= irq-aclint-swi.o
>  obj-$(CONFIG_SIFIVE_PLIC)		+= irq-sifive-plic.o
>  obj-$(CONFIG_IMX_IRQSTEER)		+= irq-imx-irqsteer.o
>  obj-$(CONFIG_IMX_INTMUX)		+= irq-imx-intmux.o
> diff --git a/drivers/irqchip/irq-aclint-swi.c b/drivers/irqchip/irq-aclint-swi.c
> new file mode 100644
> index 000000000000..f9607072cc7b
> --- /dev/null
> +++ b/drivers/irqchip/irq-aclint-swi.c
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + */
> +
> +#define pr_fmt(fmt) "aclint-swi: " fmt
> +#include <linux/cpu.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/smp.h>
> +
> +struct aclint_swi {
> +	void __iomem *sip_reg;
> +};
> +static DEFINE_PER_CPU(struct aclint_swi, aclint_swis);
> +
> +static void aclint_swi_send_ipi(const struct cpumask *target)
> +{
> +	unsigned int cpu;
> +	struct aclint_swi *swi;
> +
> +	for_each_cpu(cpu, target) {
> +		swi = per_cpu_ptr(&aclint_swis, cpu);
> +		if (!swi->sip_reg) {
> +			pr_warn("%s: CPU%d SIP register not available\n",
> +				__func__, cpu);
> +			continue;
> +		}
> +
> +		writel(1, swi->sip_reg);
> +	}
> +}
> +
> +static void aclint_swi_clear_ipi(void)
> +{
> +	struct aclint_swi *swi = this_cpu_ptr(&aclint_swis);
> +
> +	if (!swi->sip_reg) {
> +		pr_warn("%s: CPU%d SIP register not available\n",
> +			__func__, smp_processor_id());
> +		return;
> +	}
> +
> +	writel(0, swi->sip_reg);
> +}
> +
> +static struct riscv_ipi_ops aclint_swi_ipi_ops = {
> +	.name = "ACLINT-SWI",
> +	.use_for_rfence = true,
> +	.ipi_inject = aclint_swi_send_ipi,
> +	.ipi_clear = aclint_swi_clear_ipi,
> +};
> +
> +static int __init aclint_swi_init(struct device_node *node,
> +				  struct device_node *parent)
> +{
> +	void __iomem *base;
> +	struct aclint_swi *swi;
> +	u32 i, nr_irqs, nr_cpus = 0;
> +
> +	/* Map the registers */
> +	base = of_iomap(node, 0);
> +	if (!base) {
> +		pr_err("%pOFP: could not map registers\n", node);
> +		return -ENODEV;
> +	}
> +
> +	/* Iterarte over each target CPU connected with this ACLINT */
> +	nr_irqs = of_irq_count(node);
> +	for (i = 0; i < nr_irqs; i++) {
> +		struct of_phandle_args parent;
> +		int cpu, hartid;
> +
> +		if (of_irq_parse_one(node, i, &parent)) {
> +			pr_err("%pOFP: failed to parse irq %d.\n",
> +			       node, i);
> +			continue;
> +		}
> +
> +		if (parent.args[0] != RV_IRQ_SOFT) {
> +			pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
> +			       node, i, parent.args[0]);
> +			continue;
> +		}
> +
> +		hartid = riscv_of_parent_hartid(parent.np);
> +		if (hartid < 0) {
> +			pr_warn("failed to parse hart ID for irq %d.\n", i);
> +			continue;
> +		}
> +
> +		cpu = riscv_hartid_to_cpuid(hartid);
> +		if (cpu < 0) {
> +			pr_warn("Invalid cpuid for irq %d\n", i);
> +			continue;
> +		}
> +
> +		swi = per_cpu_ptr(&aclint_swis, cpu);
> +		swi->sip_reg = base + i * sizeof(u32);
> +		nr_cpus++;
> +	}
> +
> +	/* Announce the ACLINT SWI device */
> +	pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
> +
> +	/* Register the IPI operations */
> +	riscv_set_ipi_ops(&aclint_swi_ipi_ops);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_RISCV_M_MODE
> +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-mswi", aclint_swi_init);
> +#else
> +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-sswi", aclint_swi_init);
> +#endif

I'm sorry, but this really isn't an irqchip driver. This is a piece of
arch-specific code that uses *none* of the irq subsystem abstractions
apart from the IRQCHIP_DECLARE() macro.

If you implemented it on top of the IPI irq_domain abstraction, making
your IPIs actual IRQs, use the proper interrupt flows and accounting,
then it would make sense to call it an irqchip driver. But as it
stands, it has no place in drivers/irqchip.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Anup Patel]

On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sat, 12 Jun 2021 17:04:17 +0100,
> Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The RISC-V ACLINT provides MSWI and SSWI devices for M-mode and
> > S-mode software interrupts respectively. We add irqchip driver
> > which provide IPI operations based on ACLINT [M|S]SWI devices
> > to the Linux RISC-V kernel.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> >  drivers/irqchip/Kconfig          |  11 +++
> >  drivers/irqchip/Makefile         |   1 +
> >  drivers/irqchip/irq-aclint-swi.c | 122 +++++++++++++++++++++++++++++++
> >  3 files changed, 134 insertions(+)
> >  create mode 100644 drivers/irqchip/irq-aclint-swi.c
> >
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index 62543a4eccc0..2010d493b03b 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -508,6 +508,17 @@ config RISCV_INTC
> >
> >          If you don't know what to do here, say Y.
> >
> > +config RISCV_ACLINT_SWI
> > +     bool "RISC-V Advanced Core Local Interruptor Software Interrupts"
> > +     depends on RISCV
> > +     help
> > +        This enables support for software interrupts using the Advanced
> > +        Core Local Interruptor (ACLINT) found in RISC-V systems.  The
> > +        RISC-V ACLINT provides devices for inter-process interrupt and
> > +        timer functionality.
> > +
> > +        If you don't know what to do here, say Y.
> > +
> >  config SIFIVE_PLIC
> >       bool "SiFive Platform-Level Interrupt Controller"
> >       depends on RISCV
> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> > index f88cbf36a9d2..a6edf6733c1d 100644
> > --- a/drivers/irqchip/Makefile
> > +++ b/drivers/irqchip/Makefile
> > @@ -97,6 +97,7 @@ obj-$(CONFIG_QCOM_PDC)                      += qcom-pdc.o
> >  obj-$(CONFIG_CSKY_MPINTC)            += irq-csky-mpintc.o
> >  obj-$(CONFIG_CSKY_APB_INTC)          += irq-csky-apb-intc.o
> >  obj-$(CONFIG_RISCV_INTC)             += irq-riscv-intc.o
> > +obj-$(CONFIG_RISCV_ACLINT_SWI)               += irq-aclint-swi.o
> >  obj-$(CONFIG_SIFIVE_PLIC)            += irq-sifive-plic.o
> >  obj-$(CONFIG_IMX_IRQSTEER)           += irq-imx-irqsteer.o
> >  obj-$(CONFIG_IMX_INTMUX)             += irq-imx-intmux.o
> > diff --git a/drivers/irqchip/irq-aclint-swi.c b/drivers/irqchip/irq-aclint-swi.c
> > new file mode 100644
> > index 000000000000..f9607072cc7b
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-aclint-swi.c
> > @@ -0,0 +1,122 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> > + */
> > +
> > +#define pr_fmt(fmt) "aclint-swi: " fmt
> > +#include <linux/cpu.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/irq.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/smp.h>
> > +
> > +struct aclint_swi {
> > +     void __iomem *sip_reg;
> > +};
> > +static DEFINE_PER_CPU(struct aclint_swi, aclint_swis);
> > +
> > +static void aclint_swi_send_ipi(const struct cpumask *target)
> > +{
> > +     unsigned int cpu;
> > +     struct aclint_swi *swi;
> > +
> > +     for_each_cpu(cpu, target) {
> > +             swi = per_cpu_ptr(&aclint_swis, cpu);
> > +             if (!swi->sip_reg) {
> > +                     pr_warn("%s: CPU%d SIP register not available\n",
> > +                             __func__, cpu);
> > +                     continue;
> > +             }
> > +
> > +             writel(1, swi->sip_reg);
> > +     }
> > +}
> > +
> > +static void aclint_swi_clear_ipi(void)
> > +{
> > +     struct aclint_swi *swi = this_cpu_ptr(&aclint_swis);
> > +
> > +     if (!swi->sip_reg) {
> > +             pr_warn("%s: CPU%d SIP register not available\n",
> > +                     __func__, smp_processor_id());
> > +             return;
> > +     }
> > +
> > +     writel(0, swi->sip_reg);
> > +}
> > +
> > +static struct riscv_ipi_ops aclint_swi_ipi_ops = {
> > +     .name = "ACLINT-SWI",
> > +     .use_for_rfence = true,
> > +     .ipi_inject = aclint_swi_send_ipi,
> > +     .ipi_clear = aclint_swi_clear_ipi,
> > +};
> > +
> > +static int __init aclint_swi_init(struct device_node *node,
> > +                               struct device_node *parent)
> > +{
> > +     void __iomem *base;
> > +     struct aclint_swi *swi;
> > +     u32 i, nr_irqs, nr_cpus = 0;
> > +
> > +     /* Map the registers */
> > +     base = of_iomap(node, 0);
> > +     if (!base) {
> > +             pr_err("%pOFP: could not map registers\n", node);
> > +             return -ENODEV;
> > +     }
> > +
> > +     /* Iterarte over each target CPU connected with this ACLINT */
> > +     nr_irqs = of_irq_count(node);
> > +     for (i = 0; i < nr_irqs; i++) {
> > +             struct of_phandle_args parent;
> > +             int cpu, hartid;
> > +
> > +             if (of_irq_parse_one(node, i, &parent)) {
> > +                     pr_err("%pOFP: failed to parse irq %d.\n",
> > +                            node, i);
> > +                     continue;
> > +             }
> > +
> > +             if (parent.args[0] != RV_IRQ_SOFT) {
> > +                     pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
> > +                            node, i, parent.args[0]);
> > +                     continue;
> > +             }
> > +
> > +             hartid = riscv_of_parent_hartid(parent.np);
> > +             if (hartid < 0) {
> > +                     pr_warn("failed to parse hart ID for irq %d.\n", i);
> > +                     continue;
> > +             }
> > +
> > +             cpu = riscv_hartid_to_cpuid(hartid);
> > +             if (cpu < 0) {
> > +                     pr_warn("Invalid cpuid for irq %d\n", i);
> > +                     continue;
> > +             }
> > +
> > +             swi = per_cpu_ptr(&aclint_swis, cpu);
> > +             swi->sip_reg = base + i * sizeof(u32);
> > +             nr_cpus++;
> > +     }
> > +
> > +     /* Announce the ACLINT SWI device */
> > +     pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
> > +
> > +     /* Register the IPI operations */
> > +     riscv_set_ipi_ops(&aclint_swi_ipi_ops);
> > +
> > +     return 0;
> > +}
> > +
> > +#ifdef CONFIG_RISCV_M_MODE
> > +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-mswi", aclint_swi_init);
> > +#else
> > +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-sswi", aclint_swi_init);
> > +#endif
>
> I'm sorry, but this really isn't an irqchip driver. This is a piece of
> arch-specific code that uses *none* of the irq subsystem abstractions
> apart from the IRQCHIP_DECLARE() macro.

Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.

Both ACLINT MSWI and SSWI are special devices providing only IPI
support so I will re-think how to fit this.

>
> If you implemented it on top of the IPI irq_domain abstraction, making
> your IPIs actual IRQs, use the proper interrupt flows and accounting,
> then it would make sense to call it an irqchip driver. But as it
> stands, it has no place in drivers/irqchip.

Okay, let me explore IPI irq_domain if it is suitable for this.

Regards,
Anup

>
> Thanks,
>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Anup Patel]

On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sat, 12 Jun 2021 17:04:17 +0100,
> Anup Patel <anup.patel@wdc.com> wrote:
> >
> > The RISC-V ACLINT provides MSWI and SSWI devices for M-mode and
> > S-mode software interrupts respectively. We add irqchip driver
> > which provide IPI operations based on ACLINT [M|S]SWI devices
> > to the Linux RISC-V kernel.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> >  drivers/irqchip/Kconfig          |  11 +++
> >  drivers/irqchip/Makefile         |   1 +
> >  drivers/irqchip/irq-aclint-swi.c | 122 +++++++++++++++++++++++++++++++
> >  3 files changed, 134 insertions(+)
> >  create mode 100644 drivers/irqchip/irq-aclint-swi.c
> >
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index 62543a4eccc0..2010d493b03b 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -508,6 +508,17 @@ config RISCV_INTC
> >
> >          If you don't know what to do here, say Y.
> >
> > +config RISCV_ACLINT_SWI
> > +     bool "RISC-V Advanced Core Local Interruptor Software Interrupts"
> > +     depends on RISCV
> > +     help
> > +        This enables support for software interrupts using the Advanced
> > +        Core Local Interruptor (ACLINT) found in RISC-V systems.  The
> > +        RISC-V ACLINT provides devices for inter-process interrupt and
> > +        timer functionality.
> > +
> > +        If you don't know what to do here, say Y.
> > +
> >  config SIFIVE_PLIC
> >       bool "SiFive Platform-Level Interrupt Controller"
> >       depends on RISCV
> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> > index f88cbf36a9d2..a6edf6733c1d 100644
> > --- a/drivers/irqchip/Makefile
> > +++ b/drivers/irqchip/Makefile
> > @@ -97,6 +97,7 @@ obj-$(CONFIG_QCOM_PDC)                      += qcom-pdc.o
> >  obj-$(CONFIG_CSKY_MPINTC)            += irq-csky-mpintc.o
> >  obj-$(CONFIG_CSKY_APB_INTC)          += irq-csky-apb-intc.o
> >  obj-$(CONFIG_RISCV_INTC)             += irq-riscv-intc.o
> > +obj-$(CONFIG_RISCV_ACLINT_SWI)               += irq-aclint-swi.o
> >  obj-$(CONFIG_SIFIVE_PLIC)            += irq-sifive-plic.o
> >  obj-$(CONFIG_IMX_IRQSTEER)           += irq-imx-irqsteer.o
> >  obj-$(CONFIG_IMX_INTMUX)             += irq-imx-intmux.o
> > diff --git a/drivers/irqchip/irq-aclint-swi.c b/drivers/irqchip/irq-aclint-swi.c
> > new file mode 100644
> > index 000000000000..f9607072cc7b
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-aclint-swi.c
> > @@ -0,0 +1,122 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> > + */
> > +
> > +#define pr_fmt(fmt) "aclint-swi: " fmt
> > +#include <linux/cpu.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/irq.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/smp.h>
> > +
> > +struct aclint_swi {
> > +     void __iomem *sip_reg;
> > +};
> > +static DEFINE_PER_CPU(struct aclint_swi, aclint_swis);
> > +
> > +static void aclint_swi_send_ipi(const struct cpumask *target)
> > +{
> > +     unsigned int cpu;
> > +     struct aclint_swi *swi;
> > +
> > +     for_each_cpu(cpu, target) {
> > +             swi = per_cpu_ptr(&aclint_swis, cpu);
> > +             if (!swi->sip_reg) {
> > +                     pr_warn("%s: CPU%d SIP register not available\n",
> > +                             __func__, cpu);
> > +                     continue;
> > +             }
> > +
> > +             writel(1, swi->sip_reg);
> > +     }
> > +}
> > +
> > +static void aclint_swi_clear_ipi(void)
> > +{
> > +     struct aclint_swi *swi = this_cpu_ptr(&aclint_swis);
> > +
> > +     if (!swi->sip_reg) {
> > +             pr_warn("%s: CPU%d SIP register not available\n",
> > +                     __func__, smp_processor_id());
> > +             return;
> > +     }
> > +
> > +     writel(0, swi->sip_reg);
> > +}
> > +
> > +static struct riscv_ipi_ops aclint_swi_ipi_ops = {
> > +     .name = "ACLINT-SWI",
> > +     .use_for_rfence = true,
> > +     .ipi_inject = aclint_swi_send_ipi,
> > +     .ipi_clear = aclint_swi_clear_ipi,
> > +};
> > +
> > +static int __init aclint_swi_init(struct device_node *node,
> > +                               struct device_node *parent)
> > +{
> > +     void __iomem *base;
> > +     struct aclint_swi *swi;
> > +     u32 i, nr_irqs, nr_cpus = 0;
> > +
> > +     /* Map the registers */
> > +     base = of_iomap(node, 0);
> > +     if (!base) {
> > +             pr_err("%pOFP: could not map registers\n", node);
> > +             return -ENODEV;
> > +     }
> > +
> > +     /* Iterarte over each target CPU connected with this ACLINT */
> > +     nr_irqs = of_irq_count(node);
> > +     for (i = 0; i < nr_irqs; i++) {
> > +             struct of_phandle_args parent;
> > +             int cpu, hartid;
> > +
> > +             if (of_irq_parse_one(node, i, &parent)) {
> > +                     pr_err("%pOFP: failed to parse irq %d.\n",
> > +                            node, i);
> > +                     continue;
> > +             }
> > +
> > +             if (parent.args[0] != RV_IRQ_SOFT) {
> > +                     pr_err("%pOFP: invalid irq %d (hwirq %d)\n",
> > +                            node, i, parent.args[0]);
> > +                     continue;
> > +             }
> > +
> > +             hartid = riscv_of_parent_hartid(parent.np);
> > +             if (hartid < 0) {
> > +                     pr_warn("failed to parse hart ID for irq %d.\n", i);
> > +                     continue;
> > +             }
> > +
> > +             cpu = riscv_hartid_to_cpuid(hartid);
> > +             if (cpu < 0) {
> > +                     pr_warn("Invalid cpuid for irq %d\n", i);
> > +                     continue;
> > +             }
> > +
> > +             swi = per_cpu_ptr(&aclint_swis, cpu);
> > +             swi->sip_reg = base + i * sizeof(u32);
> > +             nr_cpus++;
> > +     }
> > +
> > +     /* Announce the ACLINT SWI device */
> > +     pr_info("%pOFP: providing IPIs for %d CPUs\n", node, nr_cpus);
> > +
> > +     /* Register the IPI operations */
> > +     riscv_set_ipi_ops(&aclint_swi_ipi_ops);
> > +
> > +     return 0;
> > +}
> > +
> > +#ifdef CONFIG_RISCV_M_MODE
> > +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-mswi", aclint_swi_init);
> > +#else
> > +IRQCHIP_DECLARE(riscv_aclint_swi, "riscv,aclint-sswi", aclint_swi_init);
> > +#endif
>
> I'm sorry, but this really isn't an irqchip driver. This is a piece of
> arch-specific code that uses *none* of the irq subsystem abstractions
> apart from the IRQCHIP_DECLARE() macro.

Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.

Both ACLINT MSWI and SSWI are special devices providing only IPI
support so I will re-think how to fit this.

>
> If you implemented it on top of the IPI irq_domain abstraction, making
> your IPIs actual IRQs, use the proper interrupt flows and accounting,
> then it would make sense to call it an irqchip driver. But as it
> stands, it has no place in drivers/irqchip.

Okay, let me explore IPI irq_domain if it is suitable for this.

Regards,
Anup

>
> Thanks,
>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

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Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Marc Zyngier]

On Sun, 13 Jun 2021 13:25:40 +0100,
Anup Patel <anup@brainfault.org> wrote:
> 
> On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > I'm sorry, but this really isn't an irqchip driver. This is a piece of
> > arch-specific code that uses *none* of the irq subsystem abstractions
> > apart from the IRQCHIP_DECLARE() macro.
> 
> Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.
> 
> Both ACLINT MSWI and SSWI are special devices providing only IPI
> support so I will re-think how to fit this.

It depends on how you think of IPIs in your architecture.

arm64 (and even now 32bit) have been moved to a mode where IPIs are
normal interrupts, as it helps with other things such as our pseudo
NMIs, and reduces code duplication. MIPS has done the same for a long
time (they don't have dedicated HW for that).

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Marc Zyngier]

On Sun, 13 Jun 2021 13:25:40 +0100,
Anup Patel <anup@brainfault.org> wrote:
> 
> On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
> >
> > I'm sorry, but this really isn't an irqchip driver. This is a piece of
> > arch-specific code that uses *none* of the irq subsystem abstractions
> > apart from the IRQCHIP_DECLARE() macro.
> 
> Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.
> 
> Both ACLINT MSWI and SSWI are special devices providing only IPI
> support so I will re-think how to fit this.

It depends on how you think of IPIs in your architecture.

arm64 (and even now 32bit) have been moved to a mode where IPIs are
normal interrupts, as it helps with other things such as our pseudo
NMIs, and reduces code duplication. MIPS has done the same for a long
time (they don't have dedicated HW for that).

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Anup Patel]

On Mon, Jun 14, 2021 at 3:08 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 13 Jun 2021 13:25:40 +0100,
> Anup Patel <anup@brainfault.org> wrote:
> >
> > On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
> > >
> > > I'm sorry, but this really isn't an irqchip driver. This is a piece of
> > > arch-specific code that uses *none* of the irq subsystem abstractions
> > > apart from the IRQCHIP_DECLARE() macro.
> >
> > Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.
> >
> > Both ACLINT MSWI and SSWI are special devices providing only IPI
> > support so I will re-think how to fit this.
>
> It depends on how you think of IPIs in your architecture.
>
> arm64 (and even now 32bit) have been moved to a mode where IPIs are
> normal interrupts, as it helps with other things such as our pseudo
> NMIs, and reduces code duplication. MIPS has done the same for a long
> time (they don't have dedicated HW for that).

RISC-V is also moving in a similar direction with the RISC-V advanced
interrupt architecture (AIA) specification which aims at defining an
interrupt controller having MSI support, virtualization support and
scalable for a large number of CPUs. The RISC-V AIA treats IPIs as
normal interrupts.

The RISC-V ACLINT based IPI support is for RISC-V systems which
only need a simple interrupt controller without MSI support and
virtualization support. These systems will not implement RISC-V AIA.

Regards,
Anup

>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

Re: [RFC PATCH v1 05/10] irqchip: Add ACLINT software interrupt driver

[Anup Patel]

On Mon, Jun 14, 2021 at 3:08 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 13 Jun 2021 13:25:40 +0100,
> Anup Patel <anup@brainfault.org> wrote:
> >
> > On Sun, Jun 13, 2021 at 3:11 PM Marc Zyngier <maz@kernel.org> wrote:
> > >
> > > I'm sorry, but this really isn't an irqchip driver. This is a piece of
> > > arch-specific code that uses *none* of the irq subsystem abstractions
> > > apart from the IRQCHIP_DECLARE() macro.
> >
> > Yes, I was not sure we can call it IRQCHIP hence the RFC PATCH.
> >
> > Both ACLINT MSWI and SSWI are special devices providing only IPI
> > support so I will re-think how to fit this.
>
> It depends on how you think of IPIs in your architecture.
>
> arm64 (and even now 32bit) have been moved to a mode where IPIs are
> normal interrupts, as it helps with other things such as our pseudo
> NMIs, and reduces code duplication. MIPS has done the same for a long
> time (they don't have dedicated HW for that).

RISC-V is also moving in a similar direction with the RISC-V advanced
interrupt architecture (AIA) specification which aims at defining an
interrupt controller having MSI support, virtualization support and
scalable for a large number of CPUs. The RISC-V AIA treats IPIs as
normal interrupts.

The RISC-V ACLINT based IPI support is for RISC-V systems which
only need a simple interrupt controller without MSI support and
virtualization support. These systems will not implement RISC-V AIA.

Regards,
Anup

>
>         M.
>
> --
> Without deviation from the norm, progress is not possible.

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[RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine

[Anup Patel]

The QEMU virt machine has provision to emulate ACLINT SWI device
for supervisor-mode so let's select corresponding driver from
SOC_VIRT kconfig option.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/Kconfig.socs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index ed963761fbd2..2687a0902ec4 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -27,6 +27,7 @@ config SOC_VIRT
 	select GOLDFISH
 	select RTC_DRV_GOLDFISH if RTC_CLASS
 	select SIFIVE_PLIC
+	select RISCV_ACLINT_SWI
 	help
 	  This enables support for QEMU Virt Machine.
 
-- 
2.25.1

[RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine

[Anup Patel]

The QEMU virt machine has provision to emulate ACLINT SWI device
for supervisor-mode so let's select corresponding driver from
SOC_VIRT kconfig option.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 arch/riscv/Kconfig.socs | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index ed963761fbd2..2687a0902ec4 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -27,6 +27,7 @@ config SOC_VIRT
 	select GOLDFISH
 	select RTC_DRV_GOLDFISH if RTC_CLASS
 	select SIFIVE_PLIC
+	select RISCV_ACLINT_SWI
 	help
 	  This enables support for QEMU Virt Machine.
 
-- 
2.25.1


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Re: [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine

[Bin Meng]

On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The QEMU virt machine has provision to emulate ACLINT SWI device
> for supervisor-mode so let's select corresponding driver from
> SOC_VIRT kconfig option.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/Kconfig.socs | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 06/10] RISC-V: Select ACLINT SWI driver for virt machine

[Bin Meng]

On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The QEMU virt machine has provision to emulate ACLINT SWI device
> for supervisor-mode so let's select corresponding driver from
> SOC_VIRT kconfig option.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  arch/riscv/Kconfig.socs | 1 +
>  1 file changed, 1 insertion(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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[RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device

[Anup Patel]

The RISC-V ACLINT specification is a modular specification and the
ACLINT MTIMER device is compatible with the M-mode timer functionality
of the CLINT device. This patch extends the CLINT driver to support
both CLINT device and ACLINT MTIMER device.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
 1 file changed, 30 insertions(+), 13 deletions(-)

diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index dfdcd94c1fd5..ca329c450810 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -2,8 +2,15 @@
 /*
  * Copyright (C) 2020 Western Digital Corporation or its affiliates.
  *
- * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
- * CLINT MMIO timer device.
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
+ * MMIO device which is a composite device capable of injecting M-mode
+ * software interrupts and M-mode timer interrupts.
+ *
+ * The RISC-V ACLINT specification is modular in nature and defines
+ * separate devices for M-mode software interrupt (MSWI), M-mode timer
+ * (MTIMER) and S-mode software interrupt (SSWI).
+ *
+ * This is a common driver for CLINT device and ACLINT MTIMER device.
  */
 
 #define pr_fmt(fmt) "clint: " fmt
@@ -21,14 +28,20 @@
 #include <linux/smp.h>
 #include <linux/timex.h>
 
-#ifndef CONFIG_RISCV_M_MODE
+#ifdef CONFIG_RISCV_M_MODE
 #include <asm/clint.h>
+
+u64 __iomem *clint_time_val;
+EXPORT_SYMBOL(clint_time_val);
 #endif
 
 #define CLINT_IPI_OFF		0
 #define CLINT_TIMER_CMP_OFF	0x4000
 #define CLINT_TIMER_VAL_OFF	0xbff8
 
+#define ACLINT_MTIMER_CMP_OFF	0x0000
+#define ACLINT_MTIMER_VAL_OFF	0x7ff8
+
 /* CLINT manages IPI and Timer for RISC-V M-mode  */
 static u32 __iomem *clint_ipi_base;
 static u64 __iomem *clint_timer_cmp;
@@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
 static unsigned long clint_timer_freq;
 static unsigned int clint_timer_irq;
 
-#ifdef CONFIG_RISCV_M_MODE
-u64 __iomem *clint_time_val;
-EXPORT_SYMBOL(clint_time_val);
-#endif
-
 static void clint_send_ipi(const struct cpumask *target)
 {
 	unsigned int cpu;
@@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
 		return -ENODEV;
 	}
 
-	clint_ipi_base = base + CLINT_IPI_OFF;
-	clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
-	clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+	if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {
+		clint_ipi_base = NULL;
+		clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
+		clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
+	} else {
+		clint_ipi_base = base + CLINT_IPI_OFF;
+		clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
+		clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+	}
 	clint_timer_freq = riscv_timebase;
 
 #ifdef CONFIG_RISCV_M_MODE
@@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
 		goto fail_free_irq;
 	}
 
-	riscv_set_ipi_ops(&clint_ipi_ops);
-	clint_clear_ipi();
+	if (clint_ipi_base) {
+		riscv_set_ipi_ops(&clint_ipi_ops);
+		clint_clear_ipi();
+	}
 
 	return 0;
 
@@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
 
 TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
 TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);
-- 
2.25.1

[RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device

[Anup Patel]

The RISC-V ACLINT specification is a modular specification and the
ACLINT MTIMER device is compatible with the M-mode timer functionality
of the CLINT device. This patch extends the CLINT driver to support
both CLINT device and ACLINT MTIMER device.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
 1 file changed, 30 insertions(+), 13 deletions(-)

diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index dfdcd94c1fd5..ca329c450810 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -2,8 +2,15 @@
 /*
  * Copyright (C) 2020 Western Digital Corporation or its affiliates.
  *
- * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
- * CLINT MMIO timer device.
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
+ * MMIO device which is a composite device capable of injecting M-mode
+ * software interrupts and M-mode timer interrupts.
+ *
+ * The RISC-V ACLINT specification is modular in nature and defines
+ * separate devices for M-mode software interrupt (MSWI), M-mode timer
+ * (MTIMER) and S-mode software interrupt (SSWI).
+ *
+ * This is a common driver for CLINT device and ACLINT MTIMER device.
  */
 
 #define pr_fmt(fmt) "clint: " fmt
@@ -21,14 +28,20 @@
 #include <linux/smp.h>
 #include <linux/timex.h>
 
-#ifndef CONFIG_RISCV_M_MODE
+#ifdef CONFIG_RISCV_M_MODE
 #include <asm/clint.h>
+
+u64 __iomem *clint_time_val;
+EXPORT_SYMBOL(clint_time_val);
 #endif
 
 #define CLINT_IPI_OFF		0
 #define CLINT_TIMER_CMP_OFF	0x4000
 #define CLINT_TIMER_VAL_OFF	0xbff8
 
+#define ACLINT_MTIMER_CMP_OFF	0x0000
+#define ACLINT_MTIMER_VAL_OFF	0x7ff8
+
 /* CLINT manages IPI and Timer for RISC-V M-mode  */
 static u32 __iomem *clint_ipi_base;
 static u64 __iomem *clint_timer_cmp;
@@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
 static unsigned long clint_timer_freq;
 static unsigned int clint_timer_irq;
 
-#ifdef CONFIG_RISCV_M_MODE
-u64 __iomem *clint_time_val;
-EXPORT_SYMBOL(clint_time_val);
-#endif
-
 static void clint_send_ipi(const struct cpumask *target)
 {
 	unsigned int cpu;
@@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
 		return -ENODEV;
 	}
 
-	clint_ipi_base = base + CLINT_IPI_OFF;
-	clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
-	clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+	if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {
+		clint_ipi_base = NULL;
+		clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
+		clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
+	} else {
+		clint_ipi_base = base + CLINT_IPI_OFF;
+		clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
+		clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+	}
 	clint_timer_freq = riscv_timebase;
 
 #ifdef CONFIG_RISCV_M_MODE
@@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
 		goto fail_free_irq;
 	}
 
-	riscv_set_ipi_ops(&clint_ipi_ops);
-	clint_clear_ipi();
+	if (clint_ipi_base) {
+		riscv_set_ipi_ops(&clint_ipi_ops);
+		clint_clear_ipi();
+	}
 
 	return 0;
 
@@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
 
 TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
 TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);
-- 
2.25.1


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Re: [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device

[Bin Meng]

On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V ACLINT specification is a modular specification and the
> ACLINT MTIMER device is compatible with the M-mode timer functionality
> of the CLINT device. This patch extends the CLINT driver to support
> both CLINT device and ACLINT MTIMER device.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
>  1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
> index dfdcd94c1fd5..ca329c450810 100644
> --- a/drivers/clocksource/timer-clint.c
> +++ b/drivers/clocksource/timer-clint.c
> @@ -2,8 +2,15 @@
>  /*
>   * Copyright (C) 2020 Western Digital Corporation or its affiliates.
>   *
> - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
> - * CLINT MMIO timer device.
> + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
> + * MMIO device which is a composite device capable of injecting M-mode
> + * software interrupts and M-mode timer interrupts.
> + *
> + * The RISC-V ACLINT specification is modular in nature and defines
> + * separate devices for M-mode software interrupt (MSWI), M-mode timer
> + * (MTIMER) and S-mode software interrupt (SSWI).
> + *
> + * This is a common driver for CLINT device and ACLINT MTIMER device.
>   */
>
>  #define pr_fmt(fmt) "clint: " fmt
> @@ -21,14 +28,20 @@
>  #include <linux/smp.h>
>  #include <linux/timex.h>
>
> -#ifndef CONFIG_RISCV_M_MODE
> +#ifdef CONFIG_RISCV_M_MODE
>  #include <asm/clint.h>
> +
> +u64 __iomem *clint_time_val;
> +EXPORT_SYMBOL(clint_time_val);
>  #endif
>
>  #define CLINT_IPI_OFF          0
>  #define CLINT_TIMER_CMP_OFF    0x4000
>  #define CLINT_TIMER_VAL_OFF    0xbff8
>
> +#define ACLINT_MTIMER_CMP_OFF  0x0000
> +#define ACLINT_MTIMER_VAL_OFF  0x7ff8
> +
>  /* CLINT manages IPI and Timer for RISC-V M-mode  */
>  static u32 __iomem *clint_ipi_base;
>  static u64 __iomem *clint_timer_cmp;
> @@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
>  static unsigned long clint_timer_freq;
>  static unsigned int clint_timer_irq;
>
> -#ifdef CONFIG_RISCV_M_MODE
> -u64 __iomem *clint_time_val;
> -EXPORT_SYMBOL(clint_time_val);
> -#endif
> -
>  static void clint_send_ipi(const struct cpumask *target)
>  {
>         unsigned int cpu;
> @@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
>                 return -ENODEV;
>         }
>
> -       clint_ipi_base = base + CLINT_IPI_OFF;
> -       clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> -       clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> +       if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {

This patch should come after patch 8 which introduces this DT binding

> +               clint_ipi_base = NULL;
> +               clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
> +               clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
> +       } else {
> +               clint_ipi_base = base + CLINT_IPI_OFF;
> +               clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> +               clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> +       }
>         clint_timer_freq = riscv_timebase;
>
>  #ifdef CONFIG_RISCV_M_MODE
> @@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
>                 goto fail_free_irq;
>         }
>
> -       riscv_set_ipi_ops(&clint_ipi_ops);
> -       clint_clear_ipi();
> +       if (clint_ipi_base) {
> +               riscv_set_ipi_ops(&clint_ipi_ops);
> +               clint_clear_ipi();
> +       }
>
>         return 0;
>
> @@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
>
>  TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
>  TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
> +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 07/10] clocksource: clint: Add support for ACLINT MTIMER device

[Bin Meng]

On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The RISC-V ACLINT specification is a modular specification and the
> ACLINT MTIMER device is compatible with the M-mode timer functionality
> of the CLINT device. This patch extends the CLINT driver to support
> both CLINT device and ACLINT MTIMER device.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
>  1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
> index dfdcd94c1fd5..ca329c450810 100644
> --- a/drivers/clocksource/timer-clint.c
> +++ b/drivers/clocksource/timer-clint.c
> @@ -2,8 +2,15 @@
>  /*
>   * Copyright (C) 2020 Western Digital Corporation or its affiliates.
>   *
> - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
> - * CLINT MMIO timer device.
> + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
> + * MMIO device which is a composite device capable of injecting M-mode
> + * software interrupts and M-mode timer interrupts.
> + *
> + * The RISC-V ACLINT specification is modular in nature and defines
> + * separate devices for M-mode software interrupt (MSWI), M-mode timer
> + * (MTIMER) and S-mode software interrupt (SSWI).
> + *
> + * This is a common driver for CLINT device and ACLINT MTIMER device.
>   */
>
>  #define pr_fmt(fmt) "clint: " fmt
> @@ -21,14 +28,20 @@
>  #include <linux/smp.h>
>  #include <linux/timex.h>
>
> -#ifndef CONFIG_RISCV_M_MODE
> +#ifdef CONFIG_RISCV_M_MODE
>  #include <asm/clint.h>
> +
> +u64 __iomem *clint_time_val;
> +EXPORT_SYMBOL(clint_time_val);
>  #endif
>
>  #define CLINT_IPI_OFF          0
>  #define CLINT_TIMER_CMP_OFF    0x4000
>  #define CLINT_TIMER_VAL_OFF    0xbff8
>
> +#define ACLINT_MTIMER_CMP_OFF  0x0000
> +#define ACLINT_MTIMER_VAL_OFF  0x7ff8
> +
>  /* CLINT manages IPI and Timer for RISC-V M-mode  */
>  static u32 __iomem *clint_ipi_base;
>  static u64 __iomem *clint_timer_cmp;
> @@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
>  static unsigned long clint_timer_freq;
>  static unsigned int clint_timer_irq;
>
> -#ifdef CONFIG_RISCV_M_MODE
> -u64 __iomem *clint_time_val;
> -EXPORT_SYMBOL(clint_time_val);
> -#endif
> -
>  static void clint_send_ipi(const struct cpumask *target)
>  {
>         unsigned int cpu;
> @@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
>                 return -ENODEV;
>         }
>
> -       clint_ipi_base = base + CLINT_IPI_OFF;
> -       clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> -       clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> +       if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {

This patch should come after patch 8 which introduces this DT binding

> +               clint_ipi_base = NULL;
> +               clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
> +               clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
> +       } else {
> +               clint_ipi_base = base + CLINT_IPI_OFF;
> +               clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> +               clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> +       }
>         clint_timer_freq = riscv_timebase;
>
>  #ifdef CONFIG_RISCV_M_MODE
> @@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
>                 goto fail_free_irq;
>         }
>
> -       riscv_set_ipi_ops(&clint_ipi_ops);
> -       clint_clear_ipi();
> +       if (clint_ipi_base) {
> +               riscv_set_ipi_ops(&clint_ipi_ops);
> +               clint_clear_ipi();
> +       }
>
>         return 0;
>
> @@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
>
>  TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
>  TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
> +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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[RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings

[Anup Patel]

We add DT bindings documentation for the ACLINT MTIMER device
found on RISC-V SOCs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../bindings/timer/riscv,aclint-mtimer.yaml   | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml

diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
new file mode 100644
index 000000000000..21c718f8ab4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT M-level Timer
+
+maintainers:
+  - Anup Patel <anup.patel@wdc.com>
+
+description:
+  RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
+  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
+  ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
+  at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+  The ACLINT MTIMER device directly connect to the M-level timer interrupt
+  lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
+  interrupt controller is the parent interrupt controller for the ACLINT
+  MTIMER device.
+
+  The clock frequency of ACLINT is specified via "timebase-frequency" DT
+  property of "/cpus" DT node. The "timebase-frequency" DT property is
+  described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+  compatible:
+    items:
+      - const: riscv,aclint-mtimer
+
+    description:
+      Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    timer@2004000 {
+      compatible = "riscv,aclint-mtimer";
+      interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>;
+      reg = <0x2004000 0x8000>;
+    };
+...
-- 
2.25.1

[RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings

[Anup Patel]

We add DT bindings documentation for the ACLINT MTIMER device
found on RISC-V SOCs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../bindings/timer/riscv,aclint-mtimer.yaml   | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml

diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
new file mode 100644
index 000000000000..21c718f8ab4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT M-level Timer
+
+maintainers:
+  - Anup Patel <anup.patel@wdc.com>
+
+description:
+  RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
+  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
+  ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
+  at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+  The ACLINT MTIMER device directly connect to the M-level timer interrupt
+  lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
+  interrupt controller is the parent interrupt controller for the ACLINT
+  MTIMER device.
+
+  The clock frequency of ACLINT is specified via "timebase-frequency" DT
+  property of "/cpus" DT node. The "timebase-frequency" DT property is
+  described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+  compatible:
+    items:
+      - const: riscv,aclint-mtimer
+
+    description:
+      Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    timer@2004000 {
+      compatible = "riscv,aclint-mtimer";
+      interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>;
+      reg = <0x2004000 0x8000>;
+    };
+...
-- 
2.25.1


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Re: [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings

[Bin Meng]

On Sun, Jun 13, 2021 at 12:09 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add DT bindings documentation for the ACLINT MTIMER device
> found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  .../bindings/timer/riscv,aclint-mtimer.yaml   | 55 +++++++++++++++++++
>  1 file changed, 55 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..21c718f8ab4c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT M-level Timer
> +
> +maintainers:
> +  - Anup Patel <anup.patel@wdc.com>
> +
> +description:
> +  RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
> +  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
> +  ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
> +  at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> +  The ACLINT MTIMER device directly connect to the M-level timer interrupt

connects

> +  lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
> +  interrupt controller is the parent interrupt controller for the ACLINT
> +  MTIMER device.
> +
> +  The clock frequency of ACLINT is specified via "timebase-frequency" DT
> +  property of "/cpus" DT node. The "timebase-frequency" DT property is
> +  described in Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: riscv,aclint-mtimer
> +
> +    description:
> +      Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts-extended:
> +    minItems: 1
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +
> +examples:
> +  - |
> +    timer@2004000 {
> +      compatible = "riscv,aclint-mtimer";
> +      interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>;
> +      reg = <0x2004000 0x8000>;
> +    };
> +...

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 08/10] dt-bindings: timer: Add ACLINT MTIMER bindings

[Bin Meng]

On Sun, Jun 13, 2021 at 12:09 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add DT bindings documentation for the ACLINT MTIMER device
> found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  .../bindings/timer/riscv,aclint-mtimer.yaml   | 55 +++++++++++++++++++
>  1 file changed, 55 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..21c718f8ab4c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT M-level Timer
> +
> +maintainers:
> +  - Anup Patel <anup.patel@wdc.com>
> +
> +description:
> +  RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
> +  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
> +  ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
> +  at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> +  The ACLINT MTIMER device directly connect to the M-level timer interrupt

connects

> +  lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
> +  interrupt controller is the parent interrupt controller for the ACLINT
> +  MTIMER device.
> +
> +  The clock frequency of ACLINT is specified via "timebase-frequency" DT
> +  property of "/cpus" DT node. The "timebase-frequency" DT property is
> +  described in Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: riscv,aclint-mtimer
> +
> +    description:
> +      Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts-extended:
> +    minItems: 1
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +
> +examples:
> +  - |
> +    timer@2004000 {
> +      compatible = "riscv,aclint-mtimer";
> +      interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>;
> +      reg = <0x2004000 0x8000>;
> +    };
> +...

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv

[RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings

[Anup Patel]

We add DT bindings documentation for the ACLINT MSWI and SSWI
devices found on RISC-V SOCs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../riscv,aclint-swi.yaml                     | 82 +++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
new file mode 100644
index 000000000000..bed15411c18f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT Software Interrupt Devices
+
+maintainers:
+  - Anup Patel <anup.patel@wdc.com>
+
+description:
+  RISC-V SOCs include an implementation of the M-level software interrupt
+  (MSWI) device and the S-level software interrupt (SSWI) device defined
+  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
+
+  The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
+  specification located at
+  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+  The ACLINT MSWI and SSWI devices directly connect to the M-level and
+  S-level software interrupt lines of various HARTs (or CPUs) respectively
+  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
+  parent interrupt controller for the ACLINT MSWI and SSWI devices.
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - riscv,aclint-mswi
+          - riscv,aclint-sswi
+
+    description:
+      Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
+      "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 0
+
+  interrupts-extended:
+    minItems: 1
+
+  interrupt-controller: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+  - interrupt-controller
+  - "#interrupt-cells"
+
+examples:
+  - |
+    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
+
+    interrupt-controller@2000000 {
+      compatible = "riscv,aclint-mswi";
+      interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
+      reg = <0x2000000 0x4000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
+    };
+
+  - |
+    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
+
+    interrupt-controller@2100000 {
+      compatible = "riscv,aclint-sswi";
+      interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
+      reg = <0x2100000 0x4000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
+    };
+...
-- 
2.25.1

[RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings

[Anup Patel]

We add DT bindings documentation for the ACLINT MSWI and SSWI
devices found on RISC-V SOCs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../riscv,aclint-swi.yaml                     | 82 +++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
new file mode 100644
index 000000000000..bed15411c18f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT Software Interrupt Devices
+
+maintainers:
+  - Anup Patel <anup.patel@wdc.com>
+
+description:
+  RISC-V SOCs include an implementation of the M-level software interrupt
+  (MSWI) device and the S-level software interrupt (SSWI) device defined
+  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
+
+  The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
+  specification located at
+  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+  The ACLINT MSWI and SSWI devices directly connect to the M-level and
+  S-level software interrupt lines of various HARTs (or CPUs) respectively
+  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
+  parent interrupt controller for the ACLINT MSWI and SSWI devices.
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - riscv,aclint-mswi
+          - riscv,aclint-sswi
+
+    description:
+      Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
+      "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
+
+  reg:
+    maxItems: 1
+
+  "#interrupt-cells":
+    const: 0
+
+  interrupts-extended:
+    minItems: 1
+
+  interrupt-controller: true
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+  - interrupt-controller
+  - "#interrupt-cells"
+
+examples:
+  - |
+    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
+
+    interrupt-controller@2000000 {
+      compatible = "riscv,aclint-mswi";
+      interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
+      reg = <0x2000000 0x4000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
+    };
+
+  - |
+    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
+
+    interrupt-controller@2100000 {
+      compatible = "riscv,aclint-sswi";
+      interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
+      reg = <0x2100000 0x4000>;
+      interrupt-controller;
+      #interrupt-cells = <0>;
+    };
+...
-- 
2.25.1


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Re: [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings

[Bin Meng]

On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>

The commit title should say "interrupt-controller" instead of "timer"

> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  .../riscv,aclint-swi.yaml                     | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..bed15411c18f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> +  - Anup Patel <anup.patel@wdc.com>
> +
> +description:
> +  RISC-V SOCs include an implementation of the M-level software interrupt
> +  (MSWI) device and the S-level software interrupt (SSWI) device defined
> +  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> +  The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT

nits: please remove the ( )

> +  specification located at
> +  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> +  The ACLINT MSWI and SSWI devices directly connect to the M-level and
> +  S-level software interrupt lines of various HARTs (or CPUs) respectively
> +  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> +  parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - riscv,aclint-mswi
> +          - riscv,aclint-sswi
> +
> +    description:
> +      Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
> +      "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#interrupt-cells":
> +    const: 0
> +
> +  interrupts-extended:
> +    minItems: 1
> +
> +  interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +examples:
> +  - |
> +    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> +    interrupt-controller@2000000 {
> +      compatible = "riscv,aclint-mswi";
> +      interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
> +      reg = <0x2000000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +
> +  - |
> +    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> +    interrupt-controller@2100000 {
> +      compatible = "riscv,aclint-sswi";
> +      interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
> +      reg = <0x2100000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +...

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings

[Bin Meng]

On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>

The commit title should say "interrupt-controller" instead of "timer"

> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  .../riscv,aclint-swi.yaml                     | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..bed15411c18f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> +  - Anup Patel <anup.patel@wdc.com>
> +
> +description:
> +  RISC-V SOCs include an implementation of the M-level software interrupt
> +  (MSWI) device and the S-level software interrupt (SSWI) device defined
> +  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> +  The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT

nits: please remove the ( )

> +  specification located at
> +  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> +  The ACLINT MSWI and SSWI devices directly connect to the M-level and
> +  S-level software interrupt lines of various HARTs (or CPUs) respectively
> +  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> +  parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - riscv,aclint-mswi
> +          - riscv,aclint-sswi
> +
> +    description:
> +      Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
> +      "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#interrupt-cells":
> +    const: 0
> +
> +  interrupts-extended:
> +    minItems: 1
> +
> +  interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +examples:
> +  - |
> +    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> +    interrupt-controller@2000000 {
> +      compatible = "riscv,aclint-mswi";
> +      interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
> +      reg = <0x2000000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +
> +  - |
> +    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> +    interrupt-controller@2100000 {
> +      compatible = "riscv,aclint-sswi";
> +      interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
> +      reg = <0x2100000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +...

Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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Re: [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings

[Rob Herring]

On Sat, Jun 12, 2021 at 09:34:21PM +0530, Anup Patel wrote:
> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  .../riscv,aclint-swi.yaml                     | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..bed15411c18f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> +  - Anup Patel <anup.patel@wdc.com>
> +
> +description:
> +  RISC-V SOCs include an implementation of the M-level software interrupt
> +  (MSWI) device and the S-level software interrupt (SSWI) device defined
> +  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> +  The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
> +  specification located at
> +  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> +  The ACLINT MSWI and SSWI devices directly connect to the M-level and
> +  S-level software interrupt lines of various HARTs (or CPUs) respectively
> +  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> +  parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - riscv,aclint-mswi
> +          - riscv,aclint-sswi
> +
> +    description:
> +      Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
> +      "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".

Don't write descriptions that should be schemas.

Is there no vendor or specific implementation yet?

You can write "pattern: '.*,.*-aclint-sswi$' as an entry with a comment 
to add specific compatibles.

> +
> +  reg:
> +    maxItems: 1
> +
> +  "#interrupt-cells":
> +    const: 0
> +
> +  interrupts-extended:
> +    minItems: 1

maxItems? 

> +
> +  interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +examples:
> +  - |
> +    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> +    interrupt-controller@2000000 {
> +      compatible = "riscv,aclint-mswi";
> +      interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;

format as: <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>

> +      reg = <0x2000000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +
> +  - |
> +    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> +    interrupt-controller@2100000 {
> +      compatible = "riscv,aclint-sswi";
> +      interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
> +      reg = <0x2100000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +...
> -- 
> 2.25.1
> 
> 

Re: [RFC PATCH v1 09/10] dt-bindings: timer: Add ACLINT MSWI and SSWI bindings

[Rob Herring]

On Sat, Jun 12, 2021 at 09:34:21PM +0530, Anup Patel wrote:
> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
> 
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  .../riscv,aclint-swi.yaml                     | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..bed15411c18f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> +  - Anup Patel <anup.patel@wdc.com>
> +
> +description:
> +  RISC-V SOCs include an implementation of the M-level software interrupt
> +  (MSWI) device and the S-level software interrupt (SSWI) device defined
> +  in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> +  The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
> +  specification located at
> +  https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> +  The ACLINT MSWI and SSWI devices directly connect to the M-level and
> +  S-level software interrupt lines of various HARTs (or CPUs) respectively
> +  so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> +  parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> +  - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - riscv,aclint-mswi
> +          - riscv,aclint-sswi
> +
> +    description:
> +      Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
> +      "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".

Don't write descriptions that should be schemas.

Is there no vendor or specific implementation yet?

You can write "pattern: '.*,.*-aclint-sswi$' as an entry with a comment 
to add specific compatibles.

> +
> +  reg:
> +    maxItems: 1
> +
> +  "#interrupt-cells":
> +    const: 0
> +
> +  interrupts-extended:
> +    minItems: 1

maxItems? 

> +
> +  interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts-extended
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +
> +examples:
> +  - |
> +    // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> +    interrupt-controller@2000000 {
> +      compatible = "riscv,aclint-mswi";
> +      interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;

format as: <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>

> +      reg = <0x2000000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +
> +  - |
> +    // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> +    interrupt-controller@2100000 {
> +      compatible = "riscv,aclint-sswi";
> +      interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
> +      reg = <0x2100000 0x4000>;
> +      interrupt-controller;
> +      #interrupt-cells = <0>;
> +    };
> +...
> -- 
> 2.25.1
> 
> 

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[RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers

[Anup Patel]

Add myself as maintainer for RISC-V ACLINT drivers.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b706dd20ff2b..aee0123438f2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15693,6 +15693,15 @@ S:	Maintained
 F:	drivers/mtd/nand/raw/r852.c
 F:	drivers/mtd/nand/raw/r852.h
 
+RISC-V ACLINT DRIVERS
+M:	Anup Patel <anup.patel@wdc.com>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+F:	Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
+F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
+F:	drivers/clocksource/timer-clint.c
+F:	drivers/irqchip/irq-aclint-swi.c
+
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
 M:	Palmer Dabbelt <palmer@dabbelt.com>
-- 
2.25.1

[RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers

[Anup Patel]

Add myself as maintainer for RISC-V ACLINT drivers.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b706dd20ff2b..aee0123438f2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15693,6 +15693,15 @@ S:	Maintained
 F:	drivers/mtd/nand/raw/r852.c
 F:	drivers/mtd/nand/raw/r852.h
 
+RISC-V ACLINT DRIVERS
+M:	Anup Patel <anup.patel@wdc.com>
+L:	linux-riscv@lists.infradead.org
+S:	Supported
+F:	Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
+F:	Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
+F:	drivers/clocksource/timer-clint.c
+F:	drivers/irqchip/irq-aclint-swi.c
+
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
 M:	Palmer Dabbelt <palmer@dabbelt.com>
-- 
2.25.1


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Re: [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers

[Bin Meng]

On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> Add myself as maintainer for RISC-V ACLINT drivers.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  MAINTAINERS | 9 +++++++++
>  1 file changed, 9 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [RFC PATCH v1 10/10] MAINTAINERS: Add entry for RISC-V ACLINT drivers

[Bin Meng]

On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> Add myself as maintainer for RISC-V ACLINT drivers.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
>  MAINTAINERS | 9 +++++++++
>  1 file changed, 9 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

_______________________________________________
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