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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller
Date: Tue, 4 Jun 2019 10:48:42 +0800	[thread overview]
Message-ID: <CAEUhbmVLGCodUW8eF8YJjNV5AuvyJL+YW+5EbnEjSeOY6rg53Q@mail.gmail.com> (raw)
In-Reply-To: <20190528093914.4672-4-uboot@andestech.com>

Hi Rick,

On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
>
> From: Rick Chen <rick@andestech.com>
>
> Select the v5l2 UCLASS_CACHE driver for AE350.
>
> Signed-off-by: Rick Chen <rick@andestech.com>
> Cc: Greentime Hu <greentime@andestech.com>
> ---
>  board/AndesTech/ax25-ae350/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
> index 5e682b6..dd299d9 100644
> --- a/board/AndesTech/ax25-ae350/Kconfig
> +++ b/board/AndesTech/ax25-ae350/Kconfig
> @@ -25,5 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>         def_bool y
>         select RISCV_NDS
>         imply SMP
> +       imply V5L2_CACHE

I believe L2 cache is a CPU specific feature, hence this should be
implied from arch/riscv/cpu/ax25/Kconfig

Regards,
Bin

  reply	other threads:[~2019-06-04  2:48 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-28  9:39 [U-Boot] [PATCH 0/6] Support Andes RISC-V l2cache on AE350 platform Andes
2019-05-28  9:39 ` [U-Boot] [PATCH 1/6] dm: cache: add v5l2 cache controller driver Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  8:58     ` Rick Chen
2019-06-09 17:56       ` Auer, Lukas
2019-06-10  2:26         ` Rick Chen
2019-06-10  2:32           ` Bin Meng
2019-06-12  6:32             ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 2/6] riscv: ae350: use the v5l2 driver to configure the cache Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:02     ` Rick Chen
2019-06-05  9:04     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller Andes
2019-06-04  2:48   ` Bin Meng [this message]
2019-06-05  9:25     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 4/6] riscv: cache: Flush L2 cache before jump to linux Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:24     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:33     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:38     ` Rick Chen
2019-06-05  9:39       ` Bin Meng
2019-06-09 17:57         ` Auer, Lukas

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