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From: Rick Chen <rickchen36@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/6] riscv: ae350: use the v5l2 driver to configure the cache
Date: Wed, 5 Jun 2019 17:02:35 +0800	[thread overview]
Message-ID: <CAN5B=eL-+CfmBFyHjVThGQMqd0CmQ4t26g0CmJ+ZHpMr_k-kKQ@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmXg2_KNH54NXhxLy=_PxoPPF3VkNLUwoNreTBEX8sCvZg@mail.gmail.com>

Bin Meng <bmeng.cn@gmail.com> 於 2019年6月4日 週二 上午10:48寫道:
>
> Hi Rick,
>
> On Tue, May 28, 2019 at 5:44 PM Andes <uboot@andestech.com> wrote:
> >
> > From: Rick Chen <rick@andestech.com>
> >
> > Find the UCLASS_CACHE driver to configure the cache controller's
> > settings.
> >
> > Signed-off-by: Rick Chen <rick@andestech.com>
> > Cc: Greentime Hu <greentime@andestech.com>
> > ---
> >  board/AndesTech/ax25-ae350/ax25-ae350.c | 15 +++++++++++++++
> >  1 file changed, 15 insertions(+)
> >
> > diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c
> > index 3d65ce7..686ec4a 100644
> > --- a/board/AndesTech/ax25-ae350/ax25-ae350.c
> > +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
> > @@ -11,6 +11,7 @@
> >  #include <linux/io.h>
> >  #include <faraday/ftsmc020.h>
> >  #include <fdtdec.h>
> > +#include <dm.h>
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> > @@ -93,10 +94,24 @@ int smc_init(void)
> >         return 0;
> >  }
> >
> > +int v5l2_init(void)
> > +{
> > +       struct udevice *dev;
> > +       int ret;
> > +
> > +       ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
> > +
> > +       if (ret)
> > +               return ret;
> > +
> > +       return 0;
> > +}
> > +
> >  #ifdef CONFIG_BOARD_EARLY_INIT_F
> >  int board_early_init_f(void)
> >  {
> >         smc_init();
> > +       v5l2_init();
>
> Please check the return value here, or you can make v512_init() returns void.
>
> >
> >         return 0;
> >  }
> > --
>
> Regards,
> Bin

  reply	other threads:[~2019-06-05  9:02 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-28  9:39 [U-Boot] [PATCH 0/6] Support Andes RISC-V l2cache on AE350 platform Andes
2019-05-28  9:39 ` [U-Boot] [PATCH 1/6] dm: cache: add v5l2 cache controller driver Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  8:58     ` Rick Chen
2019-06-09 17:56       ` Auer, Lukas
2019-06-10  2:26         ` Rick Chen
2019-06-10  2:32           ` Bin Meng
2019-06-12  6:32             ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 2/6] riscv: ae350: use the v5l2 driver to configure the cache Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:02     ` Rick Chen [this message]
2019-06-05  9:04     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:25     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 4/6] riscv: cache: Flush L2 cache before jump to linux Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:24     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:33     ` Rick Chen
2019-05-28  9:39 ` [U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache Andes
2019-06-04  2:48   ` Bin Meng
2019-06-05  9:38     ` Rick Chen
2019-06-05  9:39       ` Bin Meng
2019-06-09 17:57         ` Auer, Lukas

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