[U-Boot] [PATCH v4 0/4] x86: Add support for booting from TPL

[U-Boot] [PATCH v4 0/4] x86: Add support for booting from TPL

[Simon Glass]

At present SPL is used on 64-bit platforms, to allow SPL to be built as
a 32-bit program and U-Boot proper to be built as 64-bit.

However it is useful to be able to use SPL on any x86 platform, where
U-Boot needs to be updated in the field. Then SPL can select which U-Boot
to run (A or B) and most of the code can be updated. Similarly, using TPL
allows both SPL and U-Boot to be updated. This is the best approach, since
it means that all of U-Boot proper as well as SPL (in particular SDRAM
init) can be updated in the field. This provides for the smallest possible
amount of read-only (non-updateable) code: just the TPL code.

This series contains a number of changes to allow x86 boards to use TPL,
SPL and U-Boot proper. As a test, it is enabled for samus with a new
chromebook_samus_tpl board.

Changes in v4:
- Update commit message to not mention the sysreset driver.
- Drop change to SPI flash memory-map property

Changes in v3:
- Remove unneeded pch-reset node

Changes in v2:
- Sort defconfig and adjust it to build after rebase on maste

Simon Glass (4):
  x86: samus: Update device tree for SPL
  x86: samus: Update device tree for verified boot
  Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
  x86: samus: Add a target to boot through TPL

 arch/x86/dts/chromebook_samus.dts         | 53 +++++++++++++--
 board/google/Kconfig                      |  8 +++
 board/google/chromebook_samus/Kconfig     | 14 +++-
 board/google/chromebook_samus/MAINTAINERS |  7 ++
 configs/chromebook_samus_tpl_defconfig    | 82 +++++++++++++++++++++++
 include/configs/chromebook_samus.h        |  2 +
 include/pci.h                             |  6 +-
 7 files changed, 161 insertions(+), 11 deletions(-)
 create mode 100644 configs/chromebook_samus_tpl_defconfig

-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v4 1/4] x86: samus: Update device tree for SPL

[Simon Glass]

Add tags to allow required nodes to be present in SPL / TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>

---

Changes in v4:
- Update commit message to not mention the sysreset driver.
- Drop change to SPI flash memory-map property

Changes in v3:
- Remove unneeded pch-reset node

Changes in v2: None

 arch/x86/dts/chromebook_samus.dts | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index 35211ed81b1..c4207af48a7 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -17,6 +17,7 @@
 		spi0 = &spi;
 		usb0 = &usb_0;
 		usb1 = &usb_1;
+		cros-ec0 = &cros_ec;
 	};
 
 	config {
@@ -73,6 +74,7 @@
 
 		/* Put this first: it is the default */
 		gpio_unused: gpio-unused {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -80,6 +82,7 @@
 		};
 
 		gpio_acpi_sci: acpi-sci {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			invert;
@@ -87,6 +90,7 @@
 		};
 
 		gpio_acpi_smi: acpi-smi {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			invert;
@@ -94,12 +98,14 @@
 		};
 
 		gpio_input: gpio-input {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
 		};
 
 		gpio_input_invert: gpio-input-invert {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -107,9 +113,11 @@
 		};
 
 		gpio_native: gpio-native {
+			u-boot,dm-pre-reloc;
 		};
 
 		gpio_out_high: gpio-out-high {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_OUTPUT>;
 			output-value = <1>;
@@ -118,6 +126,7 @@
 		};
 
 		gpio_out_low: gpio-out-low {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_OUTPUT>;
 			output-value = <0>;
@@ -126,6 +135,7 @@
 		};
 
 		gpio_pirq: gpio-pirq {
+			u-boot,dm-pre-reloc;
 			mode-gpio;
 			direction = <PIN_INPUT>;
 			owner = <OWNER_GPIO>;
@@ -133,6 +143,7 @@
 		};
 
 		soc_gpio at 0 {
+			u-boot,dm-pre-reloc;
 			config =
 				<0 &gpio_unused 0>,	/* unused */
 				<1 &gpio_unused 0>,	/* unused */
@@ -250,8 +261,10 @@
 			spd {
 				#address-cells = <1>;
 				#size-cells = <0>;
+				u-boot,dm-pre-reloc;
 				samsung_4 {
 					reg = <6>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 11 05 0b
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -291,6 +304,7 @@
 					 * columns 10, density 4096 mb, x32
 					 */
 					reg = <8>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 11 05 0b
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -326,6 +340,7 @@
 					};
 				samsung_8 {
 					reg = <10>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 12 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -365,6 +380,7 @@
 					 * columns 11, density 4096 mb, x16
 					 */
 					reg = <12>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 04 12 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -404,6 +420,7 @@
 					 * columns 11, density 8192 mb, x16
 					 */
 					reg = <13>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 05 1a 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -443,6 +460,7 @@
 					 * columns 11, density 8192 mb, x16
 					 */
 					reg = <15>;
+					u-boot,dm-pre-reloc;
 					data = [91 20 f1 03 05 1a 05 0a
 						03 11 01 08 0a 00 50 01
 						78 78 90 50 90 11 50 e0
@@ -540,7 +558,7 @@
 			compatible = "ehci-pci";
 		};
 
-		pch at 1f,0 {
+		pch: pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,broadwell-pch";
 			u-boot,dm-pre-reloc;
@@ -559,10 +577,12 @@
 			power-enable-gpio = <&gpio_a 23 0>;
 
 			spi: spi {
+				u-boot,dm-pre-reloc;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
 				spi-flash at 0 {
+					u-boot,dm-pre-reloc;
 					#size-cells = <1>;
 					#address-cells = <1>;
 					reg = <0>;
@@ -570,6 +590,7 @@
 							"jedec,spi-nor";
 					memory-map = <0xff800000 0x00800000>;
 					rw-mrc-cache {
+						u-boot,dm-pre-reloc;
 						label = "rw-mrc-cache";
 						reg = <0x003e0000 0x00010000>;
 					};
@@ -609,7 +630,8 @@
 				#size-cells = <0>;
 				u-boot,dm-pre-reloc;
 				intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
-				cros-ec at 200 {
+				cros_ec: cros-ec {
+					u-boot,dm-pre-reloc;
 					compatible = "google,cros-ec-lpc";
 					reg = <0x204 1 0x200 1 0x880 0x80>;
 
@@ -630,7 +652,7 @@
 		sata at 1f,2 {
 			compatible = "intel,wildcatpoint-ahci";
 			reg = <0x0000fa00 0 0 0 0>;
-			u-boot,dm-pre-reloc;
+			u-boot,dm-pre-proper;
 			intel,sata-mode = "ahci";
 			intel,sata-port-map = <1>;
 			intel,sata-port0-gen3-tx = <0x72>;
@@ -645,12 +667,15 @@
 	};
 
 	tpm {
+		u-boot,dm-pre-reloc;
 		reg = <0xfed40000 0x5000>;
 		compatible = "infineon,slb9635lpc";
 	};
 
 	microcode {
+		u-boot,dm-pre-reloc;
 		update at 0 {
+			u-boot,dm-pre-reloc;
 #include "microcode/mc0306d4_00000018.dtsi"
 		};
 	};
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v4 2/4] x86: samus: Update device tree for verified boot

[Simon Glass]

Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/dts/chromebook_samus.dts | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts
index c4207af48a7..772ea5c91be 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -9,6 +9,12 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-8mb-rw.dtsi"
+#endif
+
 / {
 	model = "Google Samus";
 	compatible = "google,samus", "intel,broadwell";
@@ -581,7 +587,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "intel,ich9-spi";
-				spi-flash at 0 {
+				fwstore_spi: spi-flash at 0 {
 					u-boot,dm-pre-reloc;
 					#size-cells = <1>;
 					#address-cells = <1>;
@@ -670,6 +676,10 @@
 		u-boot,dm-pre-reloc;
 		reg = <0xfed40000 0x5000>;
 		compatible = "infineon,slb9635lpc";
+		secdata {
+			u-boot,dm-pre-reloc;
+			compatible = "google,tpm-secdata";
+		};
 	};
 
 	microcode {
@@ -693,3 +703,13 @@
 	};
 
 };
+
+&rtc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nvdata {
+		u-boot,dm-pre-reloc;
+		compatible = "google,cmos-nvdata";
+		reg = <0x26>;
+	};
+};
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v4 3/4] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"

[Simon Glass]

This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.

Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.

The offending line is in UCLASS_DRIVER(pci):

	.per_device_auto_alloc_size = sizeof(struct pci_controller),

This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.

For now, revert the commit to get things running again.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/pci.h | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/include/pci.h b/include/pci.h
index 066238a9c3c..508f7bca81c 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -546,11 +546,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
 				      struct pci_config_table *);
 
-#ifdef CONFIG_NR_DRAM_BANKS
-#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
-#else
-#define MAX_PCI_REGIONS 7
-#endif
+#define MAX_PCI_REGIONS		7
 
 #define INDIRECT_TYPE_NO_PCIE_LINK	1
 
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v4 4/4] x86: samus: Add a target to boot through TPL

[Simon Glass]

Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

Changes in v4: None
Changes in v3: None
Changes in v2:
- Sort defconfig and adjust it to build after rebase on maste

 board/google/Kconfig                      |  8 +++
 board/google/chromebook_samus/Kconfig     | 14 +++-
 board/google/chromebook_samus/MAINTAINERS |  7 ++
 configs/chromebook_samus_tpl_defconfig    | 82 +++++++++++++++++++++++
 include/configs/chromebook_samus.h        |  2 +
 5 files changed, 111 insertions(+), 2 deletions(-)
 create mode 100644 configs/chromebook_samus_tpl_defconfig

diff --git a/board/google/Kconfig b/board/google/Kconfig
index d98a5e818fc..679a0f10239 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS
 	  Chrome OS EC connected on LPC, and it provides a 2560x1700 high
 	  resolution touch-enabled LCD display.
 
+config TARGET_CHROMEBOOK_SAMUS_TPL
+	bool "Chromebook samus booting from TPL"
+	help
+	  This is a version of Samus which boots into TPL, then to SPL and
+	  U-Boot proper. This is useful where verified boot must select
+	  between different A/B versions of SPL/U-Boot, to allow upgrading of
+	  almost all U-Boot code in the field.
+
 endchoice
 
 source "board/google/chromebook_link/Kconfig"
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index afbfe53deb4..90c23cba1be 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_CHROMEBOOK_SAMUS
+if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL
 
 config SYS_BOARD
 	default "chromebook_samus"
@@ -10,7 +10,8 @@ config SYS_SOC
 	default "broadwell"
 
 config SYS_CONFIG_NAME
-	default "chromebook_samus"
+	default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS
+	default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL
 
 config SYS_TEXT_BASE
 	default 0xffe00000
@@ -39,3 +40,12 @@ config SYS_CAR_SIZE
 	default 0x40000
 
 endif
+
+if TARGET_CHROMEBOOK_SAMUS_TPL
+
+config BOARD_SPECIFIC_OPTIONS_TPL # dummy
+	def_bool y
+	select SPL
+	select TPL
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
index 5500e46b408..ca4b16500af 100644
--- a/board/google/chromebook_samus/MAINTAINERS
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/google/chromebook_samus/
 F:	include/configs/chromebook_samus.h
 F:	configs/chromebook_samus_defconfig
+
+CHROMEBOOK SAMUS TPL BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_samus/
+F:	include/configs/chromebook_samus.h
+F:	configs/chromebook_samus_tpl_defconfig
diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig
new file mode 100644
index 00000000000..6ebfaa83a19
--- /dev/null
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -0,0 +1,82 @@
+CONFIG_X86=y
+CONFIG_SYS_TEXT_BASE=0xffed0000
+CONFIG_SYS_MALLOC_F_LEN=0x1a00
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y
+CONFIG_DEBUG_UART=y
+CONFIG_HAVE_MRC=y
+CONFIG_HAVE_REFCODE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_MISC_INIT_R=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_SIZE=0x1000
+CONFIG_BLOBLIST_ADDR=0xff7c0000
+CONFIG_HANDOFF=y
+CONFIG_SPL_TEXT_BASE=0xffe70000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_NET_SUPPORT=y
+CONFIG_SPL_PCI=y
+CONFIG_SPL_PCH_SUPPORT=y
+CONFIG_TPL_PCI=y
+CONFIG_TPL_PCH_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_TPM_TEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_SPL_MAC_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
+# CONFIG_NET is not set
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_TPL_MISC=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_LPC=y
+CONFIG_SYS_NS16550=y
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_SOUND_RT5677=y
+CONFIG_SPI=y
+CONFIG_TPM_TIS_LPC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
+CONFIG_CONSOLE_SCROLL_LINES=5
+CONFIG_TPM=y
diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h
index ccb2fe8caad..2f7dd69fb82 100644
--- a/include/configs/chromebook_samus.h
+++ b/include/configs/chromebook_samus.h
@@ -23,4 +23,6 @@
 #define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_ENV_OFFSET		0x003f8000
 
+#define CONFIG_TPL_TEXT_BASE		0xfffd8000
+
 #endif	/* __CONFIG_H */
-- 
2.21.0.1020.gf2820cf01a-goog

[U-Boot] [PATCH v4 1/4] x86: samus: Update device tree for SPL

[Bin Meng]

On Wed, May 8, 2019 at 11:41 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add tags to allow required nodes to be present in SPL / TPL.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4:
> - Update commit message to not mention the sysreset driver.
> - Drop change to SPI flash memory-map property
>
> Changes in v3:
> - Remove unneeded pch-reset node
>
> Changes in v2: None
>
>  arch/x86/dts/chromebook_samus.dts | 31 ++++++++++++++++++++++++++++---
>  1 file changed, 28 insertions(+), 3 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v4 1/4] x86: samus: Update device tree for SPL

[Bin Meng]

On Wed, May 8, 2019 at 12:40 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, May 8, 2019 at 11:41 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > Add tags to allow required nodes to be present in SPL / TPL.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> >
> > ---
> >
> > Changes in v4:
> > - Update commit message to not mention the sysreset driver.
> > - Drop change to SPI flash memory-map property
> >
> > Changes in v3:
> > - Remove unneeded pch-reset node
> >
> > Changes in v2: None
> >
> >  arch/x86/dts/chromebook_samus.dts | 31 ++++++++++++++++++++++++++++---
> >  1 file changed, 28 insertions(+), 3 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 2/4] x86: samus: Update device tree for verified boot

[Bin Meng]

On Wed, May 8, 2019 at 11:41 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add nvdata drivers for the TPM and RTC as used on samus. These are needed
> for Chromium OS verified boot on samus.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/dts/chromebook_samus.dts | 22 +++++++++++++++++++++-
>  1 file changed, 21 insertions(+), 1 deletion(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 3/4] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"

[Bin Meng]

On Wed, May 8, 2019 at 11:41 AM Simon Glass <sjg@chromium.org> wrote:
>
> This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.
>
> Unfortunately this has a dramatic impact on the pre-relocation memory
> used on x86 platforms (increasing it by 2KB) since it increases the
> overhead for each PCI device from 220 bytes to 412 bytes.
>
> The offending line is in UCLASS_DRIVER(pci):
>
>         .per_device_auto_alloc_size = sizeof(struct pci_controller),
>
> This means that all PCI devices have the controller struct associated
> with them. The solution is to move the regions[] member out of the array,
> makes its size dynamic, or split UCLASS_PCI into controllers and
> non-controllers, as the comment suggests.
>
> For now, revert the commit to get things running again.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  include/pci.h | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>

applied to u-boot-x86, thanks!

[U-Boot] [PATCH v4 4/4] x86: samus: Add a target to boot through TPL

[Bin Meng]

On Wed, May 8, 2019 at 11:41 AM Simon Glass <sjg@chromium.org> wrote:
>
> Add a version of samus which supports booting from TPL to SPL and then
> to U-Boot. This allows TPL to select from an A or B SPL to support
> verified boot with field upgrade.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Sort defconfig and adjust it to build after rebase on maste
>
>  board/google/Kconfig                      |  8 +++
>  board/google/chromebook_samus/Kconfig     | 14 +++-
>  board/google/chromebook_samus/MAINTAINERS |  7 ++
>  configs/chromebook_samus_tpl_defconfig    | 82 +++++++++++++++++++++++
>  include/configs/chromebook_samus.h        |  2 +
>  5 files changed, 111 insertions(+), 2 deletions(-)
>  create mode 100644 configs/chromebook_samus_tpl_defconfig
>

applied to u-boot-x86, thanks!