* [PATCH] target/riscv: Don't wrongly overide isa version
@ 2021-08-10 3:33 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2021-08-10 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, bin.meng, Alistair.Francis, LIU Zhiwei
For some cpu, the isa version has already been set in cpu init function.
Thus only overide the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 991a6bb760..425efba0c8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
- int priv_version = PRIV_VERSION_1_11_0;
- int bext_version = BEXT_VERSION_0_93_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int priv_version = env->priv_ver;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
}
- set_priv_version(env, priv_version);
- set_bext_version(env, bext_version);
- set_vext_version(env, vext_version);
+ if (!env->priv_ver) {
+ set_priv_version(env, PRIV_VERSION_1_11_0);
+ } else if (env->priv_ver != priv_version) {
+ set_priv_version(env, priv_version);
+ }
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
@@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
target_misa |= RVH;
}
if (cpu->cfg.ext_b) {
+ int bext_version = BEXT_VERSION_0_93_0;
target_misa |= RVB;
if (cpu->cfg.bext_spec) {
@@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
+ int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] target/riscv: Don't wrongly overide isa version
@ 2021-08-10 3:33 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2021-08-10 3:33 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair.Francis, palmer, bin.meng, LIU Zhiwei
For some cpu, the isa version has already been set in cpu init function.
Thus only overide the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 991a6bb760..425efba0c8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
- int priv_version = PRIV_VERSION_1_11_0;
- int bext_version = BEXT_VERSION_0_93_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int priv_version = env->priv_ver;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
}
- set_priv_version(env, priv_version);
- set_bext_version(env, bext_version);
- set_vext_version(env, vext_version);
+ if (!env->priv_ver) {
+ set_priv_version(env, PRIV_VERSION_1_11_0);
+ } else if (env->priv_ver != priv_version) {
+ set_priv_version(env, priv_version);
+ }
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
@@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
target_misa |= RVH;
}
if (cpu->cfg.ext_b) {
+ int bext_version = BEXT_VERSION_0_93_0;
target_misa |= RVB;
if (cpu->cfg.bext_spec) {
@@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_bext_version(env, bext_version);
}
if (cpu->cfg.ext_v) {
+ int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] target/riscv: Don't wrongly overide isa version
2021-08-10 3:33 ` LIU Zhiwei
@ 2021-08-11 9:26 ` Bin Meng
-1 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2021-08-11 9:26 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Tue, Aug 10, 2021 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> For some cpu, the isa version has already been set in cpu init function.
> Thus only overide the isa version when isa version is not set, or
typo: override, please fix the commit title as well
> users set different isa version explicitly by cpu parameters.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb760..425efba0c8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> RISCVCPU *cpu = RISCV_CPU(dev);
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> - int priv_version = PRIV_VERSION_1_11_0;
> - int bext_version = BEXT_VERSION_0_93_0;
> - int vext_version = VEXT_VERSION_0_07_1;
> + int priv_version = env->priv_ver;
> target_ulong target_misa = env->misa;
> Error *local_err = NULL;
>
> @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
> }
>
> - set_priv_version(env, priv_version);
> - set_bext_version(env, bext_version);
> - set_vext_version(env, vext_version);
> + if (!env->priv_ver) {
> + set_priv_version(env, PRIV_VERSION_1_11_0);
> + } else if (env->priv_ver != priv_version) {
> + set_priv_version(env, priv_version);
> + }
This logic seems incorrect to me. So if cpu init function does not set
the priv, and cfg set it to v1.10, v1.11 will be set in the new logic.
The previous logic makes sure the cfg value overrides the cpu init
value which seems to be intended.
>
> if (cpu->cfg.mmu) {
> set_feature(env, RISCV_FEATURE_MMU);
> @@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> target_misa |= RVH;
> }
> if (cpu->cfg.ext_b) {
> + int bext_version = BEXT_VERSION_0_93_0;
> target_misa |= RVB;
>
> if (cpu->cfg.bext_spec) {
> @@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> set_bext_version(env, bext_version);
> }
> if (cpu->cfg.ext_v) {
> + int vext_version = VEXT_VERSION_0_07_1;
> target_misa |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> error_setg(errp,
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] target/riscv: Don't wrongly overide isa version
@ 2021-08-11 9:26 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2021-08-11 9:26 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Bin Meng, Alistair Francis
On Tue, Aug 10, 2021 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> For some cpu, the isa version has already been set in cpu init function.
> Thus only overide the isa version when isa version is not set, or
typo: override, please fix the commit title as well
> users set different isa version explicitly by cpu parameters.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb760..425efba0c8 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> RISCVCPU *cpu = RISCV_CPU(dev);
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> - int priv_version = PRIV_VERSION_1_11_0;
> - int bext_version = BEXT_VERSION_0_93_0;
> - int vext_version = VEXT_VERSION_0_07_1;
> + int priv_version = env->priv_ver;
> target_ulong target_misa = env->misa;
> Error *local_err = NULL;
>
> @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> }
> }
>
> - set_priv_version(env, priv_version);
> - set_bext_version(env, bext_version);
> - set_vext_version(env, vext_version);
> + if (!env->priv_ver) {
> + set_priv_version(env, PRIV_VERSION_1_11_0);
> + } else if (env->priv_ver != priv_version) {
> + set_priv_version(env, priv_version);
> + }
This logic seems incorrect to me. So if cpu init function does not set
the priv, and cfg set it to v1.10, v1.11 will be set in the new logic.
The previous logic makes sure the cfg value overrides the cpu init
value which seems to be intended.
>
> if (cpu->cfg.mmu) {
> set_feature(env, RISCV_FEATURE_MMU);
> @@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> target_misa |= RVH;
> }
> if (cpu->cfg.ext_b) {
> + int bext_version = BEXT_VERSION_0_93_0;
> target_misa |= RVB;
>
> if (cpu->cfg.bext_spec) {
> @@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> set_bext_version(env, bext_version);
> }
> if (cpu->cfg.ext_v) {
> + int vext_version = VEXT_VERSION_0_07_1;
> target_misa |= RVV;
> if (!is_power_of_2(cpu->cfg.vlen)) {
> error_setg(errp,
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] target/riscv: Don't wrongly overide isa version
2021-08-11 9:26 ` Bin Meng
@ 2021-08-11 14:06 ` LIU Zhiwei
-1 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2021-08-11 14:06 UTC (permalink / raw)
To: Bin Meng
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On 2021/8/11 下午5:26, Bin Meng wrote:
> On Tue, Aug 10, 2021 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>> For some cpu, the isa version has already been set in cpu init function.
>> Thus only overide the isa version when isa version is not set, or
> typo: override, please fix the commit title as well
OK
>
>> users set different isa version explicitly by cpu parameters.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 991a6bb760..425efba0c8 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> RISCVCPU *cpu = RISCV_CPU(dev);
>> CPURISCVState *env = &cpu->env;
>> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>> - int priv_version = PRIV_VERSION_1_11_0;
>> - int bext_version = BEXT_VERSION_0_93_0;
>> - int vext_version = VEXT_VERSION_0_07_1;
>> + int priv_version = env->priv_ver;
>> target_ulong target_misa = env->misa;
>> Error *local_err = NULL;
>>
>> @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> }
>> }
>>
>> - set_priv_version(env, priv_version);
>> - set_bext_version(env, bext_version);
>> - set_vext_version(env, vext_version);
>> + if (!env->priv_ver) {
>> + set_priv_version(env, PRIV_VERSION_1_11_0);
>> + } else if (env->priv_ver != priv_version) {
>> + set_priv_version(env, priv_version);
>> + }
> This logic seems incorrect to me. So if cpu init function does not set
> the priv, and cfg set it to v1.10, v1.11 will be set in the new logic.
Yes, it's also here.
Thanks,
Zhiwei
> The previous logic makes sure the cfg value overrides the cpu init
> value which seems to be intended.
>
>> if (cpu->cfg.mmu) {
>> set_feature(env, RISCV_FEATURE_MMU);
>> @@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> target_misa |= RVH;
>> }
>> if (cpu->cfg.ext_b) {
>> + int bext_version = BEXT_VERSION_0_93_0;
>> target_misa |= RVB;
>>
>> if (cpu->cfg.bext_spec) {
>> @@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> set_bext_version(env, bext_version);
>> }
>> if (cpu->cfg.ext_v) {
>> + int vext_version = VEXT_VERSION_0_07_1;
>> target_misa |= RVV;
>> if (!is_power_of_2(cpu->cfg.vlen)) {
>> error_setg(errp,
>> --
> Regards,
> Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] target/riscv: Don't wrongly overide isa version
@ 2021-08-11 14:06 ` LIU Zhiwei
0 siblings, 0 replies; 8+ messages in thread
From: LIU Zhiwei @ 2021-08-11 14:06 UTC (permalink / raw)
To: Bin Meng
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Bin Meng, Alistair Francis
On 2021/8/11 下午5:26, Bin Meng wrote:
> On Tue, Aug 10, 2021 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>> For some cpu, the isa version has already been set in cpu init function.
>> Thus only overide the isa version when isa version is not set, or
> typo: override, please fix the commit title as well
OK
>
>> users set different isa version explicitly by cpu parameters.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> ---
>> target/riscv/cpu.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 991a6bb760..425efba0c8 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> RISCVCPU *cpu = RISCV_CPU(dev);
>> CPURISCVState *env = &cpu->env;
>> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>> - int priv_version = PRIV_VERSION_1_11_0;
>> - int bext_version = BEXT_VERSION_0_93_0;
>> - int vext_version = VEXT_VERSION_0_07_1;
>> + int priv_version = env->priv_ver;
>> target_ulong target_misa = env->misa;
>> Error *local_err = NULL;
>>
>> @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> }
>> }
>>
>> - set_priv_version(env, priv_version);
>> - set_bext_version(env, bext_version);
>> - set_vext_version(env, vext_version);
>> + if (!env->priv_ver) {
>> + set_priv_version(env, PRIV_VERSION_1_11_0);
>> + } else if (env->priv_ver != priv_version) {
>> + set_priv_version(env, priv_version);
>> + }
> This logic seems incorrect to me. So if cpu init function does not set
> the priv, and cfg set it to v1.10, v1.11 will be set in the new logic.
Yes, it's also here.
Thanks,
Zhiwei
> The previous logic makes sure the cfg value overrides the cpu init
> value which seems to be intended.
>
>> if (cpu->cfg.mmu) {
>> set_feature(env, RISCV_FEATURE_MMU);
>> @@ -497,6 +497,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> target_misa |= RVH;
>> }
>> if (cpu->cfg.ext_b) {
>> + int bext_version = BEXT_VERSION_0_93_0;
>> target_misa |= RVB;
>>
>> if (cpu->cfg.bext_spec) {
>> @@ -515,6 +516,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> set_bext_version(env, bext_version);
>> }
>> if (cpu->cfg.ext_v) {
>> + int vext_version = VEXT_VERSION_0_07_1;
>> target_misa |= RVV;
>> if (!is_power_of_2(cpu->cfg.vlen)) {
>> error_setg(errp,
>> --
> Regards,
> Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] target/riscv: Don't wrongly overide isa version
2021-08-11 14:06 ` LIU Zhiwei
@ 2021-08-11 14:18 ` Bin Meng
-1 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2021-08-11 14:18 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Aug 11, 2021 at 10:07 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2021/8/11 下午5:26, Bin Meng wrote:
> > On Tue, Aug 10, 2021 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> >> For some cpu, the isa version has already been set in cpu init function.
> >> Thus only overide the isa version when isa version is not set, or
> > typo: override, please fix the commit title as well
> OK
> >
> >> users set different isa version explicitly by cpu parameters.
> >>
> >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> >> ---
> >> target/riscv/cpu.c | 14 ++++++++------
> >> 1 file changed, 8 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 991a6bb760..425efba0c8 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> RISCVCPU *cpu = RISCV_CPU(dev);
> >> CPURISCVState *env = &cpu->env;
> >> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> >> - int priv_version = PRIV_VERSION_1_11_0;
> >> - int bext_version = BEXT_VERSION_0_93_0;
> >> - int vext_version = VEXT_VERSION_0_07_1;
> >> + int priv_version = env->priv_ver;
> >> target_ulong target_misa = env->misa;
> >> Error *local_err = NULL;
> >>
> >> @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> }
> >> }
> >>
> >> - set_priv_version(env, priv_version);
> >> - set_bext_version(env, bext_version);
> >> - set_vext_version(env, vext_version);
> >> + if (!env->priv_ver) {
> >> + set_priv_version(env, PRIV_VERSION_1_11_0);
> >> + } else if (env->priv_ver != priv_version) {
> >> + set_priv_version(env, priv_version);
> >> + }
> > This logic seems incorrect to me. So if cpu init function does not set
> > the priv, and cfg set it to v1.10, v1.11 will be set in the new logic.
>
> Yes, it's also here.
>
But the previous logic makes sure the cfg value overrides the cpu init
value which seems to be intended. So in that case, it should still be
v1.10 not v1.11.
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] target/riscv: Don't wrongly overide isa version
@ 2021-08-11 14:18 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2021-08-11 14:18 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Bin Meng, Alistair Francis
On Wed, Aug 11, 2021 at 10:07 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2021/8/11 下午5:26, Bin Meng wrote:
> > On Tue, Aug 10, 2021 at 11:35 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> >> For some cpu, the isa version has already been set in cpu init function.
> >> Thus only overide the isa version when isa version is not set, or
> > typo: override, please fix the commit title as well
> OK
> >
> >> users set different isa version explicitly by cpu parameters.
> >>
> >> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> >> ---
> >> target/riscv/cpu.c | 14 ++++++++------
> >> 1 file changed, 8 insertions(+), 6 deletions(-)
> >>
> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> >> index 991a6bb760..425efba0c8 100644
> >> --- a/target/riscv/cpu.c
> >> +++ b/target/riscv/cpu.c
> >> @@ -392,9 +392,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> RISCVCPU *cpu = RISCV_CPU(dev);
> >> CPURISCVState *env = &cpu->env;
> >> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> >> - int priv_version = PRIV_VERSION_1_11_0;
> >> - int bext_version = BEXT_VERSION_0_93_0;
> >> - int vext_version = VEXT_VERSION_0_07_1;
> >> + int priv_version = env->priv_ver;
> >> target_ulong target_misa = env->misa;
> >> Error *local_err = NULL;
> >>
> >> @@ -417,9 +415,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >> }
> >> }
> >>
> >> - set_priv_version(env, priv_version);
> >> - set_bext_version(env, bext_version);
> >> - set_vext_version(env, vext_version);
> >> + if (!env->priv_ver) {
> >> + set_priv_version(env, PRIV_VERSION_1_11_0);
> >> + } else if (env->priv_ver != priv_version) {
> >> + set_priv_version(env, priv_version);
> >> + }
> > This logic seems incorrect to me. So if cpu init function does not set
> > the priv, and cfg set it to v1.10, v1.11 will be set in the new logic.
>
> Yes, it's also here.
>
But the previous logic makes sure the cfg value overrides the cpu init
value which seems to be intended. So in that case, it should still be
v1.10 not v1.11.
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-08-11 14:19 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-10 3:33 [PATCH] target/riscv: Don't wrongly overide isa version LIU Zhiwei
2021-08-10 3:33 ` LIU Zhiwei
2021-08-11 9:26 ` Bin Meng
2021-08-11 9:26 ` Bin Meng
2021-08-11 14:06 ` LIU Zhiwei
2021-08-11 14:06 ` LIU Zhiwei
2021-08-11 14:18 ` Bin Meng
2021-08-11 14:18 ` Bin Meng
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.