* [PATCH v5 0/1] x86: efi: Add a 64-bit coreboot payload
@ 2020-05-01 13:36 Simon Glass
2020-05-01 13:36 ` [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build Simon Glass
0 siblings, 1 reply; 8+ messages in thread
From: Simon Glass @ 2020-05-01 13:36 UTC (permalink / raw)
To: u-boot
This series creates a new 64-bit 'coreboot64' build which can be launched
from coreboot. It uses SPL to effect the jump to 64-bit mode.
This was done in an attempt to get the Ubuntu FirmwareTestSuite[1]
working. Unfortunately the latest version shows a splash screen and hangs,
perhaps due to some missing EFI support.
[1] https://wiki.ubuntu.com/FirmwareTestSuite
Changes in v5:
- Rewrite commit message to explain what coreboot is
Simon Glass (1):
x86: Add a 64-bit 'coreboot64' build
board/coreboot/coreboot/MAINTAINERS | 7 +++++
configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
doc/board/coreboot/coreboot.rst | 10 ++++++
3 files changed, 65 insertions(+)
create mode 100644 configs/coreboot64_defconfig
--
2.26.2.526.g744177e7f7-goog
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-01 13:36 [PATCH v5 0/1] x86: efi: Add a 64-bit coreboot payload Simon Glass
@ 2020-05-01 13:36 ` Simon Glass
2020-05-02 12:59 ` Bin Meng
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Simon Glass @ 2020-05-01 13:36 UTC (permalink / raw)
To: u-boot
Coreboot is a first-stage bootloader mostly used on x86 devices as an
alternative to UEFI. Coreboot runs in 32-bit mode.
U-Boot currently supports booting from coreboot as a second-stage
bootloader, also in 32-bit mode. However it is useful to be able to run
U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
over the CPU and jumps to a 64-bit U-Boot proper.
Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
This allows running 64-bit EFI images on x86, for example, without needing
a native U-Boot port for a board.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v5:
- Rewrite commit message to explain what coreboot is
board/coreboot/coreboot/MAINTAINERS | 7 +++++
configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
doc/board/coreboot/coreboot.rst | 10 ++++++
3 files changed, 65 insertions(+)
create mode 100644 configs/coreboot64_defconfig
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index 188906b080..a05673bb0b 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -4,3 +4,10 @@ S: Maintained
F: board/coreboot/coreboot/
F: include/configs/chromebook_link.h
F: configs/coreboot_defconfig
+
+COREBOOT64 BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/coreboot/coreboot/
+F: include/configs/chromebook_link.h
+F: configs/coreboot64_defconfig
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
new file mode 100644
index 0000000000..80353b8eb3
--- /dev/null
+++ b/configs/coreboot64_defconfig
@@ -0,0 +1,48 @@
+CONFIG_X86=y
+CONFIG_SYS_TEXT_BASE=0x1120000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_PRE_CON_BUF_ADDR=0x100000
+CONFIG_X86_RUN_64BIT=y
+CONFIG_VENDOR_COREBOOT=y
+CONFIG_TARGET_COREBOOT=y
+CONFIG_SPL_TEXT_BASE=0x1110000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IDE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_SPL_MAC_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="coreboot"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_PCI_PNP is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index fd974229eb..9c44c025a4 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot:
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
+
+64-bit U-Boot
+-------------
+
+In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This
+produces an image which can be booted from coreboot (32-bit). Internally it
+works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
+can be useful for running UEFI applications, for example.
+
+This has only been lightly tested.
--
2.26.2.526.g744177e7f7-goog
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-01 13:36 ` [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build Simon Glass
@ 2020-05-02 12:59 ` Bin Meng
2020-05-02 13:37 ` Heinrich Schuchardt
2020-05-04 7:26 ` Bin Meng
2 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2020-05-02 12:59 UTC (permalink / raw)
To: u-boot
On Fri, May 1, 2020 at 9:36 PM Simon Glass <sjg@chromium.org> wrote:
>
> Coreboot is a first-stage bootloader mostly used on x86 devices as an
> alternative to UEFI. Coreboot runs in 32-bit mode.
>
> U-Boot currently supports booting from coreboot as a second-stage
> bootloader, also in 32-bit mode. However it is useful to be able to run
> U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
> over the CPU and jumps to a 64-bit U-Boot proper.
>
> Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
> uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
>
> This allows running 64-bit EFI images on x86, for example, without needing
> a native U-Boot port for a board.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v5:
> - Rewrite commit message to explain what coreboot is
>
> board/coreboot/coreboot/MAINTAINERS | 7 +++++
> configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
> doc/board/coreboot/coreboot.rst | 10 ++++++
> 3 files changed, 65 insertions(+)
> create mode 100644 configs/coreboot64_defconfig
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-01 13:36 ` [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build Simon Glass
2020-05-02 12:59 ` Bin Meng
@ 2020-05-02 13:37 ` Heinrich Schuchardt
2020-05-02 13:40 ` Bin Meng
2020-05-04 7:26 ` Bin Meng
2 siblings, 1 reply; 8+ messages in thread
From: Heinrich Schuchardt @ 2020-05-02 13:37 UTC (permalink / raw)
To: u-boot
On 5/1/20 3:36 PM, Simon Glass wrote:
> Coreboot is a first-stage bootloader mostly used on x86 devices as an
> alternative to UEFI. Coreboot runs in 32-bit mode.
>
> U-Boot currently supports booting from coreboot as a second-stage
> bootloader, also in 32-bit mode. However it is useful to be able to run
> U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
> over the CPU and jumps to a 64-bit U-Boot proper.
>
> Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
> uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
>
> This allows running 64-bit EFI images on x86, for example, without needing
> a native U-Boot port for a board.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v5:
> - Rewrite commit message to explain what coreboot is
>
> board/coreboot/coreboot/MAINTAINERS | 7 +++++
> configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
> doc/board/coreboot/coreboot.rst | 10 ++++++
> 3 files changed, 65 insertions(+)
> create mode 100644 configs/coreboot64_defconfig
>
> diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
> index 188906b080..a05673bb0b 100644
> --- a/board/coreboot/coreboot/MAINTAINERS
> +++ b/board/coreboot/coreboot/MAINTAINERS
> @@ -4,3 +4,10 @@ S: Maintained
> F: board/coreboot/coreboot/
> F: include/configs/chromebook_link.h
> F: configs/coreboot_defconfig
> +
> +COREBOOT64 BOARD
> +M: Simon Glass <sjg@chromium.org>
> +S: Maintained
> +F: board/coreboot/coreboot/
> +F: include/configs/chromebook_link.h
> +F: configs/coreboot64_defconfig
> diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
> new file mode 100644
> index 0000000000..80353b8eb3
> --- /dev/null
> +++ b/configs/coreboot64_defconfig
> @@ -0,0 +1,48 @@
> +CONFIG_X86=y
> +CONFIG_SYS_TEXT_BASE=0x1120000
> +CONFIG_ENV_SIZE=0x1000
> +CONFIG_NR_DRAM_BANKS=8
> +CONFIG_PRE_CON_BUF_ADDR=0x100000
> +CONFIG_X86_RUN_64BIT=y
> +CONFIG_VENDOR_COREBOOT=y
> +CONFIG_TARGET_COREBOOT=y
> +CONFIG_SPL_TEXT_BASE=0x1110000
> +CONFIG_FIT=y
> +CONFIG_FIT_SIGNATURE=y
> +CONFIG_SHOW_BOOT_PROGRESS=y
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
The coreboot firmware supports a lot of different boards. The board may
have two SATA drives or may be using NVME drives instead. Why do we have
this BOOTARGS line instead of using CONFIG_DISTRO_DEFAULTS=y?
Best regards
Heinrich
> +CONFIG_PRE_CONSOLE_BUFFER=y
> +CONFIG_SYS_CONSOLE_INFO_QUIET=y
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_LAST_STAGE_INIT=y
> +CONFIG_HUSH_PARSER=y
> +CONFIG_CMD_IDE=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PART=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_DHCP=y
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_SOUND=y
> +CONFIG_CMD_EXT2=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_CMD_FAT=y
> +CONFIG_CMD_FS_GENERIC=y
> +CONFIG_MAC_PARTITION=y
> +# CONFIG_SPL_MAC_PARTITION is not set
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_ISO_PARTITION=y
> +CONFIG_EFI_PARTITION=y
> +# CONFIG_SPL_EFI_PARTITION is not set
> +CONFIG_DEFAULT_DEVICE_TREE="coreboot"
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_REGMAP=y
> +CONFIG_SYSCON=y
> +# CONFIG_PCI_PNP is not set
> +CONFIG_SOUND=y
> +CONFIG_SOUND_I8254=y
> +CONFIG_CONSOLE_SCROLL_LINES=5
> diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
> index fd974229eb..9c44c025a4 100644
> --- a/doc/board/coreboot/coreboot.rst
> +++ b/doc/board/coreboot/coreboot.rst
> @@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot:
> At present it seems that for Minnowboard Max, coreboot does not pass through
> the video information correctly (it always says the resolution is 0x0). This
> works correctly for link though.
> +
> +64-bit U-Boot
> +-------------
> +
> +In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This
> +produces an image which can be booted from coreboot (32-bit). Internally it
> +works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
> +can be useful for running UEFI applications, for example.
> +
> +This has only been lightly tested.
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-02 13:37 ` Heinrich Schuchardt
@ 2020-05-02 13:40 ` Bin Meng
2020-05-02 13:41 ` Bin Meng
0 siblings, 1 reply; 8+ messages in thread
From: Bin Meng @ 2020-05-02 13:40 UTC (permalink / raw)
To: u-boot
Hi Heinrich,
On Sat, May 2, 2020 at 9:38 PM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>
> On 5/1/20 3:36 PM, Simon Glass wrote:
> > Coreboot is a first-stage bootloader mostly used on x86 devices as an
> > alternative to UEFI. Coreboot runs in 32-bit mode.
> >
> > U-Boot currently supports booting from coreboot as a second-stage
> > bootloader, also in 32-bit mode. However it is useful to be able to run
> > U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
> > over the CPU and jumps to a 64-bit U-Boot proper.
> >
> > Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
> > uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
> >
> > This allows running 64-bit EFI images on x86, for example, without needing
> > a native U-Boot port for a board.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v5:
> > - Rewrite commit message to explain what coreboot is
> >
> > board/coreboot/coreboot/MAINTAINERS | 7 +++++
> > configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
> > doc/board/coreboot/coreboot.rst | 10 ++++++
> > 3 files changed, 65 insertions(+)
> > create mode 100644 configs/coreboot64_defconfig
> >
> > diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
> > index 188906b080..a05673bb0b 100644
> > --- a/board/coreboot/coreboot/MAINTAINERS
> > +++ b/board/coreboot/coreboot/MAINTAINERS
> > @@ -4,3 +4,10 @@ S: Maintained
> > F: board/coreboot/coreboot/
> > F: include/configs/chromebook_link.h
> > F: configs/coreboot_defconfig
> > +
> > +COREBOOT64 BOARD
> > +M: Simon Glass <sjg@chromium.org>
> > +S: Maintained
> > +F: board/coreboot/coreboot/
> > +F: include/configs/chromebook_link.h
> > +F: configs/coreboot64_defconfig
> > diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
> > new file mode 100644
> > index 0000000000..80353b8eb3
> > --- /dev/null
> > +++ b/configs/coreboot64_defconfig
> > @@ -0,0 +1,48 @@
> > +CONFIG_X86=y
> > +CONFIG_SYS_TEXT_BASE=0x1120000
> > +CONFIG_ENV_SIZE=0x1000
> > +CONFIG_NR_DRAM_BANKS=8
> > +CONFIG_PRE_CON_BUF_ADDR=0x100000
> > +CONFIG_X86_RUN_64BIT=y
> > +CONFIG_VENDOR_COREBOOT=y
> > +CONFIG_TARGET_COREBOOT=y
> > +CONFIG_SPL_TEXT_BASE=0x1110000
> > +CONFIG_FIT=y
> > +CONFIG_FIT_SIGNATURE=y
> > +CONFIG_SHOW_BOOT_PROGRESS=y
> > +CONFIG_USE_BOOTARGS=y
> > +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
>
> The coreboot firmware supports a lot of different boards. The board may
> have two SATA drives or may be using NVME drives instead. Why do we have
> this BOOTARGS line instead of using CONFIG_DISTRO_DEFAULTS=y?
>
Convert coreboot BOOTARGS
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-02 13:40 ` Bin Meng
@ 2020-05-02 13:41 ` Bin Meng
2020-05-02 14:14 ` Heinrich Schuchardt
0 siblings, 1 reply; 8+ messages in thread
From: Bin Meng @ 2020-05-02 13:41 UTC (permalink / raw)
To: u-boot
Hi Heinrich,
On Sat, May 2, 2020 at 9:40 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Heinrich,
>
> On Sat, May 2, 2020 at 9:38 PM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
> >
> > On 5/1/20 3:36 PM, Simon Glass wrote:
> > > Coreboot is a first-stage bootloader mostly used on x86 devices as an
> > > alternative to UEFI. Coreboot runs in 32-bit mode.
> > >
> > > U-Boot currently supports booting from coreboot as a second-stage
> > > bootloader, also in 32-bit mode. However it is useful to be able to run
> > > U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
> > > over the CPU and jumps to a 64-bit U-Boot proper.
> > >
> > > Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
> > > uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
> > >
> > > This allows running 64-bit EFI images on x86, for example, without needing
> > > a native U-Boot port for a board.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > Changes in v5:
> > > - Rewrite commit message to explain what coreboot is
> > >
> > > board/coreboot/coreboot/MAINTAINERS | 7 +++++
> > > configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
> > > doc/board/coreboot/coreboot.rst | 10 ++++++
> > > 3 files changed, 65 insertions(+)
> > > create mode 100644 configs/coreboot64_defconfig
> > >
> > > diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
> > > index 188906b080..a05673bb0b 100644
> > > --- a/board/coreboot/coreboot/MAINTAINERS
> > > +++ b/board/coreboot/coreboot/MAINTAINERS
> > > @@ -4,3 +4,10 @@ S: Maintained
> > > F: board/coreboot/coreboot/
> > > F: include/configs/chromebook_link.h
> > > F: configs/coreboot_defconfig
> > > +
> > > +COREBOOT64 BOARD
> > > +M: Simon Glass <sjg@chromium.org>
> > > +S: Maintained
> > > +F: board/coreboot/coreboot/
> > > +F: include/configs/chromebook_link.h
> > > +F: configs/coreboot64_defconfig
> > > diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
> > > new file mode 100644
> > > index 0000000000..80353b8eb3
> > > --- /dev/null
> > > +++ b/configs/coreboot64_defconfig
> > > @@ -0,0 +1,48 @@
> > > +CONFIG_X86=y
> > > +CONFIG_SYS_TEXT_BASE=0x1120000
> > > +CONFIG_ENV_SIZE=0x1000
> > > +CONFIG_NR_DRAM_BANKS=8
> > > +CONFIG_PRE_CON_BUF_ADDR=0x100000
> > > +CONFIG_X86_RUN_64BIT=y
> > > +CONFIG_VENDOR_COREBOOT=y
> > > +CONFIG_TARGET_COREBOOT=y
> > > +CONFIG_SPL_TEXT_BASE=0x1110000
> > > +CONFIG_FIT=y
> > > +CONFIG_FIT_SIGNATURE=y
> > > +CONFIG_SHOW_BOOT_PROGRESS=y
> > > +CONFIG_USE_BOOTARGS=y
> > > +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
> >
> > The coreboot firmware supports a lot of different boards. The board may
> > have two SATA drives or may be using NVME drives instead. Why do we have
> > this BOOTARGS line instead of using CONFIG_DISTRO_DEFAULTS=y?
> >
>
> Convert coreboot BOOTARGS
Sorry, hit send too soon.
Convert coreboot BOOTARGS to CONFIG_DISTRO_DEFAULTS makes sense.
Let's keep this series as it is.
Would you please come up with a patch to do distro boot for coreboot?
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-02 13:41 ` Bin Meng
@ 2020-05-02 14:14 ` Heinrich Schuchardt
0 siblings, 0 replies; 8+ messages in thread
From: Heinrich Schuchardt @ 2020-05-02 14:14 UTC (permalink / raw)
To: u-boot
On 5/2/20 3:41 PM, Bin Meng wrote:
> Hi Heinrich,
>
> On Sat, May 2, 2020 at 9:40 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> Hi Heinrich,
>>
>> On Sat, May 2, 2020 at 9:38 PM Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>>>
>>> On 5/1/20 3:36 PM, Simon Glass wrote:
>>>> Coreboot is a first-stage bootloader mostly used on x86 devices as an
>>>> alternative to UEFI. Coreboot runs in 32-bit mode.
>>>>
>>>> U-Boot currently supports booting from coreboot as a second-stage
>>>> bootloader, also in 32-bit mode. However it is useful to be able to run
>>>> U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
>>>> over the CPU and jumps to a 64-bit U-Boot proper.
>>>>
>>>> Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
>>>> uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
>>>>
>>>> This allows running 64-bit EFI images on x86, for example, without needing
>>>> a native U-Boot port for a board.
>>>>
>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>> ---
>>>>
>>>> Changes in v5:
>>>> - Rewrite commit message to explain what coreboot is
>>>>
>>>> board/coreboot/coreboot/MAINTAINERS | 7 +++++
>>>> configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
>>>> doc/board/coreboot/coreboot.rst | 10 ++++++
>>>> 3 files changed, 65 insertions(+)
>>>> create mode 100644 configs/coreboot64_defconfig
>>>>
>>>> diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
>>>> index 188906b080..a05673bb0b 100644
>>>> --- a/board/coreboot/coreboot/MAINTAINERS
>>>> +++ b/board/coreboot/coreboot/MAINTAINERS
>>>> @@ -4,3 +4,10 @@ S: Maintained
>>>> F: board/coreboot/coreboot/
>>>> F: include/configs/chromebook_link.h
>>>> F: configs/coreboot_defconfig
>>>> +
>>>> +COREBOOT64 BOARD
>>>> +M: Simon Glass <sjg@chromium.org>
>>>> +S: Maintained
>>>> +F: board/coreboot/coreboot/
>>>> +F: include/configs/chromebook_link.h
>>>> +F: configs/coreboot64_defconfig
>>>> diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
>>>> new file mode 100644
>>>> index 0000000000..80353b8eb3
>>>> --- /dev/null
>>>> +++ b/configs/coreboot64_defconfig
>>>> @@ -0,0 +1,48 @@
>>>> +CONFIG_X86=y
>>>> +CONFIG_SYS_TEXT_BASE=0x1120000
>>>> +CONFIG_ENV_SIZE=0x1000
>>>> +CONFIG_NR_DRAM_BANKS=8
>>>> +CONFIG_PRE_CON_BUF_ADDR=0x100000
>>>> +CONFIG_X86_RUN_64BIT=y
>>>> +CONFIG_VENDOR_COREBOOT=y
>>>> +CONFIG_TARGET_COREBOOT=y
>>>> +CONFIG_SPL_TEXT_BASE=0x1110000
>>>> +CONFIG_FIT=y
>>>> +CONFIG_FIT_SIGNATURE=y
>>>> +CONFIG_SHOW_BOOT_PROGRESS=y
>>>> +CONFIG_USE_BOOTARGS=y
>>>> +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
>>>
>>> The coreboot firmware supports a lot of different boards. The board may
>>> have two SATA drives or may be using NVME drives instead. Why do we have
>>> this BOOTARGS line instead of using CONFIG_DISTRO_DEFAULTS=y?
>>>
>>
>> Convert coreboot BOOTARGS
>
> Sorry, hit send too soon.
>
> Convert coreboot BOOTARGS to CONFIG_DISTRO_DEFAULTS makes sense.
>
> Let's keep this series as it is.
>
> Would you please come up with a patch to do distro boot for coreboot?
>
> Regards,
> Bin
>
If the move to DISTRO_DEFAULTS is done in a follow-up patch, I am fine
with the patch merged as is.
Best regards
Heinrich
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build
2020-05-01 13:36 ` [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build Simon Glass
2020-05-02 12:59 ` Bin Meng
2020-05-02 13:37 ` Heinrich Schuchardt
@ 2020-05-04 7:26 ` Bin Meng
2 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2020-05-04 7:26 UTC (permalink / raw)
To: u-boot
On Fri, May 1, 2020 at 9:36 PM Simon Glass <sjg@chromium.org> wrote:
>
> Coreboot is a first-stage bootloader mostly used on x86 devices as an
> alternative to UEFI. Coreboot runs in 32-bit mode.
>
> U-Boot currently supports booting from coreboot as a second-stage
> bootloader, also in 32-bit mode. However it is useful to be able to run
> U-Boot in 64-bit mode. To do this we can have a 32-bit SPL which switches
> over the CPU and jumps to a 64-bit U-Boot proper.
>
> Add a new 'coreboot64' board for running 64-bit U-Boot from coreboot. This
> uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.
>
> This allows running 64-bit EFI images on x86, for example, without needing
> a native U-Boot port for a board.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v5:
> - Rewrite commit message to explain what coreboot is
>
> board/coreboot/coreboot/MAINTAINERS | 7 +++++
> configs/coreboot64_defconfig | 48 +++++++++++++++++++++++++++++
> doc/board/coreboot/coreboot.rst | 10 ++++++
> 3 files changed, 65 insertions(+)
> create mode 100644 configs/coreboot64_defconfig
>
applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-05-04 7:26 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-01 13:36 [PATCH v5 0/1] x86: efi: Add a 64-bit coreboot payload Simon Glass
2020-05-01 13:36 ` [PATCH v5 1/1] x86: Add a 64-bit 'coreboot64' build Simon Glass
2020-05-02 12:59 ` Bin Meng
2020-05-02 13:37 ` Heinrich Schuchardt
2020-05-02 13:40 ` Bin Meng
2020-05-02 13:41 ` Bin Meng
2020-05-02 14:14 ` Heinrich Schuchardt
2020-05-04 7:26 ` Bin Meng
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.