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From: Bin Meng <bmeng.cn@gmail.com>
To: Anup Patel <anup.patel@wdc.com>, Jonathan Behrens <jonathan@fintelia.io>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v3 1/2] target/riscv: Emulate TIME CSRs for privileged mode
Date: Sun, 1 Mar 2020 16:22:49 +0800	[thread overview]
Message-ID: <CAEUhbmWhwYx__5jBiywgpc7mbJiK9CSoGcP+_DhWrs94GhG4GA@mail.gmail.com> (raw)
In-Reply-To: <20200202134217.14264-2-anup.patel@wdc.com>

On Sun, Feb 2, 2020 at 9:44 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> Currently, TIME CSRs are emulated only for user-only mode. This
> patch add TIME CSRs emulation for privileged mode.
>
> For privileged mode, the TIME CSRs will return value provided
> by rdtime callback which is registered by QEMU machine/platform
> emulation (i.e. CLINT emulation). If rdtime callback is not
> available then the monitor (i.e. OpenSBI) will trap-n-emulate
> TIME CSRs in software.
>
> We see 25+% performance improvement in hackbench numbers when
> TIME CSRs are not trap-n-emulated.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.h        |  5 +++
>  target/riscv/cpu_helper.c |  5 +++
>  target/riscv/csr.c        | 86 +++++++++++++++++++++++++++++++++++++--
>  3 files changed, 92 insertions(+), 4 deletions(-)
>

Jonathan has a patch before:
http://patchwork.ozlabs.org/patch/1106480/

The idea in his patch does similar thing according to mcounteren.TM.
But in this patch we seem to control the TIME CSR purely by software.
Is this behavior spec complaint?

Regards,
Bin


WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Anup Patel <anup.patel@wdc.com>, Jonathan Behrens <jonathan@fintelia.io>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	 Atish Patra <atish.patra@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v3 1/2] target/riscv: Emulate TIME CSRs for privileged mode
Date: Sun, 1 Mar 2020 16:22:49 +0800	[thread overview]
Message-ID: <CAEUhbmWhwYx__5jBiywgpc7mbJiK9CSoGcP+_DhWrs94GhG4GA@mail.gmail.com> (raw)
In-Reply-To: <20200202134217.14264-2-anup.patel@wdc.com>

On Sun, Feb 2, 2020 at 9:44 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> Currently, TIME CSRs are emulated only for user-only mode. This
> patch add TIME CSRs emulation for privileged mode.
>
> For privileged mode, the TIME CSRs will return value provided
> by rdtime callback which is registered by QEMU machine/platform
> emulation (i.e. CLINT emulation). If rdtime callback is not
> available then the monitor (i.e. OpenSBI) will trap-n-emulate
> TIME CSRs in software.
>
> We see 25+% performance improvement in hackbench numbers when
> TIME CSRs are not trap-n-emulated.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.h        |  5 +++
>  target/riscv/cpu_helper.c |  5 +++
>  target/riscv/csr.c        | 86 +++++++++++++++++++++++++++++++++++++--
>  3 files changed, 92 insertions(+), 4 deletions(-)
>

Jonathan has a patch before:
http://patchwork.ozlabs.org/patch/1106480/

The idea in his patch does similar thing according to mcounteren.TM.
But in this patch we seem to control the TIME CSR purely by software.
Is this behavior spec complaint?

Regards,
Bin


  reply	other threads:[~2020-03-01  8:23 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-02 13:42 [PATCH v3 0/2] RISC-V TIME CSR for privileged mode Anup Patel
2020-02-02 13:42 ` Anup Patel
2020-02-02 13:42 ` [PATCH v3 1/2] target/riscv: Emulate TIME CSRs " Anup Patel
2020-02-02 13:42   ` Anup Patel
2020-03-01  8:22   ` Bin Meng [this message]
2020-03-01  8:22     ` Bin Meng
2020-02-02 13:42 ` [PATCH v3 2/2] hw/riscv: Provide rdtime callback for TCG in CLINT emulation Anup Patel
2020-02-02 13:42   ` Anup Patel
2020-02-18 19:08 ` [PATCH v3 0/2] RISC-V TIME CSR for privileged mode Palmer Dabbelt
2020-02-18 19:08   ` Palmer Dabbelt

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