* [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
@ 2019-11-16 15:08 Bin Meng
2019-11-22 1:10 ` Bin Meng
2019-11-24 7:35 ` Alistair Francis
0 siblings, 2 replies; 11+ messages in thread
From: Bin Meng @ 2019-11-16 15:08 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to specify the board serial
number. When not given, the default serial number 1 is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9552abf..e1a5536 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -34,6 +34,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
@@ -401,6 +402,7 @@ static void riscv_sifive_u_init(MachineState *machine)
static void riscv_sifive_u_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
+ SiFiveUState *us = RISCV_U_MACHINE(ms);
SiFiveUSoCState *s = RISCV_U_SOC(obj);
object_initialize_child(obj, "e-cluster", &s->e_cluster,
@@ -433,7 +435,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_SIFIVE_U_PRCI);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
- qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", us->serial);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -452,6 +454,18 @@ static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
s->start_in_flash = value;
}
+static void sifive_u_get_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
+static void sifive_u_set_serial(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ visit_type_uint32(v, name, (uint32_t *)opaque, errp);
+}
+
static void riscv_sifive_u_machine_instance_init(Object *obj)
{
SiFiveUState *s = RISCV_U_MACHINE(obj);
@@ -463,6 +477,11 @@ static void riscv_sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to " \
"flash. Otherwise QEMU will jump to DRAM",
NULL);
+
+ s->serial = OTP_SERIAL;
+ object_property_add(obj, "serial", "uint32", sifive_u_get_serial,
+ sifive_u_set_serial, NULL, &s->serial, NULL);
+ object_property_set_description(obj, "serial", "Board serial number", NULL);
}
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5..7cf742e 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -59,6 +59,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t serial;
} SiFiveUState;
enum {
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2019-11-16 15:08 [PATCH] riscv: sifive_u: Add a "serial" property for board serial number Bin Meng
@ 2019-11-22 1:10 ` Bin Meng
2019-11-22 2:38 ` Palmer Dabbelt
2019-11-24 7:35 ` Alistair Francis
1 sibling, 1 reply; 11+ messages in thread
From: Bin Meng @ 2019-11-22 1:10 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V
On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to specify the board serial
> number. When not given, the default serial number 1 is used.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
ping?
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2019-11-22 1:10 ` Bin Meng
@ 2019-11-22 2:38 ` Palmer Dabbelt
2020-01-10 7:52 ` Bin Meng
2020-01-29 15:29 ` Palmer Dabbelt
0 siblings, 2 replies; 11+ messages in thread
From: Palmer Dabbelt @ 2019-11-22 2:38 UTC (permalink / raw)
To: bmeng.cn
Cc: Alistair Francis, Bastian Koppelmann, sagark, qemu-devel, qemu-riscv
On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
> On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> At present the board serial number is hard-coded to 1, and passed
>> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>> the serial number to generate a unique MAC address for the on-chip
>> ethernet controller. When multiple QEMU 'sifive_u' instances are
>> created and connected to the same subnet, they all have the same
>> MAC address hence it creates a unusable network.
>>
>> A new "serial" property is introduced to specify the board serial
>> number. When not given, the default serial number 1 is used.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
>> include/hw/riscv/sifive_u.h | 1 +
>> 2 files changed, 21 insertions(+), 1 deletion(-)
>>
>
> ping?
Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
with a
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Thanks!
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2019-11-16 15:08 [PATCH] riscv: sifive_u: Add a "serial" property for board serial number Bin Meng
@ 2019-11-24 7:35 ` Alistair Francis
2019-11-24 7:35 ` Alistair Francis
1 sibling, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2019-11-24 7:35 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Sat, Nov 16, 2019 at 7:09 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to specify the board serial
> number. When not given, the default serial number 1 is used.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 9552abf..e1a5536 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -34,6 +34,7 @@
> #include "qemu/log.h"
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> +#include "qapi/visitor.h"
> #include "hw/boards.h"
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> @@ -401,6 +402,7 @@ static void riscv_sifive_u_init(MachineState *machine)
> static void riscv_sifive_u_soc_init(Object *obj)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> + SiFiveUState *us = RISCV_U_MACHINE(ms);
> SiFiveUSoCState *s = RISCV_U_SOC(obj);
>
> object_initialize_child(obj, "e-cluster", &s->e_cluster,
> @@ -433,7 +435,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
> TYPE_SIFIVE_U_PRCI);
> sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
> TYPE_SIFIVE_U_OTP);
> - qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
> + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", us->serial);
> sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
> TYPE_CADENCE_GEM);
> }
> @@ -452,6 +454,18 @@ static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
> s->start_in_flash = value;
> }
>
> +static void sifive_u_get_serial(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> +}
> +
> +static void sifive_u_set_serial(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> +}
> +
> static void riscv_sifive_u_machine_instance_init(Object *obj)
> {
> SiFiveUState *s = RISCV_U_MACHINE(obj);
> @@ -463,6 +477,11 @@ static void riscv_sifive_u_machine_instance_init(Object *obj)
> "Set on to tell QEMU's ROM to jump to " \
> "flash. Otherwise QEMU will jump to DRAM",
> NULL);
> +
> + s->serial = OTP_SERIAL;
> + object_property_add(obj, "serial", "uint32", sifive_u_get_serial,
> + sifive_u_set_serial, NULL, &s->serial, NULL);
> + object_property_set_description(obj, "serial", "Board serial number", NULL);
> }
>
> static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 82667b5..7cf742e 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -59,6 +59,7 @@ typedef struct SiFiveUState {
> int fdt_size;
>
> bool start_in_flash;
> + uint32_t serial;
> } SiFiveUState;
>
> enum {
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
@ 2019-11-24 7:35 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2019-11-24 7:35 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V
On Sat, Nov 16, 2019 at 7:09 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> At present the board serial number is hard-coded to 1, and passed
> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> the serial number to generate a unique MAC address for the on-chip
> ethernet controller. When multiple QEMU 'sifive_u' instances are
> created and connected to the same subnet, they all have the same
> MAC address hence it creates a unusable network.
>
> A new "serial" property is introduced to specify the board serial
> number. When not given, the default serial number 1 is used.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 21 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 9552abf..e1a5536 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -34,6 +34,7 @@
> #include "qemu/log.h"
> #include "qemu/error-report.h"
> #include "qapi/error.h"
> +#include "qapi/visitor.h"
> #include "hw/boards.h"
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> @@ -401,6 +402,7 @@ static void riscv_sifive_u_init(MachineState *machine)
> static void riscv_sifive_u_soc_init(Object *obj)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> + SiFiveUState *us = RISCV_U_MACHINE(ms);
> SiFiveUSoCState *s = RISCV_U_SOC(obj);
>
> object_initialize_child(obj, "e-cluster", &s->e_cluster,
> @@ -433,7 +435,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
> TYPE_SIFIVE_U_PRCI);
> sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
> TYPE_SIFIVE_U_OTP);
> - qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
> + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", us->serial);
> sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
> TYPE_CADENCE_GEM);
> }
> @@ -452,6 +454,18 @@ static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
> s->start_in_flash = value;
> }
>
> +static void sifive_u_get_serial(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> +}
> +
> +static void sifive_u_set_serial(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> +}
> +
> static void riscv_sifive_u_machine_instance_init(Object *obj)
> {
> SiFiveUState *s = RISCV_U_MACHINE(obj);
> @@ -463,6 +477,11 @@ static void riscv_sifive_u_machine_instance_init(Object *obj)
> "Set on to tell QEMU's ROM to jump to " \
> "flash. Otherwise QEMU will jump to DRAM",
> NULL);
> +
> + s->serial = OTP_SERIAL;
> + object_property_add(obj, "serial", "uint32", sifive_u_get_serial,
> + sifive_u_set_serial, NULL, &s->serial, NULL);
> + object_property_set_description(obj, "serial", "Board serial number", NULL);
> }
>
> static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 82667b5..7cf742e 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -59,6 +59,7 @@ typedef struct SiFiveUState {
> int fdt_size;
>
> bool start_in_flash;
> + uint32_t serial;
> } SiFiveUState;
>
> enum {
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2019-11-22 2:38 ` Palmer Dabbelt
@ 2020-01-10 7:52 ` Bin Meng
2020-01-29 15:29 ` Palmer Dabbelt
1 sibling, 0 replies; 11+ messages in thread
From: Bin Meng @ 2020-01-10 7:52 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Bastian Koppelmann, Alistair Francis,
qemu-devel@nongnu.org Developers, Sagar Karandikar,
open list:RISC-V
Hi Palmer,
On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt
<palmerdabbelt@google.com> wrote:
>
> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> At present the board serial number is hard-coded to 1, and passed
> >> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> >> the serial number to generate a unique MAC address for the on-chip
> >> ethernet controller. When multiple QEMU 'sifive_u' instances are
> >> created and connected to the same subnet, they all have the same
> >> MAC address hence it creates a unusable network.
> >>
> >> A new "serial" property is introduced to specify the board serial
> >> number. When not given, the default serial number 1 is used.
> >>
> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >> ---
> >>
> >> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> >> include/hw/riscv/sifive_u.h | 1 +
> >> 2 files changed, 21 insertions(+), 1 deletion(-)
> >>
> >
> > ping?
>
> Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
> with a
>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Has this been applied somewhere?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
@ 2020-01-10 7:52 ` Bin Meng
0 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2020-01-10 7:52 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, Bastian Koppelmann, Sagar Karandikar,
qemu-devel@nongnu.org Developers, open list:RISC-V
Hi Palmer,
On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt
<palmerdabbelt@google.com> wrote:
>
> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> At present the board serial number is hard-coded to 1, and passed
> >> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> >> the serial number to generate a unique MAC address for the on-chip
> >> ethernet controller. When multiple QEMU 'sifive_u' instances are
> >> created and connected to the same subnet, they all have the same
> >> MAC address hence it creates a unusable network.
> >>
> >> A new "serial" property is introduced to specify the board serial
> >> number. When not given, the default serial number 1 is used.
> >>
> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >> ---
> >>
> >> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> >> include/hw/riscv/sifive_u.h | 1 +
> >> 2 files changed, 21 insertions(+), 1 deletion(-)
> >>
> >
> > ping?
>
> Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
> with a
>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Has this been applied somewhere?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2019-11-22 2:38 ` Palmer Dabbelt
2020-01-10 7:52 ` Bin Meng
@ 2020-01-29 15:29 ` Palmer Dabbelt
2020-02-10 19:55 ` Palmer Dabbelt
1 sibling, 1 reply; 11+ messages in thread
From: Palmer Dabbelt @ 2020-01-29 15:29 UTC (permalink / raw)
To: bmeng.cn
Cc: Alistair Francis, Bastian Koppelmann, sagark, qemu-devel, qemu-riscv
On Fri, 10 Jan 2020 07:52:05 GMT (+0000), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt
> <palmerdabbelt@google.com> wrote:
>>
>> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
>> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>> >>
>> >> At present the board serial number is hard-coded to 1, and passed
>> >> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>> >> the serial number to generate a unique MAC address for the on-chip
>> >> ethernet controller. When multiple QEMU 'sifive_u' instances are
>> >> created and connected to the same subnet, they all have the same
>> >> MAC address hence it creates a unusable network.
>> >>
>> >> A new "serial" property is introduced to specify the board serial
>> >> number. When not given, the default serial number 1 is used.
>> >>
>> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> >> ---
>> >>
>> >> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
>> >> include/hw/riscv/sifive_u.h | 1 +
>> >> 2 files changed, 21 insertions(+), 1 deletion(-)
>> >>
>> >
>> > ping?
>>
>> Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
>> with a
>>
>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>
> Has this been applied somewhere?
Weird, not sure how I managed to screw this up again. It's actually on for-master as
* a828041ba6 - riscv: sifive_u: Add a "serial" property for board serial number (50 seconds ago) <Bin Meng>
with any luck I'll manage to avoid screwing it up a third time.
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2020-01-29 15:29 ` Palmer Dabbelt
@ 2020-02-10 19:55 ` Palmer Dabbelt
2020-02-11 15:57 ` Bin Meng
0 siblings, 1 reply; 11+ messages in thread
From: Palmer Dabbelt @ 2020-02-10 19:55 UTC (permalink / raw)
To: bmeng.cn
Cc: Alistair Francis, Bastian Koppelmann, sagark, qemu-devel, qemu-riscv
On Wed, 29 Jan 2020 07:29:11 PST (-0800), Palmer Dabbelt wrote:
> On Fri, 10 Jan 2020 07:52:05 GMT (+0000), bmeng.cn@gmail.com wrote:
>> Hi Palmer,
>>
>> On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt
>> <palmerdabbelt@google.com> wrote:
>>>
>>> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
>>> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>> >>
>>> >> At present the board serial number is hard-coded to 1, and passed
>>> >> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
>>> >> the serial number to generate a unique MAC address for the on-chip
>>> >> ethernet controller. When multiple QEMU 'sifive_u' instances are
>>> >> created and connected to the same subnet, they all have the same
>>> >> MAC address hence it creates a unusable network.
>>> >>
>>> >> A new "serial" property is introduced to specify the board serial
>>> >> number. When not given, the default serial number 1 is used.
>>> >>
>>> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> >> ---
>>> >>
>>> >> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
>>> >> include/hw/riscv/sifive_u.h | 1 +
>>> >> 2 files changed, 21 insertions(+), 1 deletion(-)
>>> >>
>>> >
>>> > ping?
>>>
>>> Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
>>> with a
>>>
>>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>
>> Has this been applied somewhere?
>
> Weird, not sure how I managed to screw this up again. It's actually on for-master as
>
> * a828041ba6 - riscv: sifive_u: Add a "serial" property for board serial number (50 seconds ago) <Bin Meng>
>
> with any luck I'll manage to avoid screwing it up a third time.
Ah, OK -- the issue here is that this fails "make check", specifically
$ make check-qtest-riscv64
make[1]: Entering directory '/home/palmerdabbelt/life/riscv/qemu/slirp'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/palmerdabbelt/life/riscv/qemu/slirp'
CHK version_gen.h
TEST check-qtest-riscv64: tests/qtest/cdrom-test
TEST check-qtest-riscv64: tests/qtest/device-introspect-test
/home/palmerdabbelt/life/riscv/qemu/hw/riscv/sifive_u.c:406:riscv_sifive_u_soc_init: Object 0x55baf3feea00 is not an instance of type sifive_u-machine
Broken pipe
tests/qtest/libqtest.c:149: kill_qemu() detected QEMU death from signal 6 (Aborted)
ERROR - too few tests run (expected 6, got 5)
make: *** [/home/palmerdabbelt/life/riscv/qemu/tests/Makefile.include:630: check-qtest-riscv64] Error 1
which is probably how it kept getting disappeared -- I just forgot to reply on
the list. I'm going to hold it back from the PR I'm staging right now, LMK if
you have a fix.
>
>>
>> Regards,
>> Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
2020-02-10 19:55 ` Palmer Dabbelt
@ 2020-02-11 15:57 ` Bin Meng
0 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2020-02-11 15:57 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Bastian Koppelmann, Alistair Francis,
qemu-devel@nongnu.org Developers, Sagar Karandikar,
open list:RISC-V
Hi Palmer,
On Tue, Feb 11, 2020 at 3:55 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> On Wed, 29 Jan 2020 07:29:11 PST (-0800), Palmer Dabbelt wrote:
> > On Fri, 10 Jan 2020 07:52:05 GMT (+0000), bmeng.cn@gmail.com wrote:
> >> Hi Palmer,
> >>
> >> On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt
> >> <palmerdabbelt@google.com> wrote:
> >>>
> >>> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
> >>> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>> >>
> >>> >> At present the board serial number is hard-coded to 1, and passed
> >>> >> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> >>> >> the serial number to generate a unique MAC address for the on-chip
> >>> >> ethernet controller. When multiple QEMU 'sifive_u' instances are
> >>> >> created and connected to the same subnet, they all have the same
> >>> >> MAC address hence it creates a unusable network.
> >>> >>
> >>> >> A new "serial" property is introduced to specify the board serial
> >>> >> number. When not given, the default serial number 1 is used.
> >>> >>
> >>> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >>> >> ---
> >>> >>
> >>> >> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> >>> >> include/hw/riscv/sifive_u.h | 1 +
> >>> >> 2 files changed, 21 insertions(+), 1 deletion(-)
> >>> >>
> >>> >
> >>> > ping?
> >>>
> >>> Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
> >>> with a
> >>>
> >>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >>
> >> Has this been applied somewhere?
> >
> > Weird, not sure how I managed to screw this up again. It's actually on for-master as
> >
> > * a828041ba6 - riscv: sifive_u: Add a "serial" property for board serial number (50 seconds ago) <Bin Meng>
> >
> > with any luck I'll manage to avoid screwing it up a third time.
>
> Ah, OK -- the issue here is that this fails "make check", specifically
>
> $ make check-qtest-riscv64
> make[1]: Entering directory '/home/palmerdabbelt/life/riscv/qemu/slirp'
> make[1]: Nothing to be done for 'all'.
> make[1]: Leaving directory '/home/palmerdabbelt/life/riscv/qemu/slirp'
> CHK version_gen.h
> TEST check-qtest-riscv64: tests/qtest/cdrom-test
> TEST check-qtest-riscv64: tests/qtest/device-introspect-test
> /home/palmerdabbelt/life/riscv/qemu/hw/riscv/sifive_u.c:406:riscv_sifive_u_soc_init: Object 0x55baf3feea00 is not an instance of type sifive_u-machine
> Broken pipe
> tests/qtest/libqtest.c:149: kill_qemu() detected QEMU death from signal 6 (Aborted)
> ERROR - too few tests run (expected 6, got 5)
> make: *** [/home/palmerdabbelt/life/riscv/qemu/tests/Makefile.include:630: check-qtest-riscv64] Error 1
>
> which is probably how it kept getting disappeared -- I just forgot to reply on
> the list. I'm going to hold it back from the PR I'm staging right now, LMK if
> you have a fix.
OK, I will take a look. I remember I did run "make check" but it did
not report any issue before. Is 'make check-qtest-riscv64' not part of
'make check'?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] riscv: sifive_u: Add a "serial" property for board serial number
@ 2020-02-11 15:57 ` Bin Meng
0 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2020-02-11 15:57 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, Bastian Koppelmann, Sagar Karandikar,
qemu-devel@nongnu.org Developers, open list:RISC-V
Hi Palmer,
On Tue, Feb 11, 2020 at 3:55 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> On Wed, 29 Jan 2020 07:29:11 PST (-0800), Palmer Dabbelt wrote:
> > On Fri, 10 Jan 2020 07:52:05 GMT (+0000), bmeng.cn@gmail.com wrote:
> >> Hi Palmer,
> >>
> >> On Fri, Nov 22, 2019 at 10:38 AM Palmer Dabbelt
> >> <palmerdabbelt@google.com> wrote:
> >>>
> >>> On Thu, 21 Nov 2019 17:10:18 PST (-0800), bmeng.cn@gmail.com wrote:
> >>> > On Sat, Nov 16, 2019 at 11:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>> >>
> >>> >> At present the board serial number is hard-coded to 1, and passed
> >>> >> to OTP model during initialization. Firmware (FSBL, U-Boot) uses
> >>> >> the serial number to generate a unique MAC address for the on-chip
> >>> >> ethernet controller. When multiple QEMU 'sifive_u' instances are
> >>> >> created and connected to the same subnet, they all have the same
> >>> >> MAC address hence it creates a unusable network.
> >>> >>
> >>> >> A new "serial" property is introduced to specify the board serial
> >>> >> number. When not given, the default serial number 1 is used.
> >>> >>
> >>> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> >>> >> ---
> >>> >>
> >>> >> hw/riscv/sifive_u.c | 21 ++++++++++++++++++++-
> >>> >> include/hw/riscv/sifive_u.h | 1 +
> >>> >> 2 files changed, 21 insertions(+), 1 deletion(-)
> >>> >>
> >>> >
> >>> > ping?
> >>>
> >>> Sorry, it looks like I dropped this one. I've put it in the queue for 5.0,
> >>> with a
> >>>
> >>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> >>
> >> Has this been applied somewhere?
> >
> > Weird, not sure how I managed to screw this up again. It's actually on for-master as
> >
> > * a828041ba6 - riscv: sifive_u: Add a "serial" property for board serial number (50 seconds ago) <Bin Meng>
> >
> > with any luck I'll manage to avoid screwing it up a third time.
>
> Ah, OK -- the issue here is that this fails "make check", specifically
>
> $ make check-qtest-riscv64
> make[1]: Entering directory '/home/palmerdabbelt/life/riscv/qemu/slirp'
> make[1]: Nothing to be done for 'all'.
> make[1]: Leaving directory '/home/palmerdabbelt/life/riscv/qemu/slirp'
> CHK version_gen.h
> TEST check-qtest-riscv64: tests/qtest/cdrom-test
> TEST check-qtest-riscv64: tests/qtest/device-introspect-test
> /home/palmerdabbelt/life/riscv/qemu/hw/riscv/sifive_u.c:406:riscv_sifive_u_soc_init: Object 0x55baf3feea00 is not an instance of type sifive_u-machine
> Broken pipe
> tests/qtest/libqtest.c:149: kill_qemu() detected QEMU death from signal 6 (Aborted)
> ERROR - too few tests run (expected 6, got 5)
> make: *** [/home/palmerdabbelt/life/riscv/qemu/tests/Makefile.include:630: check-qtest-riscv64] Error 1
>
> which is probably how it kept getting disappeared -- I just forgot to reply on
> the list. I'm going to hold it back from the PR I'm staging right now, LMK if
> you have a fix.
OK, I will take a look. I remember I did run "make check" but it did
not report any issue before. Is 'make check-qtest-riscv64' not part of
'make check'?
Regards,
Bin
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-02-11 15:58 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-16 15:08 [PATCH] riscv: sifive_u: Add a "serial" property for board serial number Bin Meng
2019-11-22 1:10 ` Bin Meng
2019-11-22 2:38 ` Palmer Dabbelt
2020-01-10 7:52 ` Bin Meng
2020-01-10 7:52 ` Bin Meng
2020-01-29 15:29 ` Palmer Dabbelt
2020-02-10 19:55 ` Palmer Dabbelt
2020-02-11 15:57 ` Bin Meng
2020-02-11 15:57 ` Bin Meng
2019-11-24 7:35 ` Alistair Francis
2019-11-24 7:35 ` Alistair Francis
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