[PATCH v2 0/4] x86: Correct SPI memory-mapping query

[PATCH v2 0/4] x86: Correct SPI memory-mapping query

[Simon Glass]

This little series makes the SPI memory-mapping query work on all current
x86 boards where possible, returning an error code (rather than hanging)
when it fails.

It replaces the previous patch at [1]. Unfortunately it is quite a bit
more complicated.

This fixes booting on link and samus. It also fixes MRC saving on
minnowmax.

[1] http://patchwork.ozlabs.org/project/uboot/patch/20200324074524.1.Ibc9c511db58caa8a1e4c56d7e7824d7690718aeb at changeid/

Changes in v2:
- Fix a 'BFF' typo
- Add new patch to allow use before driver model is active

Simon Glass (4):
  x86: spi: Add a way to access the SPI mapping via registers
  x86: spi: Rewrite logic for obtaining the SPI memory map
  x86: spl: Print the error on SPL failure
  x86: mrccache: Allow use before driver model is active

 arch/x86/cpu/intel_common/fast_spi.c |  19 +++--
 arch/x86/include/asm/fast_spi.h      |  19 +++++
 arch/x86/include/asm/mrccache.h      |  15 ++--
 arch/x86/lib/mrccache.c              |  35 ++++++---
 arch/x86/lib/spl.c                   |   4 +-
 drivers/spi/ich.c                    | 103 +++++++++++++++++++++++----
 6 files changed, 152 insertions(+), 43 deletions(-)

-- 
2.27.0.rc0.183.gde8f92d652-goog

[PATCH v2 1/4] x86: spi: Add a way to access the SPI mapping via registers

[Simon Glass]

At present the PCI BDF (bus/device/function) is needed to access the SPI
mapping, since the registers are at BAR0. This doesn't work when PCI
auto-config has not been done yet, since BARs are unassigned.

Add another way to find the mapping, using the MMIO base, if the caller
knows this.

Also add a missing function comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/intel_common/fast_spi.c | 19 ++++++++++++++-----
 arch/x86/include/asm/fast_spi.h      | 19 +++++++++++++++++++
 2 files changed, 33 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/intel_common/fast_spi.c b/arch/x86/cpu/intel_common/fast_spi.c
index a6e3d0a5bf..5d3944dee2 100644
--- a/arch/x86/cpu/intel_common/fast_spi.c
+++ b/arch/x86/cpu/intel_common/fast_spi.c
@@ -31,21 +31,30 @@ static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs,
 	return bios_start;
 }
 
+int fast_spi_get_bios_mmap_regs(struct fast_spi_regs *regs, ulong *map_basep,
+				uint *map_sizep, uint *offsetp)
+{
+	ulong base;
+
+	base = fast_spi_get_bios_region(regs, map_sizep);
+	*map_basep = (u32)-*map_sizep - base;
+	*offsetp = base;
+
+	return 0;
+}
+
 int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
 			   uint *offsetp)
 {
 	struct fast_spi_regs *regs;
-	ulong bar, base, mmio_base;
+	ulong bar, mmio_base;
 
 	/* Special case to find mapping without probing the device */
 	pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
 	mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
 	regs = (struct fast_spi_regs *)mmio_base;
-	base = fast_spi_get_bios_region(regs, map_sizep);
-	*map_basep = (u32)-*map_sizep - base;
-	*offsetp = base;
 
-	return 0;
+	return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep, offsetp);
 }
 
 int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base)
diff --git a/arch/x86/include/asm/fast_spi.h b/arch/x86/include/asm/fast_spi.h
index 47c1da80d7..7a81d4f05c 100644
--- a/arch/x86/include/asm/fast_spi.h
+++ b/arch/x86/include/asm/fast_spi.h
@@ -64,6 +64,25 @@ check_member(fast_spi_regs, ptdata, 0xd0);
 int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
 			   uint *offsetp);
 
+/**
+ * fast_spi_get_bios_mmap_regs() - Get memory map for SPI flash given regs
+ *
+ * @regs:	SPI registers to use
+ * @map_basep:	Returns base memory address for mapped SPI
+ * @map_sizep:	Returns size of mapped SPI
+ * @offsetp:	Returns start offset of SPI flash where the map works
+ *	correctly (offsets before this are not visible)
+ * @return 0 (always)
+ */
+int fast_spi_get_bios_mmap_regs(struct fast_spi_regs *regs, ulong *map_basep,
+				uint *map_sizep, uint *offsetp);
+
+/**
+ * fast_spi_early_init() - Set up a BAR to use SPI early in U-Boot
+ *
+ * @pdev:	PCI device to use (this is the Fast SPI device)
+ * @mmio_base:	MMIO base to use to access registers
+ */
 int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base);
 
 #endif	/* ASM_FAST_SPI_H */
-- 
2.27.0.rc0.183.gde8f92d652-goog

[PATCH v2 2/4] x86: spi: Rewrite logic for obtaining the SPI memory map

[Simon Glass]

At present this logic does not work on link and samus, since their SPI
controller is not a PCI device, but a child of the PCH.

Unfortunately, fixing this involves a lot of extra logic. Still, this was
requested in the review of the fix-up patch, so here it is.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 92842147c31 ("spi: ich: Add support for get_mmap() method")
---

Changes in v2:
- Fix a 'BFF' typo

 drivers/spi/ich.c | 103 +++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 88 insertions(+), 15 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 7405062846..e1336b89c5 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -24,6 +24,7 @@
 #include <spl.h>
 #include <asm/fast_spi.h>
 #include <asm/io.h>
+#include <dm/uclass-internal.h>
 #include <asm/mtrr.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
@@ -614,15 +615,94 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
 	return ret;
 }
 
+/**
+ * ich_spi_get_basics() - Get basic information about the ICH device
+ *
+ * This works without probing any devices if requested.
+ *
+ * @bus: SPI controller to use
+ * @can_probe: true if this function is allowed to probe the PCH
+ * @pchp: Returns a pointer to the pch, or NULL if not found
+ * @ich_versionp: Returns ICH version detected on success
+ * @mmio_basep: Returns the address of the SPI registers on success
+ * @return 0 if OK, -EPROTOTYPE if the PCH could not be found, -EAGAIN if
+ *	the function cannot success without probing, possible another error if
+ *	pch_get_spi_base() fails
+ */
+static int ich_spi_get_basics(struct udevice *bus, bool can_probe,
+			      struct udevice **pchp,
+			      enum ich_version *ich_versionp, ulong *mmio_basep)
+{
+	struct udevice *pch = NULL;
+	int ret = 0;
+
+	/* Find a PCH if there is one */
+	if (can_probe) {
+		pch = dev_get_parent(bus);
+		if (device_get_uclass_id(pch) != UCLASS_PCH) {
+			uclass_first_device(UCLASS_PCH, &pch);
+			if (!pch)
+				return log_msg_ret("uclass", -EPROTOTYPE);
+		}
+	}
+
+	*ich_versionp = dev_get_driver_data(bus);
+	if (*ich_versionp == ICHV_APL)
+		*mmio_basep = dm_pci_read_bar32(bus, 0);
+	else if (pch)
+		ret = pch_get_spi_base(pch, mmio_basep);
+	else
+		return -EAGAIN;
+	*pchp = pch;
+
+	return ret;
+}
+
+/**
+ * ich_get_mmap_bus() - Handle the get_mmap() method for a bus
+ *
+ * There are several cases to consider:
+ * 1. Using of-platdata, in which case we have the BDF and can access the
+ *	registers by reading the BAR
+ * 2. Not using of-platdata, but still with a SPI controller that is on its own
+ * PCI PDF. In this case we read the BDF from the parent platdata and again get
+ *	the registers by reading the BAR
+ * 3. Using a SPI controller that is a child of the PCH, in which case we try
+ *	to find the registers by asking the PCH. This only works if the PCH has
+ *	been probed (which it will be if the bus is probed since parents are
+ *	probed before children), since the PCH may not have a PCI address until
+ *	its parent (the PCI bus itself) has been probed. If you are using this
+ *	method then you should make sure the SPI bus is probed.
+ *
+ * The first two cases are useful in early init. The last one is more useful
+ * afterwards.
+ */
 static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep,
 			    uint *map_sizep, uint *offsetp)
 {
 	pci_dev_t spi_bdf;
-
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct pci_child_platdata *pplat = dev_get_parent_platdata(bus);
+	if (device_is_on_pci_bus(bus)) {
+		struct pci_child_platdata *pplat;
+
+		pplat = dev_get_parent_platdata(bus);
+		spi_bdf = pplat->devfn;
+	} else {
+		enum ich_version ich_version;
+		struct fast_spi_regs *regs;
+		struct udevice *pch;
+		ulong mmio_base;
+		int ret;
 
-	spi_bdf = pplat->devfn;
+		ret = ich_spi_get_basics(bus, device_active(bus), &pch,
+					 &ich_version, &mmio_base);
+		if (ret)
+			return log_msg_ret("basics", ret);
+		regs = (struct fast_spi_regs *)mmio_base;
+
+		return fast_spi_get_bios_mmap_regs(regs, map_basep, map_sizep,
+						   offsetp);
+	}
 #else
 	struct ich_spi_platdata *plat = dev_get_platdata(bus);
 
@@ -866,23 +946,16 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ich_spi_platdata *plat = dev_get_platdata(dev);
+	int ret;
 
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct ich_spi_priv *priv = dev_get_priv(dev);
 
-	/* Find a PCH if there is one */
-	uclass_first_device(UCLASS_PCH, &priv->pch);
-	if (!priv->pch)
-		priv->pch = dev_get_parent(dev);
-
-	plat->ich_version = dev_get_driver_data(dev);
+	ret = ich_spi_get_basics(dev, true, &priv->pch, &plat->ich_version,
+				 &plat->mmio_base);
+	if (ret)
+		return log_msg_ret("basics", ret);
 	plat->lockdown = dev_read_bool(dev, "intel,spi-lock-down");
-	if (plat->ich_version == ICHV_APL) {
-		plat->mmio_base = dm_pci_read_bar32(dev, 0);
-	} else  {
-		/* SBASE is similar */
-		pch_get_spi_base(priv->pch, &plat->mmio_base);
-	}
 	/*
 	 * Use an int so that the property is present in of-platdata even
 	 * when false.
-- 
2.27.0.rc0.183.gde8f92d652-goog

[PATCH v2 3/4] x86: spl: Print the error on SPL failure

[Simon Glass]

The error code is often useful to figure out what is going on. Printing it
does not increase code size much, so print out the error and then hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/lib/spl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index b6f9a70ba7..cf22fa2d7b 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -164,8 +164,8 @@ void board_init_f(ulong flags)
 
 	ret = x86_spl_init();
 	if (ret) {
-		debug("Error %d\n", ret);
-		panic("x86_spl_init fail");
+		printf("x86_spl_init: error %d\n", ret);
+		hang();
 	}
 #if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
 	gd->bd = malloc(sizeof(*gd->bd));
-- 
2.27.0.rc0.183.gde8f92d652-goog

[PATCH v2 4/4] x86: mrccache: Allow use before driver model is active

[Simon Glass]

The change to avoid searching the device tree does not work on boards
wich don't have driver model set up this early, for example minnowmax.
Put back the old code (converted to livetree) as a fallback for these
devices. Also update the documentation.

This is tested on minnowmax, link, samus and coral.

Fixes: 87f1084a630 (x86: Adjust mrccache_get_region() to use livetree)
Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Add new patch to allow use before driver model is active

 arch/x86/include/asm/mrccache.h | 15 ++++----------
 arch/x86/lib/mrccache.c         | 35 +++++++++++++++++++++++----------
 2 files changed, 29 insertions(+), 21 deletions(-)

diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
index d6b7529073..b60d1171f7 100644
--- a/arch/x86/include/asm/mrccache.h
+++ b/arch/x86/include/asm/mrccache.h
@@ -66,19 +66,12 @@ int mrccache_reserve(void);
  * mrccache_get_region() - get MRC region on the SPI flash
  *
  * This gets MRC region whose offset and size are described in the device tree
- * as a subnode to the SPI flash. If a non-NULL device pointer is supplied,
- * this also probes the SPI flash device and returns its device pointer for
- * the caller to use later.
- *
- * Be careful when calling this routine with a non-NULL device pointer:
- * - driver model initialization must be complete
- * - calling in the pre-relocation phase may bring some side effects during
- *   the SPI flash device probe (eg: for SPI controllers on a PCI bus, it
- *   triggers PCI bus enumeration during which insufficient memory issue
- *   might be exposed and it causes subsequent SPI flash probe fails).
+ * as a subnode to the SPI flash. This tries to find the SPI flash device
+ * (without probing it), falling back to looking for the devicetree node if
+ * driver model is not inited or the SPI flash is not found.
  *
  * @type:	Type of MRC data to use
- * @devp:	Returns pointer to the SPI flash device
+ * @devp:	Returns pointer to the SPI flash device, if found
  * @entry:	Position and size of MRC cache in SPI flash
  * @return 0 if success, -ENOENT if SPI flash node does not exist in the
  * device tree, -EPERM if MRC region subnode does not exist in the device
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 21c71e036e..f181e8100c 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -233,6 +233,7 @@ int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
 	ulong map_base;
 	uint map_size;
 	uint offset;
+	ofnode node;
 	u32 reg[2];
 	int ret;
 
@@ -242,23 +243,36 @@ int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
 	 * memory map cannot be read.
 	 */
 	ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
-	if (!ret && !dev)
+	if (ret || !dev) {
+		/*
+		 * Fall back to searching the device tree since driver model
+		 * may not be ready yet (e.g. with FSPv1)
+		 */
+		node = ofnode_by_compatible(ofnode_null(), "jedec,spi-nor");
+		if (!ofnode_valid(node))
+			return log_msg_ret("Cannot find SPI flash\n", -ENOENT);
 		ret = -ENODEV;
-	if (ret)
-		return log_msg_ret("Cannot find SPI flash\n", ret);
-	ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
-	if (!ret) {
-		entry->base = map_base;
 	} else {
-		ret = dev_read_u32_array(dev, "memory-map", reg, 2);
+		ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
+		if (!ret)
+			entry->base = map_base;
+		node = dev_ofnode(dev);
+	}
+
+	/*
+	 * At this point we have entry->base if ret == 0. If not, then we have
+	 * the node and can look for memory-map
+	 */
+	if (ret) {
+		ret = ofnode_read_u32_array(node, "memory-map", reg, 2);
 		if (ret)
 			return log_msg_ret("Cannot find memory map\n", ret);
 		entry->base = reg[0];
 	}
 
 	/* Find the place where we put the MRC cache */
-	mrc_node = dev_read_subnode(dev, type == MRC_TYPE_NORMAL ?
-				    "rw-mrc-cache" : "rw-var-mrc-cache");
+	mrc_node = ofnode_find_subnode(node, type == MRC_TYPE_NORMAL ?
+				       "rw-mrc-cache" : "rw-var-mrc-cache");
 	if (!ofnode_valid(mrc_node))
 		return log_msg_ret("Cannot find node", -EPERM);
 
@@ -271,7 +285,8 @@ int mrccache_get_region(enum mrc_type_t type, struct udevice **devp,
 	if (devp)
 		*devp = dev;
 	debug("MRC cache type %d in '%s', offset %x, len %x, base %x\n",
-	      type, dev->name, entry->offset, entry->length, entry->base);
+	      type, dev ? dev->name : ofnode_get_name(node), entry->offset,
+	      entry->length, entry->base);
 
 	return 0;
 }
-- 
2.27.0.rc0.183.gde8f92d652-goog

[PATCH v2 1/4] x86: spi: Add a way to access the SPI mapping via registers

[Bin Meng]

On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present the PCI BDF (bus/device/function) is needed to access the SPI
> mapping, since the registers are at BAR0. This doesn't work when PCI
> auto-config has not been done yet, since BARs are unassigned.
>
> Add another way to find the mapping, using the MMIO base, if the caller
> knows this.
>
> Also add a missing function comment.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/intel_common/fast_spi.c | 19 ++++++++++++++-----
>  arch/x86/include/asm/fast_spi.h      | 19 +++++++++++++++++++
>  2 files changed, 33 insertions(+), 5 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v2 2/4] x86: spi: Rewrite logic for obtaining the SPI memory map

[Bin Meng]

On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present this logic does not work on link and samus, since their SPI
> controller is not a PCI device, but a child of the PCH.
>
> Unfortunately, fixing this involves a lot of extra logic. Still, this was
> requested in the review of the fix-up patch, so here it is.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Fixes: 92842147c31 ("spi: ich: Add support for get_mmap() method")
> ---
>
> Changes in v2:
> - Fix a 'BFF' typo
>
>  drivers/spi/ich.c | 103 +++++++++++++++++++++++++++++++++++++++-------
>  1 file changed, 88 insertions(+), 15 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)

[PATCH v2 3/4] x86: spl: Print the error on SPL failure

[Bin Meng]

On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
>
> The error code is often useful to figure out what is going on. Printing it
> does not increase code size much, so print out the error and then hang.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/lib/spl.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[PATCH v2 4/4] x86: mrccache: Allow use before driver model is active

[Bin Meng]

On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
>
> The change to avoid searching the device tree does not work on boards
> wich don't have driver model set up this early, for example minnowmax.
> Put back the old code (converted to livetree) as a fallback for these
> devices. Also update the documentation.
>
> This is tested on minnowmax, link, samus and coral.
>
> Fixes: 87f1084a630 (x86: Adjust mrccache_get_region() to use livetree)
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Add new patch to allow use before driver model is active
>
>  arch/x86/include/asm/mrccache.h | 15 ++++----------
>  arch/x86/lib/mrccache.c         | 35 +++++++++++++++++++++++----------
>  2 files changed, 29 insertions(+), 21 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)

[PATCH v2 1/4] x86: spi: Add a way to access the SPI mapping via registers

[Bin Meng]

On Thu, May 28, 2020 at 3:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present the PCI BDF (bus/device/function) is needed to access the SPI
> > mapping, since the registers are at BAR0. This doesn't work when PCI
> > auto-config has not been done yet, since BARs are unassigned.
> >
> > Add another way to find the mapping, using the MMIO base, if the caller
> > knows this.
> >
> > Also add a missing function comment.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v2: None
> >
> >  arch/x86/cpu/intel_common/fast_spi.c | 19 ++++++++++++++-----
> >  arch/x86/include/asm/fast_spi.h      | 19 +++++++++++++++++++
> >  2 files changed, 33 insertions(+), 5 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[PATCH v2 2/4] x86: spi: Rewrite logic for obtaining the SPI memory map

[Bin Meng]

On Thu, May 28, 2020 at 3:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > At present this logic does not work on link and samus, since their SPI
> > controller is not a PCI device, but a child of the PCH.
> >
> > Unfortunately, fixing this involves a lot of extra logic. Still, this was
> > requested in the review of the fix-up patch, so here it is.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > Fixes: 92842147c31 ("spi: ich: Add support for get_mmap() method")
> > ---
> >
> > Changes in v2:
> > - Fix a 'BFF' typo
> >
> >  drivers/spi/ich.c | 103 +++++++++++++++++++++++++++++++++++++++-------
> >  1 file changed, 88 insertions(+), 15 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)

applied to u-boot-x86, thanks!

[PATCH v2 3/4] x86: spl: Print the error on SPL failure

[Bin Meng]

On Thu, May 28, 2020 at 3:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > The error code is often useful to figure out what is going on. Printing it
> > does not increase code size much, so print out the error and then hang.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v2: None
> >
> >  arch/x86/lib/spl.c | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

applied to u-boot-x86, thanks!

[PATCH v2 4/4] x86: mrccache: Allow use before driver model is active

[Bin Meng]

On Thu, May 28, 2020 at 3:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Wed, May 27, 2020 at 8:58 PM Simon Glass <sjg@chromium.org> wrote:
> >
> > The change to avoid searching the device tree does not work on boards
> > wich don't have driver model set up this early, for example minnowmax.
> > Put back the old code (converted to livetree) as a fallback for these
> > devices. Also update the documentation.
> >
> > This is tested on minnowmax, link, samus and coral.
> >
> > Fixes: 87f1084a630 (x86: Adjust mrccache_get_region() to use livetree)
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v2:
> > - Add new patch to allow use before driver model is active
> >
> >  arch/x86/include/asm/mrccache.h | 15 ++++----------
> >  arch/x86/lib/mrccache.c         | 35 +++++++++++++++++++++++----------
> >  2 files changed, 29 insertions(+), 21 deletions(-)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)

applied to u-boot-x86, thanks!