* [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
@ 2021-10-22 6:01 Alistair Francis
2021-10-22 6:01 ` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function Alistair Francis
` (4 more replies)
0 siblings, 5 replies; 17+ messages in thread
From: Alistair Francis @ 2021-10-22 6:01 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, alistair23, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
Using a macro for the PLIC configuration doesn't make the code any
easier to read. Instead it makes it harder to figure out what is going
on, so let's remove it.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
include/hw/riscv/virt.h | 1 -
hw/riscv/virt.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d9105c1886..b8ef99f348 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -73,7 +73,6 @@ enum {
VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
};
-#define VIRT_PLIC_HART_CONFIG "MS"
#define VIRT_PLIC_NUM_SOURCES 127
#define VIRT_PLIC_NUM_PRIORITIES 7
#define VIRT_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index ec0cb69b8c..2d3a8ec405 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -758,7 +758,7 @@ static char *plic_hart_config_string(int hart_count)
int i;
for (i = 0; i < hart_count; i++) {
- vals[i] = VIRT_PLIC_HART_CONFIG;
+ vals[i] = "MS";
}
vals[i] = NULL;
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
@ 2021-10-22 6:01 ` Alistair Francis
2021-10-22 13:53 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
` (3 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Alistair Francis @ 2021-10-22 6:01 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, alistair23, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
Add a generic function that can create the PLIC strings.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 2 ++
hw/riscv/boot.c | 25 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 0e89400b09..baff11dd8a 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -31,6 +31,8 @@
bool riscv_is_32bit(RISCVHartArrayState *harts);
+char *riscv_plic_hart_config_string(int hart_count);
+
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 993bf89064..5629f990aa 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -38,6 +38,31 @@ bool riscv_is_32bit(RISCVHartArrayState *harts)
return riscv_cpu_is_32bit(&harts->harts[0].env);
}
+/*
+ * Return the per-socket PLIC hart topology configuration string
+ * (caller must free with g_free())
+ */
+char *riscv_plic_hart_config_string(int hart_count)
+{
+ g_autofree const char **vals = g_new(const char *, hart_count + 1);
+ int i;
+
+ for (i = 0; i < hart_count; i++) {
+ CPUState *cs = qemu_get_cpu(i);
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVS)) {
+ vals[i] = "MS";
+ } else {
+ vals[i] = "M";
+ }
+ }
+ vals[i] = NULL;
+
+ /* g_strjoinv() obliges us to cast away const here */
+ return g_strjoinv(",", (char **)vals);
+}
+
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr) {
if (riscv_is_32bit(harts)) {
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-22 6:01 ` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function Alistair Francis
@ 2021-10-22 6:01 ` Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 4/5] hw/riscv: microchip_pfsoc: " Alistair Francis
` (2 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Alistair Francis @ 2021-10-22 6:01 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, alistair23, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/sifive_u.c | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fc5790b8ce..0010b404ee 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -813,7 +813,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
- size_t plic_hart_config_len;
int i, j;
NICInfo *nd = &nd_table[0];
@@ -854,18 +853,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
l2lim_mem);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
- ms->smp.cpus;
- plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < ms->smp.cpus; i++) {
- if (i != 0) {
- strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
- plic_hart_config_len);
- } else {
- strncat(plic_hart_config, "M", plic_hart_config_len);
- }
- plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
- }
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-22 6:01 ` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-22 6:01 ` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
@ 2021-10-22 6:01 ` Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 5/5] hw/riscv: virt: " Alistair Francis
2021-10-22 10:38 ` Philippe Mathieu-Daudé
4 siblings, 1 reply; 17+ messages in thread
From: Alistair Francis @ 2021-10-22 6:01 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, alistair23, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 1 -
hw/riscv/microchip_pfsoc.c | 14 +-------------
2 files changed, 1 insertion(+), 14 deletions(-)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index d30916f45d..a0673f5f59 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -138,7 +138,6 @@ enum {
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
-#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS"
#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185
#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7
#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index e475b6d511..843caabae5 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -187,7 +187,6 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
char *plic_hart_config;
- size_t plic_hart_config_len;
NICInfo *nd;
int i;
@@ -262,18 +261,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
l2lim_mem);
/* create PLIC hart topology configuration string */
- plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
- ms->smp.cpus;
- plic_hart_config = g_malloc0(plic_hart_config_len);
- for (i = 0; i < ms->smp.cpus; i++) {
- if (i != 0) {
- strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
- plic_hart_config_len);
- } else {
- strncat(plic_hart_config, "M", plic_hart_config_len);
- }
- plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
- }
+ plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
/* PLIC */
s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
` (2 preceding siblings ...)
2021-10-22 6:01 ` [PATCH v2 4/5] hw/riscv: microchip_pfsoc: " Alistair Francis
@ 2021-10-22 6:01 ` Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 10:38 ` Philippe Mathieu-Daudé
4 siblings, 1 reply; 17+ messages in thread
From: Alistair Francis @ 2021-10-22 6:01 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, alistair23, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 20 +-------------------
1 file changed, 1 insertion(+), 19 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2d3a8ec405..8715cfe659 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -748,24 +748,6 @@ static FWCfgState *create_fw_cfg(const MachineState *mc)
return fw_cfg;
}
-/*
- * Return the per-socket PLIC hart topology configuration string
- * (caller must free with g_free())
- */
-static char *plic_hart_config_string(int hart_count)
-{
- g_autofree const char **vals = g_new(const char *, hart_count + 1);
- int i;
-
- for (i = 0; i < hart_count; i++) {
- vals[i] = "MS";
- }
- vals[i] = NULL;
-
- /* g_strjoinv() obliges us to cast away const here */
- return g_strjoinv(",", (char **)vals);
-}
-
static void virt_machine_init(MachineState *machine)
{
const MemMapEntry *memmap = virt_memmap;
@@ -840,7 +822,7 @@ static void virt_machine_init(MachineState *machine)
}
/* Per-socket PLIC hart topology configuration string */
- plic_hart_config = plic_hart_config_string(hart_count);
+ plic_hart_config = riscv_plic_hart_config_string(hart_count);
/* Per-socket PLIC */
s->plic[i] = sifive_plic_create(
--
2.31.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
@ 2021-10-22 10:38 ` Philippe Mathieu-Daudé
2021-10-22 6:01 ` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
` (3 subsequent siblings)
4 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-22 10:38 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel
Cc: alistair23, Alistair Francis, Bin Meng, Palmer Dabbelt, bmeng.cn
On 10/22/21 08:01, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Using a macro for the PLIC configuration doesn't make the code any
> easier to read. Instead it makes it harder to figure out what is going
> on, so let's remove it.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> include/hw/riscv/virt.h | 1 -
> hw/riscv/virt.c | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
No cover letter, so using the first patch.
Series:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
@ 2021-10-22 10:38 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-22 10:38 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, alistair23, Bin Meng, Alistair Francis, bmeng.cn
On 10/22/21 08:01, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Using a macro for the PLIC configuration doesn't make the code any
> easier to read. Instead it makes it harder to figure out what is going
> on, so let's remove it.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> include/hw/riscv/virt.h | 1 -
> hw/riscv/virt.c | 2 +-
> 2 files changed, 1 insertion(+), 2 deletions(-)
No cover letter, so using the first patch.
Series:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
2021-10-22 10:38 ` Philippe Mathieu-Daudé
@ 2021-10-22 13:44 ` Bin Meng
-1 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 13:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, open list:RISC-V, Bin Meng,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Alistair Francis
On Fri, Oct 22, 2021 at 6:38 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/22/21 08:01, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Using a macro for the PLIC configuration doesn't make the code any
> > easier to read. Instead it makes it harder to figure out what is going
> > on, so let's remove it.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> > include/hw/riscv/virt.h | 1 -
> > hw/riscv/virt.c | 2 +-
> > 2 files changed, 1 insertion(+), 2 deletions(-)
>
> No cover letter, so using the first patch.
It's also better to include a changelog in each patch otherwise it's
hard to track what has changed compared to v1, especially the v1 was
posted 1.5 months ago.
>
> Series:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Regards,
Bin
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration
@ 2021-10-22 13:44 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 13:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, open list:RISC-V,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng, Alistair Francis
On Fri, Oct 22, 2021 at 6:38 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 10/22/21 08:01, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Using a macro for the PLIC configuration doesn't make the code any
> > easier to read. Instead it makes it harder to figure out what is going
> > on, so let's remove it.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> > include/hw/riscv/virt.h | 1 -
> > hw/riscv/virt.c | 2 +-
> > 2 files changed, 1 insertion(+), 2 deletions(-)
>
> No cover letter, so using the first patch.
It's also better to include a changelog in each patch otherwise it's
hard to track what has changed compared to v1, especially the v1 was
posted 1.5 months ago.
>
> Series:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Regards,
Bin
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function
2021-10-22 6:01 ` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function Alistair Francis
@ 2021-10-22 13:53 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 13:53 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Oct 22, 2021 at 2:01 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Add a generic function that can create the PLIC strings.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/boot.h | 2 ++
> hw/riscv/boot.c | 25 +++++++++++++++++++++++++
> 2 files changed, 27 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function
@ 2021-10-22 13:53 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 13:53 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Bin Meng, Alistair Francis
On Fri, Oct 22, 2021 at 2:01 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Add a generic function that can create the PLIC strings.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/boot.h | 2 ++
> hw/riscv/boot.c | 25 +++++++++++++++++++++++++
> 2 files changed, 27 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function
2021-10-22 6:01 ` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
@ 2021-10-22 14:58 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 14:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 14 +-------------
> 1 file changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index fc5790b8ce..0010b404ee 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -813,7 +813,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> - size_t plic_hart_config_len;
> int i, j;
> NICInfo *nd = &nd_table[0];
>
> @@ -854,18 +853,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> - plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
SIFIVE_U_PLIC_HART_CONFIG should be removed from sifive_u.h
> - ms->smp.cpus;
> - plic_hart_config = g_malloc0(plic_hart_config_len);
> - for (i = 0; i < ms->smp.cpus; i++) {
> - if (i != 0) {
> - strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> - plic_hart_config_len);
> - } else {
> - strncat(plic_hart_config, "M", plic_hart_config_len);
> - }
> - plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
> - }
> + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
> --
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function
@ 2021-10-22 14:58 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 14:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Bin Meng, Alistair Francis
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/sifive_u.c | 14 +-------------
> 1 file changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index fc5790b8ce..0010b404ee 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -813,7 +813,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> - size_t plic_hart_config_len;
> int i, j;
> NICInfo *nd = &nd_table[0];
>
> @@ -854,18 +853,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> - plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
SIFIVE_U_PLIC_HART_CONFIG should be removed from sifive_u.h
> - ms->smp.cpus;
> - plic_hart_config = g_malloc0(plic_hart_config_len);
> - for (i = 0; i < ms->smp.cpus; i++) {
> - if (i != 0) {
> - strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> - plic_hart_config_len);
> - } else {
> - strncat(plic_hart_config, "M", plic_hart_config_len);
> - }
> - plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
> - }
> + plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
> --
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
2021-10-22 6:01 ` [PATCH v2 4/5] hw/riscv: microchip_pfsoc: " Alistair Francis
@ 2021-10-22 14:58 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 14:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/microchip_pfsoc.h | 1 -
> hw/riscv/microchip_pfsoc.c | 14 +-------------
> 2 files changed, 1 insertion(+), 14 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 4/5] hw/riscv: microchip_pfsoc: Use the PLIC config helper function
@ 2021-10-22 14:58 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 14:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Bin Meng, Alistair Francis
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/microchip_pfsoc.h | 1 -
> hw/riscv/microchip_pfsoc.c | 14 +-------------
> 2 files changed, 1 insertion(+), 14 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function
2021-10-22 6:01 ` [PATCH v2 5/5] hw/riscv: virt: " Alistair Francis
@ 2021-10-22 14:58 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 14:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Alistair Francis
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 20 +-------------------
> 1 file changed, 1 insertion(+), 19 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 5/5] hw/riscv: virt: Use the PLIC config helper function
@ 2021-10-22 14:58 ` Bin Meng
0 siblings, 0 replies; 17+ messages in thread
From: Bin Meng @ 2021-10-22 14:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis, Bin Meng, Alistair Francis
On Fri, Oct 22, 2021 at 2:02 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 20 +-------------------
> 1 file changed, 1 insertion(+), 19 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2021-10-22 15:00 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-22 6:01 [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-22 6:01 ` [PATCH v2 2/5] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-22 13:53 ` Bin Meng
2021-10-22 13:53 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 3/5] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 14:58 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 4/5] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 14:58 ` Bin Meng
2021-10-22 6:01 ` [PATCH v2 5/5] hw/riscv: virt: " Alistair Francis
2021-10-22 14:58 ` Bin Meng
2021-10-22 14:58 ` Bin Meng
2021-10-22 10:38 ` [PATCH v2 1/5] hw/riscv: virt: Don't use a macro for the PLIC configuration Philippe Mathieu-Daudé
2021-10-22 10:38 ` Philippe Mathieu-Daudé
2021-10-22 13:44 ` Bin Meng
2021-10-22 13:44 ` Bin Meng
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