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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 00/11] SMP support for RISC-V
Date: Fri, 22 Mar 2019 07:06:15 +0800	[thread overview]
Message-ID: <CAEUhbmXpCiOUVzpmMCFirWFStWQ=p6aj9dNcv5hJG_MUdVYg4w@mail.gmail.com> (raw)
In-Reply-To: <20190321153615.GB9699@bc.grid.coop>

On Thu, Mar 21, 2019 at 11:39 PM Troy Benjegerdes <hozer@hozed.org> wrote:
>
> On Sun, Mar 17, 2019 at 07:28:31PM +0100, Lukas Auer wrote:
> > This patch series adds SMP support for RISC-V to U-Boot. It allows
> > U-Boot to run on multi-hart systems (hart is the RISC-V terminology for
> > hardware thread). Images passed to bootm will be started on all harts.
> > The bootm command is currently the only one that will boot images on all
> > harts, bootefi is not yet supported.
> >
> > The patches have been successfully tested on both QEMU (machine and
> > supervisor mode) and the HiFive Unleashed board (supervisor mode), using
> > BBL and OpenSBI.
>
> Can you describe the test configuration and boot flow a little more, or post an
> SDcard image that boots with the switches as shown in the readme at [1]
>
> I don't see any board-specific memory initialization code anywhere, so I assume
> you are still using the original SiFive FSBL, and not the u-boot version that
> includes the memory init code [2]
>

Correct. Mainline U-Boot on the FU540 board runs on S-mode currently.
You can refer to documentation doc/README.sifive-fu540

> [1] https://github.com/sifive/freedom-u-sdk
> [2] https://github.com/sifive/HiFive_U-Boot
>

Regards,
Bin

  reply	other threads:[~2019-03-21 23:06 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-17 18:28 [U-Boot] [PATCH v3 00/11] SMP support for RISC-V Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 01/11] riscv: add infrastructure for calling functions on other harts Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 02/11] riscv: import the supervisor binary interface header file Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 03/11] riscv: implement IPI platform functions using SBI Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 04/11] riscv: delay initialization of caches and debug UART Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 05/11] riscv: save hart ID in register tp instead of s0 Lukas Auer
2019-03-18  5:39   ` Bin Meng
     [not found]   ` <752D002CFF5D0F4FA35C0100F1D73F3FA409D6C8@ATCPCS16.andestech.com>
2019-03-18  5:52     ` Rick Chen
2019-03-18 12:58   ` Anup Patel
2019-03-17 18:28 ` [U-Boot] [PATCH v3 06/11] riscv: add support for multi-hart systems Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 07/11] riscv: boot images passed to bootm on all harts Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 08/11] riscv: do not rely on hart ID passed by previous boot stage Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 09/11] riscv: hang if relocation of secondary harts fails Lukas Auer
2019-03-18  6:27   ` Bin Meng
2019-03-18 13:00   ` Anup Patel
2019-03-17 18:28 ` [U-Boot] [PATCH v3 10/11] riscv: fu540: enable SMP Lukas Auer
2019-03-17 18:28 ` [U-Boot] [PATCH v3 11/11] riscv: qemu: " Lukas Auer
2019-03-20 12:37 ` [U-Boot] [PATCH v3 00/11] SMP support for RISC-V Palmer Dabbelt
2019-03-20 22:26   ` Auer, Lukas
2019-03-21 15:36 ` Troy Benjegerdes
2019-03-21 23:06   ` Bin Meng [this message]
2019-03-21 23:16     ` Atish Patra
2019-03-22  3:05       ` Padmarao Begari

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