[U-Boot] [PATCH v2 0/3] RISC-V S-mode support

[U-Boot] [PATCH v2 0/3] RISC-V S-mode support

[Anup Patel]

This patchset allows us runing u-boot in S-mode which is
useful on platforms where M-mode runtime firmware is an
independent firmware and u-boot is used as last stage OS
bootloader.

The patchset based upon git://git.denx.de/u-boot-riscv.git
and is tested on QEMU in both M-mode and S-mode.

For S-mode testing, we have used u-boot.bin as payload of
latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26)
applied with following changes:

diff --git a/machine/emulation.c b/machine/emulation.c
index 132e977..def75e1 100644
--- a/machine/emulation.c
+++ b/machine/emulation.c
@@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result
 
   switch (num)
   {
+    case CSR_MISA:
+      *result = read_csr(misa);
+      return 0;
+    case CSR_MHARTID:
+      *result = read_csr(mhartid);
+      return 0;
     case CSR_CYCLE:
       if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1))
         return -1;

Changes since v1:
 - Rebased upon latest git://git.denx.de/u-boot-riscv.git
 - Add details in cover letter for running u-boot in S-mode
   using BBL

Anup Patel (3):
  riscv: Add kconfig option to run u-boot in S-mode
  riscv: qemu: Use different SYS_TEXT_BASE for S-mode
  riscv: Add S-mode defconfigs for QEMU virt machine

 arch/riscv/Kconfig                   |  6 +++++
 arch/riscv/cpu/start.S               | 33 ++++++++++++++++++++++++++++
 board/emulation/qemu-riscv/Kconfig   |  3 ++-
 configs/qemu-riscv32-smode_defconfig | 10 +++++++++
 configs/qemu-riscv64-smode_defconfig | 11 ++++++++++
 5 files changed, 62 insertions(+), 1 deletion(-)
 create mode 100644 configs/qemu-riscv32-smode_defconfig
 create mode 100644 configs/qemu-riscv64-smode_defconfig

-- 
2.17.1

[U-Boot] [PATCH v2 1/3] riscv: Add kconfig option to run u-boot in S-mode

[Anup Patel]

This patch adds kconfig option RISCV_SMODE to run u-boot in
S-mode. When this opition is enabled we use s<xyz> CSRs instead
of m<xyz> CSRs.

It is important to note that there is no equivalent S-mode CSR
for misa and mhartid CSRs so we expect M-mode runtime firmware
(BBL or equivalent) to emulate misa and mhartid CSR read.

Eventually, we will have patches to avoid accessing misa and
mhartid from S-mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
---
 arch/riscv/Kconfig     |  6 ++++++
 arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3e0af55e71..88bc0d2a43 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -55,6 +55,12 @@ config RISCV_ISA_C
 config RISCV_ISA_A
 	def_bool y
 
+config RISCV_SMODE
+	bool "Run in S-Mode"
+	default n
+	help
+	  Enable this option to build an U-Boot for RISC-V S-Mode
+
 config 32BIT
 	bool
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 5af189b338..e4276e8e19 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -39,10 +39,18 @@ _start:
 	mv	s1, a1
 
 	la	t0, trap_entry
+#ifdef CONFIG_RISCV_SMODE
+	csrw	stvec, t0
+#else
 	csrw	mtvec, t0
+#endif
 
 	/* mask all interrupts */
+#ifdef CONFIG_RISCV_SMODE
+	csrw	sie, zero
+#else
 	csrw	mie, zero
+#endif
 
 	/* Enable cache */
 	jal	icache_enable
@@ -164,7 +172,11 @@ fix_rela_dyn:
 */
 	la	t0, trap_entry
 	add	t0, t0, t6
+#ifdef CONFIG_RISCV_SMODE
+	csrw	stvec, t0
+#else
 	csrw	mtvec, t0
+#endif
 
 clear_bss:
 	la	t0, __bss_start		/* t0 <- rel __bss_start in FLASH */
@@ -236,17 +248,34 @@ trap_entry:
 	SREG	x29, 29*REGBYTES(sp)
 	SREG	x30, 30*REGBYTES(sp)
 	SREG	x31, 31*REGBYTES(sp)
+#ifdef CONFIG_RISCV_SMODE
+	csrr	a0, scause
+	csrr	a1, sepc
+#else
 	csrr	a0, mcause
 	csrr	a1, mepc
+#endif
 	mv	a2, sp
 	jal	handle_trap
+#ifdef CONFIG_RISCV_SMODE
+	csrw	sepc, a0
+#else
 	csrw	mepc, a0
+#endif
 
+#ifdef CONFIG_RISCV_SMODE
+/*
+ * Remain in S-mode after sret
+ */
+	li	t0, SSTATUS_SPP
+	csrs	sstatus, t0
+#else
 /*
  * Remain in M-mode after mret
  */
 	li	t0, MSTATUS_MPP
 	csrs	mstatus, t0
+#endif
 	LREG	x1, 1*REGBYTES(sp)
 	LREG	x2, 2*REGBYTES(sp)
 	LREG	x3, 3*REGBYTES(sp)
@@ -279,4 +308,8 @@ trap_entry:
 	LREG	x30, 30*REGBYTES(sp)
 	LREG	x31, 31*REGBYTES(sp)
 	addi	sp, sp, 32*REGBYTES
+#ifdef CONFIG_RISCV_SMODE
+	sret
+#else
 	mret
+#endif
-- 
2.17.1

[U-Boot] [PATCH v2 2/3] riscv: qemu: Use different SYS_TEXT_BASE for S-mode

[Anup Patel]

When u-boot runs in S-mode, the M-mode runtime firmware
(BBL or equivalent) uses memory range in 0x80000000 to
0x80200000. Due to this, we cannot use 0x80000000 as
SYS_TEXT_BASE when running in S-mode. Instead for S-mode,
we use 0x80200000 as SYS_TEXT_BASE.

Even Linux RISC-V kernel ignores/reserves memory range
0x80000000 to 0x80200000 because it runs in S-mode.

Signed-off-by: Anup Patel <anup@brainfault.org>
---
 board/emulation/qemu-riscv/Kconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 33ca253432..56bb5337d4 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -13,7 +13,8 @@ config SYS_CONFIG_NAME
 	default "qemu-riscv"
 
 config SYS_TEXT_BASE
-	default 0x80000000
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80200000 if RISCV_SMODE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-- 
2.17.1

[U-Boot] [PATCH v2 3/3] riscv: Add S-mode defconfigs for QEMU virt machine

[Anup Patel]

This patch adds S-mode defconfigs for QEMU virt machine so
that we can run u-boot in S-mode on QEMU using M-mode runtime
firmware (BBL or equivalent).

Signed-off-by: Anup Patel <anup@brainfault.org>
---
 configs/qemu-riscv32-smode_defconfig | 10 ++++++++++
 configs/qemu-riscv64-smode_defconfig | 11 +++++++++++
 2 files changed, 21 insertions(+)
 create mode 100644 configs/qemu-riscv32-smode_defconfig
 create mode 100644 configs/qemu-riscv64-smode_defconfig

diff --git a/configs/qemu-riscv32-smode_defconfig b/configs/qemu-riscv32-smode_defconfig
new file mode 100644
index 0000000000..0a84ec1874
--- /dev/null
+++ b/configs/qemu-riscv32-smode_defconfig
@@ -0,0 +1,10 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/configs/qemu-riscv64-smode_defconfig b/configs/qemu-riscv64-smode_defconfig
new file mode 100644
index 0000000000..b012443370
--- /dev/null
+++ b/configs/qemu-riscv64-smode_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_QEMU_VIRT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+# CONFIG_CMD_MII is not set
+CONFIG_OF_PRIOR_STAGE=y
-- 
2.17.1

[U-Boot] [PATCH v2 1/3] riscv: Add kconfig option to run u-boot in S-mode

[Bin Meng]

Hi Anup,

On Tue, Nov 20, 2018 at 7:29 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patch adds kconfig option RISCV_SMODE to run u-boot in
> S-mode. When this opition is enabled we use s<xyz> CSRs instead
> of m<xyz> CSRs.
>
> It is important to note that there is no equivalent S-mode CSR
> for misa and mhartid CSRs so we expect M-mode runtime firmware
> (BBL or equivalent) to emulate misa and mhartid CSR read.
>
> Eventually, we will have patches to avoid accessing misa and
> mhartid from S-mode.
>

What patches?

> Signed-off-by: Anup Patel <anup@brainfault.org>
> ---
>  arch/riscv/Kconfig     |  6 ++++++
>  arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++++++++++++
>  2 files changed, 39 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 3e0af55e71..88bc0d2a43 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -55,6 +55,12 @@ config RISCV_ISA_C
>  config RISCV_ISA_A
>         def_bool y
>
> +config RISCV_SMODE
> +       bool "Run in S-Mode"
> +       default n

nits: 'default n' is not needed

> +       help
> +         Enable this option to build an U-Boot for RISC-V S-Mode
> +
>  config 32BIT
>         bool
>

[snip]

Other than that,

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin

[U-Boot] [PATCH v2 2/3] riscv: qemu: Use different SYS_TEXT_BASE for S-mode

[Bin Meng]

On Tue, Nov 20, 2018 at 7:29 PM Anup Patel <anup@brainfault.org> wrote:
>
> When u-boot runs in S-mode, the M-mode runtime firmware
> (BBL or equivalent) uses memory range in 0x80000000 to
> 0x80200000. Due to this, we cannot use 0x80000000 as
> SYS_TEXT_BASE when running in S-mode. Instead for S-mode,
> we use 0x80200000 as SYS_TEXT_BASE.
>
> Even Linux RISC-V kernel ignores/reserves memory range
> 0x80000000 to 0x80200000 because it runs in S-mode.
>
> Signed-off-by: Anup Patel <anup@brainfault.org>
> ---
>  board/emulation/qemu-riscv/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH v2 3/3] riscv: Add S-mode defconfigs for QEMU virt machine

[Bin Meng]

On Tue, Nov 20, 2018 at 7:29 PM Anup Patel <anup@brainfault.org> wrote:
>
> This patch adds S-mode defconfigs for QEMU virt machine so
> that we can run u-boot in S-mode on QEMU using M-mode runtime
> firmware (BBL or equivalent).
>
> Signed-off-by: Anup Patel <anup@brainfault.org>
> ---
>  configs/qemu-riscv32-smode_defconfig | 10 ++++++++++
>  configs/qemu-riscv64-smode_defconfig | 11 +++++++++++

nits: please use the name: qemu-riscv*_smode_defconfig (_ instead of -)

>  2 files changed, 21 insertions(+)
>  create mode 100644 configs/qemu-riscv32-smode_defconfig
>  create mode 100644 configs/qemu-riscv64-smode_defconfig
>

Please update board/emulation/qemu-riscv/MAINTAINERS to include these
2 defconfigs, otherwise buildman will report warnings.

Other than that,

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

[snip]

Regards,
Bin

[U-Boot] [PATCH v2 1/3] riscv: Add kconfig option to run u-boot in S-mode

[Anup Patel]

On Tue, Nov 20, 2018 at 7:08 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Anup,
>
> On Tue, Nov 20, 2018 at 7:29 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > This patch adds kconfig option RISCV_SMODE to run u-boot in
> > S-mode. When this opition is enabled we use s<xyz> CSRs instead
> > of m<xyz> CSRs.
> >
> > It is important to note that there is no equivalent S-mode CSR
> > for misa and mhartid CSRs so we expect M-mode runtime firmware
> > (BBL or equivalent) to emulate misa and mhartid CSR read.
> >
> > Eventually, we will have patches to avoid accessing misa and
> > mhartid from S-mode.
> >
>
> What patches?

What I meant was in-future we will have more patches to avoid
accessing misa and mhartid from S-mode.

I will re-phrase it.

>
> > Signed-off-by: Anup Patel <anup@brainfault.org>
> > ---
> >  arch/riscv/Kconfig     |  6 ++++++
> >  arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++++++++++++
> >  2 files changed, 39 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 3e0af55e71..88bc0d2a43 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -55,6 +55,12 @@ config RISCV_ISA_C
> >  config RISCV_ISA_A
> >         def_bool y
> >
> > +config RISCV_SMODE
> > +       bool "Run in S-Mode"
> > +       default n
>
> nits: 'default n' is not needed

Sure, I will drop it.

>
> > +       help
> > +         Enable this option to build an U-Boot for RISC-V S-Mode
> > +
> >  config 32BIT
> >         bool
> >
>
> [snip]
>
> Other than that,
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>

Thanks,
Anup

[U-Boot] [PATCH v2 3/3] riscv: Add S-mode defconfigs for QEMU virt machine

[Anup Patel]

On Tue, Nov 20, 2018 at 7:09 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Nov 20, 2018 at 7:29 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > This patch adds S-mode defconfigs for QEMU virt machine so
> > that we can run u-boot in S-mode on QEMU using M-mode runtime
> > firmware (BBL or equivalent).
> >
> > Signed-off-by: Anup Patel <anup@brainfault.org>
> > ---
> >  configs/qemu-riscv32-smode_defconfig | 10 ++++++++++
> >  configs/qemu-riscv64-smode_defconfig | 11 +++++++++++
>
> nits: please use the name: qemu-riscv*_smode_defconfig (_ instead of -)

OK, I will update filename of defconfigs

>
> >  2 files changed, 21 insertions(+)
> >  create mode 100644 configs/qemu-riscv32-smode_defconfig
> >  create mode 100644 configs/qemu-riscv64-smode_defconfig
> >
>
> Please update board/emulation/qemu-riscv/MAINTAINERS to include these
> 2 defconfigs, otherwise buildman will report warnings.

Sure, I will update MAINTAINERS file.

>
> Other than that,
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Tested-by: Bin Meng <bmeng.cn@gmail.com>
>

Thanks,
Anup