* [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf
@ 2023-02-13 9:45 LIU Zhiwei
2023-02-13 10:29 ` weiwei
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: LIU Zhiwei @ 2023-02-13 9:45 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair.Francis, bin.meng, frank.chang, liweiwei, dbarboza,
palmer, LIU Zhiwei
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these instructions on qemu-riscv32.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 00de879787..3073c54871 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
#define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
-static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
+static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
@@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
#define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
-static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
+static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
typedef uint##BITWIDTH##_t ETYPE; \
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf
2023-02-13 9:45 [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf LIU Zhiwei
@ 2023-02-13 10:29 ` weiwei
2023-02-13 15:56 ` Frank Chang
2023-02-16 16:18 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: weiwei @ 2023-02-13 10:29 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel, qemu-riscv
Cc: liweiwei, Alistair.Francis, bin.meng, frank.chang, dbarboza, palmer
On 2023/2/13 17:45, LIU Zhiwei wrote:
> vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
> scalar input should be uint64_t to hold the 64 bits float register.And the
> same for vslide1down_##BITWIDTH.
>
> This bug is caught when run these instructions on qemu-riscv32.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/vector_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 00de879787..3073c54871 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
> GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
>
> #define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
> -static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> +static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> typedef uint##BITWIDTH##_t ETYPE; \
> @@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
> GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
>
> #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
> -static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> +static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> typedef uint##BITWIDTH##_t ETYPE; \
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Regards,
Weiwei Li
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf
2023-02-13 9:45 [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf LIU Zhiwei
2023-02-13 10:29 ` weiwei
@ 2023-02-13 15:56 ` Frank Chang
2023-02-16 16:18 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Frank Chang @ 2023-02-13 15:56 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, Alistair.Francis, bin.meng, liweiwei,
dbarboza, palmer
[-- Attachment #1: Type: text/plain, Size: 1707 bytes --]
Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Mon, Feb 13, 2023 at 5:45 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
wrote:
> vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
> scalar input should be uint64_t to hold the 64 bits float register.And the
> same for vslide1down_##BITWIDTH.
>
> This bug is caught when run these instructions on qemu-riscv32.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/vector_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 00de879787..3073c54871 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
> GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
>
> #define GEN_VEXT_VSLIE1UP(BITWIDTH, H)
> \
> -static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,
> \
> +static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1,
> \
> void *vs2, CPURISCVState *env, uint32_t desc)
> \
> {
> \
> typedef uint##BITWIDTH##_t ETYPE;
> \
> @@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
> GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
>
> #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H)
> \
> -static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,
> \
> +static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1,
> \
> void *vs2, CPURISCVState *env, uint32_t desc)
> \
> {
> \
> typedef uint##BITWIDTH##_t ETYPE;
> \
> --
> 2.17.1
>
>
[-- Attachment #2: Type: text/html, Size: 2735 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf
2023-02-13 9:45 [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf LIU Zhiwei
2023-02-13 10:29 ` weiwei
2023-02-13 15:56 ` Frank Chang
@ 2023-02-16 16:18 ` Palmer Dabbelt
2 siblings, 0 replies; 4+ messages in thread
From: Palmer Dabbelt @ 2023-02-16 16:18 UTC (permalink / raw)
To: zhiwei_liu
Cc: qemu-devel, qemu-riscv, Alistair Francis, bin.meng, frank.chang,
liweiwei, dbarboza, zhiwei_liu
On Mon, 13 Feb 2023 01:45:50 PST (-0800), zhiwei_liu@linux.alibaba.com wrote:
> vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
> scalar input should be uint64_t to hold the 64 bits float register.And the
> same for vslide1down_##BITWIDTH.
>
> This bug is caught when run these instructions on qemu-riscv32.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
> target/riscv/vector_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 00de879787..3073c54871 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
> GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
>
> #define GEN_VEXT_VSLIE1UP(BITWIDTH, H) \
> -static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> +static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> typedef uint##BITWIDTH##_t ETYPE; \
> @@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
> GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
>
> #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H) \
> -static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1, \
> +static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1, \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> typedef uint##BITWIDTH##_t ETYPE; \
Thanks, applied to riscv-to-apply.next.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-02-16 16:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-13 9:45 [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf LIU Zhiwei
2023-02-13 10:29 ` weiwei
2023-02-13 15:56 ` Frank Chang
2023-02-16 16:18 ` Palmer Dabbelt
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.