* [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort.
@ 2015-06-15 15:15 fred.konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus fred.konrad
` (6 more replies)
0 siblings, 7 replies; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This is the second version of this patch-set of the implementation of the Xilinx
DisplayPort and DPDMA.
This second version took a lot of coding style fix and the blending is fixed as
well. See changes at the bottom.
First patch introduces an AUX bus needed by the DP to read the DPCD.
It's also possible to connect an I2C device on it to to I2C through AUX
commands. The drivers requires I2C broadcast write to be modeled as well which
seems to be missing currently upstream.
Details of the DPDMA part:
* DPDMA is implemented as a QEMU SYSBUS device.
* Interrupts are implemented except the axi error and fifo.
Details of the XILINX-DP:
* DP is also implemented as a QEMU SYSBUS. Multiple memory regions are used to
avoid having a single big region as there are holes in the DP memory map.
* An aux-bus has been implemented, it creates a memory map for aux slaves and
has an i2c bus (which is already implemented in QEMU).
* The normal programmable i2c clock and controller implementation is missing
from the QEMU tree so the easiest way for us was to implement a dummy-clk
driver in the kernel. It's a clock which does nothing but fakes a clock such
that the DPDMA driver works. The patch will be send separately.
* The graphic plane works on channel 3, video on channel 0 and audios on
channel 4 and 5.
Thanks,
Fred
V1 -> V2 changes:
* xlnx-zynqmp:
* Remove the dummy object_property_add_child(..).
* dpcd:
* Compile only when the ZYNQMP platform is compiled.
* Use qemu_log instead of printf.
* Compile test debug traces.
* Remove the unused current_reg.
* Remove the blank realize.
* Use dpcd_ prefixes instead of aux_ prefixes.
* Add a reset callback.
* Add the VMSD.
* Add size constraint in the MemoryRegionOps structure instead of asserting.
* Style fixes.
* aux:
* Compile only when the ZYNQMP platform is compiled.
* Remove the class init and the class for aux-slave.
* dpdma:
* Compile only when the ZYNQMP platform is compiled.
* Unify per channel macro in one, simplify the switch case.
* Use extractXX.
* Make DPDMA_GBL an or'ed register.
* dp:
* Compile only when the ZYNQMP platform is compiled.
* Don't look at the audio channel count.
* Use a third pixman plane when we do blending.
* other:
* Drop the useless "console: add qemu_alloc_display_format." patch as
suggested by Gerd.
* Rebase on current master (f3e3b083d4c266ea864ae3c83da49d4086857679).
KONRAD Frederic (6):
Introduce AUX bus.
i2c: implement broadcast write.
introduce dpcd module.
Introduce xilinx dpdma.
Introduce xilinx dp.
arm: xlnx-zynqmp: Add DisplayPort and DPDMA.
Peter Maydell (1):
hw/i2c-ddc.c: Implement DDC I2C slave
hw/arm/xlnx-zynqmp.c | 20 +
hw/display/Makefile.objs | 1 +
hw/display/dpcd.c | 151 +++++
hw/display/dpcd.h | 72 +++
hw/display/xilinx_dp.c | 1427 ++++++++++++++++++++++++++++++++++++++++++
hw/display/xilinx_dp.h | 129 ++++
hw/dma/Makefile.objs | 1 +
hw/dma/xilinx_dpdma.c | 779 +++++++++++++++++++++++
hw/dma/xilinx_dpdma.h | 71 +++
hw/i2c/Makefile.objs | 2 +-
hw/i2c/core.c | 46 +-
hw/i2c/i2c-ddc.c | 288 +++++++++
hw/i2c/i2c-ddc.h | 34 +
hw/misc/Makefile.objs | 1 +
hw/misc/aux.c | 411 ++++++++++++
include/hw/arm/xlnx-zynqmp.h | 4 +
include/hw/aux.h | 116 ++++
17 files changed, 3551 insertions(+), 2 deletions(-)
create mode 100644 hw/display/dpcd.c
create mode 100644 hw/display/dpcd.h
create mode 100644 hw/display/xilinx_dp.c
create mode 100644 hw/display/xilinx_dp.h
create mode 100644 hw/dma/xilinx_dpdma.c
create mode 100644 hw/dma/xilinx_dpdma.h
create mode 100644 hw/i2c/i2c-ddc.c
create mode 100644 hw/i2c/i2c-ddc.h
create mode 100644 hw/misc/aux.c
create mode 100644 include/hw/aux.h
--
1.9.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus.
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 6:21 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write fred.konrad
` (5 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This introduces a new bus: aux-bus.
It contains an address space for aux slaves devices and a bridge to an I2C bus
for I2C through AUX transactions.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/aux.c | 411 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/aux.h | 116 ++++++++++++++
3 files changed, 528 insertions(+)
create mode 100644 hw/misc/aux.c
create mode 100644 include/hw/aux.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 4aa76ff..11a721f 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -40,3 +40,4 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_EDU) += edu.o
+obj-$(CONFIG_XLNX_ZYNQMP) += aux.o
diff --git a/hw/misc/aux.c b/hw/misc/aux.c
new file mode 100644
index 0000000..b72608e
--- /dev/null
+++ b/hw/misc/aux.c
@@ -0,0 +1,411 @@
+/*
+ * aux.c
+ *
+ * Copyright 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/*
+ * This is an implementation of the AUX bus for VESA Display Port v1.1a.
+ */
+
+#include "hw/aux.h"
+#include "hw/i2c/i2c.h"
+#include "monitor/monitor.h"
+
+/* #define DEBUG_AUX */
+
+#ifdef DEBUG_AUX
+#define DPRINTF(fmt, ...)\
+do { printf("aux: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)do {} while (0)
+#endif
+
+#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
+#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
+
+typedef struct AUXTOI2CState AUXTOI2CState;
+
+struct AUXBus {
+ BusState qbus;
+ AUXSlave *current_dev;
+ AUXSlave *dev;
+ uint32_t last_i2c_address;
+ aux_command last_transaction;
+
+ AUXTOI2CState *bridge;
+
+ MemoryRegion *aux_io;
+ AddressSpace aux_addr_space;
+};
+
+static Property aux_props[] = {
+ DEFINE_PROP_UINT64("address", struct AUXSlave, address, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+#define TYPE_AUX_BUS "aux-bus"
+#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
+
+static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
+
+static void aux_bus_class_init(ObjectClass *klass, void *data)
+{
+ /*
+ * AUXSlave has an mmio so we need to change the way we print information
+ * in monitor.
+ */
+ BusClass *k = BUS_CLASS(klass);
+ k->print_dev = aux_slave_dev_print;
+}
+
+static const TypeInfo aux_bus_info = {
+ .name = TYPE_AUX_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(AUXBus),
+ .class_init = aux_bus_class_init
+};
+
+AUXBus *aux_init_bus(DeviceState *parent, const char *name)
+{
+ AUXBus *bus;
+
+ bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
+
+ /*
+ * Create the bridge.
+ */
+ bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
+
+ /*
+ * Memory related.
+ */
+ bus->aux_io = g_malloc(sizeof(*bus->aux_io));
+ memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
+ address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
+ return bus;
+}
+
+static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev)
+{
+ memory_region_add_subregion(bus->aux_io, dev->address, dev->mmio);
+}
+
+void aux_set_slave_address(AUXSlave *dev, uint32_t address)
+{
+ qdev_prop_set_uint64(DEVICE(dev), "address", address);
+}
+
+static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
+{
+ return (dev == DEVICE(bus->bridge));
+}
+
+/*
+ * Make a native request on the AUX bus.
+ */
+static aux_reply aux_native_request(AUXBus *bus, aux_command cmd,
+ uint32_t address, uint8_t len,
+ uint8_t *data)
+{
+ /*
+ * Transactions on aux address map are 1bytes len time.
+ */
+ aux_reply ret = AUX_NACK;
+ size_t i;
+
+ switch (cmd) {
+ case READ_AUX:
+ for (i = 0; i < len; i++) {
+ if (!address_space_rw(&bus->aux_addr_space, address++,
+ MEMTXATTRS_UNSPECIFIED, data++, 1, false)) {
+ ret = AUX_I2C_ACK;
+ } else {
+ ret = AUX_NACK;
+ break;
+ }
+ }
+ break;
+ case WRITE_AUX:
+ for (i = 0; i < len; i++) {
+ if (!address_space_rw(&bus->aux_addr_space, address++,
+ MEMTXATTRS_UNSPECIFIED, data++, 1, true)) {
+ ret = AUX_I2C_ACK;
+ } else {
+ ret = AUX_NACK;
+ break;
+ }
+ }
+ break;
+ default:
+ abort();
+ break;
+ }
+
+ return ret;
+}
+
+aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
+ uint8_t len, uint8_t *data)
+{
+ DPRINTF("request at address 0x%5.5X, command %u, len %u\n", address, cmd,
+ len);
+
+ int temp;
+ aux_reply ret = AUX_NACK;
+ I2CBus *i2c_bus = aux_get_i2c_bus(bus);
+
+ switch (cmd) {
+ /*
+ * Forward the request on the AUX bus..
+ */
+ case WRITE_AUX:
+ case READ_AUX:
+ ret = aux_native_request(bus, cmd, address, len, data);
+ break;
+ /*
+ * Classic I2C transactions..
+ */
+ case READ_I2C:
+ if (i2c_bus_busy(i2c_bus)) {
+ i2c_end_transfer(i2c_bus);
+ }
+
+ if (i2c_start_transfer(i2c_bus, address, 1)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+
+ while (len > 0) {
+ temp = i2c_recv(i2c_bus);
+
+ if (temp < 0) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+
+ *data++ = temp;
+ len--;
+ }
+ i2c_end_transfer(i2c_bus);
+ ret = AUX_I2C_ACK;
+ break;
+ case WRITE_I2C:
+ if (i2c_bus_busy(i2c_bus)) {
+ i2c_end_transfer(i2c_bus);
+ }
+
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+
+ while (len > 0) {
+ if (!i2c_send(i2c_bus, *data++)) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+ len--;
+ }
+ i2c_end_transfer(i2c_bus);
+ ret = AUX_I2C_ACK;
+ break;
+ /*
+ * I2C MOT transactions.
+ *
+ * Here we send a start when:
+ * - We didn't start transaction yet.
+ * - We had a READ and we do a WRITE.
+ * - We change the address.
+ */
+ case WRITE_I2C_MOT:
+ if (!i2c_bus_busy(i2c_bus)) {
+ /*
+ * No transactions started..
+ */
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ } else if ((address != bus->last_i2c_address) ||
+ (bus->last_transaction == READ_I2C_MOT)) {
+ /*
+ * Transaction started but we need to restart..
+ */
+ i2c_end_transfer(i2c_bus);
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ }
+
+ while (len > 0) {
+ if (!i2c_send(i2c_bus, *data++)) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+ len--;
+ }
+ bus->last_transaction = WRITE_I2C_MOT;
+ bus->last_i2c_address = address;
+ ret = AUX_I2C_ACK;
+ break;
+ case READ_I2C_MOT:
+ if (!i2c_bus_busy(i2c_bus)) {
+ /*
+ * No transactions started..
+ */
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ } else if (address != bus->last_i2c_address) {
+ /*
+ * Transaction started but we need to restart..
+ */
+ i2c_end_transfer(i2c_bus);
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ }
+
+ while (len > 0) {
+ temp = i2c_recv(i2c_bus);
+
+ if (temp < 0) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+
+ *data++ = temp;
+ len--;
+ }
+ bus->last_transaction = READ_I2C_MOT;
+ bus->last_i2c_address = address;
+ ret = AUX_I2C_ACK;
+ break;
+ default:
+ DPRINTF("Not implemented!\n");
+ ret = AUX_NACK;
+ break;
+ }
+
+ DPRINTF("reply: %u\n", ret);
+ return ret;
+}
+
+/*
+ * AUX to I2C bridge.
+ */
+struct AUXTOI2CState {
+ DeviceState parent_obj;
+ I2CBus *i2c_bus;
+};
+
+I2CBus *aux_get_i2c_bus(AUXBus *bus)
+{
+ return bus->bridge->i2c_bus;
+}
+
+static void aux_bridge_init(Object *obj)
+{
+ AUXTOI2CState *s = AUXTOI2C(obj);
+ /*
+ * Create the I2C Bus.
+ */
+ s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
+}
+
+static const TypeInfo aux_to_i2c_type_info = {
+ .name = TYPE_AUXTOI2C,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AUXTOI2CState),
+ .instance_init = aux_bridge_init
+};
+
+/*
+ * AUX Slave.
+ */
+static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
+{
+ AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
+ hwaddr size;
+ AUXSlave *s;
+
+ /*
+ * Don't print anything if the device is I2C "bridge".
+ */
+ if (aux_bus_is_bridge(bus, dev)) {
+ return;
+ }
+
+ s = AUX_SLAVE(dev);
+
+ size = memory_region_size(s->mmio);
+ monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ indent, "", s->address, size);
+}
+
+DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr)
+{
+ DeviceState *dev;
+
+ dev = qdev_create(&bus->qbus, name);
+ qdev_prop_set_uint64(dev, "address", addr);
+ qdev_init_nofail(dev);
+ aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev));
+ return dev;
+}
+
+void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
+{
+ aux_slave->mmio = mmio;
+}
+
+static void aux_slave_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *k = DEVICE_CLASS(klass);
+ set_bit(DEVICE_CATEGORY_MISC, k->categories);
+ k->bus_type = TYPE_AUX_BUS;
+ k->props = aux_props;
+}
+
+static const TypeInfo aux_slave_type_info = {
+ .name = TYPE_AUX_SLAVE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AUXSlave),
+ .abstract = true,
+ .class_init = aux_slave_class_init,
+};
+
+static void aux_slave_register_types(void)
+{
+ type_register_static(&aux_bus_info);
+ type_register_static(&aux_slave_type_info);
+ type_register_static(&aux_to_i2c_type_info);
+}
+
+type_init(aux_slave_register_types)
diff --git a/include/hw/aux.h b/include/hw/aux.h
new file mode 100644
index 0000000..7b29ee1
--- /dev/null
+++ b/include/hw/aux.h
@@ -0,0 +1,116 @@
+/*
+ * aux.h
+ *
+ * Copyright (C)2014 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef QEMU_AUX_H
+#define QEMU_AUX_H
+
+#include "hw/qdev.h"
+
+enum aux_command {
+ WRITE_I2C = 0,
+ READ_I2C = 1,
+ WRITE_I2C_STATUS = 2,
+ WRITE_I2C_MOT = 4,
+ READ_I2C_MOT = 5,
+ WRITE_AUX = 8,
+ READ_AUX = 9
+};
+
+enum aux_reply {
+ AUX_I2C_ACK = 0,
+ AUX_NACK = 1,
+ AUX_DEFER = 2,
+ AUX_I2C_NACK = 4,
+ AUX_I2C_DEFER = 8
+};
+
+typedef struct AUXBus AUXBus;
+typedef struct AUXSlave AUXSlave;
+typedef enum aux_command aux_command;
+typedef enum aux_reply aux_reply;
+
+#define TYPE_AUX_SLAVE "aux-slave"
+#define AUX_SLAVE(obj) \
+ OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
+
+struct AUXSlave {
+ /* < private > */
+ DeviceState parent_obj;
+
+ /* address of the device on the aux bus. */
+ hwaddr address;
+ /* memory region associated. */
+ MemoryRegion *mmio;
+};
+
+/*
+ * \func aux_init_bus
+ * \brief Init an aux bus.
+ * \param parent The device where this bus is located.
+ * \param name The name of the bus.
+ * \return The new aux bus.
+ */
+AUXBus *aux_init_bus(DeviceState *parent, const char *name);
+
+/*
+ * \func aux_slave_set_address
+ * \brief Set the address of the slave on the aux bus.
+ * \param dev The aux slave device.
+ * \param address The address to give to the slave.
+ */
+void aux_set_slave_address(AUXSlave *dev, uint32_t address);
+
+/*
+ * \func aux_request
+ * \brief Make a request on the bus.
+ * \param bus Ths bus where the request happen.
+ * \param cmd The command requested.
+ * \param address The 20bits address of the slave.
+ * \param len The length of the read or write.
+ * \param data The data array which will be filled or read during transfer.
+ * \return Return the reply of the request.
+ */
+aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
+ uint8_t len, uint8_t *data);
+
+/*
+ * \func aux_get_i2c_bus
+ * \brief Get the i2c bus for I2C over AUX command.
+ * \param bus The aux bus.
+ * \return Return the i2c bus associated.
+ */
+I2CBus *aux_get_i2c_bus(AUXBus *bus);
+
+/*
+ * \func aux_init_mmio
+ * \brief Init an mmio for an aux slave, must be called after
+ * memory_region_init_io.
+ * \param aux_slave The aux slave.
+ * \param mmio The mmio to be registered.
+ */
+void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
+
+DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
+
+#endif /* !QEMU_AUX_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write.
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 6:35 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 3/7] introduce dpcd module fred.konrad
` (4 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This does a write to every slaves when the I2C bus get a write to address 0.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/i2c/core.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index 5a64026..db1cbdd 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -15,6 +15,7 @@ struct I2CBus
I2CSlave *current_dev;
I2CSlave *dev;
uint8_t saved_address;
+ bool broadcast;
};
static Property i2c_props[] = {
@@ -67,6 +68,8 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
+
+ bus->broadcast = false;
return bus;
}
@@ -89,6 +92,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
I2CSlave *slave = NULL;
I2CSlaveClass *sc;
+ if (address == 0x00) {
+ /*
+ * This is a broadcast.
+ */
+ QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+ I2CSlave *dev = I2C_SLAVE(kid->child);
+ sc = I2C_SLAVE_GET_CLASS(dev);
+ bus->broadcast = true;
+ if (sc->event) {
+ sc->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
+ }
+ }
+ return 0;
+ }
+
QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
DeviceState *qdev = kid->child;
I2CSlave *candidate = I2C_SLAVE(qdev);
@@ -114,9 +132,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
void i2c_end_transfer(I2CBus *bus)
{
+ BusChild *kid;
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
+ if (bus->broadcast) {
+ QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+ I2CSlave *dev = I2C_SLAVE(kid->child);
+ sc = I2C_SLAVE_GET_CLASS(dev);
+ if (sc->event) {
+ sc->event(dev, I2C_FINISH);
+ }
+ }
+ bus->broadcast = false;
+ }
+
if (!dev) {
return;
}
@@ -131,8 +161,22 @@ void i2c_end_transfer(I2CBus *bus)
int i2c_send(I2CBus *bus, uint8_t data)
{
+ BusChild *kid;
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
+ int ret = 0;
+
+ if (bus->broadcast) {
+ QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+ I2CSlave *dev = I2C_SLAVE(kid->child);
+ sc = I2C_SLAVE_GET_CLASS(dev);
+ bus->broadcast = true;
+ if (sc->send) {
+ ret |= sc->send(dev, data);
+ }
+ }
+ return ret;
+ }
if (!dev) {
return -1;
@@ -151,7 +195,7 @@ int i2c_recv(I2CBus *bus)
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
- if (!dev) {
+ if ((!dev) || (bus->broadcast)) {
return -1;
}
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 3/7] introduce dpcd module.
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus fred.konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 6:44 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 4/7] hw/i2c-ddc.c: Implement DDC I2C slave fred.konrad
` (3 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This introduces a DPCD modules. It wires on a aux-bus and can be accessed by
driver to get lane-speed, etc.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/display/Makefile.objs | 1 +
hw/display/dpcd.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
hw/display/dpcd.h | 72 ++++++++++++++++++++++
3 files changed, 224 insertions(+)
create mode 100644 hw/display/dpcd.c
create mode 100644 hw/display/dpcd.h
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 61c80f3..f75094f 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -36,3 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
obj-$(CONFIG_VIRTIO) += virtio-gpu.o
+obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o
diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
new file mode 100644
index 0000000..b4eeea7
--- /dev/null
+++ b/hw/display/dpcd.c
@@ -0,0 +1,151 @@
+/*
+ * dpcd.c
+ *
+ * Copyright (C)2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/*
+ * This is a simple AUX slave which emulates a connected screen.
+ */
+
+#include "hw/aux.h"
+#include "dpcd.h"
+
+#ifndef DEBUG_DPCD
+#define DEBUG_DPCD 0
+#endif
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_DPCD) { \
+ qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
+ } \
+} while (0);
+
+#define DPCD_READABLE_AREA 0x600
+
+struct DPCDState {
+ AUXSlave parent_obj;
+
+ /*
+ * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
+ */
+ uint8_t dpcd_info[DPCD_READABLE_AREA];
+
+ MemoryRegion iomem;
+};
+
+static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
+{
+ uint64_t ret;
+ DPCDState *e = DPCD(opaque);
+
+ if (offset < DPCD_READABLE_AREA) {
+ ret = e->dpcd_info[offset];
+ } else {
+ ret = 0;
+ }
+
+ DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
+ return ret;
+}
+
+static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ DPCDState *e = DPCD(opaque);
+
+ DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
+
+ if (offset < DPCD_READABLE_AREA) {
+ e->dpcd_info[offset] = value;
+ }
+}
+
+static const MemoryRegionOps aux_ops = {
+ .read = dpcd_read,
+ .write = dpcd_write,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
+static void dpcd_reset(DeviceState *dev)
+{
+ DPCDState *s = DPCD(dev);
+ memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
+
+ s->dpcd_info[0x00] = DPCD_REV_1_0;
+ s->dpcd_info[0x01] = DPCD_5_4GBPS;
+ s->dpcd_info[0x02] = 0x1;
+ s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
+ s->dpcd_info[0x09] = 0xFF;
+
+ /* CR DONE, CE DONE, SYMBOL LOCKED.. */
+ s->dpcd_info[0x202] = 0x07;
+ /* INTERLANE_ALIGN_DONE.. */
+ s->dpcd_info[0x204] = 0x01;
+ s->dpcd_info[0x205] = 0x01;
+}
+
+static void dpcd_init(Object *obj)
+{
+ DPCDState *s = DPCD(obj);
+
+ memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
+ aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_dpcd = {
+ .name = TYPE_DPCD,
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void dpcd_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ dc->reset = dpcd_reset;
+ dc->vmsd = &vmstate_dpcd;
+}
+
+static const TypeInfo dpcd_info = {
+ .name = TYPE_DPCD,
+ .parent = TYPE_AUX_SLAVE,
+ .instance_size = sizeof(DPCDState),
+ .class_init = dpcd_class_init,
+ .instance_init = dpcd_init,
+};
+
+static void dpcd_register_types(void)
+{
+ type_register_static(&dpcd_info);
+}
+
+type_init(dpcd_register_types)
diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
new file mode 100644
index 0000000..57c393b
--- /dev/null
+++ b/hw/display/dpcd.h
@@ -0,0 +1,72 @@
+/*
+ * dpcd.h
+ *
+ * Copyright (C)2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef DPCD_H
+#define DPCD_H
+
+typedef struct DPCDState DPCDState;
+
+#define TYPE_DPCD "dpcd"
+#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
+
+/* DCPD Revision. */
+#define DPCD_REV_1_0 0x10
+#define DPCD_REV_1_1 0x11
+
+/* DCPD Max Link Rate. */
+#define DPCD_1_62GBPS 0x06
+#define DPCD_2_7GBPS 0x0A
+#define DPCD_5_4GBPS 0x14
+
+/* DCPD Max down spread. */
+#define DPCD_UP_TO_0_5 0x01
+#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
+
+/* DCPD Downstream port type. */
+#define DPCD_DISPLAY_PORT 0x00
+#define DPCD_ANALOG 0x02
+#define DPCD_DVI_HDMI 0x04
+#define DPCD_OTHER 0x06
+
+/* DPCD Format conversion. */
+#define DPCD_FORMAT_CONVERSION 0x08
+
+/* Main link channel coding. */
+#define DPCD_ANSI_8B_10B 0x01
+
+/* Down stream port count. */
+#define DPCD_OUI_SUPPORTED 0x80
+
+/* Receiver port capability. */
+#define DPCD_EDID_PRESENT 0x02
+#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
+
+/* Down stream port capability. */
+#define DPCD_CAP_DISPLAY_PORT 0x000
+#define DPCD_CAP_ANALOG_VGA 0x001
+#define DPCD_CAP_DVI 0x002
+#define DPCD_CAP_HDMI 0x003
+#define DPCD_CAP_OTHER 0x100
+
+#endif /* !DPCD_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 4/7] hw/i2c-ddc.c: Implement DDC I2C slave
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
` (2 preceding siblings ...)
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 3/7] introduce dpcd module fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 7:03 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 5/7] Introduce xilinx dpdma fred.konrad
` (2 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: Peter Maydell <peter.maydell@linaro.org>
Implement an I2C slave which implements DDC and returns the
EDID data for an attached monitor.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
- Rebased on the current master.
- Modified for QOM.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/i2c/Makefile.objs | 2 +-
hw/i2c/i2c-ddc.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/i2c/i2c-ddc.h | 34 ++++++
3 files changed, 323 insertions(+), 1 deletion(-)
create mode 100644 hw/i2c/i2c-ddc.c
create mode 100644 hw/i2c/i2c-ddc.h
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 0f13060..307a73b 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-y += core.o smbus.o smbus_eeprom.o
+common-obj-y += core.o smbus.o smbus_eeprom.o i2c-ddc.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
new file mode 100644
index 0000000..71b303c
--- /dev/null
+++ b/hw/i2c/i2c-ddc.c
@@ -0,0 +1,288 @@
+/* A simple I2C slave for returning monitor EDID data via DDC.
+ *
+ * Copyright (c) 2011 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "hw/i2c/i2c.h"
+#include "i2c-ddc.h"
+
+/* #define DEBUG_I2CDDC */
+#ifdef DEBUG_I2CDDC
+#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+/* Structure defining a monitor's characteristics in a
+ * readable format: this should be passed to build_edid_blob()
+ * to convert it into the 128 byte binary EDID blob.
+ * Not all bits of the EDID are customisable here.
+ */
+typedef struct {
+ char manuf_id[3]; /* three upper case letters */
+ uint16_t product_id;
+ uint32_t serial_no;
+ uint8_t manuf_week;
+ int manuf_year;
+ uint8_t h_cm;
+ uint8_t v_cm;
+ uint8_t gamma;
+ char monitor_name[14];
+ char serial_no_string[14];
+ /* Range limits */
+ uint8_t vmin; /* Hz */
+ uint8_t vmax; /* Hz */
+ uint8_t hmin; /* kHz */
+ uint8_t hmax; /* kHz */
+ uint8_t pixclock; /* MHz / 10 */
+ uint8_t timing_data[18];
+} edid_data;
+
+/* EDID data for a simple LCD monitor */
+static const edid_data lcd_edid = {
+ /* The manuf_id ought really to be an assigned EISA ID */
+ .manuf_id = "QMU",
+ .product_id = 0,
+ .serial_no = 1,
+ .manuf_week = 1,
+ .manuf_year = 2011,
+ .h_cm = 40,
+ .v_cm = 30,
+ .gamma = 0x78,
+ .monitor_name = "QEMU monitor",
+ .serial_no_string = "1",
+ .vmin = 40,
+ .vmax = 120,
+ .hmin = 30,
+ .hmax = 100,
+ .pixclock = 18,
+ .timing_data = {
+ /* Borrowed from a 21" LCD */
+ 0x48, 0x3f, 0x40, 0x30, 0x62, 0xb0, 0x32, 0x40, 0x40,
+ 0xc0, 0x13, 0x00, 0x98, 0x32, 0x11, 0x00, 0x00, 0x1e
+ }
+};
+
+static uint8_t manuf_char_to_int(char c)
+{
+ return (c - 'A') & 0x1f;
+}
+
+static void write_ascii_descriptor_block(uint8_t *descblob, uint8_t blocktype,
+ const char *string)
+{
+ /* Write an EDID Descriptor Block of the "ascii string" type */
+ int i;
+ descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
+ descblob[3] = blocktype;
+ /* The rest is 13 bytes of ASCII; if less then the rest must
+ * be filled with newline then spaces
+ */
+ for (i = 5; i < 19; i++) {
+ descblob[i] = string[i - 5];
+ if (!descblob[i]) {
+ break;
+ }
+ }
+ if (i < 19) {
+ descblob[i++] = '\n';
+ }
+ for ( ; i < 19; i++) {
+ descblob[i] = ' ';
+ }
+}
+
+static void write_range_limits_descriptor(const edid_data *edid,
+ uint8_t *descblob)
+{
+ int i;
+ descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
+ descblob[3] = 0xfd;
+ descblob[5] = edid->vmin;
+ descblob[6] = edid->vmax;
+ descblob[7] = edid->hmin;
+ descblob[8] = edid->hmax;
+ descblob[9] = edid->pixclock;
+ descblob[10] = 0;
+ descblob[11] = 0xa;
+ for (i = 12; i < 19; i++) {
+ descblob[i] = 0x20;
+ }
+}
+
+static void build_edid_blob(const edid_data *edid, uint8_t *blob)
+{
+ /* Write an EDID 1.3 format blob (128 bytes) based
+ * on the edid_data structure.
+ */
+ int i;
+ uint8_t cksum;
+
+ /* 00-07 : header */
+ blob[0] = blob[7] = 0;
+ for (i = 1 ; i < 7; i++) {
+ blob[i] = 0xff;
+ }
+ /* 08-09 : manufacturer ID */
+ blob[8] = (manuf_char_to_int(edid->manuf_id[0]) << 2)
+ | (manuf_char_to_int(edid->manuf_id[1]) >> 3);
+ blob[9] = (manuf_char_to_int(edid->manuf_id[1]) << 5)
+ | manuf_char_to_int(edid->manuf_id[2]);
+ /* 10-11 : product ID code */
+ blob[10] = edid->product_id;
+ blob[11] = edid->product_id >> 8;
+ blob[12] = edid->serial_no;
+ blob[13] = edid->serial_no >> 8;
+ blob[14] = edid->serial_no >> 16;
+ blob[15] = edid->serial_no >> 24;
+ /* 16 : week of manufacture */
+ blob[16] = edid->manuf_week;
+ /* 17 : year of manufacture - 1990 */
+ blob[17] = edid->manuf_year - 1990;
+ /* 18, 19 : EDID version and revision */
+ blob[18] = 1;
+ blob[19] = 3;
+ /* 20 - 24 : basic display parameters */
+ /* We are always a digital display */
+ blob[20] = 0x80;
+ /* 21, 22 : max h/v size in cm */
+ blob[21] = edid->h_cm;
+ blob[22] = edid->v_cm;
+ /* 23 : gamma (divide by 100 then add 1 for actual value) */
+ blob[23] = edid->gamma;
+ /* 24 feature support: no power management, RGB, preferred timing mode,
+ * standard colour space
+ */
+ blob[24] = 0x0e;
+ /* 25 - 34 : chromaticity coordinates. These are the
+ * standard sRGB chromaticity values
+ */
+ blob[25] = 0xee;
+ blob[26] = 0x91;
+ blob[27] = 0xa3;
+ blob[28] = 0x54;
+ blob[29] = 0x4c;
+ blob[30] = 0x99;
+ blob[31] = 0x26;
+ blob[32] = 0x0f;
+ blob[33] = 0x50;
+ blob[34] = 0x54;
+ /* 35, 36 : Established timings: claim to support everything */
+ blob[35] = blob[36] = 0xff;
+ /* 37 : manufacturer's reserved timing: none */
+ blob[37] = 0;
+ /* 38 - 53 : standard timing identification
+ * don't claim anything beyond what the 'established timings'
+ * already provide. Unused slots must be (0x1, 0x1)
+ */
+ for (i = 38; i < 54; i++) {
+ blob[i] = 0x1;
+ }
+ /* 54 - 71 : descriptor block 1 : must be preferred timing data */
+ memcpy(blob + 54, edid->timing_data, 18);
+ /* 72 - 89, 90 - 107, 108 - 125 : descriptor block 2, 3, 4
+ * Order not important, but we must have a monitor name and a
+ * range limits descriptor.
+ */
+ write_range_limits_descriptor(edid, blob + 72);
+ write_ascii_descriptor_block(blob + 90, 0xfc, edid->monitor_name);
+ write_ascii_descriptor_block(blob + 108, 0xff, edid->serial_no_string);
+
+ /* 126 : extension flag */
+ blob[126] = 0;
+
+ cksum = 0;
+ DPRINTF("EDID blob:");
+ for (i = 0; i < 127; i++) {
+ cksum += blob[i];
+ DPRINTF("%c0x%02x,", i % 8 ? ' ' : '\n', blob[i]);
+ }
+ /* 127 : checksum */
+ blob[127] = -cksum;
+ DPRINTF(" 0x%02x\n", blob[127]);
+}
+
+static void i2c_ddc_reset(DeviceState *ds)
+{
+ I2CDDCState *s = I2CDDC(ds);
+ s->firstbyte = 0;
+ s->reg = 0;
+}
+
+static void i2c_ddc_event(I2CSlave *i2c, enum i2c_event event)
+{
+ I2CDDCState *s = I2CDDC(i2c);
+ if (event == I2C_START_SEND) {
+ s->firstbyte = 1;
+ }
+}
+
+static int i2c_ddc_rx(I2CSlave *i2c)
+{
+ I2CDDCState *s = I2CDDC(i2c);
+
+ int value;
+ value = s->edid_blob[s->reg];
+
+ s->reg++;
+ return value;
+}
+
+static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
+{
+ I2CDDCState *s = I2CDDC(i2c);
+ if (s->firstbyte) {
+ s->reg = data;
+ s->firstbyte = 0;
+ DPRINTF("[EDID] Written new pointer: %u\n", data);
+ return 1;
+ }
+
+ /* Ignore all writes */
+ s->reg++;
+ return 1;
+}
+
+static void i2c_ddc_init(Object *obj)
+{
+ I2CDDCState *s = I2CDDC(obj);
+ build_edid_blob(&lcd_edid, s->edid_blob);
+}
+
+static void i2c_ddc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ I2CSlaveClass *klass = I2C_SLAVE_CLASS(oc);
+
+ dc->reset = i2c_ddc_reset;
+ klass->event = i2c_ddc_event;
+ klass->recv = i2c_ddc_rx;
+ klass->send = i2c_ddc_tx;
+}
+
+static TypeInfo i2c_ddc_info = {
+ .name = TYPE_I2CDDC,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(I2CDDCState),
+ .instance_init = i2c_ddc_init,
+ .class_init = i2c_ddc_class_init
+};
+
+static void ddc_register_devices(void)
+{
+ type_register_static(&i2c_ddc_info);
+}
+
+type_init(ddc_register_devices);
diff --git a/hw/i2c/i2c-ddc.h b/hw/i2c/i2c-ddc.h
new file mode 100644
index 0000000..fdf802e
--- /dev/null
+++ b/hw/i2c/i2c-ddc.h
@@ -0,0 +1,34 @@
+/* A simple I2C slave for returning monitor EDID data via DDC.
+ *
+ * Copyright (c) 2011 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef I2C_DDC
+#define I2C_DDC
+
+/* A simple I2C slave which just returns the contents of its EDID blob. */
+
+typedef struct I2CDDCState {
+ I2CSlave i2c;
+ int firstbyte;
+ uint8_t reg;
+ uint8_t edid_blob[128];
+} I2CDDCState;
+
+#define TYPE_I2CDDC "i2c-ddc"
+#define I2CDDC(obj) OBJECT_CHECK(I2CDDCState, (obj), TYPE_I2CDDC)
+
+#endif /* !I2C_DDC */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 5/7] Introduce xilinx dpdma.
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
` (3 preceding siblings ...)
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 4/7] hw/i2c-ddc.c: Implement DDC I2C slave fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 7:41 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 6/7] Introduce xilinx dp fred.konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 7/7] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This is the implementation of the DPDMA.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/dma/Makefile.objs | 1 +
hw/dma/xilinx_dpdma.c | 779 ++++++++++++++++++++++++++++++++++++++++++++++++++
hw/dma/xilinx_dpdma.h | 71 +++++
3 files changed, 851 insertions(+)
create mode 100644 hw/dma/xilinx_dpdma.c
create mode 100644 hw/dma/xilinx_dpdma.h
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 0e65ed0..a9934c5 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
+obj-$(CONFIG_XLNX_ZYNQMP) += xilinx_dpdma.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
diff --git a/hw/dma/xilinx_dpdma.c b/hw/dma/xilinx_dpdma.c
new file mode 100644
index 0000000..50c5919
--- /dev/null
+++ b/hw/dma/xilinx_dpdma.c
@@ -0,0 +1,779 @@
+/*
+ * xilinx_dpdma.c
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "xilinx_dpdma.h"
+
+#ifndef DEBUG_DPDMA
+#define DEBUG_DPDMA 0
+#endif
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_DPDMA) { \
+ qemu_log("xilinx_dpdma: " fmt , ## __VA_ARGS__); \
+ } \
+} while (0);
+
+/*
+ * Registers offset for DPDMA.
+ */
+#define DPDMA_ERR_CTRL (0x0000)
+#define DPDMA_ISR (0x0004 >> 2)
+#define DPDMA_IMR (0x0008 >> 2)
+#define DPDMA_IEN (0x000C >> 2)
+#define DPDMA_IDS (0x0010 >> 2)
+#define DPDMA_EISR (0x0014 >> 2)
+#define DPDMA_EIMR (0x0018 >> 2)
+#define DPDMA_EIEN (0x001C >> 2)
+#define DPDMA_EIDS (0x0020 >> 2)
+#define DPDMA_CNTL (0x0100 >> 2)
+#define DPDMA_GBL (0x0104 >> 2)
+#define DPDMA_GBL_TRG_CH(n) (1 << n)
+#define DPDMA_GBL_RTRG_CH(n) (1 << 6 << n)
+#define DPDMA_ALC0_CNTL (0x0108 >> 2)
+#define DPDMA_ALC0_STATUS (0x010C >> 2)
+#define DPDMA_ALC0_MAX (0x0110 >> 2)
+#define DPDMA_ALC0_MIN (0x0114 >> 2)
+#define DPDMA_ALC0_ACC (0x0118 >> 2)
+#define DPDMA_ALC0_ACC_TRAN (0x011C >> 2)
+#define DPDMA_ALC1_CNTL (0x0120 >> 2)
+#define DPDMA_ALC1_STATUS (0x0124 >> 2)
+#define DPDMA_ALC1_MAX (0x0128 >> 2)
+#define DPDMA_ALC1_MIN (0x012C >> 2)
+#define DPDMA_ALC1_ACC (0x0130 >> 2)
+#define DPDMA_ALC1_ACC_TRAN (0x0134 >> 2)
+#define DPDMA_DSCR_STRT_ADDRE_CH(n) ((0x0200 + n * 0x100) >> 2)
+#define DPDMA_DSCR_STRT_ADDR_CH(n) ((0x0204 + n * 0x100) >> 2)
+#define DPDMA_DSCR_NEXT_ADDRE_CH(n) ((0x0208 + n * 0x100) >> 2)
+#define DPDMA_DSCR_NEXT_ADDR_CH(n) ((0x020C + n * 0x100) >> 2)
+#define DPDMA_PYLD_CUR_ADDRE_CH(n) ((0x0210 + n * 0x100) >> 2)
+#define DPDMA_PYLD_CUR_ADDR_CH(n) ((0x0214 + n * 0x100) >> 2)
+#define DPDMA_CNTL_CH(n) ((0x0218 + n * 0x100) >> 2)
+#define DPDMA_CNTL_CH_EN (1)
+#define DPDMA_CNTL_CH_PAUSED (1 << 1)
+#define DPDMA_STATUS_CH(n) ((0x021C + n * 0x100) >> 2)
+#define DPDMA_STATUS_BURST_TYPE (1 << 4)
+#define DPDMA_STATUS_MODE (1 << 5)
+#define DPDMA_STATUS_EN_CRC (1 << 6)
+#define DPDMA_STATUS_LAST_DSCR (1 << 7)
+#define DPDMA_STATUS_LDSCR_FRAME (1 << 8)
+#define DPDMA_STATUS_IGNR_DONE (1 << 9)
+#define DPDMA_STATUS_DSCR_DONE (1 << 10)
+#define DPDMA_STATUS_EN_DSCR_UP (1 << 11)
+#define DPDMA_STATUS_EN_DSCR_INTR (1 << 12)
+#define DPDMA_STATUS_PREAMBLE_OFF (13)
+#define DPDMA_VDO_CH(n) ((0x0220 + n * 0x100) >> 2)
+#define DPDMA_PYLD_SZ_CH(n) ((0x0224 + n * 0x100) >> 2)
+#define DPDMA_DSCR_ID_CH(n) ((0x0228 + n * 0x100) >> 2)
+
+/*
+ * Descriptor control field.
+ */
+#define CONTROL_PREAMBLE_VALUE 0xA5
+
+#define CONTROL_PREAMBLE 0xFF
+#define EN_DSCR_DONE_INTR (1 << 8)
+#define EN_DSCR_UPDATE (1 << 9)
+#define IGNORE_DONE (1 << 10)
+#define AXI_BURST_TYPE (1 << 11)
+#define AXCACHE (0x0F << 12)
+#define AXPROT (0x2 << 16)
+#define DESCRIPTOR_MODE (1 << 18)
+#define LAST_DESCRIPTOR (1 << 19)
+#define ENABLE_CRC (1 << 20)
+#define LAST_DESCRIPTOR_OF_FRAME (1 << 21)
+
+/*
+ * Descriptor timestamp field.
+ */
+#define STATUS_DONE (1 << 31)
+
+#define DPDMA_FRAG_MAX_SZ (4096)
+
+typedef enum DPDMABurstType {
+ DPDMA_INCR = 0,
+ DPDMA_FIXED = 1
+} DPDMABurstType;
+
+typedef enum DPDMAMode {
+ DPDMA_CONTIGOUS = 0,
+ DPDMA_FRAGMENTED = 1
+} DPDMAMode;
+
+typedef struct DPDMADescriptor {
+ uint32_t control;
+ uint32_t descriptor_id;
+ /* transfer size in byte. */
+ uint32_t xfer_size;
+ uint32_t line_size_stride;
+ uint32_t timestamp_lsb;
+ uint32_t timestamp_msb;
+ /* contains extension for both descriptor and source. */
+ uint32_t address_extension;
+ uint32_t next_descriptor;
+ uint32_t source_address;
+ uint32_t address_extension_23;
+ uint32_t address_extension_45;
+ uint32_t source_address2;
+ uint32_t source_address3;
+ uint32_t source_address4;
+ uint32_t source_address5;
+ uint32_t crc;
+} DPDMADescriptor;
+
+static bool xilinx_dpdma_desc_is_last(DPDMADescriptor *desc)
+{
+ return ((desc->control & LAST_DESCRIPTOR) != 0);
+}
+
+static bool xilinx_dpdma_desc_is_last_of_frame(DPDMADescriptor *desc)
+{
+ return ((desc->control & LAST_DESCRIPTOR_OF_FRAME) != 0);
+}
+
+static uint64_t xilinx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
+ uint8_t frag)
+{
+ uint64_t addr = 0;
+ assert(frag < 5);
+
+ switch (frag) {
+ case 0:
+ addr = desc->source_address
+ + (extract32(desc->address_extension, 16, 12) << 20);
+ break;
+ case 1:
+ addr = desc->source_address2
+ + (extract32(desc->address_extension_23, 0, 12) << 8);
+ break;
+ case 2:
+ addr = desc->source_address3
+ + (extract32(desc->address_extension_23, 16, 12) << 20);
+ break;
+ case 3:
+ addr = desc->source_address4
+ + (extract32(desc->address_extension_45, 0, 12) << 8);
+ break;
+ case 4:
+ addr = desc->source_address5
+ + (extract32(desc->address_extension_45, 16, 12) << 20);
+ break;
+ default:
+ addr = 0;
+ break;
+ }
+
+ return addr;
+}
+
+static uint32_t xilinx_dpdma_desc_get_transfer_size(DPDMADescriptor *desc)
+{
+ return desc->xfer_size;
+}
+
+static uint32_t xilinx_dpdma_desc_get_line_size(DPDMADescriptor *desc)
+{
+ return extract32(desc->line_size_stride, 0, 18);
+}
+
+static uint32_t xilinx_dpdma_desc_get_line_stride(DPDMADescriptor *desc)
+{
+ return extract32(desc->line_size_stride, 18, 14) * 16;
+}
+
+static inline bool xilinx_dpdma_desc_crc_enabled(DPDMADescriptor *desc)
+{
+ return (desc->control & ENABLE_CRC) != 0;
+}
+
+static inline bool xilinx_dpdma_desc_check_crc(DPDMADescriptor *desc)
+{
+ uint32_t *p = (uint32_t *)desc;
+ uint32_t crc = 0;
+ uint8_t i;
+
+ /*
+ * CRC is calculated on the whole descriptor except the last 32bits word
+ * using 32bits addition.
+ */
+ for (i = 0; i < 15; i++) {
+ crc += p[i];
+ }
+
+ return crc == desc->crc;
+}
+
+static inline bool xilinx_dpdma_desc_completion_interrupt(DPDMADescriptor *desc)
+{
+ return (desc->control & EN_DSCR_DONE_INTR) != 0;
+}
+
+static inline bool xilinx_dpdma_desc_is_valid(DPDMADescriptor *desc)
+{
+ return (desc->control & CONTROL_PREAMBLE) == CONTROL_PREAMBLE_VALUE;
+}
+
+static inline bool xilinx_dpdma_desc_is_contiguous(DPDMADescriptor *desc)
+{
+ return (desc->control & DESCRIPTOR_MODE) == 0;
+}
+
+static inline bool xilinx_dpdma_desc_update_enabled(DPDMADescriptor *desc)
+{
+ return (desc->control & EN_DSCR_UPDATE) != 0;
+}
+
+static inline void xilinx_dpdma_desc_set_done(DPDMADescriptor *desc)
+{
+ desc->timestamp_msb |= STATUS_DONE;
+}
+
+static inline bool xilinx_dpdma_desc_is_already_done(DPDMADescriptor *desc)
+{
+ return (desc->timestamp_msb & STATUS_DONE) != 0;
+}
+
+static inline bool xilinx_dpdma_desc_ignore_done_bit(DPDMADescriptor *desc)
+{
+ return (desc->control & IGNORE_DONE) != 0;
+}
+
+static const VMStateDescription vmstate_xilinx_dpdma = {
+ .name = TYPE_XILINX_DPDMA,
+ .version_id = 1,
+ .fields = (VMStateField[]) {
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void xilinx_dpdma_update_irq(XilinxDPDMAState *s)
+{
+ uint32_t flags;
+
+ flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR]))
+ | (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR])));
+ qemu_set_irq(s->irq, flags != 0);
+}
+
+static uint64_t xilinx_dpdma_descriptor_start_address(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return (s->registers[DPDMA_DSCR_STRT_ADDRE_CH(channel)] << 16)
+ + s->registers[DPDMA_DSCR_STRT_ADDR_CH(channel)];
+}
+
+static uint64_t xilinx_dpdma_descriptor_next_address(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return ((uint64_t)s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] << 32)
+ + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)];
+}
+
+static inline void xilinx_dpdma_set_desc_next_address(XilinxDPDMAState *s,
+ uint8_t channel,
+ uint64_t addr)
+{
+ s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] = extract64(addr, 32, 32);
+ s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = extract64(addr, 0, 32);
+}
+
+static bool xilinx_dpdma_is_channel_enabled(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_EN) != 0;
+}
+
+static bool xilinx_dpdma_is_channel_paused(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_PAUSED) != 0;
+}
+
+static inline bool xilinx_dpdma_is_channel_retriggered(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ /* Clear the retriggered bit after reading it. */
+ bool channel_is_retriggered = s->registers[DPDMA_GBL]
+ & DPDMA_GBL_RTRG_CH(channel);
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_RTRG_CH(channel);
+ return channel_is_retriggered;
+}
+
+static inline bool xilinx_dpdma_is_channel_triggered(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return s->registers[DPDMA_GBL] & DPDMA_GBL_TRG_CH(channel);
+}
+
+static void xilinx_dpdma_update_desc_info(XilinxDPDMAState *s, uint8_t channel,
+ DPDMADescriptor *desc)
+{
+ s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] =
+ extract32(desc->address_extension, 0, 16);
+ s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = desc->next_descriptor;
+ s->registers[DPDMA_PYLD_CUR_ADDRE_CH(channel)] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_PYLD_CUR_ADDR_CH(channel)] = desc->source_address;
+ s->registers[DPDMA_VDO_CH(channel)] =
+ extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_PYLD_SZ_CH(channel)] = desc->xfer_size;
+ s->registers[DPDMA_DSCR_ID_CH(channel)] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_STATUS_CH(channel)] =
+ extract32(desc->control, 0, 8) << 13;
+ if ((desc->control & EN_DSCR_DONE_INTR) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_INTR;
+ }
+ if ((desc->control & EN_DSCR_UPDATE) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_UP;
+ }
+ if ((desc->timestamp_msb & STATUS_DONE) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_DSCR_DONE;
+ }
+ if ((desc->control & IGNORE_DONE) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_IGNR_DONE;
+ }
+ if ((desc->control & LAST_DESCRIPTOR_OF_FRAME) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LDSCR_FRAME;
+ }
+ if ((desc->control & LAST_DESCRIPTOR) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LAST_DSCR;
+ }
+ if ((desc->control & ENABLE_CRC) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_CRC;
+ }
+ if ((desc->control & DESCRIPTOR_MODE) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_MODE;
+ }
+ if ((desc->control & AXI_BURST_TYPE) != 0) {
+ s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_BURST_TYPE;
+ }
+}
+
+#ifdef DEBUG_DPDMA
+static void xilinx_dpdma_dump_descriptor(DPDMADescriptor *desc)
+{
+ uint8_t *p = (uint8_t *)desc;
+ size_t i;
+
+ qemu_log("DUMP DESCRIPTOR:\n");
+ for (i = 0; i < 64; i++) {
+ qemu_log(" %" PRIx8, *p++);
+ if (((i + 1) % 4) == 0) {
+ qemu_log("\n");
+ }
+ }
+}
+#endif
+
+static uint64_t xilinx_dpdma_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ XilinxDPDMAState *s = XILINX_DPDMA(opaque);
+
+ DPRINTF("read @%" HWADDR_PRIx "\n", offset);
+ offset = offset >> 2;
+
+ switch (offset) {
+ /*
+ * Trying to read a write only register.
+ */
+ case DPDMA_GBL:
+ return 0;
+ default:
+ assert(offset <= (0xFFC >> 2));
+ return s->registers[offset];
+ }
+ return 0;
+}
+
+static void xilinx_dpdma_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XilinxDPDMAState *s = XILINX_DPDMA(opaque);
+
+ DPRINTF("write @%" HWADDR_PRIx " = %" PRIx64 "\n", offset, value);
+ offset = offset >> 2;
+
+ switch (offset) {
+ case DPDMA_ISR:
+ s->registers[DPDMA_ISR] &= ~value;
+ xilinx_dpdma_update_irq(s);
+ break;
+ case DPDMA_IEN:
+ value = ~value;
+ s->registers[DPDMA_IMR] &= value;
+ break;
+ case DPDMA_IDS:
+ s->registers[DPDMA_IMR] |= value;
+ break;
+ case DPDMA_EISR:
+ value = ~value;
+ s->registers[DPDMA_EISR] &= value;
+ xilinx_dpdma_update_irq(s);
+ break;
+ case DPDMA_EIEN:
+ value = ~value;
+ s->registers[DPDMA_EIMR] &= value;
+ break;
+ case DPDMA_EIDS:
+ s->registers[DPDMA_EIMR] |= value;
+ break;
+ case DPDMA_IMR:
+ case DPDMA_EIMR:
+ case DPDMA_DSCR_NEXT_ADDRE_CH(0):
+ case DPDMA_DSCR_NEXT_ADDRE_CH(1):
+ case DPDMA_DSCR_NEXT_ADDRE_CH(2):
+ case DPDMA_DSCR_NEXT_ADDRE_CH(3):
+ case DPDMA_DSCR_NEXT_ADDRE_CH(4):
+ case DPDMA_DSCR_NEXT_ADDRE_CH(5):
+ case DPDMA_DSCR_NEXT_ADDR_CH(0):
+ case DPDMA_DSCR_NEXT_ADDR_CH(1):
+ case DPDMA_DSCR_NEXT_ADDR_CH(2):
+ case DPDMA_DSCR_NEXT_ADDR_CH(3):
+ case DPDMA_DSCR_NEXT_ADDR_CH(4):
+ case DPDMA_DSCR_NEXT_ADDR_CH(5):
+ case DPDMA_PYLD_CUR_ADDRE_CH(0):
+ case DPDMA_PYLD_CUR_ADDRE_CH(1):
+ case DPDMA_PYLD_CUR_ADDRE_CH(2):
+ case DPDMA_PYLD_CUR_ADDRE_CH(3):
+ case DPDMA_PYLD_CUR_ADDRE_CH(4):
+ case DPDMA_PYLD_CUR_ADDRE_CH(5):
+ case DPDMA_PYLD_CUR_ADDR_CH(0):
+ case DPDMA_PYLD_CUR_ADDR_CH(1):
+ case DPDMA_PYLD_CUR_ADDR_CH(2):
+ case DPDMA_PYLD_CUR_ADDR_CH(3):
+ case DPDMA_PYLD_CUR_ADDR_CH(4):
+ case DPDMA_PYLD_CUR_ADDR_CH(5):
+ case DPDMA_STATUS_CH(0):
+ case DPDMA_STATUS_CH(1):
+ case DPDMA_STATUS_CH(2):
+ case DPDMA_STATUS_CH(3):
+ case DPDMA_STATUS_CH(4):
+ case DPDMA_STATUS_CH(5):
+ case DPDMA_VDO_CH(0):
+ case DPDMA_VDO_CH(1):
+ case DPDMA_VDO_CH(2):
+ case DPDMA_VDO_CH(3):
+ case DPDMA_VDO_CH(4):
+ case DPDMA_VDO_CH(5):
+ case DPDMA_PYLD_SZ_CH(0):
+ case DPDMA_PYLD_SZ_CH(1):
+ case DPDMA_PYLD_SZ_CH(2):
+ case DPDMA_PYLD_SZ_CH(3):
+ case DPDMA_PYLD_SZ_CH(4):
+ case DPDMA_PYLD_SZ_CH(5):
+ case DPDMA_DSCR_ID_CH(0):
+ case DPDMA_DSCR_ID_CH(1):
+ case DPDMA_DSCR_ID_CH(2):
+ case DPDMA_DSCR_ID_CH(3):
+ case DPDMA_DSCR_ID_CH(4):
+ case DPDMA_DSCR_ID_CH(5):
+ /*
+ * Trying to write to a read only register..
+ */
+ break;
+ case DPDMA_GBL:
+ /*
+ * This is a write only register so it's read as zero in the read
+ * callback.
+ * We store the value anyway so we can know if the channel is
+ * enabled.
+ */
+ s->registers[offset] |= value & 0x00000FFF;
+ break;
+ case DPDMA_DSCR_STRT_ADDRE_CH(0):
+ case DPDMA_DSCR_STRT_ADDRE_CH(1):
+ case DPDMA_DSCR_STRT_ADDRE_CH(2):
+ case DPDMA_DSCR_STRT_ADDRE_CH(3):
+ case DPDMA_DSCR_STRT_ADDRE_CH(4):
+ case DPDMA_DSCR_STRT_ADDRE_CH(5):
+ value &= 0x0000FFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CNTL_CH(0):
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(0);
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CNTL_CH(1):
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(1);
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CNTL_CH(2):
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(2);
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CNTL_CH(3):
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(3);
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CNTL_CH(4):
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(4);
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CNTL_CH(5):
+ s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(5);
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ default:
+ assert(offset <= (0xFFC >> 2));
+ s->registers[offset] = value;
+ break;
+ }
+}
+
+static const MemoryRegionOps dma_ops = {
+ .read = xilinx_dpdma_read,
+ .write = xilinx_dpdma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void xilinx_dpdma_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ XilinxDPDMAState *s = XILINX_DPDMA(obj);
+
+ memory_region_init_io(&s->iomem, obj, &dma_ops, s,
+ TYPE_XILINX_DPDMA, 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static void xilinx_dpdma_reset(DeviceState *dev)
+{
+ XilinxDPDMAState *s = XILINX_DPDMA(dev);
+
+ memset(s->registers, 0, sizeof(s->registers));
+ s->registers[DPDMA_IMR] = 0x07FFFFFF;
+ s->registers[DPDMA_EIMR] = 0xFFFFFFFF;
+ s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF;
+ s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF;
+}
+
+static void xilinx_dpdma_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->vmsd = &vmstate_xilinx_dpdma;
+ dc->reset = xilinx_dpdma_reset;
+}
+
+static const TypeInfo xilinx_dpdma_info = {
+ .name = TYPE_XILINX_DPDMA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XilinxDPDMAState),
+ .instance_init = xilinx_dpdma_init,
+ .class_init = xilinx_dpdma_class_init,
+};
+
+static void xilinx_dpdma_register_types(void)
+{
+ type_register_static(&xilinx_dpdma_info);
+}
+
+size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
+ bool one_desc)
+{
+ uint64_t desc_addr;
+ uint64_t source_addr[6];
+ DPDMADescriptor desc;
+ bool done = false;
+ size_t ptr = 0;
+
+ assert(channel <= 5);
+
+ /* Trigger a VSYNC IRQ when the graphic callback asks for data. */
+ if (channel == 3) {
+ s->registers[DPDMA_ISR] |= (1 << 27);
+ xilinx_dpdma_update_irq(s);
+ }
+
+ DPRINTF("dpdma_start_channel() on channel %u\n", channel);
+
+ if (!xilinx_dpdma_is_channel_triggered(s, channel)) {
+ DPRINTF("Channel isn't triggered..\n");
+ return 0;
+ }
+
+ if (!xilinx_dpdma_is_channel_enabled(s, channel)) {
+ DPRINTF("Channel isn't enabled..\n");
+ return 0;
+ }
+
+ if (xilinx_dpdma_is_channel_paused(s, channel)) {
+ DPRINTF("Channel is paused..\n");
+ return 0;
+ }
+
+ do {
+ if ((s->operation_finished[channel])
+ || xilinx_dpdma_is_channel_retriggered(s, channel)) {
+ desc_addr = xilinx_dpdma_descriptor_start_address(s, channel);
+ s->operation_finished[channel] = false;
+ } else {
+ desc_addr = xilinx_dpdma_descriptor_next_address(s, channel);
+ }
+
+ if (dma_memory_read(&address_space_memory, desc_addr, &desc,
+ sizeof(DPDMADescriptor))) {
+ s->registers[DPDMA_EISR] |= ((1 << 1) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Can't get the descriptor.\n");
+ break;
+ }
+
+ xilinx_dpdma_update_desc_info(s, channel, &desc);
+
+#ifdef DEBUG_DPDMA
+ xilinx_dpdma_dump_descriptor(&desc);
+#endif
+
+ DPRINTF("location of the descriptor: %" PRIx64 "\n", desc_addr);
+ if (!xilinx_dpdma_desc_is_valid(&desc)) {
+ s->registers[DPDMA_EISR] |= ((1 << 7) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Invalid descriptor..\n");
+ break;
+ }
+
+ if (xilinx_dpdma_desc_crc_enabled(&desc)
+ && !xilinx_dpdma_desc_check_crc(&desc)) {
+ s->registers[DPDMA_EISR] |= ((1 << 13) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Bad CRC for descriptor..\n");
+ break;
+ }
+
+ if (xilinx_dpdma_desc_is_already_done(&desc)
+ && !xilinx_dpdma_desc_ignore_done_bit(&desc)) {
+ /* We are trying to process an already processed descriptor. */
+ s->registers[DPDMA_EISR] |= ((1 << 25) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Already processed descriptor..\n");
+ break;
+ }
+
+ done = xilinx_dpdma_desc_is_last(&desc)
+ || xilinx_dpdma_desc_is_last_of_frame(&desc);
+
+ s->operation_finished[channel] = done;
+ if (s->data[channel]) {
+ int64_t transfer_len =
+ xilinx_dpdma_desc_get_transfer_size(&desc);
+ uint32_t line_size = xilinx_dpdma_desc_get_line_size(&desc);
+ uint32_t line_stride = xilinx_dpdma_desc_get_line_stride(&desc);
+ if (xilinx_dpdma_desc_is_contiguous(&desc)) {
+ source_addr[0] =
+ xilinx_dpdma_desc_get_source_address(&desc, 0);
+ while (transfer_len != 0) {
+ if (dma_memory_read(&address_space_memory,
+ source_addr[0],
+ &s->data[channel][ptr],
+ line_size)) {
+ s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
+ xilinx_dpdma_update_irq(s);
+ DPRINTF("Can't get data.\n");
+ break;
+ }
+ ptr += line_size;
+ transfer_len -= line_size;
+ source_addr[0] += line_stride;
+ }
+ } else {
+ DPRINTF("Source address:\n");
+ int frag;
+ for (frag = 0; frag < 5; frag++) {
+ source_addr[frag] =
+ xilinx_dpdma_desc_get_source_address(&desc, frag);
+ DPRINTF("Fragment %u: %" PRIx64 "\n", frag + 1,
+ source_addr[frag]);
+ }
+
+ frag = 0;
+ while ((transfer_len < 0) && (frag < 5)) {
+ size_t fragment_len = DPDMA_FRAG_MAX_SZ
+ - (source_addr[frag] % DPDMA_FRAG_MAX_SZ);
+
+ if (dma_memory_read(&address_space_memory,
+ source_addr[frag],
+ &(s->data[channel][ptr]),
+ fragment_len)) {
+ s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
+ xilinx_dpdma_update_irq(s);
+ DPRINTF("Can't get data.\n");
+ break;
+ }
+ ptr += fragment_len;
+ transfer_len -= fragment_len;
+ frag += 1;
+ }
+ }
+ }
+
+ if (xilinx_dpdma_desc_update_enabled(&desc)) {
+ /* The descriptor need to be updated when it's completed. */
+ DPRINTF("update the descriptor with the done flag set.\n");
+ xilinx_dpdma_desc_set_done(&desc);
+ dma_memory_write(&address_space_memory, desc_addr, &desc,
+ sizeof(DPDMADescriptor));
+ }
+
+ if (xilinx_dpdma_desc_completion_interrupt(&desc)) {
+ DPRINTF("completion interrupt enabled!\n");
+ s->registers[DPDMA_ISR] |= (1 << channel);
+ xilinx_dpdma_update_irq(s);
+ }
+
+ } while (!done && !one_desc);
+
+ return ptr;
+}
+
+void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
+ void *p)
+{
+ if (!s) {
+ qemu_log_mask(LOG_UNIMP, "DPDMA client not attached to valid DPDMA"
+ " instance\n");
+ return;
+ }
+
+ assert(channel <= 5);
+ s->data[channel] = p;
+}
+
+type_init(xilinx_dpdma_register_types)
diff --git a/hw/dma/xilinx_dpdma.h b/hw/dma/xilinx_dpdma.h
new file mode 100644
index 0000000..f92167d
--- /dev/null
+++ b/hw/dma/xilinx_dpdma.h
@@ -0,0 +1,71 @@
+/*
+ * xilinx_dpdma.h
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef XILINX_DPDMA_H
+#define XILINX_DPDMA_H
+
+#include "hw/sysbus.h"
+#include "ui/console.h"
+#include "sysemu/dma.h"
+
+struct XilinxDPDMAState {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ uint32_t registers[0x1000 >> 2];
+ uint8_t *data[6];
+ bool operation_finished[6];
+ qemu_irq irq;
+};
+
+typedef struct XilinxDPDMAState XilinxDPDMAState;
+
+#define TYPE_XILINX_DPDMA "xlnx.dpdma"
+#define XILINX_DPDMA(obj) OBJECT_CHECK(XilinxDPDMAState, (obj), \
+ TYPE_XILINX_DPDMA)
+
+/*
+ * \func xilinx_dpdma_start_operation.
+ * \brief Start the operation on the specified channel. The DPDMA get the
+ * current descriptor and retrieve data to the buffer specified by
+ * dpdma_set_host_data_location.
+ * \arg s The DPDMA instance.
+ * \arg channel The channel to start.
+ * \return the number of byte transfered by the DPDMA or 0 if an error occured.
+ */
+size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
+ bool one_desc);
+
+/*
+ * \func xilinx_dpdma_set_host_data_location.
+ * \brief Set the location in the host memory where to store the data out from
+ * the dma channel.
+ * \arg s The DPDMA instance.
+ * \arg channel The channel associated to the pointer.
+ * \arg p The buffer where to store the data.
+ */
+/* XXX: add a maximum size arg and send an interrupt in case of overflow. */
+void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
+ void *p);
+
+#endif /* !XILINX_DPDMA_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 6/7] Introduce xilinx dp.
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
` (4 preceding siblings ...)
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 5/7] Introduce xilinx dpdma fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 8:21 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 7/7] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This is the implementation of the DisplayPort.
It has an aux-bus to access dpcd and edid needed for the driver to complete.
Graphic plane is connected to the channel 3.
Video plane is connected to the channel 0.
Audio stream are connected to the channels 4 and 5.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/display/Makefile.objs | 2 +-
hw/display/xilinx_dp.c | 1427 ++++++++++++++++++++++++++++++++++++++++++++++
hw/display/xilinx_dp.h | 129 +++++
3 files changed, 1557 insertions(+), 1 deletion(-)
create mode 100644 hw/display/xilinx_dp.c
create mode 100644 hw/display/xilinx_dp.h
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index f75094f..f418dbc 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -36,4 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
obj-$(CONFIG_VIRTIO) += virtio-gpu.o
-obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o
+obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o xilinx_dp.o
diff --git a/hw/display/xilinx_dp.c b/hw/display/xilinx_dp.c
new file mode 100644
index 0000000..cf48d8b
--- /dev/null
+++ b/hw/display/xilinx_dp.c
@@ -0,0 +1,1427 @@
+/*
+ * xilinx_dp.c
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "xilinx_dp.h"
+
+#ifndef DEBUG_DP
+#define DEBUG_DP 0
+#endif
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_DP) { \
+ qemu_log("xilinx_dp: " fmt , ## __VA_ARGS__); \
+ } \
+} while (0);
+
+/*
+ * Register offset for DP.
+ */
+#define DP_LINK_BW_SET (0x0000 >> 2)
+#define DP_LANE_COUNT_SET (0x0004 >> 2)
+#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
+#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
+#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
+#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
+#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
+#define DP_SOFTWARE_RESET (0x001C >> 2)
+#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
+#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
+#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
+#define DP_VERSION_REGISTER (0x00F8 >> 2)
+#define DP_CORE_ID (0x00FC >> 2)
+#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
+#define AUX_ADDR_ONLY_MASK (0x1000)
+#define AUX_COMMAND_MASK (0x0F00)
+#define AUX_COMMAND_SHIFT (8)
+#define AUX_COMMAND_NBYTES (0x000F)
+#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
+#define DP_AUX_ADDRESS (0x0108 >> 2)
+#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
+#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
+#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
+#define DP_AUX_REPLY_DATA (0x0134 >> 2)
+#define DP_AUX_REPLY_CODE (0x0138 >> 2)
+#define DP_AUX_REPLY_COUNT (0x013C >> 2)
+#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
+#define DP_REPLY_STATUS (0x014C >> 2)
+#define DP_HPD_DURATION (0x0150 >> 2)
+#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
+#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
+#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
+#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
+#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
+#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
+#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
+#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
+#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
+#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
+#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
+#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
+#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
+#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
+#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
+#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
+#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
+#define DP_INIT_WAIT (0x01CC >> 2)
+#define DP_PHY_RESET (0x0200 >> 2)
+#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
+#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
+#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
+#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
+#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
+#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
+#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
+#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
+#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
+#define DP_PHY_STATUS (0x0280 >> 2)
+#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
+#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
+#define DP_TX_AUDIO_INFO_DATA0 (0x0308 >> 2)
+#define DP_TX_AUDIO_INFO_DATA1 (0x030C >> 2)
+#define DP_TX_AUDIO_INFO_DATA2 (0x0310 >> 2)
+#define DP_TX_AUDIO_INFO_DATA3 (0x0314 >> 2)
+#define DP_TX_AUDIO_INFO_DATA4 (0x0318 >> 2)
+#define DP_TX_AUDIO_INFO_DATA5 (0x031C >> 2)
+#define DP_TX_AUDIO_INFO_DATA6 (0x0320 >> 2)
+#define DP_TX_AUDIO_INFO_DATA7 (0x0324 >> 2)
+#define DP_TX_M_AUD (0x0328 >> 2)
+#define DP_TX_N_AUD (0x032C >> 2)
+#define DP_TX_AUDIO_EXT_DATA0 (0x0330 >> 2)
+#define DP_TX_AUDIO_EXT_DATA1 (0x0334 >> 2)
+#define DP_TX_AUDIO_EXT_DATA2 (0x0338 >> 2)
+#define DP_TX_AUDIO_EXT_DATA3 (0x033C >> 2)
+#define DP_TX_AUDIO_EXT_DATA4 (0x0340 >> 2)
+#define DP_TX_AUDIO_EXT_DATA5 (0x0344 >> 2)
+#define DP_TX_AUDIO_EXT_DATA6 (0x0348 >> 2)
+#define DP_TX_AUDIO_EXT_DATA7 (0x034C >> 2)
+#define DP_TX_AUDIO_EXT_DATA8 (0x0350 >> 2)
+#define DP_INT_STATUS (0x03A0 >> 2)
+#define DP_INT_MASK (0x03A4 >> 2)
+#define DP_INT_EN (0x03A8 >> 2)
+#define DP_INT_DS (0x03AC >> 2)
+
+/*
+ * Registers offset for Audio Video Buffer configuration.
+ */
+#define V_BLEND_OFFSET (0xA000)
+#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
+#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
+#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
+#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
+#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
+#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
+#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF0 (0x0020 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF1 (0x0024 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF2 (0x0028 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF3 (0x002C >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF4 (0x0030 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF5 (0x0034 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF6 (0x0038 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF7 (0x003C >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF8 (0x0040 >> 2)
+#define V_BLEND_IN1CSC_COEFF0 (0x0044 >> 2)
+#define V_BLEND_IN1CSC_COEFF1 (0x0048 >> 2)
+#define V_BLEND_IN1CSC_COEFF2 (0x004C >> 2)
+#define V_BLEND_IN1CSC_COEFF3 (0x0050 >> 2)
+#define V_BLEND_IN1CSC_COEFF4 (0x0054 >> 2)
+#define V_BLEND_IN1CSC_COEFF5 (0x0058 >> 2)
+#define V_BLEND_IN1CSC_COEFF6 (0x005C >> 2)
+#define V_BLEND_IN1CSC_COEFF7 (0x0060 >> 2)
+#define V_BLEND_IN1CSC_COEFF8 (0x0064 >> 2)
+#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
+#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
+#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
+#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
+#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
+#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
+#define V_BLEND_IN2CSC_COEFF0 (0x0080 >> 2)
+#define V_BLEND_IN2CSC_COEFF1 (0x0084 >> 2)
+#define V_BLEND_IN2CSC_COEFF2 (0x0088 >> 2)
+#define V_BLEND_IN2CSC_COEFF3 (0x008C >> 2)
+#define V_BLEND_IN2CSC_COEFF4 (0x0090 >> 2)
+#define V_BLEND_IN2CSC_COEFF5 (0x0094 >> 2)
+#define V_BLEND_IN2CSC_COEFF6 (0x0098 >> 2)
+#define V_BLEND_IN2CSC_COEFF7 (0x009C >> 2)
+#define V_BLEND_IN2CSC_COEFF8 (0x00A0 >> 2)
+#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
+#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
+#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
+#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
+#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
+#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
+#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
+
+/*
+ * Registers offset for Audio Video Buffer configuration.
+ */
+#define AV_BUF_MANAGER_OFFSET (0xB000)
+#define AV_BUF_FORMAT (0x0000 >> 2)
+#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
+#define AV_CHBUF0 (0x0010 >> 2)
+#define AV_CHBUF1 (0x0014 >> 2)
+#define AV_CHBUF2 (0x0018 >> 2)
+#define AV_CHBUF3 (0x001C >> 2)
+#define AV_CHBUF4 (0x0020 >> 2)
+#define AV_CHBUF5 (0x0024 >> 2)
+#define AV_BUF_STC_CONTROL (0x002C >> 2)
+#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
+#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
+#define AV_BUF_STC_ADJ (0x0038 >> 2)
+#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
+#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
+#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
+#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
+#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
+#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
+#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
+#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
+#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
+#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
+#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
+#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
+#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
+#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
+#define AV_BUF_SRST_REG (0x0124 >> 2)
+#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
+#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
+#define AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR (0x0200 >> 2)
+#define AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR (0x0204 >> 2)
+#define AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR (0x0208 >> 2)
+#define AV_BUF_VIDEO_COMP0_SCALE_FACTOR (0x020C >> 2)
+#define AV_BUF_VIDEO_COMP1_SCALE_FACTOR (0x0210 >> 2)
+#define AV_BUF_VIDEO_COMP2_SCALE_FACTOR (0x0214 >> 2)
+#define AV_BUF_LIVE_VIDEO_COMP0_SF (0x0218 >> 2)
+#define AV_BUF_LIVE_VIDEO_COMP1_SF (0x021C >> 2)
+#define AV_BUF_LIVE_VIDEO_COMP2_SF (0x0220 >> 2)
+#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
+#define AV_BUF_LIVE_GFX_COMP0_SF (0x0228 >> 2)
+#define AV_BUF_LIVE_GFX_COMP1_SF (0x022C >> 2)
+#define AV_BUF_LIVE_GFX_COMP2_SF (0x0230 >> 2)
+#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
+
+#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
+#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
+#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
+#define AUD_CH_STATUS_REG0 (0x0008 >> 2)
+#define AUD_CH_STATUS_REG1 (0x000C >> 2)
+#define AUD_CH_STATUS_REG2 (0x0010 >> 2)
+#define AUD_CH_STATUS_REG3 (0x0014 >> 2)
+#define AUD_CH_STATUS_REG4 (0x0018 >> 2)
+#define AUD_CH_STATUS_REG5 (0x001C >> 2)
+#define AUD_CH_A_DATA_REG0 (0x0020 >> 2)
+#define AUD_CH_A_DATA_REG1 (0x0024 >> 2)
+#define AUD_CH_A_DATA_REG2 (0x0028 >> 2)
+#define AUD_CH_A_DATA_REG3 (0x002C >> 2)
+#define AUD_CH_A_DATA_REG4 (0x0030 >> 2)
+#define AUD_CH_A_DATA_REG5 (0x0034 >> 2)
+#define AUD_CH_B_DATA_REG0 (0x0038 >> 2)
+#define AUD_CH_B_DATA_REG1 (0x003C >> 2)
+#define AUD_CH_B_DATA_REG2 (0x0040 >> 2)
+#define AUD_CH_B_DATA_REG3 (0x0044 >> 2)
+#define AUD_CH_B_DATA_REG4 (0x0048 >> 2)
+#define AUD_CH_B_DATA_REG5 (0x004C >> 2)
+
+typedef enum dp_graphic_fmt {
+ DP_GRAPHIC_RGBA8888 = 0 << 8,
+ DP_GRAPHIC_ABGR8888 = 1 << 8,
+ DP_GRAPHIC_RGB888 = 2 << 8,
+ DP_GRAPHIC_BGR888 = 3 << 8,
+ DP_GRAPHIC_RGBA5551 = 4 << 8,
+ DP_GRAPHIC_RGBA4444 = 5 << 8,
+ DP_GRAPHIC_RGB565 = 6 << 8,
+ DP_GRAPHIC_8BPP = 7 << 8,
+ DP_GRAPHIC_4BPP = 8 << 8,
+ DP_GRAPHIC_2BPP = 9 << 8,
+ DP_GRAPHIC_1BPP = 10 << 8,
+ DP_GRAPHIC_MASK = 0xF << 8
+} dp_graphic_fmt;
+
+typedef enum dp_video_fmt {
+ DP_NL_VID_CB_Y0_CR_Y1 = 0,
+ DP_NL_VID_CR_Y0_CB_Y1 = 1,
+ DP_NL_VID_Y0_CR_Y1_CB = 2,
+ DP_NL_VID_Y0_CB_Y1_CR = 3,
+ DP_NL_VID_YV16 = 4,
+ DP_NL_VID_YV24 = 5,
+ DP_NL_VID_YV16CL = 6,
+ DP_NL_VID_MONO = 7,
+ DP_NL_VID_YV16CL2 = 8,
+ DP_NL_VID_YUV444 = 9,
+ DP_NL_VID_RGB888 = 10,
+ DP_NL_VID_RGBA8880 = 11,
+ DP_NL_VID_RGB888_10BPC = 12,
+ DP_NL_VID_YUV444_10BPC = 13,
+ DP_NL_VID_YV16CL2_10BPC = 14,
+ DP_NL_VID_YV16CL_10BPC = 15,
+ DP_NL_VID_YV16_10BPC = 16,
+ DP_NL_VID_YV24_10BPC = 17,
+ DP_NL_VID_Y_ONLY_10BPC = 18,
+ DP_NL_VID_YV16_420 = 19,
+ DP_NL_VID_YV16CL_420 = 20,
+ DP_NL_VID_YV16CL2_420 = 21,
+ DP_NL_VID_YV16_420_10BPC = 22,
+ DP_NL_VID_YV16CL_420_10BPC = 23,
+ DP_NL_VID_YV16CL2_420_10BPC = 24,
+ DP_NL_VID_FMT_MASK = 0x1F
+} dp_video_fmt;
+
+static const VMStateDescription vmstate_dp = {
+ .name = TYPE_XILINX_DP,
+ .version_id = 1,
+ .fields = (VMStateField[]){
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void xilinx_dp_update_irq(XilinxDPState *s);
+
+static uint64_t xilinx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ default:
+ return s->audio_registers[offset];
+ }
+}
+
+static void xilinx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ case AUDIO_MIXER_META_DATA:
+ s->audio_registers[offset] = value & 0x00000001;
+ break;
+ default:
+ s->audio_registers[offset] = value;
+ break;
+ }
+}
+
+static const MemoryRegionOps audio_ops = {
+ .read = xilinx_dp_audio_read,
+ .write = xilinx_dp_audio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static inline uint32_t xilinx_dp_audio_get_volume(XilinxDPState *s,
+ uint8_t channel)
+{
+ switch (channel) {
+ case 0:
+ return s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL] & 0xFFFF;
+ case 1:
+ return (s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL] >> 16) & 0xFFFF;
+ default:
+ return 0;
+ }
+}
+
+static inline void xilinx_dp_audio_activate(XilinxDPState *s)
+{
+ bool activated =
+ ((s->core_registers[DP_TX_AUDIO_CONTROL] & 0x00000001) != 0);
+ AUD_set_active_out(s->amixer_output_stream, activated);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 4, &s->audio_buffer_0);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 5, &s->audio_buffer_1);
+}
+
+static inline void xilinx_dp_audio_mix_buffer(XilinxDPState *s)
+{
+ /*
+ * Audio packets are signed and have this shape:
+ * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
+ * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 |
+ *
+ * Output audio is 16bits saturated.
+ */
+ int i;
+
+ if ((s->audio_data_available[0]) && (xilinx_dp_audio_get_volume(s, 0))) {
+ for (i = 0; i < s->audio_data_available[0] / 2; i++) {
+ s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
+ * xilinx_dp_audio_get_volume(s, 0) / 8192;
+ }
+ s->byte_left = s->audio_data_available[0];
+ } else {
+ memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
+ }
+
+ if ((s->audio_data_available[1]) && (xilinx_dp_audio_get_volume(s, 1))) {
+ if ((s->audio_data_available[0] == 0)
+ || (s->audio_data_available[1] == s->audio_data_available[0])) {
+ for (i = 0; i < s->audio_data_available[1] / 2; i++) {
+ s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
+ * xilinx_dp_audio_get_volume(s, 1) / 8192;
+ }
+ s->byte_left = s->audio_data_available[1];
+ }
+ }
+
+ for (i = 0; i < s->byte_left / 2; i++) {
+ s->out_buffer[i] = s->temp_buffer[i];
+ if (s->temp_buffer[i] < -32767) {
+ s->out_buffer[i] = -32767;
+ }
+ if (s->temp_buffer[i] > 32767) {
+ s->out_buffer[i] = 32767;
+ }
+ }
+
+ s->data_ptr = 0;
+}
+
+static void xilinx_dp_audio_callback(void *opaque, int avail)
+{
+ /*
+ * Get some data from the DPDMA and compute them. Then wait QEMU's audio
+ * subsystem to call this callback.
+ */
+ XilinxDPState *s = XILINX_DP(opaque);
+ size_t written = 0;
+ static uint8_t buffer;
+
+ /* If there are already some data don't get more data. */
+ if (s->byte_left == 0) {
+ buffer++;
+ s->audio_data_available[0] = xilinx_dpdma_start_operation(s->dpdma, 4,
+ true);
+ s->audio_data_available[1] = xilinx_dpdma_start_operation(s->dpdma, 5,
+ true);
+ xilinx_dp_audio_mix_buffer(s);
+ }
+
+ /* Send the buffer through the audio. */
+ if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
+ if (s->byte_left != 0) {
+ written = AUD_write(s->amixer_output_stream,
+ &s->out_buffer[s->data_ptr], s->byte_left);
+ } else {
+ /*
+ * There is nothing to play.. We don't have any data! Fill the
+ * buffer with zero's and send it.
+ */
+ written = 0;
+ memset(s->out_buffer, 0, 1024);
+ AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
+ }
+ } else {
+ written = AUD_write(s->amixer_output_stream,
+ &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
+ }
+ s->byte_left -= written;
+ s->data_ptr += written;
+}
+
+/*
+ * AUX channel related function.
+ */
+static void xilinx_dp_aux_clear_rx_fifo(XilinxDPState *s)
+{
+ fifo8_reset(&s->rx_fifo);
+}
+
+static void xilinx_dp_aux_push_rx_fifo(XilinxDPState *s, uint8_t *buf,
+ size_t len)
+{
+ int i;
+
+ DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
+ for (i = 0; i < len; i++) {
+ if (fifo8_is_full(&s->rx_fifo)) {
+ DPRINTF("rx_fifo overflow..\n");
+ abort();
+ }
+ fifo8_push(&s->rx_fifo, buf[i]);
+ }
+}
+
+static uint8_t xilinx_dp_aux_pop_rx_fifo(XilinxDPState *s)
+{
+ uint8_t ret;
+
+ if (fifo8_is_empty(&s->rx_fifo)) {
+ DPRINTF("rx_fifo underflow..\n");
+ abort();
+ }
+ ret = fifo8_pop(&s->rx_fifo);
+ DPRINTF("pop 0x%2.2X from rx_fifo.\n", ret);
+ return ret;
+}
+
+static void xilinx_dp_aux_clear_tx_fifo(XilinxDPState *s)
+{
+ fifo8_reset(&s->tx_fifo);
+}
+
+static void xilinx_dp_aux_push_tx_fifo(XilinxDPState *s, uint8_t *buf,
+ size_t len)
+{
+ int i;
+
+ DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
+ for (i = 0; i < len; i++) {
+ if (fifo8_is_full(&s->tx_fifo)) {
+ DPRINTF("tx_fifo overflow..\n");
+ abort();
+ }
+ fifo8_push(&s->tx_fifo, buf[i]);
+ }
+}
+
+static uint8_t xilinx_dp_aux_pop_tx_fifo(XilinxDPState *s)
+{
+ uint8_t ret;
+
+ if (fifo8_is_empty(&s->tx_fifo)) {
+ DPRINTF("tx_fifo underflow..\n");
+ abort();
+ }
+ ret = fifo8_pop(&s->tx_fifo);
+ DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
+ return ret;
+}
+
+static uint32_t xilinx_dp_aux_get_address(XilinxDPState *s)
+{
+ return s->core_registers[DP_AUX_ADDRESS];
+}
+
+static uint8_t xilinx_dp_aux_get_data(XilinxDPState *s)
+{
+ return xilinx_dp_aux_pop_rx_fifo(s);
+}
+
+static void xilinx_dp_aux_set_data(XilinxDPState *s, uint8_t value)
+{
+ xilinx_dp_aux_push_tx_fifo(s, &value, 1);
+}
+
+/*
+ * Get command from the register.
+ */
+static void xilinx_dp_aux_set_command(XilinxDPState *s, uint32_t value)
+{
+ bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
+ aux_command cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
+ uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
+ uint8_t buf[16];
+ int i;
+
+ /*
+ * When an address_only command is executed nothing happen to the fifo, so
+ * just make nbytes = 0.
+ */
+ if (address_only) {
+ nbytes = 0;
+ }
+
+ switch (cmd) {
+ case READ_AUX:
+ case READ_I2C:
+ case READ_I2C_MOT:
+ s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
+ xilinx_dp_aux_get_address(s),
+ nbytes, buf);
+ s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
+
+ if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
+ xilinx_dp_aux_push_rx_fifo(s, buf, nbytes);
+ }
+ break;
+ case WRITE_AUX:
+ case WRITE_I2C:
+ case WRITE_I2C_MOT:
+ for (i = 0; i < nbytes; i++) {
+ buf[i] = xilinx_dp_aux_pop_tx_fifo(s);
+ }
+ s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
+ xilinx_dp_aux_get_address(s),
+ nbytes, buf);
+ xilinx_dp_aux_clear_tx_fifo(s);
+ break;
+ case WRITE_I2C_STATUS:
+ default:
+ abort();
+ break;
+ }
+
+ s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
+}
+
+static void xilinx_dp_set_dpdma(Object *obj, const char *name, Object *val,
+ Error **errp)
+{
+ XilinxDPState *s = XILINX_DP(obj);
+ if (s->console) {
+ DisplaySurface *surface = qemu_console_surface(s->console);
+ XilinxDPDMAState *dma = XILINX_DPDMA(val);
+ xilinx_dpdma_set_host_data_location(dma, 3, surface_data(surface));
+ }
+}
+
+static inline uint8_t xilinx_dp_global_alpha_value(XilinxDPState *s)
+{
+ return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
+}
+
+static inline bool xilinx_dp_global_alpha_enabled(XilinxDPState *s)
+{
+ /*
+ * If the alpha is totally opaque (255) we don't consider the alpha is
+ * disabled to reduce CPU consumption.
+ */
+ return ((xilinx_dp_global_alpha_value(s) != 0xFF) &&
+ ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
+}
+
+static void xilinx_dp_recreate_surface(XilinxDPState *s)
+{
+ /*
+ * Two possibilities, if blending is enabled the console display bout_plane,
+ * if not g_plane is displayed.
+ */
+ uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
+ uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
+ DisplaySurface *current_console_surface = qemu_console_surface(s->console);
+
+ if ((width != 0) && (height != 0)) {
+ /*
+ * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the
+ * surface we need to be carefull and don't free the surface associated
+ * to the console or double free will happen.
+ */
+ if (s->bout_plane.surface != current_console_surface) {
+ qemu_free_displaysurface(s->bout_plane.surface);
+ }
+ if (s->v_plane.surface != current_console_surface) {
+ qemu_free_displaysurface(s->v_plane.surface);
+ }
+ if (s->g_plane.surface != current_console_surface) {
+ qemu_free_displaysurface(s->g_plane.surface);
+
+ }
+
+ s->g_plane.surface
+ = qemu_create_displaysurface_from(width, height,
+ s->g_plane.format, 0, NULL);
+ s->v_plane.surface
+ = qemu_create_displaysurface_from(width, height,
+ s->v_plane.format, 0, NULL);
+ if (xilinx_dp_global_alpha_enabled(s)) {
+ s->bout_plane.surface =
+ qemu_create_displaysurface_from(width,
+ height,
+ s->g_plane.format,
+ 0, NULL);
+ dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
+ } else {
+ s->bout_plane.surface = NULL;
+ dpy_gfx_replace_surface(s->console, s->g_plane.surface);
+ }
+
+ xilinx_dpdma_set_host_data_location(s->dpdma, 3,
+ surface_data(s->g_plane.surface));
+ xilinx_dpdma_set_host_data_location(s->dpdma, 0,
+ surface_data(s->v_plane.surface));
+ }
+}
+
+/*
+ * Change the graphic format of the surface.
+ * XXX: To be completed.
+ */
+static void xilinx_dp_change_graphic_fmt(XilinxDPState *s)
+{
+ switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
+ case DP_GRAPHIC_RGBA8888:
+ s->g_plane.format = PIXMAN_r8g8b8a8;
+ break;
+ case DP_GRAPHIC_ABGR8888:
+ s->g_plane.format = PIXMAN_a8b8g8r8;
+ break;
+ case DP_GRAPHIC_RGB565:
+ s->g_plane.format = PIXMAN_r5g6b5;
+ break;
+ case DP_GRAPHIC_RGB888:
+ s->g_plane.format = PIXMAN_r8g8b8;
+ break;
+ case DP_GRAPHIC_BGR888:
+ s->g_plane.format = PIXMAN_b8g8r8;
+ break;
+ default:
+ DPRINTF("error: unsupported graphic format %u.\n",
+ s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
+ abort();
+ break;
+ }
+
+ switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
+ case 0:
+ s->v_plane.format = PIXMAN_r8g8b8a8;
+ break;
+ case DP_NL_VID_RGBA8880:
+ s->v_plane.format = PIXMAN_r8g8b8a8;
+ break;
+ default:
+ DPRINTF("error: unsupported video format %u.\n",
+ s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
+ abort();
+ break;
+ }
+
+ xilinx_dp_recreate_surface(s);
+}
+
+static void xilinx_dp_update_irq(XilinxDPState *s)
+{
+ uint32_t flags;
+
+ flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
+ DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
+ qemu_set_irq(s->irq, flags != 0);
+}
+
+static uint64_t xilinx_dp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ uint64_t ret = 0;
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ /*
+ * Trying to read a write only register.
+ */
+ case DP_TX_USER_FIFO_OVERFLOW:
+ ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
+ s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
+ break;
+ case DP_AUX_WRITE_FIFO:
+ ret = 0;
+ break;
+ case DP_AUX_REPLY_DATA:
+ ret = xilinx_dp_aux_get_data(s);
+ break;
+ case DP_INTERRUPT_SIGNAL_STATE:
+ /*
+ * XXX: Not sure it is the right thing to do actually.
+ * The register is not written by the device driver so it's stuck
+ * to 0x04.
+ */
+ ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
+ s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
+ break;
+ case DP_TX_AUDIO_INFO_DATA0:
+ case DP_TX_AUDIO_INFO_DATA1:
+ case DP_TX_AUDIO_INFO_DATA2:
+ case DP_TX_AUDIO_INFO_DATA3:
+ case DP_TX_AUDIO_INFO_DATA4:
+ case DP_TX_AUDIO_INFO_DATA5:
+ case DP_TX_AUDIO_INFO_DATA6:
+ case DP_TX_AUDIO_INFO_DATA7:
+ case DP_TX_AUDIO_EXT_DATA0:
+ case DP_TX_AUDIO_EXT_DATA1:
+ case DP_TX_AUDIO_EXT_DATA2:
+ case DP_TX_AUDIO_EXT_DATA3:
+ case DP_TX_AUDIO_EXT_DATA4:
+ case DP_TX_AUDIO_EXT_DATA5:
+ case DP_TX_AUDIO_EXT_DATA6:
+ case DP_TX_AUDIO_EXT_DATA7:
+ case DP_TX_AUDIO_EXT_DATA8:
+ /* write only registers */
+ ret = 0;
+ break;
+ default:
+ assert(offset <= (0x3AC >> 2));
+ ret = s->core_registers[offset];
+ break;
+ }
+
+ DPRINTF("core read @%" PRIx64 " = 0x%8.8lX\n", offset << 2, ret);
+ return ret;
+}
+
+static void xilinx_dp_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ DPRINTF("core write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ /*
+ * Only special write case are handled.
+ */
+ case DP_LINK_BW_SET:
+ s->core_registers[offset] = value & 0x000000FF;
+ break;
+ case DP_LANE_COUNT_SET:
+ case DP_MAIN_STREAM_MISC0:
+ s->core_registers[offset] = value & 0x0000000F;
+ break;
+ case DP_TRAINING_PATTERN_SET:
+ case DP_LINK_QUAL_PATTERN_SET:
+ case DP_MAIN_STREAM_POLARITY:
+ case DP_PHY_VOLTAGE_DIFF_LANE_0:
+ case DP_PHY_VOLTAGE_DIFF_LANE_1:
+ s->core_registers[offset] = value & 0x00000003;
+ break;
+ case DP_ENHANCED_FRAME_EN:
+ case DP_SCRAMBLING_DISABLE:
+ case DP_DOWNSPREAD_CTRL:
+ case DP_MAIN_STREAM_ENABLE:
+ case DP_TRANSMIT_PRBS7:
+ s->core_registers[offset] = value & 0x00000001;
+ break;
+ case DP_PHY_CLOCK_SELECT:
+ s->core_registers[offset] = value & 0x00000007;
+ case DP_SOFTWARE_RESET:
+ /*
+ * No need to update this bit as it's read '0'.
+ */
+ /*
+ * TODO: reset IP.
+ */
+ break;
+ case DP_TRANSMITTER_ENABLE:
+ s->core_registers[offset] = value & 0x01;
+ break;
+ case DP_FORCE_SCRAMBLER_RESET:
+ /*
+ * No need to update this bit as it's read '0'.
+ */
+ /*
+ * TODO: force a scrambler reset??
+ */
+ break;
+ case DP_AUX_COMMAND_REGISTER:
+ s->core_registers[offset] = value & 0x00001F0F;
+ xilinx_dp_aux_set_command(s, s->core_registers[offset]);
+ break;
+ case DP_MAIN_STREAM_HTOTAL:
+ case DP_MAIN_STREAM_VTOTAL:
+ case DP_MAIN_STREAM_HSTART:
+ case DP_MAIN_STREAM_VSTART:
+ s->core_registers[offset] = value & 0x0000FFFF;
+ break;
+ case DP_MAIN_STREAM_HRES:
+ case DP_MAIN_STREAM_VRES:
+ s->core_registers[offset] = value & 0x0000FFFF;
+ xilinx_dp_recreate_surface(s);
+ break;
+ case DP_MAIN_STREAM_HSWIDTH:
+ case DP_MAIN_STREAM_VSWIDTH:
+ s->core_registers[offset] = value & 0x00007FFF;
+ break;
+ case DP_MAIN_STREAM_MISC1:
+ s->core_registers[offset] = value & 0x00000086;
+ break;
+ case DP_MAIN_STREAM_M_VID:
+ case DP_MAIN_STREAM_N_VID:
+ s->core_registers[offset] = value & 0x00FFFFFF;
+ break;
+ case DP_MSA_TRANSFER_UNIT_SIZE:
+ case DP_MIN_BYTES_PER_TU:
+ case DP_INIT_WAIT:
+ s->core_registers[offset] = value & 0x00000007;
+ break;
+ case DP_USER_DATA_COUNT_PER_LANE:
+ s->core_registers[offset] = value & 0x0003FFFF;
+ break;
+ case DP_FRAC_BYTES_PER_TU:
+ s->core_registers[offset] = value & 0x000003FF;
+ break;
+ case DP_PHY_RESET:
+ s->core_registers[offset] = value & 0x00010003;
+ /*
+ * TODO: Reset something?
+ */
+ break;
+ case DP_TX_PHY_POWER_DOWN:
+ s->core_registers[offset] = value & 0x0000000F;
+ /*
+ * TODO: Power down things?
+ */
+ break;
+ case DP_AUX_WRITE_FIFO:
+ xilinx_dp_aux_set_data(s, value & 0x0000000F);
+ break;
+ case DP_AUX_CLOCK_DIVIDER:
+ break;
+ case DP_AUX_REPLY_COUNT:
+ /*
+ * Writing to this register clear the counter.
+ */
+ s->core_registers[offset] = 0x00000000;
+ break;
+ case DP_AUX_ADDRESS:
+ s->core_registers[offset] = value & 0x000FFFFF;
+ break;
+ case DP_VERSION_REGISTER:
+ case DP_CORE_ID:
+ case DP_TX_USER_FIFO_OVERFLOW:
+ case DP_AUX_REPLY_DATA:
+ case DP_AUX_REPLY_CODE:
+ case DP_REPLY_DATA_COUNT:
+ case DP_REPLY_STATUS:
+ case DP_HPD_DURATION:
+ /*
+ * Write to read only location..
+ */
+ break;
+ case DP_TX_AUDIO_CONTROL:
+ s->core_registers[offset] = value & 0x00000001;
+ xilinx_dp_audio_activate(s);
+ break;
+ case DP_TX_AUDIO_CHANNELS:
+ s->core_registers[offset] = value & 0x00000007;
+ xilinx_dp_audio_activate(s);
+ break;
+ case DP_INT_STATUS:
+ s->core_registers[DP_INT_STATUS] &= ~value;
+ xilinx_dp_update_irq(s);
+ break;
+ case DP_INT_EN:
+ s->core_registers[DP_INT_MASK] &= ~value;
+ xilinx_dp_update_irq(s);
+ break;
+ case DP_INT_DS:
+ s->core_registers[DP_INT_MASK] |= ~value;
+ xilinx_dp_update_irq(s);
+ break;
+ default:
+ assert(offset <= (0x504C >> 2));
+ s->core_registers[offset] = value;
+ break;
+ }
+}
+
+static const MemoryRegionOps dp_ops = {
+ .read = xilinx_dp_read,
+ .write = xilinx_dp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+/*
+ * This is to handle Read/Write to the Video Blender.
+ */
+static void xilinx_dp_vblend_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ bool alpha_was_enabled;
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ DPRINTF("vblend: write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ case V_BLEND_BG_CLR_0:
+ case V_BLEND_BG_CLR_1:
+ case V_BLEND_BG_CLR_2:
+ s->vblend_registers[offset] = value & 0x00000FFF;
+ break;
+ case V_BLEND_SET_GLOBAL_ALPHA_REG:
+ /*
+ * A write to this register can enable or disable blending. Thus we need
+ * to recreate the surfaces.
+ */
+ alpha_was_enabled = xilinx_dp_global_alpha_enabled(s);
+ s->vblend_registers[offset] = value & 0x000001FF;
+ if (xilinx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
+ xilinx_dp_recreate_surface(s);
+ }
+ break;
+ case V_BLEND_OUTPUT_VID_FORMAT:
+ s->vblend_registers[offset] = value & 0x00000017;
+ break;
+ case V_BLEND_LAYER0_CONTROL:
+ case V_BLEND_LAYER1_CONTROL:
+ s->vblend_registers[offset] = value & 0x00000103;
+ break;
+ case V_BLEND_RGB2YCBCR_COEFF0:
+ case V_BLEND_RGB2YCBCR_COEFF1:
+ case V_BLEND_RGB2YCBCR_COEFF2:
+ case V_BLEND_RGB2YCBCR_COEFF3:
+ case V_BLEND_RGB2YCBCR_COEFF4:
+ case V_BLEND_RGB2YCBCR_COEFF5:
+ case V_BLEND_RGB2YCBCR_COEFF6:
+ case V_BLEND_RGB2YCBCR_COEFF7:
+ case V_BLEND_RGB2YCBCR_COEFF8:
+ case V_BLEND_IN1CSC_COEFF0:
+ case V_BLEND_IN1CSC_COEFF1:
+ case V_BLEND_IN1CSC_COEFF2:
+ case V_BLEND_IN1CSC_COEFF3:
+ case V_BLEND_IN1CSC_COEFF4:
+ case V_BLEND_IN1CSC_COEFF5:
+ case V_BLEND_IN1CSC_COEFF6:
+ case V_BLEND_IN1CSC_COEFF7:
+ case V_BLEND_IN1CSC_COEFF8:
+ case V_BLEND_IN2CSC_COEFF0:
+ case V_BLEND_IN2CSC_COEFF1:
+ case V_BLEND_IN2CSC_COEFF2:
+ case V_BLEND_IN2CSC_COEFF3:
+ case V_BLEND_IN2CSC_COEFF4:
+ case V_BLEND_IN2CSC_COEFF5:
+ case V_BLEND_IN2CSC_COEFF6:
+ case V_BLEND_IN2CSC_COEFF7:
+ case V_BLEND_IN2CSC_COEFF8:
+ s->vblend_registers[offset] = value & 0x0000FFFF;
+ break;
+ case V_BLEND_LUMA_IN1CSC_OFFSET:
+ case V_BLEND_CR_IN1CSC_OFFSET:
+ case V_BLEND_CB_IN1CSC_OFFSET:
+ case V_BLEND_LUMA_IN2CSC_OFFSET:
+ case V_BLEND_CR_IN2CSC_OFFSET:
+ case V_BLEND_CB_IN2CSC_OFFSET:
+ case V_BLEND_LUMA_OUTCSC_OFFSET:
+ case V_BLEND_CR_OUTCSC_OFFSET:
+ case V_BLEND_CB_OUTCSC_OFFSET:
+ s->vblend_registers[offset] = value & 0x3FFF7FFF;
+ break;
+ case V_BLEND_CHROMA_KEY_ENABLE:
+ s->vblend_registers[offset] = value & 0x00000003;
+ break;
+ case V_BLEND_CHROMA_KEY_COMP1:
+ case V_BLEND_CHROMA_KEY_COMP2:
+ case V_BLEND_CHROMA_KEY_COMP3:
+ s->vblend_registers[offset] = value & 0x0FFF0FFF;
+ break;
+ default:
+ s->vblend_registers[offset] = value;
+ break;
+ }
+}
+
+static uint64_t xilinx_dp_vblend_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ uint32_t ret;
+
+ offset = offset >> 2;
+
+ ret = s->vblend_registers[offset];
+ DPRINTF("vblend: read @%" PRIx64 " = 0x%8.8X\n", offset << 2, ret);
+ return ret;
+}
+
+static const MemoryRegionOps vblend_ops = {
+ .read = xilinx_dp_vblend_read,
+ .write = xilinx_dp_vblend_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+/*
+ * This is to handle Read/Write to the Audio Video buffer manager.
+ */
+static void xilinx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ case AV_BUF_FORMAT:
+ s->avbufm_registers[offset] = value & 0x00000FFF;
+ xilinx_dp_change_graphic_fmt(s);
+ break;
+ case AV_CHBUF0:
+ case AV_CHBUF1:
+ case AV_CHBUF2:
+ case AV_CHBUF3:
+ case AV_CHBUF4:
+ case AV_CHBUF5:
+ s->avbufm_registers[offset] = value & 0x0000007F;
+ break;
+ case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
+ s->avbufm_registers[offset] = value & 0x0000007F;
+ break;
+ case AV_BUF_DITHER_CONFIG:
+ s->avbufm_registers[offset] = value & 0x000007FF;
+ break;
+ case AV_BUF_DITHER_CONFIG_MAX:
+ case AV_BUF_DITHER_CONFIG_MIN:
+ s->avbufm_registers[offset] = value & 0x00000FFF;
+ break;
+ case AV_BUF_PATTERN_GEN_SELECT:
+ s->avbufm_registers[offset] = value & 0xFFFFFF03;
+ break;
+ case AV_BUF_AUD_VID_CLK_SOURCE:
+ s->avbufm_registers[offset] = value & 0x00000007;
+ break;
+ case AV_BUF_SRST_REG:
+ s->avbufm_registers[offset] = value & 0x00000002;
+ break;
+ case AV_BUF_AUDIO_CH_CONFIG:
+ s->avbufm_registers[offset] = value & 0x00000003;
+ break;
+ case AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR:
+ case AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR:
+ case AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR:
+ case AV_BUF_VIDEO_COMP0_SCALE_FACTOR:
+ case AV_BUF_VIDEO_COMP1_SCALE_FACTOR:
+ case AV_BUF_VIDEO_COMP2_SCALE_FACTOR:
+ s->avbufm_registers[offset] = value & 0x0000FFFF;
+ break;
+ case AV_BUF_LIVE_VIDEO_COMP0_SF:
+ case AV_BUF_LIVE_VIDEO_COMP1_SF:
+ case AV_BUF_LIVE_VIDEO_COMP2_SF:
+ case AV_BUF_LIVE_VID_CONFIG:
+ case AV_BUF_LIVE_GFX_COMP0_SF:
+ case AV_BUF_LIVE_GFX_COMP1_SF:
+ case AV_BUF_LIVE_GFX_COMP2_SF:
+ case AV_BUF_LIVE_GFX_CONFIG:
+ case AV_BUF_NON_LIVE_LATENCY:
+ case AV_BUF_STC_CONTROL:
+ case AV_BUF_STC_INIT_VALUE0:
+ case AV_BUF_STC_INIT_VALUE1:
+ case AV_BUF_STC_ADJ:
+ case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
+ case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
+ case AV_BUF_STC_EXT_VSYNC_TS_REG0:
+ case AV_BUF_STC_EXT_VSYNC_TS_REG1:
+ case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
+ case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
+ case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
+ case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
+ case AV_BUF_STC_SNAPSHOT0:
+ case AV_BUF_STC_SNAPSHOT1:
+ case AV_BUF_HCOUNT_VCOUNT_INT0:
+ case AV_BUF_HCOUNT_VCOUNT_INT1:
+ /*
+ * Non implemented.
+ */
+ break;
+ default:
+ s->avbufm_registers[offset] = value;
+ break;
+ }
+}
+
+static uint64_t xilinx_dp_avbufm_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ offset = offset >> 2;
+
+ return s->avbufm_registers[offset];
+}
+
+static const MemoryRegionOps avbufm_ops = {
+ .read = xilinx_dp_avbufm_read,
+ .write = xilinx_dp_avbufm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+/*
+ * This is a global alpha blending using pixman.
+ * Both graphic and video planes are multiplied with the global alpha
+ * coefficient and added.
+ */
+static inline void xilinx_dp_blend_surface(XilinxDPState *s)
+{
+ pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1.0) };
+ pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1.0) };
+
+ if ((surface_width(s->g_plane.surface)
+ != surface_width(s->v_plane.surface)) ||
+ (surface_height(s->g_plane.surface)
+ != surface_height(s->v_plane.surface))) {
+ return;
+ }
+
+ alpha1[2] = pixman_double_to_fixed((double)(xilinx_dp_global_alpha_value(s))
+ / 256.0);
+ alpha2[2] = pixman_double_to_fixed((255.0
+ - (double)xilinx_dp_global_alpha_value(s))
+ / 256.0);
+
+ pixman_image_set_filter(s->g_plane.surface->image,
+ PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
+ pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
+ s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
+ surface_width(s->g_plane.surface),
+ surface_height(s->g_plane.surface));
+ pixman_image_set_filter(s->v_plane.surface->image,
+ PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
+ pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
+ s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
+ surface_width(s->g_plane.surface),
+ surface_height(s->g_plane.surface));
+}
+
+static void xilinx_dp_update_display(void *opaque)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ if (DEBUG_DP) {
+ int64_t last_time = 0;
+ int64_t frame = 0;
+ int64_t time = get_clock();
+ int64_t fps;
+
+ if (last_time == 0) {
+ last_time = get_clock();
+ }
+ frame++;
+ if (last_time + 1000000000 < time) {
+ fps = (1000000000.0 * frame) / (time - last_time);
+ last_time = time;
+ frame = 0;
+ DPRINTF("xilinx_dp: %ldfps\n", fps);
+ }
+ }
+
+
+ if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
+ return;
+ }
+
+ s->core_registers[DP_INT_STATUS] |= (1 << 13);
+ xilinx_dp_update_irq(s);
+
+ /*
+ * Trigger the DMA channel.
+ */
+ if (!xilinx_dpdma_start_operation(s->dpdma, 3, false)) {
+ /*
+ * An error occured don't do anything with the data..
+ * Trigger an underflow interrupt.
+ */
+ s->core_registers[DP_INT_STATUS] |= (1 << 21);
+ xilinx_dp_update_irq(s);
+ return;
+ }
+
+ if (xilinx_dp_global_alpha_enabled(s)) {
+ if (!xilinx_dpdma_start_operation(s->dpdma, 0, false)) {
+ s->core_registers[DP_INT_STATUS] |= (1 << 21);
+ xilinx_dp_update_irq(s);
+ return;
+ }
+ xilinx_dp_blend_surface(s);
+ }
+
+ /*
+ * XXX: We might want to update only what changed.
+ */
+ dpy_gfx_update(s->console, 0, 0, surface_width(s->g_plane.surface),
+ surface_height(s->g_plane.surface));
+}
+
+static void xilinx_dp_invalidate_display(void *opaque)
+{
+
+}
+
+static const GraphicHwOps xilinx_dp_gfx_ops = {
+ .invalidate = xilinx_dp_invalidate_display,
+ .gfx_update = xilinx_dp_update_display,
+};
+
+static void xilinx_dp_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ XilinxDPState *s = XILINX_DP(obj);
+
+ memory_region_init(&s->container, obj, TYPE_XILINX_DP, 0xC050);
+
+ memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XILINX_DP
+ ".core", 0x3AF);
+ memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
+
+ memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XILINX_DP
+ ".v_blend", 0x1DF);
+ memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
+
+ memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XILINX_DP
+ ".av_buffer_manager", 0x238);
+ memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
+ memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XILINX_DP
+ ".audio", sizeof(s->audio_registers));
+ memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
+ sysbus_init_mmio(sbd, &s->container);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ object_property_add_link(obj, "dpdma", TYPE_XILINX_DPDMA,
+ (Object **) &s->dpdma,
+ xilinx_dp_set_dpdma,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ &error_abort);
+
+ s->byte_left = 0;
+
+ /*
+ * Initialize AUX Bus.
+ */
+ s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
+
+ /*
+ * Initialize DPCD and EDID..
+ */
+ s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
+ s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
+ i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
+}
+
+static void xilinx_dp_realize(DeviceState *dev, Error **errp)
+{
+ XilinxDPState *s = XILINX_DP(dev);
+ DisplaySurface *surface;
+
+ s->console = graphic_console_init(dev, 0, &xilinx_dp_gfx_ops, s);
+ surface = qemu_console_surface(s->console);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 3, surface_data(surface));
+ fifo8_create(&s->rx_fifo, 16);
+ fifo8_create(&s->tx_fifo, 16);
+
+ /* Audio */
+ struct audsettings as;
+ as.freq = 44100;
+ as.nchannels = 2;
+ as.fmt = AUD_FMT_S16;
+ as.endianness = 0;
+
+ AUD_register_card("xilinx_dp.audio", &s->aud_card);
+
+ s->amixer_output_stream = AUD_open_out(&s->aud_card,
+ s->amixer_output_stream,
+ "xilinx_dp.audio.out",
+ s,
+ xilinx_dp_audio_callback,
+ &as);
+ AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
+ xilinx_dp_audio_activate(s);
+}
+
+static void xilinx_dp_reset(DeviceState *dev)
+{
+ XilinxDPState *s = XILINX_DP(dev);
+
+ /*
+ * Reset the Display Port registers.
+ */
+ memset(s->core_registers, 0, sizeof(s->core_registers));
+ s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
+ s->core_registers[DP_CORE_ID] = 0x01020000;
+ s->core_registers[DP_REPLY_STATUS] = 0x00000010;
+ s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
+ s->core_registers[DP_INIT_WAIT] = 0x00000020;
+ s->core_registers[DP_PHY_RESET] = 0x00010003;
+ s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
+
+ s->core_registers[DP_PHY_STATUS] = 0x00000043;
+ s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
+
+ /*
+ * Video Blender register reset.
+ */
+ s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF0] = 0x00001000;
+ s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF4] = 0x00001000;
+ s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF8] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN1CSC_COEFF0] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN1CSC_COEFF4] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN1CSC_COEFF8] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN2CSC_COEFF0] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN2CSC_COEFF4] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN2CSC_COEFF8] = 0x00001000;
+
+ /*
+ * Audio Video Buffer Manager register reset.
+ */
+ s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
+ s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
+ s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
+ s->avbufm_registers[AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_VIDEO_COMP0_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_VIDEO_COMP1_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_VIDEO_COMP2_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP0_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP1_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP2_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_GFX_COMP0_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_GFX_COMP1_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_GFX_COMP2_SF] = 0x00010101;
+
+ /*
+ * Audio register reset.
+ */
+ memset(s->audio_registers, 0, sizeof(s->audio_registers));
+
+ xilinx_dp_aux_clear_rx_fifo(s);
+ xilinx_dp_change_graphic_fmt(s);
+}
+
+static void xilinx_dp_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = xilinx_dp_realize;
+ dc->vmsd = &vmstate_dp;
+ dc->reset = xilinx_dp_reset;
+}
+
+static const TypeInfo xilinx_dp_info = {
+ .name = TYPE_XILINX_DP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XilinxDPState),
+ .instance_init = xilinx_dp_init,
+ .class_init = xilinx_dp_class_init,
+};
+
+static void xilinx_dp_register_types(void)
+{
+ type_register_static(&xilinx_dp_info);
+}
+
+type_init(xilinx_dp_register_types)
diff --git a/hw/display/xilinx_dp.h b/hw/display/xilinx_dp.h
new file mode 100644
index 0000000..44fdefd
--- /dev/null
+++ b/hw/display/xilinx_dp.h
@@ -0,0 +1,129 @@
+/*
+ * xilinx_dp.h
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "hw/sysbus.h"
+#include "ui/console.h"
+#include "hw/aux.h"
+#include "hw/i2c/i2c.h"
+#include "hw/display/dpcd.h"
+#include "hw/i2c/i2c-ddc.h"
+#include "qemu/fifo8.h"
+#include "hw/dma/xilinx_dpdma.h"
+#include "audio/audio.h"
+
+#ifndef XILINX_DP_H
+#define XILINX_DP_H
+
+#define AUD_CHBUF_MAX_DEPTH 32768
+#define MAX_QEMU_BUFFER_SIZE 4096
+
+struct PixmanPlane {
+ pixman_format_code_t format;
+ DisplaySurface *surface;
+};
+
+struct XilinxDPState {
+ SysBusDevice parent_obj;
+ MemoryRegion container;
+
+ /*
+ * Registers for the Core.
+ */
+ uint32_t core_registers[0x3AF >> 2];
+ MemoryRegion core_iomem;
+
+ /*
+ * Registers for Audio Video Buffer Manager.
+ */
+ uint32_t avbufm_registers[0x238 >> 2];
+ MemoryRegion avbufm_iomem;
+
+ /*
+ * Register for Video Blender.
+ */
+ uint32_t vblend_registers[0x1DF >> 2];
+ MemoryRegion vblend_iomem;
+
+ /*
+ * Registers for Audio.
+ */
+ uint32_t audio_registers[0x50 >> 2];
+ MemoryRegion audio_iomem;
+
+ QemuConsole *console;
+
+ /*
+ * This is the planes used to display in console. When the blending is
+ * enabled bout_plane is displayed in console else it's g_plane.
+ */
+ struct PixmanPlane g_plane;
+ struct PixmanPlane v_plane;
+ struct PixmanPlane bout_plane;
+
+ /*
+ * Audio related.
+ */
+ QEMUSoundCard aud_card;
+ SWVoiceOut *amixer_output_stream;
+ int16_t audio_buffer_0[AUD_CHBUF_MAX_DEPTH];
+ int16_t audio_buffer_1[AUD_CHBUF_MAX_DEPTH];
+ size_t audio_data_available[2];
+ int64_t temp_buffer[AUD_CHBUF_MAX_DEPTH];
+ int16_t out_buffer[AUD_CHBUF_MAX_DEPTH];
+ size_t byte_left; /* byte available in out_buffer. */
+ size_t data_ptr; /* next byte to be sent to QEMU. */
+
+ /*
+ * Associated DPDMA controller.
+ */
+ XilinxDPDMAState *dpdma;
+
+ /*
+ * IRQ.
+ */
+ qemu_irq irq;
+
+ /*
+ * AUX bus.
+ */
+ AUXBus *aux_bus;
+
+ Fifo8 rx_fifo;
+ Fifo8 tx_fifo;
+
+ uint32_t last_request;
+
+ /*
+ * XXX: This should be in an other module.
+ */
+ DPCDState *dpcd;
+ I2CDDCState *edid;
+};
+
+typedef struct XilinxDPState XilinxDPState;
+
+#define TYPE_XILINX_DP "xlnx.v-dp"
+#define XILINX_DP(obj) OBJECT_CHECK(XilinxDPState, (obj), TYPE_XILINX_DP)
+
+#endif /* !XILINX_DP_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH V2 7/7] arm: xlnx-zynqmp: Add DisplayPort and DPDMA.
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
` (5 preceding siblings ...)
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 6/7] Introduce xilinx dp fred.konrad
@ 2015-06-15 15:15 ` fred.konrad
2015-06-24 8:23 ` Peter Crosthwaite
6 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-06-15 15:15 UTC (permalink / raw)
To: qemu-devel
Cc: peter.maydell, peter.crosthwaite, hyunk, mark.burton,
guillaume.delbergue, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This adds the DP and the DPDMA to the Zynq MP.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 4 ++++
2 files changed, 24 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 6b01965..c29046a 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -28,6 +28,12 @@
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
+#define DP_ADDR 0xfd4a0000
+#define DP_IRQ 113
+
+#define DPDMA_ADDR 0xfd4c0000
+#define DPDMA_IRQ 116
+
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
};
@@ -83,6 +89,11 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
}
+
+ object_initialize(&s->dp, sizeof(s->dp), TYPE_XILINX_DP);
+ qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
+ object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XILINX_DPDMA);
+ qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -186,6 +197,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
gic_spi[uart_intr[i]]);
}
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
+ object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
+ object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
+ object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
+ &error_abort);
}
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 79c2b0b..66ec010 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,8 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/dma/xilinx_dpdma.h"
+#include "hw/display/xilinx_dp.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -52,6 +54,8 @@ typedef struct XlnxZynqMPState {
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+ XilinxDPState dp;
+ XilinxDPDMAState dpdma;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus.
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus fred.konrad
@ 2015-06-24 6:21 ` Peter Crosthwaite
2015-07-06 16:27 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 6:21 UTC (permalink / raw)
To: Fréderic Konrad, Markus Armbruster
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This introduces a new bus: aux-bus.
>
> It contains an address space for aux slaves devices and a bridge to an I2C bus
> for I2C through AUX transactions.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/misc/Makefile.objs | 1 +
> hw/misc/aux.c | 411 ++++++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/aux.h | 116 ++++++++++++++
> 3 files changed, 528 insertions(+)
> create mode 100644 hw/misc/aux.c
> create mode 100644 include/hw/aux.h
>
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index 4aa76ff..11a721f 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -40,3 +40,4 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
>
> obj-$(CONFIG_PVPANIC) += pvpanic.o
> obj-$(CONFIG_EDU) += edu.o
> +obj-$(CONFIG_XLNX_ZYNQMP) += aux.o
Aux is not ZYNQ specific, it should have its own config that is just
set by the aarch64 defconfig.
> diff --git a/hw/misc/aux.c b/hw/misc/aux.c
> new file mode 100644
> index 0000000..b72608e
> --- /dev/null
> +++ b/hw/misc/aux.c
> @@ -0,0 +1,411 @@
> +/*
> + * aux.c
> + *
> + * Copyright 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +/*
> + * This is an implementation of the AUX bus for VESA Display Port v1.1a.
> + */
> +
> +#include "hw/aux.h"
> +#include "hw/i2c/i2c.h"
> +#include "monitor/monitor.h"
> +
> +/* #define DEBUG_AUX */
Just drop the commented out define.
> +
> +#ifdef DEBUG_AUX
> +#define DPRINTF(fmt, ...)\
> +do { printf("aux: " fmt , ## __VA_ARGS__); } while (0)
Use a regular if for conditional debug prinfery.
Also do not use printf, use qemu_log.
> +#else
> +#define DPRINTF(fmt, ...)do {} while (0)
> +#endif
> +
> +#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
> +#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
> +
> +typedef struct AUXTOI2CState AUXTOI2CState;
> +
> +struct AUXBus {
/*< private >*/
> + BusState qbus;
/*< public > */
> + AUXSlave *current_dev;
> + AUXSlave *dev;
> + uint32_t last_i2c_address;
> + aux_command last_transaction;
> +
> + AUXTOI2CState *bridge;
> +
> + MemoryRegion *aux_io;
> + AddressSpace aux_addr_space;
> +};
Modern QOM conventions require the state struct to be in a header.
This allows for embedding the device its containers.
> +
> +static Property aux_props[] = {
> + DEFINE_PROP_UINT64("address", struct AUXSlave, address, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +#define TYPE_AUX_BUS "aux-bus"
> +#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
> +
> +static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
> +
> +static void aux_bus_class_init(ObjectClass *klass, void *data)
> +{
> + /*
> + * AUXSlave has an mmio so we need to change the way we print information
MMIO
> + * in monitor.
> + */
Can you move the comment below the declaration?
> + BusClass *k = BUS_CLASS(klass);
blank line.
> + k->print_dev = aux_slave_dev_print;
> +}
> +
> +static const TypeInfo aux_bus_info = {
> + .name = TYPE_AUX_BUS,
> + .parent = TYPE_BUS,
> + .instance_size = sizeof(AUXBus),
> + .class_init = aux_bus_class_init
> +};
> +
> +AUXBus *aux_init_bus(DeviceState *parent, const char *name)
> +{
> + AUXBus *bus;
> +
> + bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
> +
> + /*
> + * Create the bridge.
> + */
Code is self documenting, comment unneeded.
> + bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
> +
> + /*
> + * Memory related.
> + */
Make a one-line comment.
> + bus->aux_io = g_malloc(sizeof(*bus->aux_io));
> + memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
> + address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
> + return bus;
> +}
> +
> +static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev)
> +{
> + memory_region_add_subregion(bus->aux_io, dev->address, dev->mmio);
> +}
> +
> +void aux_set_slave_address(AUXSlave *dev, uint32_t address)
> +{
> + qdev_prop_set_uint64(DEVICE(dev), "address", address);
> +}
> +
Do these two need to be separate? Can you just pass the address to
aux_bus_map_device and remove the .address field from the bus?
> +static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
> +{
> + return (dev == DEVICE(bus->bridge));
> +}
> +
> +/*
> + * Make a native request on the AUX bus.
> + */
> +static aux_reply aux_native_request(AUXBus *bus, aux_command cmd,
> + uint32_t address, uint8_t len,
> + uint8_t *data)
> +{
> + /*
> + * Transactions on aux address map are 1bytes len time.
> + */
> + aux_reply ret = AUX_NACK;
> + size_t i;
> +
> + switch (cmd) {
> + case READ_AUX:
> + for (i = 0; i < len; i++) {
> + if (!address_space_rw(&bus->aux_addr_space, address++,
> + MEMTXATTRS_UNSPECIFIED, data++, 1, false)) {
address_space_read. Although ...
> + ret = AUX_I2C_ACK;
> + } else {
> + ret = AUX_NACK;
> + break;
> + }
> + }
> + break;
> + case WRITE_AUX:
You can remove the code duplication with:
switch(cmd) {
case (WRITE_AUX):
is_write = true;
/* fallthrough */
case (READ_AUX):
for(...) {
address_space_rw(..., is_write);
> + for (i = 0; i < len; i++) {
> + if (!address_space_rw(&bus->aux_addr_space, address++,
> + MEMTXATTRS_UNSPECIFIED, data++, 1, true)) {
> + ret = AUX_I2C_ACK;
> + } else {
> + ret = AUX_NACK;
> + break;
> + }
> + }
> + break;
> + default:
> + abort();
g_assert_not_reached
> + break;
> + }
> +
> + return ret;
> +}
> +
> +aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
> + uint8_t len, uint8_t *data)
> +{
> + DPRINTF("request at address 0x%5.5X, command %u, len %u\n", address, cmd,
> + len);
PRIx32
> +
> + int temp;
> + aux_reply ret = AUX_NACK;
> + I2CBus *i2c_bus = aux_get_i2c_bus(bus);
> +
The DRPINTF before the declarations is a C99 mixed code and decls
which is discouraged. Do the DPRINTF after the decls.
> + switch (cmd) {
> + /*
> + * Forward the request on the AUX bus..
> + */
> + case WRITE_AUX:
> + case READ_AUX:
> + ret = aux_native_request(bus, cmd, address, len, data);
> + break;
indentation.
> + /*
> + * Classic I2C transactions..
> + */
> + case READ_I2C:
> + if (i2c_bus_busy(i2c_bus)) {
> + i2c_end_transfer(i2c_bus);
> + }
> +
> + if (i2c_start_transfer(i2c_bus, address, 1)) {
> + ret = AUX_I2C_NACK;
> + break;
> + }
> +
> + while (len > 0) {
> + temp = i2c_recv(i2c_bus);
> +
> + if (temp < 0) {
> + ret = AUX_I2C_NACK;
This nack ...
> + i2c_end_transfer(i2c_bus);
> + break;
> + }
> +
> + *data++ = temp;
> + len--;
> + }
> + i2c_end_transfer(i2c_bus);
> + ret = AUX_I2C_ACK;
... will get overridden by this ack.
> + break;
Indentation.
> + case WRITE_I2C:
> + if (i2c_bus_busy(i2c_bus)) {
> + i2c_end_transfer(i2c_bus);
> + }
> +
> + if (i2c_start_transfer(i2c_bus, address, 0)) {
> + ret = AUX_I2C_NACK;
> + break;
> + }
> +
> + while (len > 0) {
> + if (!i2c_send(i2c_bus, *data++)) {
> + ret = AUX_I2C_NACK;
> + i2c_end_transfer(i2c_bus);
> + break;
> + }
> + len--;
> + }
> + i2c_end_transfer(i2c_bus);
> + ret = AUX_I2C_ACK;
same. You might be needing a goto from those in-the-loop nacks, but
the shortest way I can think of is:
ret = AUX_I2C_ACK;
while (...) {
if (!i2c_send) {
ret = NACK;
break;
}
len--;
}
i2c_end_transfer(...).
> + break;
> + /*
> + * I2C MOT transactions.
> + *
> + * Here we send a start when:
> + * - We didn't start transaction yet.
> + * - We had a READ and we do a WRITE.
> + * - We change the address.
"changed"
> + */
> + case WRITE_I2C_MOT:
> + if (!i2c_bus_busy(i2c_bus)) {
> + /*
> + * No transactions started..
> + */
> + if (i2c_start_transfer(i2c_bus, address, 0)) {
> + ret = AUX_I2C_NACK;
> + break;
> + }
> + } else if ((address != bus->last_i2c_address) ||
> + (bus->last_transaction == READ_I2C_MOT)) {
> + /*
> + * Transaction started but we need to restart..
> + */
> + i2c_end_transfer(i2c_bus);
> + if (i2c_start_transfer(i2c_bus, address, 0)) {
> + ret = AUX_I2C_NACK;
> + break;
> + }
> + }
> +
> + while (len > 0) {
> + if (!i2c_send(i2c_bus, *data++)) {
> + ret = AUX_I2C_NACK;
> + i2c_end_transfer(i2c_bus);
> + break;
> + }
> + len--;
> + }
> + bus->last_transaction = WRITE_I2C_MOT;
> + bus->last_i2c_address = address;
> + ret = AUX_I2C_ACK;
> + break;
> + case READ_I2C_MOT:
This read vs write code is very similar from one to the other. It can
be factored out as such:
case WRITE_I2C_MOT:
is_write = true;
/*fallthrough */
case READ_I2C_MOT:
> + if (!i2c_bus_busy(i2c_bus)) {
> + /*
> + * No transactions started..
> + */
> + if (i2c_start_transfer(i2c_bus, address, 0)) {
> + ret = AUX_I2C_NACK;
> + break;
> + }
> + } else if (address != bus->last_i2c_address) {
The restart condition here is different to write. Mainly, you do not
restart on a change from write to read. Perhaps worth a comment, or
list-comment the read restart conditions like you did for write.
> + /*
> + * Transaction started but we need to restart..
> + */
> + i2c_end_transfer(i2c_bus);
> + if (i2c_start_transfer(i2c_bus, address, 0)) {
> + ret = AUX_I2C_NACK;
> + break;
> + }
> + }
> +
> + while (len > 0) {
if (is_write) {
i2c_err = i2c_send(...) ? - 1 : 0;
} else {
> + temp = i2c_recv(i2c_bus);
i2c_err = temp < 0;
}
> +
> + if (temp < 0) {
> + ret = AUX_I2C_NACK;
> + i2c_end_transfer(i2c_bus);
> + break;
> + }
> +
if (is_write) {
> + *data++ = temp;
}
> + len--;
> + }
> + bus->last_transaction = READ_I2C_MOT;
> + bus->last_i2c_address = address;
> + ret = AUX_I2C_ACK;
> + break;
> + default:
> + DPRINTF("Not implemented!\n");
> + ret = AUX_NACK;
> + break;
> + }
> +
> + DPRINTF("reply: %u\n", ret);
> + return ret;
> +}
> +
> +/*
> + * AUX to I2C bridge.
> + */
> +struct AUXTOI2CState {
/*< private >*/
> + DeviceState parent_obj;
/*< public >*/
> + I2CBus *i2c_bus;
> +};
Will need to move to the header.
> +
> +I2CBus *aux_get_i2c_bus(AUXBus *bus)
> +{
> + return bus->bridge->i2c_bus;
> +}
> +
> +static void aux_bridge_init(Object *obj)
> +{
> + AUXTOI2CState *s = AUXTOI2C(obj);
> + /*
> + * Create the I2C Bus.
> + */
self documenting.
> + s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
> +}
> +
> +static const TypeInfo aux_to_i2c_type_info = {
> + .name = TYPE_AUXTOI2C,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(AUXTOI2CState),
> + .instance_init = aux_bridge_init
> +};
> +
> +/*
> + * AUX Slave.
> + */
> +static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
> +{
> + AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
> + hwaddr size;
> + AUXSlave *s;
> +
> + /*
> + * Don't print anything if the device is I2C "bridge".
> + */
> + if (aux_bus_is_bridge(bus, dev)) {
> + return;
> + }
> +
> + s = AUX_SLAVE(dev);
> +
> + size = memory_region_size(s->mmio);
> + monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
> + indent, "", s->address, size);
> +}
> +
> +DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr)
> +{
> + DeviceState *dev;
> +
> + dev = qdev_create(&bus->qbus, name);
> + qdev_prop_set_uint64(dev, "address", addr);
> + qdev_init_nofail(dev);
> + aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev));
> + return dev;
> +}
qdev_create helpers are depracated. The code should just be inlined
into the creating machine models or container devs.
> +
> +void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
> +{
> + aux_slave->mmio = mmio;
Should this assert on repeated calls?
> +}
> +
> +static void aux_slave_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *k = DEVICE_CLASS(klass);
> + set_bit(DEVICE_CATEGORY_MISC, k->categories);
> + k->bus_type = TYPE_AUX_BUS;
> + k->props = aux_props;
> +}
> +
> +static const TypeInfo aux_slave_type_info = {
> + .name = TYPE_AUX_SLAVE,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(AUXSlave),
> + .abstract = true,
> + .class_init = aux_slave_class_init,
> +};
> +
> +static void aux_slave_register_types(void)
> +{
> + type_register_static(&aux_bus_info);
> + type_register_static(&aux_slave_type_info);
> + type_register_static(&aux_to_i2c_type_info);
> +}
> +
> +type_init(aux_slave_register_types)
> diff --git a/include/hw/aux.h b/include/hw/aux.h
> new file mode 100644
> index 0000000..7b29ee1
> --- /dev/null
> +++ b/include/hw/aux.h
> @@ -0,0 +1,116 @@
> +/*
> + * aux.h
> + *
> + * Copyright (C)2014 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef QEMU_AUX_H
> +#define QEMU_AUX_H
> +
> +#include "hw/qdev.h"
> +
> +enum aux_command {
AUXCommand.
> + WRITE_I2C = 0,
> + READ_I2C = 1,
> + WRITE_I2C_STATUS = 2,
> + WRITE_I2C_MOT = 4,
> + READ_I2C_MOT = 5,
> + WRITE_AUX = 8,
> + READ_AUX = 9
> +};
> +
> +enum aux_reply {
AUXReply.
> + AUX_I2C_ACK = 0,
> + AUX_NACK = 1,
> + AUX_DEFER = 2,
> + AUX_I2C_NACK = 4,
> + AUX_I2C_DEFER = 8
> +};
> +
> +typedef struct AUXBus AUXBus;
> +typedef struct AUXSlave AUXSlave;
> +typedef enum aux_command aux_command;
> +typedef enum aux_reply aux_reply;
> +
> +#define TYPE_AUX_SLAVE "aux-slave"
> +#define AUX_SLAVE(obj) \
> + OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
> +
> +struct AUXSlave {
> + /* < private > */
> + DeviceState parent_obj;
> +
/*< public >*/
> + /* address of the device on the aux bus. */
> + hwaddr address;
Can this be encapsulated by mmio. There is memory_region_get_addr().
> + /* memory region associated. */
> + MemoryRegion *mmio;
> +};
> +
> +/*
> + * \func aux_init_bus
> + * \brief Init an aux bus.
> + * \param parent The device where this bus is located.
> + * \param name The name of the bus.
> + * \return The new aux bus.
Please use the /** @ style documentation.
Regards,
Peter
> + */
> +AUXBus *aux_init_bus(DeviceState *parent, const char *name);
> +
> +/*
> + * \func aux_slave_set_address
> + * \brief Set the address of the slave on the aux bus.
> + * \param dev The aux slave device.
> + * \param address The address to give to the slave.
> + */
> +void aux_set_slave_address(AUXSlave *dev, uint32_t address);
> +
> +/*
> + * \func aux_request
> + * \brief Make a request on the bus.
> + * \param bus Ths bus where the request happen.
> + * \param cmd The command requested.
> + * \param address The 20bits address of the slave.
> + * \param len The length of the read or write.
> + * \param data The data array which will be filled or read during transfer.
> + * \return Return the reply of the request.
> + */
> +aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
> + uint8_t len, uint8_t *data);
> +
> +/*
> + * \func aux_get_i2c_bus
> + * \brief Get the i2c bus for I2C over AUX command.
> + * \param bus The aux bus.
> + * \return Return the i2c bus associated.
> + */
> +I2CBus *aux_get_i2c_bus(AUXBus *bus);
> +
> +/*
> + * \func aux_init_mmio
> + * \brief Init an mmio for an aux slave, must be called after
> + * memory_region_init_io.
> + * \param aux_slave The aux slave.
> + * \param mmio The mmio to be registered.
> + */
> +void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
> +
> +DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
> +
> +#endif /* !QEMU_AUX_H */
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write.
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write fred.konrad
@ 2015-06-24 6:35 ` Peter Crosthwaite
2015-07-06 16:28 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 6:35 UTC (permalink / raw)
To: Fréderic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This does a write to every slaves when the I2C bus get a write to address 0.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/i2c/core.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> index 5a64026..db1cbdd 100644
> --- a/hw/i2c/core.c
> +++ b/hw/i2c/core.c
> @@ -15,6 +15,7 @@ struct I2CBus
> I2CSlave *current_dev;
> I2CSlave *dev;
> uint8_t saved_address;
> + bool broadcast;
> };
>
> static Property i2c_props[] = {
> @@ -67,6 +68,8 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
>
> bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
> vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
> +
> + bus->broadcast = false;
0 initialiser should not be needed for new QOM object.
> return bus;
> }
>
> @@ -89,6 +92,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
> I2CSlave *slave = NULL;
> I2CSlaveClass *sc;
>
> + if (address == 0x00) {
> + /*
> + * This is a broadcast.
> + */
One line comment.
> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> + I2CSlave *dev = I2C_SLAVE(kid->child);
> + sc = I2C_SLAVE_GET_CLASS(dev);
> + bus->broadcast = true;
Move outside loop.
> + if (sc->event) {
> + sc->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
> + }
> + }
> + return 0;
> + }
> +
> QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> DeviceState *qdev = kid->child;
> I2CSlave *candidate = I2C_SLAVE(qdev);
> @@ -114,9 +132,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
>
> void i2c_end_transfer(I2CBus *bus)
> {
> + BusChild *kid;
> I2CSlave *dev = bus->current_dev;
> I2CSlaveClass *sc;
>
> + if (bus->broadcast) {
> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> + I2CSlave *dev = I2C_SLAVE(kid->child);
> + sc = I2C_SLAVE_GET_CLASS(dev);
> + if (sc->event) {
> + sc->event(dev, I2C_FINISH);
> + }
> + }
> + bus->broadcast = false;
> + }
> +
> if (!dev) {
> return;
> }
> @@ -131,8 +161,22 @@ void i2c_end_transfer(I2CBus *bus)
>
> int i2c_send(I2CBus *bus, uint8_t data)
> {
> + BusChild *kid;
> I2CSlave *dev = bus->current_dev;
> I2CSlaveClass *sc;
> + int ret = 0;
> +
> + if (bus->broadcast) {
> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> + I2CSlave *dev = I2C_SLAVE(kid->child);
> + sc = I2C_SLAVE_GET_CLASS(dev);
> + bus->broadcast = true;
> + if (sc->send) {
> + ret |= sc->send(dev, data);
> + }
> + }
Still not sure about the duped core functionality of each of these
APIs. That is, the same code is needed in both a looped form and a 1
form. Can this be solved by listifying current_dev? That is, ->current
dev is turned into a list which in the normal case will be populated
with 1 element by start_transfer() for the current dev. In the
broadcast case, all qbus.children are added to the list. The broadcast
bool is then removed. start() send() and end_transfer() then just loop
through the list unconditionally.
Regards,
Peter
> + return ret;
> + }
>
> if (!dev) {
> return -1;
> @@ -151,7 +195,7 @@ int i2c_recv(I2CBus *bus)
> I2CSlave *dev = bus->current_dev;
> I2CSlaveClass *sc;
>
> - if (!dev) {
> + if ((!dev) || (bus->broadcast)) {
> return -1;
> }
>
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 3/7] introduce dpcd module.
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 3/7] introduce dpcd module fred.konrad
@ 2015-06-24 6:44 ` Peter Crosthwaite
2015-07-06 16:30 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 6:44 UTC (permalink / raw)
To: Fréderic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This introduces a DPCD modules. It wires on a aux-bus and can be accessed by
"module"
> driver to get lane-speed, etc.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/display/Makefile.objs | 1 +
> hw/display/dpcd.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
> hw/display/dpcd.h | 72 ++++++++++++++++++++++
> 3 files changed, 224 insertions(+)
> create mode 100644 hw/display/dpcd.c
> create mode 100644 hw/display/dpcd.h
>
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index 61c80f3..f75094f 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -36,3 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
>
> obj-$(CONFIG_VIRTIO) += virtio-gpu.o
> +obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o
Make a DPCD config and add to aarch64 defconfig.
> diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
> new file mode 100644
> index 0000000..b4eeea7
> --- /dev/null
> +++ b/hw/display/dpcd.c
> @@ -0,0 +1,151 @@
> +/*
> + * dpcd.c
> + *
> + * Copyright (C)2015 : GreenSocs Ltd
(C) 2015
(missing space)
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +/*
> + * This is a simple AUX slave which emulates a connected screen.
> + */
> +
> +#include "hw/aux.h"
> +#include "dpcd.h"
> +
> +#ifndef DEBUG_DPCD
> +#define DEBUG_DPCD 0
> +#endif
> +
> +#define DPRINTF(fmt, ...) do { \
> + if (DEBUG_DPCD) { \
> + qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
> + } \
> +} while (0);
> +
> +#define DPCD_READABLE_AREA 0x600
> +
> +struct DPCDState {
/*< public >*/
> + AUXSlave parent_obj;
> +
/*< private >*/
> + /*
> + * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
> + */
> + uint8_t dpcd_info[DPCD_READABLE_AREA];
> +
> + MemoryRegion iomem;
> +};
> +
> +static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + uint64_t ret;
make a uint8_t
> + DPCDState *e = DPCD(opaque);
> +
> + if (offset < DPCD_READABLE_AREA) {
> + ret = e->dpcd_info[offset];
> + } else {
> + ret = 0;
> + }
> +
> + DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
to avoid this cast, and just let the implicit cast on the return
handle it for you.
PRIx8
HWADDR_PRIx
> + return ret;
> +}
> +
> +static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
> + unsigned size)
> +{
> + DPCDState *e = DPCD(opaque);
> +
> + DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
> +
PRIx8
HWADDR_PRIx
> + if (offset < DPCD_READABLE_AREA) {
> + e->dpcd_info[offset] = value;
> + }
Should there be a else for a guest error?
> +}
> +
> +static const MemoryRegionOps aux_ops = {
> + .read = dpcd_read,
> + .write = dpcd_write,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> +static void dpcd_reset(DeviceState *dev)
> +{
> + DPCDState *s = DPCD(dev);
blank line.
> + memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
> +
> + s->dpcd_info[0x00] = DPCD_REV_1_0;
> + s->dpcd_info[0x01] = DPCD_5_4GBPS;
> + s->dpcd_info[0x02] = 0x1;
> + s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
> + s->dpcd_info[0x09] = 0xFF;
> +
> + /* CR DONE, CE DONE, SYMBOL LOCKED.. */
> + s->dpcd_info[0x202] = 0x07;
> + /* INTERLANE_ALIGN_DONE.. */
> + s->dpcd_info[0x204] = 0x01;
> + s->dpcd_info[0x205] = 0x01;
Magic numbers for both offsets and fields should be defined.
> +}
> +
> +static void dpcd_init(Object *obj)
> +{
> + DPCDState *s = DPCD(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
> + aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
> +}
> +
> +static const VMStateDescription vmstate_dpcd = {
> + .name = TYPE_DPCD,
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void dpcd_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
blank line.
Regards,
Peter
> + dc->reset = dpcd_reset;
> + dc->vmsd = &vmstate_dpcd;
> +}
> +
> +static const TypeInfo dpcd_info = {
> + .name = TYPE_DPCD,
> + .parent = TYPE_AUX_SLAVE,
> + .instance_size = sizeof(DPCDState),
> + .class_init = dpcd_class_init,
> + .instance_init = dpcd_init,
> +};
> +
> +static void dpcd_register_types(void)
> +{
> + type_register_static(&dpcd_info);
> +}
> +
> +type_init(dpcd_register_types)
> diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
> new file mode 100644
> index 0000000..57c393b
> --- /dev/null
> +++ b/hw/display/dpcd.h
> @@ -0,0 +1,72 @@
> +/*
> + * dpcd.h
> + *
> + * Copyright (C)2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef DPCD_H
> +#define DPCD_H
> +
> +typedef struct DPCDState DPCDState;
> +
> +#define TYPE_DPCD "dpcd"
> +#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
> +
> +/* DCPD Revision. */
> +#define DPCD_REV_1_0 0x10
> +#define DPCD_REV_1_1 0x11
> +
> +/* DCPD Max Link Rate. */
> +#define DPCD_1_62GBPS 0x06
> +#define DPCD_2_7GBPS 0x0A
> +#define DPCD_5_4GBPS 0x14
> +
> +/* DCPD Max down spread. */
> +#define DPCD_UP_TO_0_5 0x01
> +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
> +
> +/* DCPD Downstream port type. */
> +#define DPCD_DISPLAY_PORT 0x00
> +#define DPCD_ANALOG 0x02
> +#define DPCD_DVI_HDMI 0x04
> +#define DPCD_OTHER 0x06
> +
> +/* DPCD Format conversion. */
> +#define DPCD_FORMAT_CONVERSION 0x08
> +
> +/* Main link channel coding. */
> +#define DPCD_ANSI_8B_10B 0x01
> +
> +/* Down stream port count. */
> +#define DPCD_OUI_SUPPORTED 0x80
> +
> +/* Receiver port capability. */
> +#define DPCD_EDID_PRESENT 0x02
> +#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
> +
> +/* Down stream port capability. */
> +#define DPCD_CAP_DISPLAY_PORT 0x000
> +#define DPCD_CAP_ANALOG_VGA 0x001
> +#define DPCD_CAP_DVI 0x002
> +#define DPCD_CAP_HDMI 0x003
> +#define DPCD_CAP_OTHER 0x100
> +
> +#endif /* !DPCD_H */
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 4/7] hw/i2c-ddc.c: Implement DDC I2C slave
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 4/7] hw/i2c-ddc.c: Implement DDC I2C slave fred.konrad
@ 2015-06-24 7:03 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 7:03 UTC (permalink / raw)
To: Fréderic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: Peter Maydell <peter.maydell@linaro.org>
>
> Implement an I2C slave which implements DDC and returns the
> EDID data for an attached monitor.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>
> - Rebased on the current master.
> - Modified for QOM.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/i2c/Makefile.objs | 2 +-
> hw/i2c/i2c-ddc.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/i2c/i2c-ddc.h | 34 ++++++
> 3 files changed, 323 insertions(+), 1 deletion(-)
> create mode 100644 hw/i2c/i2c-ddc.c
> create mode 100644 hw/i2c/i2c-ddc.h
>
> diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
> index 0f13060..307a73b 100644
> --- a/hw/i2c/Makefile.objs
> +++ b/hw/i2c/Makefile.objs
> @@ -1,4 +1,4 @@
> -common-obj-y += core.o smbus.o smbus_eeprom.o
> +common-obj-y += core.o smbus.o smbus_eeprom.o i2c-ddc.o
Needs own config.
> common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
> common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
> common-obj-$(CONFIG_APM) += pm_smbus.o
> diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
> new file mode 100644
> index 0000000..71b303c
> --- /dev/null
> +++ b/hw/i2c/i2c-ddc.c
> @@ -0,0 +1,288 @@
> +/* A simple I2C slave for returning monitor EDID data via DDC.
> + *
> + * Copyright (c) 2011 Linaro Limited
> + * Written by Peter Maydell
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "hw/i2c/i2c.h"
> +#include "i2c-ddc.h"
> +
> +/* #define DEBUG_I2CDDC */
> +#ifdef DEBUG_I2CDDC
> +#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...) do {} while (0)
> +#endif
Regular if.
> +
> +/* Structure defining a monitor's characteristics in a
> + * readable format: this should be passed to build_edid_blob()
> + * to convert it into the 128 byte binary EDID blob.
> + * Not all bits of the EDID are customisable here.
> + */
> +typedef struct {
> + char manuf_id[3]; /* three upper case letters */
> + uint16_t product_id;
> + uint32_t serial_no;
> + uint8_t manuf_week;
> + int manuf_year;
> + uint8_t h_cm;
> + uint8_t v_cm;
> + uint8_t gamma;
> + char monitor_name[14];
> + char serial_no_string[14];
> + /* Range limits */
> + uint8_t vmin; /* Hz */
> + uint8_t vmax; /* Hz */
> + uint8_t hmin; /* kHz */
> + uint8_t hmax; /* kHz */
> + uint8_t pixclock; /* MHz / 10 */
> + uint8_t timing_data[18];
> +} edid_data;
EDIDDdata.
> +
> +/* EDID data for a simple LCD monitor */
> +static const edid_data lcd_edid = {
> + /* The manuf_id ought really to be an assigned EISA ID */
> + .manuf_id = "QMU",
> + .product_id = 0,
> + .serial_no = 1,
> + .manuf_week = 1,
> + .manuf_year = 2011,
> + .h_cm = 40,
> + .v_cm = 30,
> + .gamma = 0x78,
> + .monitor_name = "QEMU monitor",
> + .serial_no_string = "1",
> + .vmin = 40,
> + .vmax = 120,
> + .hmin = 30,
> + .hmax = 100,
> + .pixclock = 18,
> + .timing_data = {
> + /* Borrowed from a 21" LCD */
> + 0x48, 0x3f, 0x40, 0x30, 0x62, 0xb0, 0x32, 0x40, 0x40,
> + 0xc0, 0x13, 0x00, 0x98, 0x32, 0x11, 0x00, 0x00, 0x1e
> + }
> +};
> +
> +static uint8_t manuf_char_to_int(char c)
> +{
> + return (c - 'A') & 0x1f;
> +}
> +
> +static void write_ascii_descriptor_block(uint8_t *descblob, uint8_t blocktype,
> + const char *string)
> +{
> + /* Write an EDID Descriptor Block of the "ascii string" type */
> + int i;
> + descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
> + descblob[3] = blocktype;
> + /* The rest is 13 bytes of ASCII; if less then the rest must
> + * be filled with newline then spaces
> + */
> + for (i = 5; i < 19; i++) {
> + descblob[i] = string[i - 5];
> + if (!descblob[i]) {
> + break;
> + }
> + }
strncpy? HACKING says don't use it due to non-null termination but it
is exactly the correct semantic for this job.
> + if (i < 19) {
> + descblob[i++] = '\n';
> + }
> + for ( ; i < 19; i++) {
> + descblob[i] = ' ';
> + }
> +}
> +
> +static void write_range_limits_descriptor(const edid_data *edid,
> + uint8_t *descblob)
> +{
> + int i;
> + descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
> + descblob[3] = 0xfd;
> + descblob[5] = edid->vmin;
> + descblob[6] = edid->vmax;
> + descblob[7] = edid->hmin;
> + descblob[8] = edid->hmax;
> + descblob[9] = edid->pixclock;
> + descblob[10] = 0;
> + descblob[11] = 0xa;
> + for (i = 12; i < 19; i++) {
> + descblob[i] = 0x20;
> + }
> +}
> +
> +static void build_edid_blob(const edid_data *edid, uint8_t *blob)
> +{
> + /* Write an EDID 1.3 format blob (128 bytes) based
> + * on the edid_data structure.
> + */
> + int i;
> + uint8_t cksum;
> +
> + /* 00-07 : header */
> + blob[0] = blob[7] = 0;
> + for (i = 1 ; i < 7; i++) {
> + blob[i] = 0xff;
> + }
> + /* 08-09 : manufacturer ID */
> + blob[8] = (manuf_char_to_int(edid->manuf_id[0]) << 2)
> + | (manuf_char_to_int(edid->manuf_id[1]) >> 3);
> + blob[9] = (manuf_char_to_int(edid->manuf_id[1]) << 5)
> + | manuf_char_to_int(edid->manuf_id[2]);
> + /* 10-11 : product ID code */
> + blob[10] = edid->product_id;
> + blob[11] = edid->product_id >> 8;
> + blob[12] = edid->serial_no;
> + blob[13] = edid->serial_no >> 8;
> + blob[14] = edid->serial_no >> 16;
> + blob[15] = edid->serial_no >> 24;
> + /* 16 : week of manufacture */
> + blob[16] = edid->manuf_week;
> + /* 17 : year of manufacture - 1990 */
> + blob[17] = edid->manuf_year - 1990;
> + /* 18, 19 : EDID version and revision */
> + blob[18] = 1;
> + blob[19] = 3;
> + /* 20 - 24 : basic display parameters */
> + /* We are always a digital display */
> + blob[20] = 0x80;
> + /* 21, 22 : max h/v size in cm */
> + blob[21] = edid->h_cm;
> + blob[22] = edid->v_cm;
> + /* 23 : gamma (divide by 100 then add 1 for actual value) */
> + blob[23] = edid->gamma;
> + /* 24 feature support: no power management, RGB, preferred timing mode,
> + * standard colour space
> + */
> + blob[24] = 0x0e;
> + /* 25 - 34 : chromaticity coordinates. These are the
> + * standard sRGB chromaticity values
> + */
> + blob[25] = 0xee;
> + blob[26] = 0x91;
> + blob[27] = 0xa3;
> + blob[28] = 0x54;
> + blob[29] = 0x4c;
> + blob[30] = 0x99;
> + blob[31] = 0x26;
> + blob[32] = 0x0f;
> + blob[33] = 0x50;
> + blob[34] = 0x54;
> + /* 35, 36 : Established timings: claim to support everything */
> + blob[35] = blob[36] = 0xff;
> + /* 37 : manufacturer's reserved timing: none */
> + blob[37] = 0;
> + /* 38 - 53 : standard timing identification
> + * don't claim anything beyond what the 'established timings'
> + * already provide. Unused slots must be (0x1, 0x1)
> + */
> + for (i = 38; i < 54; i++) {
> + blob[i] = 0x1;
> + }
> + /* 54 - 71 : descriptor block 1 : must be preferred timing data */
> + memcpy(blob + 54, edid->timing_data, 18);
> + /* 72 - 89, 90 - 107, 108 - 125 : descriptor block 2, 3, 4
> + * Order not important, but we must have a monitor name and a
> + * range limits descriptor.
> + */
> + write_range_limits_descriptor(edid, blob + 72);
> + write_ascii_descriptor_block(blob + 90, 0xfc, edid->monitor_name);
> + write_ascii_descriptor_block(blob + 108, 0xff, edid->serial_no_string);
> +
> + /* 126 : extension flag */
> + blob[126] = 0;
> +
> + cksum = 0;
> + DPRINTF("EDID blob:");
> + for (i = 0; i < 127; i++) {
> + cksum += blob[i];
> + DPRINTF("%c0x%02x,", i % 8 ? ' ' : '\n', blob[i]);
qemu_hexdump.
> + }
> + /* 127 : checksum */
> + blob[127] = -cksum;
> + DPRINTF(" 0x%02x\n", blob[127]);
But probably do it here.
> +}
> +
> +static void i2c_ddc_reset(DeviceState *ds)
> +{
> + I2CDDCState *s = I2CDDC(ds);
Blank line.
> + s->firstbyte = 0;
> + s->reg = 0;
> +}
> +
> +static void i2c_ddc_event(I2CSlave *i2c, enum i2c_event event)
> +{
> + I2CDDCState *s = I2CDDC(i2c);
Blank line.
> + if (event == I2C_START_SEND) {
> + s->firstbyte = 1;
> + }
> +}
> +
> +static int i2c_ddc_rx(I2CSlave *i2c)
> +{
> + I2CDDCState *s = I2CDDC(i2c);
> +
> + int value;
> + value = s->edid_blob[s->reg];
> +
> + s->reg++;
> + return value;
> +}
> +
> +static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
> +{
> + I2CDDCState *s = I2CDDC(i2c);
> + if (s->firstbyte) {
> + s->reg = data;
> + s->firstbyte = 0;
> + DPRINTF("[EDID] Written new pointer: %u\n", data);
> + return 1;
> + }
> +
> + /* Ignore all writes */
> + s->reg++;
> + return 1;
> +}
> +
> +static void i2c_ddc_init(Object *obj)
> +{
> + I2CDDCState *s = I2CDDC(obj);
> + build_edid_blob(&lcd_edid, s->edid_blob);
> +}
> +
> +static void i2c_ddc_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + I2CSlaveClass *klass = I2C_SLAVE_CLASS(oc);
klass is usually used for the name of an ObjectClass. The local var
name should truncate the type by convention. This should probably be
"isc".
> +
> + dc->reset = i2c_ddc_reset;
Missing VMSD support.
> + klass->event = i2c_ddc_event;
> + klass->recv = i2c_ddc_rx;
> + klass->send = i2c_ddc_tx;
> +}
> +
> +static TypeInfo i2c_ddc_info = {
> + .name = TYPE_I2CDDC,
> + .parent = TYPE_I2C_SLAVE,
> + .instance_size = sizeof(I2CDDCState),
> + .instance_init = i2c_ddc_init,
> + .class_init = i2c_ddc_class_init
> +};
> +
> +static void ddc_register_devices(void)
> +{
> + type_register_static(&i2c_ddc_info);
> +}
> +
> +type_init(ddc_register_devices);
> diff --git a/hw/i2c/i2c-ddc.h b/hw/i2c/i2c-ddc.h
> new file mode 100644
> index 0000000..fdf802e
> --- /dev/null
> +++ b/hw/i2c/i2c-ddc.h
> @@ -0,0 +1,34 @@
> +/* A simple I2C slave for returning monitor EDID data via DDC.
> + *
> + * Copyright (c) 2011 Linaro Limited
> + * Written by Peter Maydell
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef I2C_DDC
> +#define I2C_DDC
> +
> +/* A simple I2C slave which just returns the contents of its EDID blob. */
> +
> +typedef struct I2CDDCState {
/*< private >*/
> + I2CSlave i2c;
/*< public >*/
Regards,
Peter
> + int firstbyte;
> + uint8_t reg;
> + uint8_t edid_blob[128];
> +} I2CDDCState;
> +
> +#define TYPE_I2CDDC "i2c-ddc"
> +#define I2CDDC(obj) OBJECT_CHECK(I2CDDCState, (obj), TYPE_I2CDDC)
> +
> +#endif /* !I2C_DDC */
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 5/7] Introduce xilinx dpdma.
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 5/7] Introduce xilinx dpdma fred.konrad
@ 2015-06-24 7:41 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 7:41 UTC (permalink / raw)
To: Fréderic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This is the implementation of the DPDMA.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/dma/Makefile.objs | 1 +
> hw/dma/xilinx_dpdma.c | 779 ++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/dma/xilinx_dpdma.h | 71 +++++
hyphens in filesnames.
I am also trying to change the convention of using "xilinx" to "xlnx"
to save on 80 char wraps and make it consisitent with the typenames.
git filter-branch with a tree-filter that does the sed ops on the new
files might make short work on this.
s/xilinx/xlnx
s/Xilinx/Xlnx
s/XILINX/XLNX
> 3 files changed, 851 insertions(+)
> create mode 100644 hw/dma/xilinx_dpdma.c
> create mode 100644 hw/dma/xilinx_dpdma.h
>
> diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
> index 0e65ed0..a9934c5 100644
> --- a/hw/dma/Makefile.objs
> +++ b/hw/dma/Makefile.objs
> @@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
> common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
> common-obj-$(CONFIG_STP2000) += sparc32_dma.o
> common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
> +obj-$(CONFIG_XLNX_ZYNQMP) += xilinx_dpdma.o
>
> obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
> obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
> diff --git a/hw/dma/xilinx_dpdma.c b/hw/dma/xilinx_dpdma.c
> new file mode 100644
> index 0000000..50c5919
> --- /dev/null
> +++ b/hw/dma/xilinx_dpdma.c
> @@ -0,0 +1,779 @@
> +/*
> + * xilinx_dpdma.c
> + *
> + * Copyright (C) 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#include "xilinx_dpdma.h"
> +
> +#ifndef DEBUG_DPDMA
> +#define DEBUG_DPDMA 0
> +#endif
> +
> +#define DPRINTF(fmt, ...) do { \
> + if (DEBUG_DPDMA) { \
> + qemu_log("xilinx_dpdma: " fmt , ## __VA_ARGS__); \
> + } \
> +} while (0);
> +
> +/*
> + * Registers offset for DPDMA.
> + */
Add blank lines to create some logical groupings. My rule of thumb, is
a run of regs that don't define fields can be group together, but a
reg that defs fields must be on its own (with its fields). This would
mean:
> +#define DPDMA_ERR_CTRL (0x0000)
> +#define DPDMA_ISR (0x0004 >> 2)
> +#define DPDMA_IMR (0x0008 >> 2)
> +#define DPDMA_IEN (0x000C >> 2)
> +#define DPDMA_IDS (0x0010 >> 2)
> +#define DPDMA_EISR (0x0014 >> 2)
> +#define DPDMA_EIMR (0x0018 >> 2)
> +#define DPDMA_EIEN (0x001C >> 2)
> +#define DPDMA_EIDS (0x0020 >> 2)
> +#define DPDMA_CNTL (0x0100 >> 2)
blank line.
> +#define DPDMA_GBL (0x0104 >> 2)
> +#define DPDMA_GBL_TRG_CH(n) (1 << n)
> +#define DPDMA_GBL_RTRG_CH(n) (1 << 6 << n)
blank line.
> +#define DPDMA_ALC0_CNTL (0x0108 >> 2)
> +#define DPDMA_ALC0_STATUS (0x010C >> 2)
> +#define DPDMA_ALC0_MAX (0x0110 >> 2)
> +#define DPDMA_ALC0_MIN (0x0114 >> 2)
> +#define DPDMA_ALC0_ACC (0x0118 >> 2)
> +#define DPDMA_ALC0_ACC_TRAN (0x011C >> 2)
> +#define DPDMA_ALC1_CNTL (0x0120 >> 2)
> +#define DPDMA_ALC1_STATUS (0x0124 >> 2)
> +#define DPDMA_ALC1_MAX (0x0128 >> 2)
> +#define DPDMA_ALC1_MIN (0x012C >> 2)
> +#define DPDMA_ALC1_ACC (0x0130 >> 2)
> +#define DPDMA_ALC1_ACC_TRAN (0x0134 >> 2)
blank line (I'd do this one just for separation between ALC and DSCR groupings).
> +#define DPDMA_DSCR_STRT_ADDRE_CH(n) ((0x0200 + n * 0x100) >> 2)
> +#define DPDMA_DSCR_STRT_ADDR_CH(n) ((0x0204 + n * 0x100) >> 2)
> +#define DPDMA_DSCR_NEXT_ADDRE_CH(n) ((0x0208 + n * 0x100) >> 2)
> +#define DPDMA_DSCR_NEXT_ADDR_CH(n) ((0x020C + n * 0x100) >> 2)
> +#define DPDMA_PYLD_CUR_ADDRE_CH(n) ((0x0210 + n * 0x100) >> 2)
> +#define DPDMA_PYLD_CUR_ADDR_CH(n) ((0x0214 + n * 0x100) >> 2)
blank line
> +#define DPDMA_CNTL_CH(n) ((0x0218 + n * 0x100) >> 2)
> +#define DPDMA_CNTL_CH_EN (1)
> +#define DPDMA_CNTL_CH_PAUSED (1 << 1)
blank line
> +#define DPDMA_STATUS_CH(n) ((0x021C + n * 0x100) >> 2)
> +#define DPDMA_STATUS_BURST_TYPE (1 << 4)
> +#define DPDMA_STATUS_MODE (1 << 5)
> +#define DPDMA_STATUS_EN_CRC (1 << 6)
> +#define DPDMA_STATUS_LAST_DSCR (1 << 7)
> +#define DPDMA_STATUS_LDSCR_FRAME (1 << 8)
> +#define DPDMA_STATUS_IGNR_DONE (1 << 9)
> +#define DPDMA_STATUS_DSCR_DONE (1 << 10)
> +#define DPDMA_STATUS_EN_DSCR_UP (1 << 11)
> +#define DPDMA_STATUS_EN_DSCR_INTR (1 << 12)
> +#define DPDMA_STATUS_PREAMBLE_OFF (13)
blank line
> +#define DPDMA_VDO_CH(n) ((0x0220 + n * 0x100) >> 2)
> +#define DPDMA_PYLD_SZ_CH(n) ((0x0224 + n * 0x100) >> 2)
> +#define DPDMA_DSCR_ID_CH(n) ((0x0228 + n * 0x100) >> 2)
> +
> +/*
> + * Descriptor control field.
> + */
> +#define CONTROL_PREAMBLE_VALUE 0xA5
> +
> +#define CONTROL_PREAMBLE 0xFF
> +#define EN_DSCR_DONE_INTR (1 << 8)
> +#define EN_DSCR_UPDATE (1 << 9)
> +#define IGNORE_DONE (1 << 10)
> +#define AXI_BURST_TYPE (1 << 11)
> +#define AXCACHE (0x0F << 12)
> +#define AXPROT (0x2 << 16)
> +#define DESCRIPTOR_MODE (1 << 18)
> +#define LAST_DESCRIPTOR (1 << 19)
> +#define ENABLE_CRC (1 << 20)
These macros should have CONTROL_ prefix (maybe even a DESCR_ in there
too). Macros like unqualified ENABLE_CRC are prone to namespace
collision.
> +#define LAST_DESCRIPTOR_OF_FRAME (1 << 21)
> +
> +/*
> + * Descriptor timestamp field.
> + */
> +#define STATUS_DONE (1 << 31)
> +
> +#define DPDMA_FRAG_MAX_SZ (4096)
> +
> +typedef enum DPDMABurstType {
> + DPDMA_INCR = 0,
> + DPDMA_FIXED = 1
> +} DPDMABurstType;
> +
> +typedef enum DPDMAMode {
> + DPDMA_CONTIGOUS = 0,
> + DPDMA_FRAGMENTED = 1
> +} DPDMAMode;
> +
> +typedef struct DPDMADescriptor {
> + uint32_t control;
> + uint32_t descriptor_id;
> + /* transfer size in byte. */
> + uint32_t xfer_size;
> + uint32_t line_size_stride;
> + uint32_t timestamp_lsb;
> + uint32_t timestamp_msb;
> + /* contains extension for both descriptor and source. */
> + uint32_t address_extension;
> + uint32_t next_descriptor;
> + uint32_t source_address;
> + uint32_t address_extension_23;
> + uint32_t address_extension_45;
> + uint32_t source_address2;
> + uint32_t source_address3;
> + uint32_t source_address4;
> + uint32_t source_address5;
> + uint32_t crc;
> +} DPDMADescriptor;
> +
> +static bool xilinx_dpdma_desc_is_last(DPDMADescriptor *desc)
> +{
> + return ((desc->control & LAST_DESCRIPTOR) != 0);
> +}
> +
> +static bool xilinx_dpdma_desc_is_last_of_frame(DPDMADescriptor *desc)
> +{
> + return ((desc->control & LAST_DESCRIPTOR_OF_FRAME) != 0);
> +}
> +
> +static uint64_t xilinx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
> + uint8_t frag)
> +{
> + uint64_t addr = 0;
> + assert(frag < 5);
> +
> + switch (frag) {
> + case 0:
> + addr = desc->source_address
> + + (extract32(desc->address_extension, 16, 12) << 20);
> + break;
> + case 1:
> + addr = desc->source_address2
> + + (extract32(desc->address_extension_23, 0, 12) << 8);
> + break;
> + case 2:
> + addr = desc->source_address3
> + + (extract32(desc->address_extension_23, 16, 12) << 20);
> + break;
> + case 3:
> + addr = desc->source_address4
> + + (extract32(desc->address_extension_45, 0, 12) << 8);
> + break;
> + case 4:
> + addr = desc->source_address5
> + + (extract32(desc->address_extension_45, 16, 12) << 20);
> + break;
> + default:
> + addr = 0;
> + break;
> + }
> +
> + return addr;
> +}
> +
> +static uint32_t xilinx_dpdma_desc_get_transfer_size(DPDMADescriptor *desc)
> +{
> + return desc->xfer_size;
> +}
> +
> +static uint32_t xilinx_dpdma_desc_get_line_size(DPDMADescriptor *desc)
> +{
> + return extract32(desc->line_size_stride, 0, 18);
> +}
> +
> +static uint32_t xilinx_dpdma_desc_get_line_stride(DPDMADescriptor *desc)
> +{
> + return extract32(desc->line_size_stride, 18, 14) * 16;
> +}
> +
> +static inline bool xilinx_dpdma_desc_crc_enabled(DPDMADescriptor *desc)
> +{
> + return (desc->control & ENABLE_CRC) != 0;
> +}
> +
> +static inline bool xilinx_dpdma_desc_check_crc(DPDMADescriptor *desc)
> +{
> + uint32_t *p = (uint32_t *)desc;
> + uint32_t crc = 0;
> + uint8_t i;
> +
> + /*
> + * CRC is calculated on the whole descriptor except the last 32bits word
> + * using 32bits addition.
> + */
> + for (i = 0; i < 15; i++) {
> + crc += p[i];
> + }
> +
> + return crc == desc->crc;
> +}
> +
> +static inline bool xilinx_dpdma_desc_completion_interrupt(DPDMADescriptor *desc)
> +{
> + return (desc->control & EN_DSCR_DONE_INTR) != 0;
> +}
> +
> +static inline bool xilinx_dpdma_desc_is_valid(DPDMADescriptor *desc)
> +{
> + return (desc->control & CONTROL_PREAMBLE) == CONTROL_PREAMBLE_VALUE;
> +}
> +
> +static inline bool xilinx_dpdma_desc_is_contiguous(DPDMADescriptor *desc)
> +{
> + return (desc->control & DESCRIPTOR_MODE) == 0;
> +}
> +
> +static inline bool xilinx_dpdma_desc_update_enabled(DPDMADescriptor *desc)
> +{
> + return (desc->control & EN_DSCR_UPDATE) != 0;
> +}
> +
> +static inline void xilinx_dpdma_desc_set_done(DPDMADescriptor *desc)
> +{
> + desc->timestamp_msb |= STATUS_DONE;
> +}
> +
> +static inline bool xilinx_dpdma_desc_is_already_done(DPDMADescriptor *desc)
> +{
> + return (desc->timestamp_msb & STATUS_DONE) != 0;
> +}
> +
> +static inline bool xilinx_dpdma_desc_ignore_done_bit(DPDMADescriptor *desc)
> +{
> + return (desc->control & IGNORE_DONE) != 0;
> +}
> +
> +static const VMStateDescription vmstate_xilinx_dpdma = {
> + .name = TYPE_XILINX_DPDMA,
> + .version_id = 1,
> + .fields = (VMStateField[]) {
> +
Doesn't feel right, Is there really no savable state?
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void xilinx_dpdma_update_irq(XilinxDPDMAState *s)
> +{
> + uint32_t flags;
bool irq_state.
> +
> + flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR]))
irq_state =
> + | (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR])));
||
It's a bit of a nit, but the bitwise oring of the two masked registers
has no physical meaning, it's conceptually a logical oring.
> + qemu_set_irq(s->irq, flags != 0);
> +}
> +
> +static uint64_t xilinx_dpdma_descriptor_start_address(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return (s->registers[DPDMA_DSCR_STRT_ADDRE_CH(channel)] << 16)
> + + s->registers[DPDMA_DSCR_STRT_ADDR_CH(channel)];
> +}
> +
> +static uint64_t xilinx_dpdma_descriptor_next_address(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return ((uint64_t)s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] << 32)
> + + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)];
> +}
> +
> +static inline void xilinx_dpdma_set_desc_next_address(XilinxDPDMAState *s,
> + uint8_t channel,
> + uint64_t addr)
> +{
> + s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] = extract64(addr, 32, 32);
> + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = extract64(addr, 0, 32);
> +}
> +
> +static bool xilinx_dpdma_is_channel_enabled(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_EN) != 0;
> +}
> +
> +static bool xilinx_dpdma_is_channel_paused(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return (s->registers[DPDMA_CNTL_CH(channel)] & DPDMA_CNTL_CH_PAUSED) != 0;
> +}
> +
> +static inline bool xilinx_dpdma_is_channel_retriggered(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + /* Clear the retriggered bit after reading it. */
> + bool channel_is_retriggered = s->registers[DPDMA_GBL]
> + & DPDMA_GBL_RTRG_CH(channel);
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_RTRG_CH(channel);
> + return channel_is_retriggered;
> +}
> +
> +static inline bool xilinx_dpdma_is_channel_triggered(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return s->registers[DPDMA_GBL] & DPDMA_GBL_TRG_CH(channel);
> +}
> +
> +static void xilinx_dpdma_update_desc_info(XilinxDPDMAState *s, uint8_t channel,
> + DPDMADescriptor *desc)
> +{
> + s->registers[DPDMA_DSCR_NEXT_ADDRE_CH(channel)] =
> + extract32(desc->address_extension, 0, 16);
> + s->registers[DPDMA_DSCR_NEXT_ADDR_CH(channel)] = desc->next_descriptor;
> + s->registers[DPDMA_PYLD_CUR_ADDRE_CH(channel)] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_PYLD_CUR_ADDR_CH(channel)] = desc->source_address;
> + s->registers[DPDMA_VDO_CH(channel)] =
> + extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_PYLD_SZ_CH(channel)] = desc->xfer_size;
> + s->registers[DPDMA_DSCR_ID_CH(channel)] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_STATUS_CH(channel)] =
> + extract32(desc->control, 0, 8) << 13;
> + if ((desc->control & EN_DSCR_DONE_INTR) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_INTR;
> + }
> + if ((desc->control & EN_DSCR_UPDATE) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_DSCR_UP;
> + }
> + if ((desc->timestamp_msb & STATUS_DONE) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_DSCR_DONE;
> + }
> + if ((desc->control & IGNORE_DONE) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_IGNR_DONE;
> + }
> + if ((desc->control & LAST_DESCRIPTOR_OF_FRAME) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LDSCR_FRAME;
> + }
> + if ((desc->control & LAST_DESCRIPTOR) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_LAST_DSCR;
> + }
> + if ((desc->control & ENABLE_CRC) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_EN_CRC;
> + }
> + if ((desc->control & DESCRIPTOR_MODE) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_MODE;
> + }
> + if ((desc->control & AXI_BURST_TYPE) != 0) {
> + s->registers[DPDMA_STATUS_CH(channel)] |= DPDMA_STATUS_BURST_TYPE;
> + }
> +}
> +
> +#ifdef DEBUG_DPDMA
> +static void xilinx_dpdma_dump_descriptor(DPDMADescriptor *desc)
> +{
> + uint8_t *p = (uint8_t *)desc;
> + size_t i;
> +
> + qemu_log("DUMP DESCRIPTOR:\n");
> + for (i = 0; i < 64; i++) {
> + qemu_log(" %" PRIx8, *p++);
> + if (((i + 1) % 4) == 0) {
> + qemu_log("\n");
> + }
> + }
qemu_hexdump
> +}
> +#endif
> +
> +static uint64_t xilinx_dpdma_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + XilinxDPDMAState *s = XILINX_DPDMA(opaque);
> +
> + DPRINTF("read @%" HWADDR_PRIx "\n", offset);
> + offset = offset >> 2;
> +
> + switch (offset) {
> + /*
> + * Trying to read a write only register.
> + */
> + case DPDMA_GBL:
> + return 0;
> + default:
> + assert(offset <= (0xFFC >> 2));
> + return s->registers[offset];
> + }
> + return 0;
> +}
> +
> +static void xilinx_dpdma_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + XilinxDPDMAState *s = XILINX_DPDMA(opaque);
> +
> + DPRINTF("write @%" HWADDR_PRIx " = %" PRIx64 "\n", offset, value);
> + offset = offset >> 2;
> +
> + switch (offset) {
> + case DPDMA_ISR:
> + s->registers[DPDMA_ISR] &= ~value;
> + xilinx_dpdma_update_irq(s);
> + break;
> + case DPDMA_IEN:
> + value = ~value;
> + s->registers[DPDMA_IMR] &= value;
inconsistent with ISR W1C above. I think it is better to just use
~value inline here too. People are used to seeing &= ~ all at once for
a W1C.
> + break;
> + case DPDMA_IDS:
> + s->registers[DPDMA_IMR] |= value;
> + break;
> + case DPDMA_EISR:
> + value = ~value;
same.
> + s->registers[DPDMA_EISR] &= value;
> + xilinx_dpdma_update_irq(s);
> + break;
> + case DPDMA_EIEN:
> + value = ~value;
same.
> + s->registers[DPDMA_EIMR] &= value;
> + break;
> + case DPDMA_EIDS:
> + s->registers[DPDMA_EIMR] |= value;
> + break;
> + case DPDMA_IMR:
> + case DPDMA_EIMR:
> + case DPDMA_DSCR_NEXT_ADDRE_CH(0):
> + case DPDMA_DSCR_NEXT_ADDRE_CH(1):
> + case DPDMA_DSCR_NEXT_ADDRE_CH(2):
> + case DPDMA_DSCR_NEXT_ADDRE_CH(3):
> + case DPDMA_DSCR_NEXT_ADDRE_CH(4):
> + case DPDMA_DSCR_NEXT_ADDRE_CH(5):
> + case DPDMA_DSCR_NEXT_ADDR_CH(0):
> + case DPDMA_DSCR_NEXT_ADDR_CH(1):
> + case DPDMA_DSCR_NEXT_ADDR_CH(2):
> + case DPDMA_DSCR_NEXT_ADDR_CH(3):
> + case DPDMA_DSCR_NEXT_ADDR_CH(4):
> + case DPDMA_DSCR_NEXT_ADDR_CH(5):
> + case DPDMA_PYLD_CUR_ADDRE_CH(0):
> + case DPDMA_PYLD_CUR_ADDRE_CH(1):
> + case DPDMA_PYLD_CUR_ADDRE_CH(2):
> + case DPDMA_PYLD_CUR_ADDRE_CH(3):
> + case DPDMA_PYLD_CUR_ADDRE_CH(4):
> + case DPDMA_PYLD_CUR_ADDRE_CH(5):
> + case DPDMA_PYLD_CUR_ADDR_CH(0):
> + case DPDMA_PYLD_CUR_ADDR_CH(1):
> + case DPDMA_PYLD_CUR_ADDR_CH(2):
> + case DPDMA_PYLD_CUR_ADDR_CH(3):
> + case DPDMA_PYLD_CUR_ADDR_CH(4):
> + case DPDMA_PYLD_CUR_ADDR_CH(5):
> + case DPDMA_STATUS_CH(0):
> + case DPDMA_STATUS_CH(1):
> + case DPDMA_STATUS_CH(2):
> + case DPDMA_STATUS_CH(3):
> + case DPDMA_STATUS_CH(4):
> + case DPDMA_STATUS_CH(5):
> + case DPDMA_VDO_CH(0):
> + case DPDMA_VDO_CH(1):
> + case DPDMA_VDO_CH(2):
> + case DPDMA_VDO_CH(3):
> + case DPDMA_VDO_CH(4):
> + case DPDMA_VDO_CH(5):
> + case DPDMA_PYLD_SZ_CH(0):
> + case DPDMA_PYLD_SZ_CH(1):
> + case DPDMA_PYLD_SZ_CH(2):
> + case DPDMA_PYLD_SZ_CH(3):
> + case DPDMA_PYLD_SZ_CH(4):
> + case DPDMA_PYLD_SZ_CH(5):
> + case DPDMA_DSCR_ID_CH(0):
> + case DPDMA_DSCR_ID_CH(1):
> + case DPDMA_DSCR_ID_CH(2):
> + case DPDMA_DSCR_ID_CH(3):
> + case DPDMA_DSCR_ID_CH(4):
> + case DPDMA_DSCR_ID_CH(5):
This repetition ...
> + /*
> + * Trying to write to a read only register..
> + */
> + break;
> + case DPDMA_GBL:
> + /*
> + * This is a write only register so it's read as zero in the read
> + * callback.
> + * We store the value anyway so we can know if the channel is
> + * enabled.
> + */
> + s->registers[offset] |= value & 0x00000FFF;
> + break;
> + case DPDMA_DSCR_STRT_ADDRE_CH(0):
> + case DPDMA_DSCR_STRT_ADDRE_CH(1):
> + case DPDMA_DSCR_STRT_ADDRE_CH(2):
> + case DPDMA_DSCR_STRT_ADDRE_CH(3):
> + case DPDMA_DSCR_STRT_ADDRE_CH(4):
> + case DPDMA_DSCR_STRT_ADDRE_CH(5):
> + value &= 0x0000FFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CNTL_CH(0):
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(0);
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CNTL_CH(1):
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(1);
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CNTL_CH(2):
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(2);
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CNTL_CH(3):
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(3);
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CNTL_CH(4):
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(4);
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CNTL_CH(5):
> + s->registers[DPDMA_GBL] &= ~DPDMA_GBL_TRG_CH(5);
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
And this rep here can be further reduced by having two switch cases.
First switch case handles all the "non channel" stuff. The default:
case uses the address to calculate the channel id:
channel = ((offset << 2) - 0x200) >> 9
offset_channel = offset - (0x200 >> 2)
Then switch on offset_channel using channel as the index into DPDMA_GBL_TRG_CH.
> + default:
> + assert(offset <= (0xFFC >> 2));
> + s->registers[offset] = value;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps dma_ops = {
> + .read = xilinx_dpdma_read,
> + .write = xilinx_dpdma_write,
Needs access restricitions (I think you only support 32b ops).
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void xilinx_dpdma_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + XilinxDPDMAState *s = XILINX_DPDMA(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &dma_ops, s,
> + TYPE_XILINX_DPDMA, 0x1000);
> + sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void xilinx_dpdma_reset(DeviceState *dev)
> +{
> + XilinxDPDMAState *s = XILINX_DPDMA(dev);
> +
> + memset(s->registers, 0, sizeof(s->registers));
> + s->registers[DPDMA_IMR] = 0x07FFFFFF;
> + s->registers[DPDMA_EIMR] = 0xFFFFFFFF;
> + s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF;
> + s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF;
> +}
> +
> +static void xilinx_dpdma_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->vmsd = &vmstate_xilinx_dpdma;
> + dc->reset = xilinx_dpdma_reset;
> +}
> +
> +static const TypeInfo xilinx_dpdma_info = {
> + .name = TYPE_XILINX_DPDMA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XilinxDPDMAState),
> + .instance_init = xilinx_dpdma_init,
> + .class_init = xilinx_dpdma_class_init,
> +};
> +
> +static void xilinx_dpdma_register_types(void)
> +{
> + type_register_static(&xilinx_dpdma_info);
> +}
> +
> +size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
> + bool one_desc)
> +{
> + uint64_t desc_addr;
> + uint64_t source_addr[6];
> + DPDMADescriptor desc;
> + bool done = false;
> + size_t ptr = 0;
> +
> + assert(channel <= 5);
> +
> + /* Trigger a VSYNC IRQ when the graphic callback asks for data. */
> + if (channel == 3) {
> + s->registers[DPDMA_ISR] |= (1 << 27);
> + xilinx_dpdma_update_irq(s);
> + }
> +
> + DPRINTF("dpdma_start_channel() on channel %u\n", channel);
"%s" __func__
PRIx8
> +
> + if (!xilinx_dpdma_is_channel_triggered(s, channel)) {
> + DPRINTF("Channel isn't triggered..\n");
> + return 0;
> + }
> +
> + if (!xilinx_dpdma_is_channel_enabled(s, channel)) {
> + DPRINTF("Channel isn't enabled..\n");
> + return 0;
> + }
> +
> + if (xilinx_dpdma_is_channel_paused(s, channel)) {
> + DPRINTF("Channel is paused..\n");
> + return 0;
> + }
> +
> + do {
> + if ((s->operation_finished[channel])
> + || xilinx_dpdma_is_channel_retriggered(s, channel)) {
> + desc_addr = xilinx_dpdma_descriptor_start_address(s, channel);
> + s->operation_finished[channel] = false;
> + } else {
> + desc_addr = xilinx_dpdma_descriptor_next_address(s, channel);
> + }
> +
> + if (dma_memory_read(&address_space_memory, desc_addr, &desc,
> + sizeof(DPDMADescriptor))) {
> + s->registers[DPDMA_EISR] |= ((1 << 1) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Can't get the descriptor.\n");
> + break;
> + }
> +
> + xilinx_dpdma_update_desc_info(s, channel, &desc);
> +
> +#ifdef DEBUG_DPDMA
> + xilinx_dpdma_dump_descriptor(&desc);
> +#endif
> +
> + DPRINTF("location of the descriptor: %" PRIx64 "\n", desc_addr);
> + if (!xilinx_dpdma_desc_is_valid(&desc)) {
> + s->registers[DPDMA_EISR] |= ((1 << 7) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Invalid descriptor..\n");
> + break;
> + }
> +
> + if (xilinx_dpdma_desc_crc_enabled(&desc)
> + && !xilinx_dpdma_desc_check_crc(&desc)) {
> + s->registers[DPDMA_EISR] |= ((1 << 13) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Bad CRC for descriptor..\n");
> + break;
> + }
> +
> + if (xilinx_dpdma_desc_is_already_done(&desc)
> + && !xilinx_dpdma_desc_ignore_done_bit(&desc)) {
> + /* We are trying to process an already processed descriptor. */
> + s->registers[DPDMA_EISR] |= ((1 << 25) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Already processed descriptor..\n");
> + break;
> + }
> +
> + done = xilinx_dpdma_desc_is_last(&desc)
> + || xilinx_dpdma_desc_is_last_of_frame(&desc);
> +
> + s->operation_finished[channel] = done;
> + if (s->data[channel]) {
> + int64_t transfer_len =
> + xilinx_dpdma_desc_get_transfer_size(&desc);
> + uint32_t line_size = xilinx_dpdma_desc_get_line_size(&desc);
> + uint32_t line_stride = xilinx_dpdma_desc_get_line_stride(&desc);
> + if (xilinx_dpdma_desc_is_contiguous(&desc)) {
> + source_addr[0] =
> + xilinx_dpdma_desc_get_source_address(&desc, 0);
> + while (transfer_len != 0) {
> + if (dma_memory_read(&address_space_memory,
> + source_addr[0],
> + &s->data[channel][ptr],
> + line_size)) {
> + s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
> + xilinx_dpdma_update_irq(s);
> + DPRINTF("Can't get data.\n");
> + break;
> + }
> + ptr += line_size;
> + transfer_len -= line_size;
> + source_addr[0] += line_stride;
> + }
> + } else {
> + DPRINTF("Source address:\n");
> + int frag;
> + for (frag = 0; frag < 5; frag++) {
> + source_addr[frag] =
> + xilinx_dpdma_desc_get_source_address(&desc, frag);
> + DPRINTF("Fragment %u: %" PRIx64 "\n", frag + 1,
> + source_addr[frag]);
> + }
> +
> + frag = 0;
> + while ((transfer_len < 0) && (frag < 5)) {
> + size_t fragment_len = DPDMA_FRAG_MAX_SZ
> + - (source_addr[frag] % DPDMA_FRAG_MAX_SZ);
> +
> + if (dma_memory_read(&address_space_memory,
> + source_addr[frag],
> + &(s->data[channel][ptr]),
> + fragment_len)) {
> + s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
> + xilinx_dpdma_update_irq(s);
> + DPRINTF("Can't get data.\n");
> + break;
> + }
> + ptr += fragment_len;
> + transfer_len -= fragment_len;
> + frag += 1;
> + }
> + }
> + }
> +
> + if (xilinx_dpdma_desc_update_enabled(&desc)) {
> + /* The descriptor need to be updated when it's completed. */
> + DPRINTF("update the descriptor with the done flag set.\n");
> + xilinx_dpdma_desc_set_done(&desc);
> + dma_memory_write(&address_space_memory, desc_addr, &desc,
> + sizeof(DPDMADescriptor));
> + }
> +
> + if (xilinx_dpdma_desc_completion_interrupt(&desc)) {
> + DPRINTF("completion interrupt enabled!\n");
> + s->registers[DPDMA_ISR] |= (1 << channel);
> + xilinx_dpdma_update_irq(s);
> + }
> +
> + } while (!done && !one_desc);
> +
> + return ptr;
> +}
> +
> +void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
> + void *p)
> +{
> + if (!s) {
> + qemu_log_mask(LOG_UNIMP, "DPDMA client not attached to valid DPDMA"
> + " instance\n");
> + return;
> + }
> +
> + assert(channel <= 5);
> + s->data[channel] = p;
> +}
> +
> +type_init(xilinx_dpdma_register_types)
> diff --git a/hw/dma/xilinx_dpdma.h b/hw/dma/xilinx_dpdma.h
> new file mode 100644
> index 0000000..f92167d
> --- /dev/null
> +++ b/hw/dma/xilinx_dpdma.h
> @@ -0,0 +1,71 @@
> +/*
> + * xilinx_dpdma.h
> + *
> + * Copyright (C) 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef XILINX_DPDMA_H
> +#define XILINX_DPDMA_H
> +
> +#include "hw/sysbus.h"
> +#include "ui/console.h"
> +#include "sysemu/dma.h"
> +
> +struct XilinxDPDMAState {
/*< private > */
> + SysBusDevice parent_obj;
/*< public > */
> + MemoryRegion iomem;
> + uint32_t registers[0x1000 >> 2];
> + uint8_t *data[6];
> + bool operation_finished[6];
> + qemu_irq irq;
> +};
> +
> +typedef struct XilinxDPDMAState XilinxDPDMAState;
> +
> +#define TYPE_XILINX_DPDMA "xlnx.dpdma"
> +#define XILINX_DPDMA(obj) OBJECT_CHECK(XilinxDPDMAState, (obj), \
> + TYPE_XILINX_DPDMA)
> +
> +/*
> + * \func xilinx_dpdma_start_operation.
> + * \brief Start the operation on the specified channel. The DPDMA get the
> + * current descriptor and retrieve data to the buffer specified by
> + * dpdma_set_host_data_location.
> + * \arg s The DPDMA instance.
> + * \arg channel The channel to start.
> + * \return the number of byte transfered by the DPDMA or 0 if an error occured.
Comment style.
Regards,
Peter
> + */
> +size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
> + bool one_desc);
> +
> +/*
> + * \func xilinx_dpdma_set_host_data_location.
> + * \brief Set the location in the host memory where to store the data out from
> + * the dma channel.
> + * \arg s The DPDMA instance.
> + * \arg channel The channel associated to the pointer.
> + * \arg p The buffer where to store the data.
> + */
> +/* XXX: add a maximum size arg and send an interrupt in case of overflow. */
> +void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
> + void *p);
> +
> +#endif /* !XILINX_DPDMA_H */
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 6/7] Introduce xilinx dp.
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 6/7] Introduce xilinx dp fred.konrad
@ 2015-06-24 8:21 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 8:21 UTC (permalink / raw)
To: Fréderic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This is the implementation of the DisplayPort.
>
> It has an aux-bus to access dpcd and edid needed for the driver to complete.
>
No need to reference the driver.
> Graphic plane is connected to the channel 3.
> Video plane is connected to the channel 0.
> Audio stream are connected to the channels 4 and 5.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/display/Makefile.objs | 2 +-
> hw/display/xilinx_dp.c | 1427 ++++++++++++++++++++++++++++++++++++++++++++++
> hw/display/xilinx_dp.h | 129 +++++
> 3 files changed, 1557 insertions(+), 1 deletion(-)
> create mode 100644 hw/display/xilinx_dp.c
> create mode 100644 hw/display/xilinx_dp.h
>
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index f75094f..f418dbc 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -36,4 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
>
> obj-$(CONFIG_VIRTIO) += virtio-gpu.o
> -obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o
> +obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o xilinx_dp.o
Give each file its own line. It makes Makefile.objs diffs easier reading.
Same comments as before about name stems and filenames.
> diff --git a/hw/display/xilinx_dp.c b/hw/display/xilinx_dp.c
> new file mode 100644
> index 0000000..cf48d8b
> --- /dev/null
> +++ b/hw/display/xilinx_dp.c
> @@ -0,0 +1,1427 @@
> +/*
> + * xilinx_dp.c
> + *
> + * Copyright (C) 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#include "xilinx_dp.h"
> +
> +#ifndef DEBUG_DP
> +#define DEBUG_DP 0
> +#endif
> +
> +#define DPRINTF(fmt, ...) do { \
> + if (DEBUG_DP) { \
> + qemu_log("xilinx_dp: " fmt , ## __VA_ARGS__); \
> + } \
> +} while (0);
> +
> +/*
> + * Register offset for DP.
> + */
Blank lines between logical groupings.
> +#define DP_LINK_BW_SET (0x0000 >> 2)
> +#define DP_LANE_COUNT_SET (0x0004 >> 2)
> +#define DP_ENHANCED_FRAME_EN (0x0008 >> 2)
> +#define DP_TRAINING_PATTERN_SET (0x000C >> 2)
> +#define DP_LINK_QUAL_PATTERN_SET (0x0010 >> 2)
> +#define DP_SCRAMBLING_DISABLE (0x0014 >> 2)
> +#define DP_DOWNSPREAD_CTRL (0x0018 >> 2)
> +#define DP_SOFTWARE_RESET (0x001C >> 2)
> +#define DP_TRANSMITTER_ENABLE (0x0080 >> 2)
> +#define DP_MAIN_STREAM_ENABLE (0x0084 >> 2)
> +#define DP_FORCE_SCRAMBLER_RESET (0x00C0 >> 2)
> +#define DP_VERSION_REGISTER (0x00F8 >> 2)
> +#define DP_CORE_ID (0x00FC >> 2)
> +#define DP_AUX_COMMAND_REGISTER (0x0100 >> 2)
> +#define AUX_ADDR_ONLY_MASK (0x1000)
> +#define AUX_COMMAND_MASK (0x0F00)
> +#define AUX_COMMAND_SHIFT (8)
> +#define AUX_COMMAND_NBYTES (0x000F)
> +#define DP_AUX_WRITE_FIFO (0x0104 >> 2)
> +#define DP_AUX_ADDRESS (0x0108 >> 2)
> +#define DP_AUX_CLOCK_DIVIDER (0x010C >> 2)
> +#define DP_TX_USER_FIFO_OVERFLOW (0x0110 >> 2)
> +#define DP_INTERRUPT_SIGNAL_STATE (0x0130 >> 2)
> +#define DP_AUX_REPLY_DATA (0x0134 >> 2)
> +#define DP_AUX_REPLY_CODE (0x0138 >> 2)
> +#define DP_AUX_REPLY_COUNT (0x013C >> 2)
> +#define DP_REPLY_DATA_COUNT (0x0148 >> 2)
> +#define DP_REPLY_STATUS (0x014C >> 2)
> +#define DP_HPD_DURATION (0x0150 >> 2)
> +#define DP_MAIN_STREAM_HTOTAL (0x0180 >> 2)
> +#define DP_MAIN_STREAM_VTOTAL (0x0184 >> 2)
> +#define DP_MAIN_STREAM_POLARITY (0x0188 >> 2)
> +#define DP_MAIN_STREAM_HSWIDTH (0x018C >> 2)
> +#define DP_MAIN_STREAM_VSWIDTH (0x0190 >> 2)
> +#define DP_MAIN_STREAM_HRES (0x0194 >> 2)
> +#define DP_MAIN_STREAM_VRES (0x0198 >> 2)
> +#define DP_MAIN_STREAM_HSTART (0x019C >> 2)
> +#define DP_MAIN_STREAM_VSTART (0x01A0 >> 2)
> +#define DP_MAIN_STREAM_MISC0 (0x01A4 >> 2)
> +#define DP_MAIN_STREAM_MISC1 (0x01A8 >> 2)
> +#define DP_MAIN_STREAM_M_VID (0x01AC >> 2)
> +#define DP_MSA_TRANSFER_UNIT_SIZE (0x01B0 >> 2)
> +#define DP_MAIN_STREAM_N_VID (0x01B4 >> 2)
> +#define DP_USER_DATA_COUNT_PER_LANE (0x01BC >> 2)
> +#define DP_MIN_BYTES_PER_TU (0x01C4 >> 2)
> +#define DP_FRAC_BYTES_PER_TU (0x01C8 >> 2)
> +#define DP_INIT_WAIT (0x01CC >> 2)
> +#define DP_PHY_RESET (0x0200 >> 2)
> +#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x0220 >> 2)
> +#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x0224 >> 2)
> +#define DP_TRANSMIT_PRBS7 (0x0230 >> 2)
> +#define DP_PHY_CLOCK_SELECT (0x0234 >> 2)
> +#define DP_TX_PHY_POWER_DOWN (0x0238 >> 2)
> +#define DP_PHY_PRECURSOR_LANE_0 (0x023C >> 2)
> +#define DP_PHY_PRECURSOR_LANE_1 (0x0240 >> 2)
> +#define DP_PHY_POSTCURSOR_LANE_0 (0x024C >> 2)
> +#define DP_PHY_POSTCURSOR_LANE_1 (0x0250 >> 2)
> +#define DP_PHY_STATUS (0x0280 >> 2)
> +#define DP_TX_AUDIO_CONTROL (0x0300 >> 2)
> +#define DP_TX_AUDIO_CHANNELS (0x0304 >> 2)
> +#define DP_TX_AUDIO_INFO_DATA0 (0x0308 >> 2)
> +#define DP_TX_AUDIO_INFO_DATA1 (0x030C >> 2)
> +#define DP_TX_AUDIO_INFO_DATA2 (0x0310 >> 2)
> +#define DP_TX_AUDIO_INFO_DATA3 (0x0314 >> 2)
> +#define DP_TX_AUDIO_INFO_DATA4 (0x0318 >> 2)
> +#define DP_TX_AUDIO_INFO_DATA5 (0x031C >> 2)
> +#define DP_TX_AUDIO_INFO_DATA6 (0x0320 >> 2)
> +#define DP_TX_AUDIO_INFO_DATA7 (0x0324 >> 2)
Define once and index in on N.
> +#define DP_TX_M_AUD (0x0328 >> 2)
> +#define DP_TX_N_AUD (0x032C >> 2)
> +#define DP_TX_AUDIO_EXT_DATA0 (0x0330 >> 2)
> +#define DP_TX_AUDIO_EXT_DATA1 (0x0334 >> 2)
> +#define DP_TX_AUDIO_EXT_DATA2 (0x0338 >> 2)
> +#define DP_TX_AUDIO_EXT_DATA3 (0x033C >> 2)
> +#define DP_TX_AUDIO_EXT_DATA4 (0x0340 >> 2)
> +#define DP_TX_AUDIO_EXT_DATA5 (0x0344 >> 2)
> +#define DP_TX_AUDIO_EXT_DATA6 (0x0348 >> 2)
> +#define DP_TX_AUDIO_EXT_DATA7 (0x034C >> 2)
> +#define DP_TX_AUDIO_EXT_DATA8 (0x0350 >> 2)
Index.
> +#define DP_INT_STATUS (0x03A0 >> 2)
> +#define DP_INT_MASK (0x03A4 >> 2)
> +#define DP_INT_EN (0x03A8 >> 2)
> +#define DP_INT_DS (0x03AC >> 2)
> +
> +/*
> + * Registers offset for Audio Video Buffer configuration.
> + */
> +#define V_BLEND_OFFSET (0xA000)
> +#define V_BLEND_BG_CLR_0 (0x0000 >> 2)
> +#define V_BLEND_BG_CLR_1 (0x0004 >> 2)
> +#define V_BLEND_BG_CLR_2 (0x0008 >> 2)
> +#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x000C >> 2)
> +#define V_BLEND_OUTPUT_VID_FORMAT (0x0014 >> 2)
> +#define V_BLEND_LAYER0_CONTROL (0x0018 >> 2)
> +#define V_BLEND_LAYER1_CONTROL (0x001C >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF0 (0x0020 >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF1 (0x0024 >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF2 (0x0028 >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF3 (0x002C >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF4 (0x0030 >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF5 (0x0034 >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF6 (0x0038 >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF7 (0x003C >> 2)
> +#define V_BLEND_RGB2YCBCR_COEFF8 (0x0040 >> 2)
> +#define V_BLEND_IN1CSC_COEFF0 (0x0044 >> 2)
> +#define V_BLEND_IN1CSC_COEFF1 (0x0048 >> 2)
> +#define V_BLEND_IN1CSC_COEFF2 (0x004C >> 2)
> +#define V_BLEND_IN1CSC_COEFF3 (0x0050 >> 2)
> +#define V_BLEND_IN1CSC_COEFF4 (0x0054 >> 2)
> +#define V_BLEND_IN1CSC_COEFF5 (0x0058 >> 2)
> +#define V_BLEND_IN1CSC_COEFF6 (0x005C >> 2)
> +#define V_BLEND_IN1CSC_COEFF7 (0x0060 >> 2)
> +#define V_BLEND_IN1CSC_COEF8 (0x0064 >> 2)
Index.
Missing "F" on #8?
> +#define V_BLEND_LUMA_IN1CSC_OFFSET (0x0068 >> 2)
> +#define V_BLEND_CR_IN1CSC_OFFSET (0x006C >> 2)
> +#define V_BLEND_CB_IN1CSC_OFFSET (0x0070 >> 2)
> +#define V_BLEND_LUMA_OUTCSC_OFFSET (0x0074 >> 2)
> +#define V_BLEND_CR_OUTCSC_OFFSET (0x0078 >> 2)
> +#define V_BLEND_CB_OUTCSC_OFFSET (0x007C >> 2)
> +#define V_BLEND_IN2CSC_COEFF0 (0x0080 >> 2)
> +#define V_BLEND_IN2CSC_COEFF1 (0x0084 >> 2)
> +#define V_BLEND_IN2CSC_COEFF2 (0x0088 >> 2)
> +#define V_BLEND_IN2CSC_COEFF3 (0x008C >> 2)
> +#define V_BLEND_IN2CSC_COEFF4 (0x0090 >> 2)
> +#define V_BLEND_IN2CSC_COEFF5 (0x0094 >> 2)
> +#define V_BLEND_IN2CSC_COEFF6 (0x0098 >> 2)
> +#define V_BLEND_IN2CSC_COEFF7 (0x009C >> 2)
> +#define V_BLEND_IN2CSC_COEFF8 (0x00A0 >> 2)
Index.
> +#define V_BLEND_LUMA_IN2CSC_OFFSET (0x00A4 >> 2)
> +#define V_BLEND_CR_IN2CSC_OFFSET (0x00A8 >> 2)
> +#define V_BLEND_CB_IN2CSC_OFFSET (0x00AC >> 2)
> +#define V_BLEND_CHROMA_KEY_ENABLE (0x01D0 >> 2)
> +#define V_BLEND_CHROMA_KEY_COMP1 (0x01D4 >> 2)
> +#define V_BLEND_CHROMA_KEY_COMP2 (0x01D8 >> 2)
> +#define V_BLEND_CHROMA_KEY_COMP3 (0x01DC >> 2)
> +
> +/*
> + * Registers offset for Audio Video Buffer configuration.
> + */
> +#define AV_BUF_MANAGER_OFFSET (0xB000)
> +#define AV_BUF_FORMAT (0x0000 >> 2)
> +#define AV_BUF_NON_LIVE_LATENCY (0x0008 >> 2)
> +#define AV_CHBUF0 (0x0010 >> 2)
> +#define AV_CHBUF1 (0x0014 >> 2)
> +#define AV_CHBUF2 (0x0018 >> 2)
> +#define AV_CHBUF3 (0x001C >> 2)
> +#define AV_CHBUF4 (0x0020 >> 2)
> +#define AV_CHBUF5 (0x0024 >> 2)
> +#define AV_BUF_STC_CONTROL (0x002C >> 2)
> +#define AV_BUF_STC_INIT_VALUE0 (0x0030 >> 2)
> +#define AV_BUF_STC_INIT_VALUE1 (0x0034 >> 2)
> +#define AV_BUF_STC_ADJ (0x0038 >> 2)
> +#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x003C >> 2)
> +#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x0040 >> 2)
> +#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x0044 >> 2)
> +#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x0048 >> 2)
> +#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x004C >> 2)
> +#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x0050 >> 2)
> +#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x0054 >> 2)
> +#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x0058 >> 2)
> +#define AV_BUF_STC_SNAPSHOT0 (0x0060 >> 2)
> +#define AV_BUF_STC_SNAPSHOT1 (0x0064 >> 2)
> +#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x0070 >> 2)
> +#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x0074 >> 2)
> +#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x0078 >> 2)
> +#define AV_BUF_DITHER_CONFIG (0x007C >> 2)
> +#define AV_BUF_DITHER_CONFIG_MAX (0x008C >> 2)
> +#define AV_BUF_DITHER_CONFIG_MIN (0x0090 >> 2)
> +#define AV_BUF_PATTERN_GEN_SELECT (0x0100 >> 2)
> +#define AV_BUF_AUD_VID_CLK_SOURCE (0x0120 >> 2)
> +#define AV_BUF_SRST_REG (0x0124 >> 2)
> +#define AV_BUF_AUDIO_RDY_INTERVAL (0x0128 >> 2)
> +#define AV_BUF_AUDIO_CH_CONFIG (0x012C >> 2)
> +#define AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR (0x0200 >> 2)
> +#define AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR (0x0204 >> 2)
> +#define AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR (0x0208 >> 2)
> +#define AV_BUF_VIDEO_COMP0_SCALE_FACTOR (0x020C >> 2)
> +#define AV_BUF_VIDEO_COMP1_SCALE_FACTOR (0x0210 >> 2)
> +#define AV_BUF_VIDEO_COMP2_SCALE_FACTOR (0x0214 >> 2)
> +#define AV_BUF_LIVE_VIDEO_COMP0_SF (0x0218 >> 2)
> +#define AV_BUF_LIVE_VIDEO_COMP1_SF (0x021C >> 2)
> +#define AV_BUF_LIVE_VIDEO_COMP2_SF (0x0220 >> 2)
> +#define AV_BUF_LIVE_VID_CONFIG (0x0224 >> 2)
> +#define AV_BUF_LIVE_GFX_COMP0_SF (0x0228 >> 2)
> +#define AV_BUF_LIVE_GFX_COMP1_SF (0x022C >> 2)
> +#define AV_BUF_LIVE_GFX_COMP2_SF (0x0230 >> 2)
I think these COMP things can be indexed too.
> +#define AV_BUF_LIVE_GFX_CONFIG (0x0234 >> 2)
> +
> +#define AUDIO_MIXER_REGISTER_OFFSET (0xC000)
> +#define AUDIO_MIXER_VOLUME_CONTROL (0x0000 >> 2)
> +#define AUDIO_MIXER_META_DATA (0x0004 >> 2)
> +#define AUD_CH_STATUS_REG0 (0x0008 >> 2)
> +#define AUD_CH_STATUS_REG1 (0x000C >> 2)
> +#define AUD_CH_STATUS_REG2 (0x0010 >> 2)
> +#define AUD_CH_STATUS_REG3 (0x0014 >> 2)
> +#define AUD_CH_STATUS_REG4 (0x0018 >> 2)
> +#define AUD_CH_STATUS_REG5 (0x001C >> 2)
> +#define AUD_CH_A_DATA_REG0 (0x0020 >> 2)
> +#define AUD_CH_A_DATA_REG1 (0x0024 >> 2)
> +#define AUD_CH_A_DATA_REG2 (0x0028 >> 2)
> +#define AUD_CH_A_DATA_REG3 (0x002C >> 2)
> +#define AUD_CH_A_DATA_REG4 (0x0030 >> 2)
> +#define AUD_CH_A_DATA_REG5 (0x0034 >> 2)
> +#define AUD_CH_B_DATA_REG0 (0x0038 >> 2)
> +#define AUD_CH_B_DATA_REG1 (0x003C >> 2)
> +#define AUD_CH_B_DATA_REG2 (0x0040 >> 2)
> +#define AUD_CH_B_DATA_REG3 (0x0044 >> 2)
> +#define AUD_CH_B_DATA_REG4 (0x0048 >> 2)
> +#define AUD_CH_B_DATA_REG5 (0x004C >> 2)
> +
Index.
> +typedef enum dp_graphic_fmt {
DPGraphicFmt
> + DP_GRAPHIC_RGBA8888 = 0 << 8,
> + DP_GRAPHIC_ABGR8888 = 1 << 8,
> + DP_GRAPHIC_RGB888 = 2 << 8,
> + DP_GRAPHIC_BGR888 = 3 << 8,
> + DP_GRAPHIC_RGBA5551 = 4 << 8,
> + DP_GRAPHIC_RGBA4444 = 5 << 8,
> + DP_GRAPHIC_RGB565 = 6 << 8,
> + DP_GRAPHIC_8BPP = 7 << 8,
> + DP_GRAPHIC_4BPP = 8 << 8,
> + DP_GRAPHIC_2BPP = 9 << 8,
> + DP_GRAPHIC_1BPP = 10 << 8,
> + DP_GRAPHIC_MASK = 0xF << 8
Is it better to define them without the shift and the user handles shifting?
> +} dp_graphic_fmt;
> +
> +typedef enum dp_video_fmt {
DPVideoFmt
> + DP_NL_VID_CB_Y0_CR_Y1 = 0,
> + DP_NL_VID_CR_Y0_CB_Y1 = 1,
> + DP_NL_VID_Y0_CR_Y1_CB = 2,
> + DP_NL_VID_Y0_CB_Y1_CR = 3,
> + DP_NL_VID_YV16 = 4,
> + DP_NL_VID_YV24 = 5,
> + DP_NL_VID_YV16CL = 6,
> + DP_NL_VID_MONO = 7,
> + DP_NL_VID_YV16CL2 = 8,
> + DP_NL_VID_YUV444 = 9,
> + DP_NL_VID_RGB888 = 10,
> + DP_NL_VID_RGBA8880 = 11,
> + DP_NL_VID_RGB888_10BPC = 12,
> + DP_NL_VID_YUV444_10BPC = 13,
> + DP_NL_VID_YV16CL2_10BPC = 14,
> + DP_NL_VID_YV16CL_10BPC = 15,
> + DP_NL_VID_YV16_10BPC = 16,
> + DP_NL_VID_YV24_10BPC = 17,
> + DP_NL_VID_Y_ONLY_10BPC = 18,
> + DP_NL_VID_YV16_420 = 19,
> + DP_NL_VID_YV16CL_420 = 20,
> + DP_NL_VID_YV16CL2_420 = 21,
> + DP_NL_VID_YV16_420_10BPC = 22,
> + DP_NL_VID_YV16CL_420_10BPC = 23,
> + DP_NL_VID_YV16CL2_420_10BPC = 24,
> + DP_NL_VID_FMT_MASK = 0x1F
> +} dp_video_fmt;
> +
> +static const VMStateDescription vmstate_dp = {
> + .name = TYPE_XILINX_DP,
> + .version_id = 1,
> + .fields = (VMStateField[]){
> +
Same comment.
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void xilinx_dp_update_irq(XilinxDPState *s);
> +
> +static uint64_t xilinx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> +
> + offset = offset >> 2;
> +
> + switch (offset) {
> + default:
drop switch.
> + return s->audio_registers[offset];
> + }
> +}
> +
> +static void xilinx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
> + unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> +
> + offset = offset >> 2;
> +
> + switch (offset) {
> + case AUDIO_MIXER_META_DATA:
> + s->audio_registers[offset] = value & 0x00000001;
> + break;
> + default:
> + s->audio_registers[offset] = value;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps audio_ops = {
> + .read = xilinx_dp_audio_read,
> + .write = xilinx_dp_audio_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static inline uint32_t xilinx_dp_audio_get_volume(XilinxDPState *s,
> + uint8_t channel)
> +{
> + switch (channel) {
> + case 0:
> + return s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL] & 0xFFFF;
extract32
> + case 1:
> + return (s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL] >> 16) & 0xFFFF;
extract32
> + default:
> + return 0;
> + }
> +}
> +
> +static inline void xilinx_dp_audio_activate(XilinxDPState *s)
> +{
> + bool activated =
> + ((s->core_registers[DP_TX_AUDIO_CONTROL] & 0x00000001) != 0);
Mask should be macro'd.
> + AUD_set_active_out(s->amixer_output_stream, activated);
> + xilinx_dpdma_set_host_data_location(s->dpdma, 4, &s->audio_buffer_0);
> + xilinx_dpdma_set_host_data_location(s->dpdma, 5, &s->audio_buffer_1);
4, 5 should be macrod. These are the defs of the DMA channels right?
> +}
> +
> +static inline void xilinx_dp_audio_mix_buffer(XilinxDPState *s)
> +{
> + /*
> + * Audio packets are signed and have this shape:
> + * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
> + * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 |
> + *
> + * Output audio is 16bits saturated.
> + */
> + int i;
> +
> + if ((s->audio_data_available[0]) && (xilinx_dp_audio_get_volume(s, 0))) {
> + for (i = 0; i < s->audio_data_available[0] / 2; i++) {
> + s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
> + * xilinx_dp_audio_get_volume(s, 0) / 8192;
> + }
> + s->byte_left = s->audio_data_available[0];
> + } else {
> + memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
> + }
> +
> + if ((s->audio_data_available[1]) && (xilinx_dp_audio_get_volume(s, 1))) {
> + if ((s->audio_data_available[0] == 0)
> + || (s->audio_data_available[1] == s->audio_data_available[0])) {
> + for (i = 0; i < s->audio_data_available[1] / 2; i++) {
> + s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
> + * xilinx_dp_audio_get_volume(s, 1) / 8192;
> + }
> + s->byte_left = s->audio_data_available[1];
> + }
> + }
> +
> + for (i = 0; i < s->byte_left / 2; i++) {
> + s->out_buffer[i] = s->temp_buffer[i];
> + if (s->temp_buffer[i] < -32767) {
> + s->out_buffer[i] = -32767;
> + }
Strange that -32768 is not valid. This means the saturation arithmatic
is using one less than the full 64k range.
> + if (s->temp_buffer[i] > 32767) {
> + s->out_buffer[i] = 32767;
> + }
MIN and MAX macros remove need for ifs.
> + }
> +
> + s->data_ptr = 0;
> +}
> +
> +static void xilinx_dp_audio_callback(void *opaque, int avail)
> +{
> + /*
> + * Get some data from the DPDMA and compute them. Then wait QEMU's audio
> + * subsystem to call this callback.
I think "them" needs more qaulification. Are you reffering to the data?
"wait for" or "wait on".
> + */
> + XilinxDPState *s = XILINX_DP(opaque);
> + size_t written = 0;
> + static uint8_t buffer;
> +
> + /* If there are already some data don't get more data. */
> + if (s->byte_left == 0) {
> + buffer++;
> + s->audio_data_available[0] = xilinx_dpdma_start_operation(s->dpdma, 4,
> + true);
> + s->audio_data_available[1] = xilinx_dpdma_start_operation(s->dpdma, 5,
> + true);
> + xilinx_dp_audio_mix_buffer(s);
> + }
> +
> + /* Send the buffer through the audio. */
> + if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
> + if (s->byte_left != 0) {
> + written = AUD_write(s->amixer_output_stream,
> + &s->out_buffer[s->data_ptr], s->byte_left);
> + } else {
> + /*
> + * There is nothing to play.. We don't have any data! Fill the
> + * buffer with zero's and send it.
> + */
> + written = 0;
> + memset(s->out_buffer, 0, 1024);
> + AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
> + }
> + } else {
> + written = AUD_write(s->amixer_output_stream,
> + &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
> + }
> + s->byte_left -= written;
> + s->data_ptr += written;
> +}
> +
> +/*
> + * AUX channel related function.
> + */
> +static void xilinx_dp_aux_clear_rx_fifo(XilinxDPState *s)
> +{
> + fifo8_reset(&s->rx_fifo);
> +}
> +
> +static void xilinx_dp_aux_push_rx_fifo(XilinxDPState *s, uint8_t *buf,
> + size_t len)
> +{
fifo8_push_all to remove loop. May obsolete the need for this function
and can just do from caller.
> + int i;
> +
> + DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
> + for (i = 0; i < len; i++) {
> + if (fifo8_is_full(&s->rx_fifo)) {
> + DPRINTF("rx_fifo overflow..\n");
> + abort();
> + }
> + fifo8_push(&s->rx_fifo, buf[i]);
> + }
> +}
> +
> +static uint8_t xilinx_dp_aux_pop_rx_fifo(XilinxDPState *s)
> +{
> + uint8_t ret;
> +
> + if (fifo8_is_empty(&s->rx_fifo)) {
> + DPRINTF("rx_fifo underflow..\n");
> + abort();
> + }
> + ret = fifo8_pop(&s->rx_fifo);
> + DPRINTF("pop 0x%2.2X from rx_fifo.\n", ret);
PRIx8
> + return ret;
> +}
> +
> +static void xilinx_dp_aux_clear_tx_fifo(XilinxDPState *s)
> +{
> + fifo8_reset(&s->tx_fifo);
> +}
> +
> +static void xilinx_dp_aux_push_tx_fifo(XilinxDPState *s, uint8_t *buf,
> + size_t len)
> +{
same.
> + int i;
> +
> + DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
> + for (i = 0; i < len; i++) {
> + if (fifo8_is_full(&s->tx_fifo)) {
> + DPRINTF("tx_fifo overflow..\n");
> + abort();
> + }
> + fifo8_push(&s->tx_fifo, buf[i]);
> + }
> +}
> +
> +static uint8_t xilinx_dp_aux_pop_tx_fifo(XilinxDPState *s)
> +{
> + uint8_t ret;
> +
> + if (fifo8_is_empty(&s->tx_fifo)) {
> + DPRINTF("tx_fifo underflow..\n");
> + abort();
> + }
> + ret = fifo8_pop(&s->tx_fifo);
> + DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
> + return ret;
> +}
> +
> +static uint32_t xilinx_dp_aux_get_address(XilinxDPState *s)
> +{
> + return s->core_registers[DP_AUX_ADDRESS];
> +}
> +
> +static uint8_t xilinx_dp_aux_get_data(XilinxDPState *s)
> +{
> + return xilinx_dp_aux_pop_rx_fifo(s);
> +}
> +
> +static void xilinx_dp_aux_set_data(XilinxDPState *s, uint8_t value)
> +{
> + xilinx_dp_aux_push_tx_fifo(s, &value, 1);
> +}
> +
> +/*
> + * Get command from the register.
> + */
> +static void xilinx_dp_aux_set_command(XilinxDPState *s, uint32_t value)
> +{
> + bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
> + aux_command cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
> + uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
> + uint8_t buf[16];
> + int i;
> +
> + /*
> + * When an address_only command is executed nothing happen to the fifo, so
> + * just make nbytes = 0.
> + */
> + if (address_only) {
> + nbytes = 0;
> + }
> +
> + switch (cmd) {
> + case READ_AUX:
> + case READ_I2C:
> + case READ_I2C_MOT:
> + s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
> + xilinx_dp_aux_get_address(s),
> + nbytes, buf);
> + s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
> +
> + if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
> + xilinx_dp_aux_push_rx_fifo(s, buf, nbytes);
> + }
> + break;
> + case WRITE_AUX:
> + case WRITE_I2C:
> + case WRITE_I2C_MOT:
> + for (i = 0; i < nbytes; i++) {
> + buf[i] = xilinx_dp_aux_pop_tx_fifo(s);
> + }
> + s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
> + xilinx_dp_aux_get_address(s),
> + nbytes, buf);
> + xilinx_dp_aux_clear_tx_fifo(s);
> + break;
> + case WRITE_I2C_STATUS:
> + default:
> + abort();
> + break;
> + }
> +
> + s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
> +}
> +
> +static void xilinx_dp_set_dpdma(Object *obj, const char *name, Object *val,
> + Error **errp)
> +{
> + XilinxDPState *s = XILINX_DP(obj);
> + if (s->console) {
> + DisplaySurface *surface = qemu_console_surface(s->console);
> + XilinxDPDMAState *dma = XILINX_DPDMA(val);
> + xilinx_dpdma_set_host_data_location(dma, 3, surface_data(surface));
> + }
> +}
> +
> +static inline uint8_t xilinx_dp_global_alpha_value(XilinxDPState *s)
> +{
> + return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
> +}
> +
> +static inline bool xilinx_dp_global_alpha_enabled(XilinxDPState *s)
> +{
> + /*
> + * If the alpha is totally opaque (255) we don't consider the alpha is
> + * disabled to reduce CPU consumption.
Double negative.
> + */
> + return ((xilinx_dp_global_alpha_value(s) != 0xFF) &&
> + ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
> +}
> +
> +static void xilinx_dp_recreate_surface(XilinxDPState *s)
> +{
> + /*
> + * Two possibilities, if blending is enabled the console display bout_plane,
"displays"
> + * if not g_plane is displayed.
> + */
> + uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
> + uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
> + DisplaySurface *current_console_surface = qemu_console_surface(s->console);
> +
> + if ((width != 0) && (height != 0)) {
> + /*
> + * As dpy_gfx_replace_surface calls qemu_free_displaysurface on the
> + * surface we need to be carefull and don't free the surface associated
> + * to the console or double free will happen.
> + */
> + if (s->bout_plane.surface != current_console_surface) {
> + qemu_free_displaysurface(s->bout_plane.surface);
> + }
> + if (s->v_plane.surface != current_console_surface) {
> + qemu_free_displaysurface(s->v_plane.surface);
> + }
> + if (s->g_plane.surface != current_console_surface) {
> + qemu_free_displaysurface(s->g_plane.surface);
> +
> + }
> +
> + s->g_plane.surface
> + = qemu_create_displaysurface_from(width, height,
> + s->g_plane.format, 0, NULL);
> + s->v_plane.surface
> + = qemu_create_displaysurface_from(width, height,
> + s->v_plane.format, 0, NULL);
> + if (xilinx_dp_global_alpha_enabled(s)) {
> + s->bout_plane.surface =
> + qemu_create_displaysurface_from(width,
> + height,
> + s->g_plane.format,
> + 0, NULL);
> + dpy_gfx_replace_surface(s->console, s->bout_plane.surface);
> + } else {
> + s->bout_plane.surface = NULL;
> + dpy_gfx_replace_surface(s->console, s->g_plane.surface);
> + }
> +
> + xilinx_dpdma_set_host_data_location(s->dpdma, 3,
> + surface_data(s->g_plane.surface));
> + xilinx_dpdma_set_host_data_location(s->dpdma, 0,
> + surface_data(s->v_plane.surface));
> + }
> +}
> +
> +/*
> + * Change the graphic format of the surface.
> + * XXX: To be completed.
> + */
> +static void xilinx_dp_change_graphic_fmt(XilinxDPState *s)
> +{
> + switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
> + case DP_GRAPHIC_RGBA8888:
> + s->g_plane.format = PIXMAN_r8g8b8a8;
> + break;
> + case DP_GRAPHIC_ABGR8888:
> + s->g_plane.format = PIXMAN_a8b8g8r8;
> + break;
> + case DP_GRAPHIC_RGB565:
> + s->g_plane.format = PIXMAN_r5g6b5;
> + break;
> + case DP_GRAPHIC_RGB888:
> + s->g_plane.format = PIXMAN_r8g8b8;
> + break;
> + case DP_GRAPHIC_BGR888:
> + s->g_plane.format = PIXMAN_b8g8r8;
> + break;
> + default:
> + DPRINTF("error: unsupported graphic format %u.\n",
> + s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
> + abort();
> + break;
> + }
> +
> + switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
> + case 0:
> + s->v_plane.format = PIXMAN_r8g8b8a8;
> + break;
> + case DP_NL_VID_RGBA8880:
> + s->v_plane.format = PIXMAN_r8g8b8a8;
> + break;
> + default:
> + DPRINTF("error: unsupported video format %u.\n",
> + s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
> + abort();
> + break;
> + }
> +
> + xilinx_dp_recreate_surface(s);
> +}
> +
> +static void xilinx_dp_update_irq(XilinxDPState *s)
> +{
> + uint32_t flags;
> +
> + flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
> + DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
> + qemu_set_irq(s->irq, flags != 0);
> +}
> +
> +static uint64_t xilinx_dp_read(void *opaque, hwaddr offset, unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> + uint64_t ret = 0;
> +
> + offset = offset >> 2;
> +
> + switch (offset) {
> + /*
> + * Trying to read a write only register.
> + */
> + case DP_TX_USER_FIFO_OVERFLOW:
> + ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
> + s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
> + break;
> + case DP_AUX_WRITE_FIFO:
> + ret = 0;
> + break;
> + case DP_AUX_REPLY_DATA:
> + ret = xilinx_dp_aux_get_data(s);
> + break;
> + case DP_INTERRUPT_SIGNAL_STATE:
> + /*
> + * XXX: Not sure it is the right thing to do actually.
> + * The register is not written by the device driver so it's stuck
> + * to 0x04.
> + */
> + ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
> + s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
> + break;
> + case DP_TX_AUDIO_INFO_DATA0:
> + case DP_TX_AUDIO_INFO_DATA1:
> + case DP_TX_AUDIO_INFO_DATA2:
> + case DP_TX_AUDIO_INFO_DATA3:
> + case DP_TX_AUDIO_INFO_DATA4:
> + case DP_TX_AUDIO_INFO_DATA5:
> + case DP_TX_AUDIO_INFO_DATA6:
> + case DP_TX_AUDIO_INFO_DATA7:
> + case DP_TX_AUDIO_EXT_DATA0:
> + case DP_TX_AUDIO_EXT_DATA1:
> + case DP_TX_AUDIO_EXT_DATA2:
> + case DP_TX_AUDIO_EXT_DATA3:
> + case DP_TX_AUDIO_EXT_DATA4:
> + case DP_TX_AUDIO_EXT_DATA5:
> + case DP_TX_AUDIO_EXT_DATA6:
> + case DP_TX_AUDIO_EXT_DATA7:
> + case DP_TX_AUDIO_EXT_DATA8:
> + /* write only registers */
> + ret = 0;
> + break;
> + default:
> + assert(offset <= (0x3AC >> 2));
> + ret = s->core_registers[offset];
> + break;
> + }
> +
> + DPRINTF("core read @%" PRIx64 " = 0x%8.8lX\n", offset << 2, ret);
> + return ret;
> +}
> +
> +static void xilinx_dp_write(void *opaque, hwaddr offset, uint64_t value,
> + unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> +
> + DPRINTF("core write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
> +
> + offset = offset >> 2;
> +
> + switch (offset) {
> + /*
> + * Only special write case are handled.
> + */
> + case DP_LINK_BW_SET:
> + s->core_registers[offset] = value & 0x000000FF;
> + break;
> + case DP_LANE_COUNT_SET:
> + case DP_MAIN_STREAM_MISC0:
> + s->core_registers[offset] = value & 0x0000000F;
> + break;
> + case DP_TRAINING_PATTERN_SET:
> + case DP_LINK_QUAL_PATTERN_SET:
> + case DP_MAIN_STREAM_POLARITY:
> + case DP_PHY_VOLTAGE_DIFF_LANE_0:
> + case DP_PHY_VOLTAGE_DIFF_LANE_1:
> + s->core_registers[offset] = value & 0x00000003;
> + break;
> + case DP_ENHANCED_FRAME_EN:
> + case DP_SCRAMBLING_DISABLE:
> + case DP_DOWNSPREAD_CTRL:
> + case DP_MAIN_STREAM_ENABLE:
> + case DP_TRANSMIT_PRBS7:
> + s->core_registers[offset] = value & 0x00000001;
> + break;
> + case DP_PHY_CLOCK_SELECT:
> + s->core_registers[offset] = value & 0x00000007;
> + case DP_SOFTWARE_RESET:
> + /*
> + * No need to update this bit as it's read '0'.
> + */
> + /*
> + * TODO: reset IP.
> + */
> + break;
> + case DP_TRANSMITTER_ENABLE:
> + s->core_registers[offset] = value & 0x01;
> + break;
> + case DP_FORCE_SCRAMBLER_RESET:
> + /*
> + * No need to update this bit as it's read '0'.
> + */
> + /*
> + * TODO: force a scrambler reset??
> + */
> + break;
> + case DP_AUX_COMMAND_REGISTER:
> + s->core_registers[offset] = value & 0x00001F0F;
> + xilinx_dp_aux_set_command(s, s->core_registers[offset]);
> + break;
> + case DP_MAIN_STREAM_HTOTAL:
> + case DP_MAIN_STREAM_VTOTAL:
> + case DP_MAIN_STREAM_HSTART:
> + case DP_MAIN_STREAM_VSTART:
> + s->core_registers[offset] = value & 0x0000FFFF;
> + break;
> + case DP_MAIN_STREAM_HRES:
> + case DP_MAIN_STREAM_VRES:
> + s->core_registers[offset] = value & 0x0000FFFF;
> + xilinx_dp_recreate_surface(s);
> + break;
> + case DP_MAIN_STREAM_HSWIDTH:
> + case DP_MAIN_STREAM_VSWIDTH:
> + s->core_registers[offset] = value & 0x00007FFF;
> + break;
> + case DP_MAIN_STREAM_MISC1:
> + s->core_registers[offset] = value & 0x00000086;
> + break;
> + case DP_MAIN_STREAM_M_VID:
> + case DP_MAIN_STREAM_N_VID:
> + s->core_registers[offset] = value & 0x00FFFFFF;
> + break;
> + case DP_MSA_TRANSFER_UNIT_SIZE:
> + case DP_MIN_BYTES_PER_TU:
> + case DP_INIT_WAIT:
> + s->core_registers[offset] = value & 0x00000007;
> + break;
> + case DP_USER_DATA_COUNT_PER_LANE:
> + s->core_registers[offset] = value & 0x0003FFFF;
> + break;
> + case DP_FRAC_BYTES_PER_TU:
> + s->core_registers[offset] = value & 0x000003FF;
> + break;
> + case DP_PHY_RESET:
> + s->core_registers[offset] = value & 0x00010003;
> + /*
> + * TODO: Reset something?
> + */
> + break;
> + case DP_TX_PHY_POWER_DOWN:
> + s->core_registers[offset] = value & 0x0000000F;
> + /*
> + * TODO: Power down things?
> + */
> + break;
> + case DP_AUX_WRITE_FIFO:
> + xilinx_dp_aux_set_data(s, value & 0x0000000F);
> + break;
> + case DP_AUX_CLOCK_DIVIDER:
> + break;
> + case DP_AUX_REPLY_COUNT:
> + /*
> + * Writing to this register clear the counter.
> + */
> + s->core_registers[offset] = 0x00000000;
> + break;
> + case DP_AUX_ADDRESS:
> + s->core_registers[offset] = value & 0x000FFFFF;
> + break;
> + case DP_VERSION_REGISTER:
> + case DP_CORE_ID:
> + case DP_TX_USER_FIFO_OVERFLOW:
> + case DP_AUX_REPLY_DATA:
> + case DP_AUX_REPLY_CODE:
> + case DP_REPLY_DATA_COUNT:
> + case DP_REPLY_STATUS:
> + case DP_HPD_DURATION:
> + /*
> + * Write to read only location..
> + */
> + break;
> + case DP_TX_AUDIO_CONTROL:
> + s->core_registers[offset] = value & 0x00000001;
> + xilinx_dp_audio_activate(s);
> + break;
> + case DP_TX_AUDIO_CHANNELS:
> + s->core_registers[offset] = value & 0x00000007;
> + xilinx_dp_audio_activate(s);
> + break;
> + case DP_INT_STATUS:
> + s->core_registers[DP_INT_STATUS] &= ~value;
> + xilinx_dp_update_irq(s);
> + break;
> + case DP_INT_EN:
> + s->core_registers[DP_INT_MASK] &= ~value;
> + xilinx_dp_update_irq(s);
> + break;
> + case DP_INT_DS:
> + s->core_registers[DP_INT_MASK] |= ~value;
> + xilinx_dp_update_irq(s);
> + break;
> + default:
> + assert(offset <= (0x504C >> 2));
> + s->core_registers[offset] = value;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps dp_ops = {
> + .read = xilinx_dp_read,
> + .write = xilinx_dp_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +/*
> + * This is to handle Read/Write to the Video Blender.
> + */
> +static void xilinx_dp_vblend_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> + bool alpha_was_enabled;
> + assert(size == 4);
> + assert((offset % 4) == 0);
Let memory API enforce aligns and sizes.
> +
> + DPRINTF("vblend: write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
> +
> + offset = offset >> 2;
> +
> + switch (offset) {
> + case V_BLEND_BG_CLR_0:
> + case V_BLEND_BG_CLR_1:
> + case V_BLEND_BG_CLR_2:
> + s->vblend_registers[offset] = value & 0x00000FFF;
> + break;
> + case V_BLEND_SET_GLOBAL_ALPHA_REG:
> + /*
> + * A write to this register can enable or disable blending. Thus we need
> + * to recreate the surfaces.
> + */
> + alpha_was_enabled = xilinx_dp_global_alpha_enabled(s);
> + s->vblend_registers[offset] = value & 0x000001FF;
> + if (xilinx_dp_global_alpha_enabled(s) != alpha_was_enabled) {
> + xilinx_dp_recreate_surface(s);
> + }
> + break;
> + case V_BLEND_OUTPUT_VID_FORMAT:
> + s->vblend_registers[offset] = value & 0x00000017;
> + break;
> + case V_BLEND_LAYER0_CONTROL:
> + case V_BLEND_LAYER1_CONTROL:
> + s->vblend_registers[offset] = value & 0x00000103;
> + break;
> + case V_BLEND_RGB2YCBCR_COEFF0:
> + case V_BLEND_RGB2YCBCR_COEFF1:
> + case V_BLEND_RGB2YCBCR_COEFF2:
> + case V_BLEND_RGB2YCBCR_COEFF3:
> + case V_BLEND_RGB2YCBCR_COEFF4:
> + case V_BLEND_RGB2YCBCR_COEFF5:
> + case V_BLEND_RGB2YCBCR_COEFF6:
> + case V_BLEND_RGB2YCBCR_COEFF7:
> + case V_BLEND_RGB2YCBCR_COEFF8:
> + case V_BLEND_IN1CSC_COEFF0:
> + case V_BLEND_IN1CSC_COEFF1:
> + case V_BLEND_IN1CSC_COEFF2:
> + case V_BLEND_IN1CSC_COEFF3:
> + case V_BLEND_IN1CSC_COEFF4:
> + case V_BLEND_IN1CSC_COEFF5:
> + case V_BLEND_IN1CSC_COEFF6:
> + case V_BLEND_IN1CSC_COEFF7:
> + case V_BLEND_IN1CSC_COEFF8:
> + case V_BLEND_IN2CSC_COEFF0:
> + case V_BLEND_IN2CSC_COEFF1:
> + case V_BLEND_IN2CSC_COEFF2:
> + case V_BLEND_IN2CSC_COEFF3:
> + case V_BLEND_IN2CSC_COEFF4:
> + case V_BLEND_IN2CSC_COEFF5:
> + case V_BLEND_IN2CSC_COEFF6:
> + case V_BLEND_IN2CSC_COEFF7:
> + case V_BLEND_IN2CSC_COEFF8:
> + s->vblend_registers[offset] = value & 0x0000FFFF;
> + break;
> + case V_BLEND_LUMA_IN1CSC_OFFSET:
> + case V_BLEND_CR_IN1CSC_OFFSET:
> + case V_BLEND_CB_IN1CSC_OFFSET:
> + case V_BLEND_LUMA_IN2CSC_OFFSET:
> + case V_BLEND_CR_IN2CSC_OFFSET:
> + case V_BLEND_CB_IN2CSC_OFFSET:
> + case V_BLEND_LUMA_OUTCSC_OFFSET:
> + case V_BLEND_CR_OUTCSC_OFFSET:
> + case V_BLEND_CB_OUTCSC_OFFSET:
> + s->vblend_registers[offset] = value & 0x3FFF7FFF;
> + break;
> + case V_BLEND_CHROMA_KEY_ENABLE:
> + s->vblend_registers[offset] = value & 0x00000003;
> + break;
> + case V_BLEND_CHROMA_KEY_COMP1:
> + case V_BLEND_CHROMA_KEY_COMP2:
> + case V_BLEND_CHROMA_KEY_COMP3:
> + s->vblend_registers[offset] = value & 0x0FFF0FFF;
> + break;
> + default:
> + s->vblend_registers[offset] = value;
> + break;
> + }
> +}
> +
> +static uint64_t xilinx_dp_vblend_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> + uint32_t ret;
> +
> + offset = offset >> 2;
> +
> + ret = s->vblend_registers[offset];
> + DPRINTF("vblend: read @%" PRIx64 " = 0x%8.8X\n", offset << 2, ret);
> + return ret;
> +}
> +
> +static const MemoryRegionOps vblend_ops = {
> + .read = xilinx_dp_vblend_read,
> + .write = xilinx_dp_vblend_write,
Access restrictions can be defined here.
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +/*
> + * This is to handle Read/Write to the Audio Video buffer manager.
> + */
> +static void xilinx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
> + unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> +
Missing DPRINTF?
> + offset = offset >> 2;
> +
> + switch (offset) {
> + case AV_BUF_FORMAT:
> + s->avbufm_registers[offset] = value & 0x00000FFF;
> + xilinx_dp_change_graphic_fmt(s);
> + break;
> + case AV_CHBUF0:
> + case AV_CHBUF1:
> + case AV_CHBUF2:
> + case AV_CHBUF3:
> + case AV_CHBUF4:
> + case AV_CHBUF5:
> + s->avbufm_registers[offset] = value & 0x0000007F;
> + break;
> + case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
> + s->avbufm_registers[offset] = value & 0x0000007F;
> + break;
> + case AV_BUF_DITHER_CONFIG:
> + s->avbufm_registers[offset] = value & 0x000007FF;
> + break;
> + case AV_BUF_DITHER_CONFIG_MAX:
> + case AV_BUF_DITHER_CONFIG_MIN:
> + s->avbufm_registers[offset] = value & 0x00000FFF;
> + break;
> + case AV_BUF_PATTERN_GEN_SELECT:
> + s->avbufm_registers[offset] = value & 0xFFFFFF03;
> + break;
> + case AV_BUF_AUD_VID_CLK_SOURCE:
> + s->avbufm_registers[offset] = value & 0x00000007;
> + break;
> + case AV_BUF_SRST_REG:
> + s->avbufm_registers[offset] = value & 0x00000002;
> + break;
> + case AV_BUF_AUDIO_CH_CONFIG:
> + s->avbufm_registers[offset] = value & 0x00000003;
> + break;
> + case AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR:
> + case AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR:
> + case AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR:
> + case AV_BUF_VIDEO_COMP0_SCALE_FACTOR:
> + case AV_BUF_VIDEO_COMP1_SCALE_FACTOR:
> + case AV_BUF_VIDEO_COMP2_SCALE_FACTOR:
> + s->avbufm_registers[offset] = value & 0x0000FFFF;
> + break;
> + case AV_BUF_LIVE_VIDEO_COMP0_SF:
> + case AV_BUF_LIVE_VIDEO_COMP1_SF:
> + case AV_BUF_LIVE_VIDEO_COMP2_SF:
> + case AV_BUF_LIVE_VID_CONFIG:
> + case AV_BUF_LIVE_GFX_COMP0_SF:
> + case AV_BUF_LIVE_GFX_COMP1_SF:
> + case AV_BUF_LIVE_GFX_COMP2_SF:
> + case AV_BUF_LIVE_GFX_CONFIG:
> + case AV_BUF_NON_LIVE_LATENCY:
> + case AV_BUF_STC_CONTROL:
> + case AV_BUF_STC_INIT_VALUE0:
> + case AV_BUF_STC_INIT_VALUE1:
> + case AV_BUF_STC_ADJ:
> + case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
> + case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
> + case AV_BUF_STC_EXT_VSYNC_TS_REG0:
> + case AV_BUF_STC_EXT_VSYNC_TS_REG1:
> + case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
> + case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
> + case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
> + case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
> + case AV_BUF_STC_SNAPSHOT0:
> + case AV_BUF_STC_SNAPSHOT1:
> + case AV_BUF_HCOUNT_VCOUNT_INT0:
> + case AV_BUF_HCOUNT_VCOUNT_INT1:
> + /*
> + * Non implemented.
> + */
qemu_log_mask(LOG_UNIMP,
> + break;
> + default:
> + s->avbufm_registers[offset] = value;
> + break;
> + }
> +}
> +
> +static uint64_t xilinx_dp_avbufm_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> + assert(size == 4);
> + assert((offset % 4) == 0);
> +
> + offset = offset >> 2;
> +
> + return s->avbufm_registers[offset];
> +}
> +
> +static const MemoryRegionOps avbufm_ops = {
> + .read = xilinx_dp_avbufm_read,
> + .write = xilinx_dp_avbufm_write,
same comments WRT align and size.
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +/*
> + * This is a global alpha blending using pixman.
> + * Both graphic and video planes are multiplied with the global alpha
> + * coefficient and added.
> + */
> +static inline void xilinx_dp_blend_surface(XilinxDPState *s)
> +{
> + pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
> + pixman_double_to_fixed(1),
> + pixman_double_to_fixed(1.0) };
> + pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
> + pixman_double_to_fixed(1),
> + pixman_double_to_fixed(1.0) };
> +
> + if ((surface_width(s->g_plane.surface)
> + != surface_width(s->v_plane.surface)) ||
> + (surface_height(s->g_plane.surface)
> + != surface_height(s->v_plane.surface))) {
> + return;
> + }
> +
> + alpha1[2] = pixman_double_to_fixed((double)(xilinx_dp_global_alpha_value(s))
> + / 256.0);
> + alpha2[2] = pixman_double_to_fixed((255.0
> + - (double)xilinx_dp_global_alpha_value(s))
> + / 256.0);
> +
> + pixman_image_set_filter(s->g_plane.surface->image,
> + PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
> + pixman_image_composite(PIXMAN_OP_SRC, s->g_plane.surface->image, 0,
> + s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
> + surface_width(s->g_plane.surface),
> + surface_height(s->g_plane.surface));
> + pixman_image_set_filter(s->v_plane.surface->image,
> + PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
> + pixman_image_composite(PIXMAN_OP_ADD, s->v_plane.surface->image, 0,
> + s->bout_plane.surface->image, 0, 0, 0, 0, 0, 0,
> + surface_width(s->g_plane.surface),
> + surface_height(s->g_plane.surface));
> +}
> +
> +static void xilinx_dp_update_display(void *opaque)
> +{
> + XilinxDPState *s = XILINX_DP(opaque);
> +
> + if (DEBUG_DP) {
> + int64_t last_time = 0;
> + int64_t frame = 0;
> + int64_t time = get_clock();
> + int64_t fps;
> +
> + if (last_time == 0) {
> + last_time = get_clock();
> + }
> + frame++;
> + if (last_time + 1000000000 < time) {
> + fps = (1000000000.0 * frame) / (time - last_time);
> + last_time = time;
> + frame = 0;
> + DPRINTF("xilinx_dp: %ldfps\n", fps);
> + }
> + }
> +
> +
> + if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
> + return;
> + }
> +
> + s->core_registers[DP_INT_STATUS] |= (1 << 13);
> + xilinx_dp_update_irq(s);
> +
> + /*
> + * Trigger the DMA channel.
> + */
> + if (!xilinx_dpdma_start_operation(s->dpdma, 3, false)) {
> + /*
> + * An error occured don't do anything with the data..
> + * Trigger an underflow interrupt.
> + */
> + s->core_registers[DP_INT_STATUS] |= (1 << 21);
> + xilinx_dp_update_irq(s);
> + return;
> + }
> +
> + if (xilinx_dp_global_alpha_enabled(s)) {
> + if (!xilinx_dpdma_start_operation(s->dpdma, 0, false)) {
> + s->core_registers[DP_INT_STATUS] |= (1 << 21);
> + xilinx_dp_update_irq(s);
> + return;
> + }
> + xilinx_dp_blend_surface(s);
> + }
> +
> + /*
> + * XXX: We might want to update only what changed.
> + */
> + dpy_gfx_update(s->console, 0, 0, surface_width(s->g_plane.surface),
> + surface_height(s->g_plane.surface));
> +}
> +
> +static void xilinx_dp_invalidate_display(void *opaque)
> +{
> +
> +}
> +
Should the gfx core just null guard this?
> +static const GraphicHwOps xilinx_dp_gfx_ops = {
> + .invalidate = xilinx_dp_invalidate_display,
> + .gfx_update = xilinx_dp_update_display,
> +};
> +
> +static void xilinx_dp_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + XilinxDPState *s = XILINX_DP(obj);
> +
> + memory_region_init(&s->container, obj, TYPE_XILINX_DP, 0xC050);
> +
> + memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XILINX_DP
> + ".core", 0x3AF);
> + memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
> +
> + memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XILINX_DP
> + ".v_blend", 0x1DF);
> + memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
> +
> + memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XILINX_DP
> + ".av_buffer_manager", 0x238);
> + memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
> + memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XILINX_DP
> + ".audio", sizeof(s->audio_registers));
> + memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
> + sysbus_init_mmio(sbd, &s->container);
> +
> + sysbus_init_irq(sbd, &s->irq);
> +
> + object_property_add_link(obj, "dpdma", TYPE_XILINX_DPDMA,
> + (Object **) &s->dpdma,
> + xilinx_dp_set_dpdma,
> + OBJ_PROP_LINK_UNREF_ON_RELEASE,
> + &error_abort);
> +
> + s->byte_left = 0;
Is this device state and should it be in reset?
> +
> + /*
> + * Initialize AUX Bus.
> + */
> + s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
> +
> + /*
> + * Initialize DPCD and EDID..
> + */
> + s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
> + s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
Are these off-chip and should be created by the machine model?
> + i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
> +}
> +
> +static void xilinx_dp_realize(DeviceState *dev, Error **errp)
> +{
> + XilinxDPState *s = XILINX_DP(dev);
> + DisplaySurface *surface;
> +
> + s->console = graphic_console_init(dev, 0, &xilinx_dp_gfx_ops, s);
> + surface = qemu_console_surface(s->console);
> + xilinx_dpdma_set_host_data_location(s->dpdma, 3, surface_data(surface));
> + fifo8_create(&s->rx_fifo, 16);
> + fifo8_create(&s->tx_fifo, 16);
fifo_creates should move to _init
> +
> + /* Audio */
> + struct audsettings as;
def should move up top of fn.
> + as.freq = 44100;
> + as.nchannels = 2;
> + as.fmt = AUD_FMT_S16;
> + as.endianness = 0;
> +
> + AUD_register_card("xilinx_dp.audio", &s->aud_card);
> +
> + s->amixer_output_stream = AUD_open_out(&s->aud_card,
> + s->amixer_output_stream,
> + "xilinx_dp.audio.out",
> + s,
> + xilinx_dp_audio_callback,
> + &as);
> + AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
> + xilinx_dp_audio_activate(s);
> +}
> +
> +static void xilinx_dp_reset(DeviceState *dev)
> +{
> + XilinxDPState *s = XILINX_DP(dev);
> +
> + /*
> + * Reset the Display Port registers.
> + */
self documenting.
> + memset(s->core_registers, 0, sizeof(s->core_registers));
> + s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
> + s->core_registers[DP_CORE_ID] = 0x01020000;
> + s->core_registers[DP_REPLY_STATUS] = 0x00000010;
> + s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
> + s->core_registers[DP_INIT_WAIT] = 0x00000020;
> + s->core_registers[DP_PHY_RESET] = 0x00010003;
> + s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
> +
> + s->core_registers[DP_PHY_STATUS] = 0x00000043;
> + s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
> +
> + /*
> + * Video Blender register reset.
> + */
> + s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF0] = 0x00001000;
> + s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF4] = 0x00001000;
> + s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF8] = 0x00001000;
> + s->vblend_registers[V_BLEND_IN1CSC_COEFF0] = 0x00001000;
> + s->vblend_registers[V_BLEND_IN1CSC_COEFF4] = 0x00001000;
> + s->vblend_registers[V_BLEND_IN1CSC_COEFF8] = 0x00001000;
> + s->vblend_registers[V_BLEND_IN2CSC_COEFF0] = 0x00001000;
> + s->vblend_registers[V_BLEND_IN2CSC_COEFF4] = 0x00001000;
> + s->vblend_registers[V_BLEND_IN2CSC_COEFF8] = 0x00001000;
Probably loopable once the indexing macros are defined.
> +
> + /*
> + * Audio Video Buffer Manager register reset.
> + */
> + s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
> + s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
> + s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
> + s->avbufm_registers[AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR] = 0x00010101;
> + s->avbufm_registers[AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR] = 0x00010101;
> + s->avbufm_registers[AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR] = 0x00010101;
> + s->avbufm_registers[AV_BUF_VIDEO_COMP0_SCALE_FACTOR] = 0x00010101;
> + s->avbufm_registers[AV_BUF_VIDEO_COMP1_SCALE_FACTOR] = 0x00010101;
> + s->avbufm_registers[AV_BUF_VIDEO_COMP2_SCALE_FACTOR] = 0x00010101;
> + s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP0_SF] = 0x00010101;
> + s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP1_SF] = 0x00010101;
> + s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP2_SF] = 0x00010101;
> + s->avbufm_registers[AV_BUF_LIVE_GFX_COMP0_SF] = 0x00010101;
> + s->avbufm_registers[AV_BUF_LIVE_GFX_COMP1_SF] = 0x00010101;
> + s->avbufm_registers[AV_BUF_LIVE_GFX_COMP2_SF] = 0x00010101;
> +
Same.
> + /*
> + * Audio register reset.
> + */
> + memset(s->audio_registers, 0, sizeof(s->audio_registers));
> +
> + xilinx_dp_aux_clear_rx_fifo(s);
> + xilinx_dp_change_graphic_fmt(s);
> +}
> +
> +static void xilinx_dp_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->realize = xilinx_dp_realize;
> + dc->vmsd = &vmstate_dp;
> + dc->reset = xilinx_dp_reset;
> +}
> +
> +static const TypeInfo xilinx_dp_info = {
> + .name = TYPE_XILINX_DP,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XilinxDPState),
> + .instance_init = xilinx_dp_init,
> + .class_init = xilinx_dp_class_init,
> +};
> +
> +static void xilinx_dp_register_types(void)
> +{
> + type_register_static(&xilinx_dp_info);
> +}
> +
> +type_init(xilinx_dp_register_types)
> diff --git a/hw/display/xilinx_dp.h b/hw/display/xilinx_dp.h
> new file mode 100644
> index 0000000..44fdefd
> --- /dev/null
> +++ b/hw/display/xilinx_dp.h
> @@ -0,0 +1,129 @@
> +/*
> + * xilinx_dp.h
> + *
> + * Copyright (C) 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#include "hw/sysbus.h"
> +#include "ui/console.h"
> +#include "hw/aux.h"
> +#include "hw/i2c/i2c.h"
> +#include "hw/display/dpcd.h"
> +#include "hw/i2c/i2c-ddc.h"
> +#include "qemu/fifo8.h"
> +#include "hw/dma/xilinx_dpdma.h"
> +#include "audio/audio.h"
> +
> +#ifndef XILINX_DP_H
> +#define XILINX_DP_H
> +
> +#define AUD_CHBUF_MAX_DEPTH 32768
Is this related to the 32767 saturation logic and should this def be used there?
> +#define MAX_QEMU_BUFFER_SIZE 4096
> +
> +struct PixmanPlane {
> + pixman_format_code_t format;
> + DisplaySurface *surface;
> +};
> +
Does this concept belong in core code?
> +struct XilinxDPState {
/*< private >*/
> + SysBusDevice parent_obj;
/*< public >*/
> + MemoryRegion container;
> +
> + /*
> + * Registers for the Core.
> + */
self documenting.
> + uint32_t core_registers[0x3AF >> 2];
> + MemoryRegion core_iomem;
> +
> + /*
> + * Registers for Audio Video Buffer Manager.
> + */
> + uint32_t avbufm_registers[0x238 >> 2];
> + MemoryRegion avbufm_iomem;
> +
> + /*
> + * Register for Video Blender.
> + */
> + uint32_t vblend_registers[0x1DF >> 2];
> + MemoryRegion vblend_iomem;
> +
> + /*
> + * Registers for Audio.
> + */
> + uint32_t audio_registers[0x50 >> 2];
> + MemoryRegion audio_iomem;
> +
> + QemuConsole *console;
> +
> + /*
> + * This is the planes used to display in console. When the blending is
> + * enabled bout_plane is displayed in console else it's g_plane.
> + */
> + struct PixmanPlane g_plane;
> + struct PixmanPlane v_plane;
> + struct PixmanPlane bout_plane;
> +
> + /*
> + * Audio related.
> + */
> + QEMUSoundCard aud_card;
> + SWVoiceOut *amixer_output_stream;
> + int16_t audio_buffer_0[AUD_CHBUF_MAX_DEPTH];
> + int16_t audio_buffer_1[AUD_CHBUF_MAX_DEPTH];
> + size_t audio_data_available[2];
> + int64_t temp_buffer[AUD_CHBUF_MAX_DEPTH];
> + int16_t out_buffer[AUD_CHBUF_MAX_DEPTH];
> + size_t byte_left; /* byte available in out_buffer. */
> + size_t data_ptr; /* next byte to be sent to QEMU. */
> +
> + /*
> + * Associated DPDMA controller.
> + */
> + XilinxDPDMAState *dpdma;
> +
> + /*
> + * IRQ.
> + */
Self doc.
> + qemu_irq irq;
> +
> + /*
> + * AUX bus.
> + */
Self doc.
> + AUXBus *aux_bus;
> +
> + Fifo8 rx_fifo;
> + Fifo8 tx_fifo;
> +
> + uint32_t last_request;
> +
> + /*
> + * XXX: This should be in an other module.
> + */
Probably the machine model.
Regards,
Peter
> + DPCDState *dpcd;
> + I2CDDCState *edid;
> +};
> +
> +typedef struct XilinxDPState XilinxDPState;
> +
> +#define TYPE_XILINX_DP "xlnx.v-dp"
> +#define XILINX_DP(obj) OBJECT_CHECK(XilinxDPState, (obj), TYPE_XILINX_DP)
> +
> +#endif /* !XILINX_DP_H */
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 7/7] arm: xlnx-zynqmp: Add DisplayPort and DPDMA.
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 7/7] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
@ 2015-06-24 8:23 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-06-24 8:23 UTC (permalink / raw)
To: Fréderic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This adds the DP and the DPDMA to the Zynq MP.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
> hw/arm/xlnx-zynqmp.c | 20 ++++++++++++++++++++
> include/hw/arm/xlnx-zynqmp.h | 4 ++++
> 2 files changed, 24 insertions(+)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 6b01965..c29046a 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -28,6 +28,12 @@
> #define GIC_DIST_ADDR 0xf9010000
> #define GIC_CPU_ADDR 0xf9020000
>
> +#define DP_ADDR 0xfd4a0000
> +#define DP_IRQ 113
> +
> +#define DPDMA_ADDR 0xfd4c0000
> +#define DPDMA_IRQ 116
> +
> static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
> 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
> };
> @@ -83,6 +89,11 @@ static void xlnx_zynqmp_init(Object *obj)
> object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
> qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
> }
> +
> + object_initialize(&s->dp, sizeof(s->dp), TYPE_XILINX_DP);
> + qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
> + object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XILINX_DPDMA);
> + qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
> }
>
> static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> @@ -186,6 +197,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
> gic_spi[uart_intr[i]]);
> }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
> + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
> + object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
> + object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
> + &error_abort);
> }
>
> static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 79c2b0b..66ec010 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -22,6 +22,8 @@
> #include "hw/intc/arm_gic.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/char/cadence_uart.h"
> +#include "hw/dma/xilinx_dpdma.h"
> +#include "hw/display/xilinx_dp.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
> #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
> @@ -52,6 +54,8 @@ typedef struct XlnxZynqMPState {
> MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
> CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
> CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
> + XilinxDPState dp;
> + XilinxDPDMAState dpdma;
> } XlnxZynqMPState;
>
> #define XLNX_ZYNQMP_H
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus.
2015-06-24 6:21 ` Peter Crosthwaite
@ 2015-07-06 16:27 ` Frederic Konrad
0 siblings, 0 replies; 20+ messages in thread
From: Frederic Konrad @ 2015-07-06 16:27 UTC (permalink / raw)
To: Peter Crosthwaite, Markus Armbruster
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On 24/06/2015 08:21, Peter Crosthwaite wrote:
> On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This introduces a new bus: aux-bus.
>>
>> It contains an address space for aux slaves devices and a bridge to an I2C bus
>> for I2C through AUX transactions.
>>
>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>> ---
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/aux.c | 411 ++++++++++++++++++++++++++++++++++++++++++++++++++
>> include/hw/aux.h | 116 ++++++++++++++
>> 3 files changed, 528 insertions(+)
>> create mode 100644 hw/misc/aux.c
>> create mode 100644 include/hw/aux.h
>>
>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
>> index 4aa76ff..11a721f 100644
>> --- a/hw/misc/Makefile.objs
>> +++ b/hw/misc/Makefile.objs
>> @@ -40,3 +40,4 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
>>
>> obj-$(CONFIG_PVPANIC) += pvpanic.o
>> obj-$(CONFIG_EDU) += edu.o
>> +obj-$(CONFIG_XLNX_ZYNQMP) += aux.o
> Aux is not ZYNQ specific, it should have its own config that is just
> set by the aarch64 defconfig.
>
>> diff --git a/hw/misc/aux.c b/hw/misc/aux.c
>> new file mode 100644
>> index 0000000..b72608e
>> --- /dev/null
>> +++ b/hw/misc/aux.c
>> @@ -0,0 +1,411 @@
>> +/*
>> + * aux.c
>> + *
>> + * Copyright 2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option)any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +/*
>> + * This is an implementation of the AUX bus for VESA Display Port v1.1a.
>> + */
>> +
>> +#include "hw/aux.h"
>> +#include "hw/i2c/i2c.h"
>> +#include "monitor/monitor.h"
>> +
>> +/* #define DEBUG_AUX */
> Just drop the commented out define.
>
>> +
>> +#ifdef DEBUG_AUX
>> +#define DPRINTF(fmt, ...)\
>> +do { printf("aux: " fmt , ## __VA_ARGS__); } while (0)
> Use a regular if for conditional debug prinfery.
>
> Also do not use printf, use qemu_log.
>
>> +#else
>> +#define DPRINTF(fmt, ...)do {} while (0)
>> +#endif
>> +
>> +#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
>> +#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
>> +
>> +typedef struct AUXTOI2CState AUXTOI2CState;
>> +
>> +struct AUXBus {
> /*< private >*/
>
>> + BusState qbus;
> /*< public > */
>
>> + AUXSlave *current_dev;
>> + AUXSlave *dev;
>> + uint32_t last_i2c_address;
>> + aux_command last_transaction;
>> +
>> + AUXTOI2CState *bridge;
>> +
>> + MemoryRegion *aux_io;
>> + AddressSpace aux_addr_space;
>> +};
> Modern QOM conventions require the state struct to be in a header.
> This allows for embedding the device its containers.
>
>> +
>> +static Property aux_props[] = {
>> + DEFINE_PROP_UINT64("address", struct AUXSlave, address, 0),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +#define TYPE_AUX_BUS "aux-bus"
>> +#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
>> +
>> +static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
>> +
>> +static void aux_bus_class_init(ObjectClass *klass, void *data)
>> +{
>> + /*
>> + * AUXSlave has an mmio so we need to change the way we print information
> MMIO
>
>> + * in monitor.
>> + */
> Can you move the comment below the declaration?
>
>> + BusClass *k = BUS_CLASS(klass);
> blank line.
>
>> + k->print_dev = aux_slave_dev_print;
>> +}
>> +
>> +static const TypeInfo aux_bus_info = {
>> + .name = TYPE_AUX_BUS,
>> + .parent = TYPE_BUS,
>> + .instance_size = sizeof(AUXBus),
>> + .class_init = aux_bus_class_init
>> +};
>> +
>> +AUXBus *aux_init_bus(DeviceState *parent, const char *name)
>> +{
>> + AUXBus *bus;
>> +
>> + bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
>> +
>> + /*
>> + * Create the bridge.
>> + */
> Code is self documenting, comment unneeded.
>
>> + bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
>> +
>> + /*
>> + * Memory related.
>> + */
> Make a one-line comment.
>
>> + bus->aux_io = g_malloc(sizeof(*bus->aux_io));
>> + memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
>> + address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
>> + return bus;
>> +}
>> +
>> +static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev)
>> +{
>> + memory_region_add_subregion(bus->aux_io, dev->address, dev->mmio);
>> +}
>> +
>> +void aux_set_slave_address(AUXSlave *dev, uint32_t address)
>> +{
>> + qdev_prop_set_uint64(DEVICE(dev), "address", address);
>> +}
>> +
> Do these two need to be separate? Can you just pass the address to
> aux_bus_map_device and remove the .address field from the bus?
>
>> +static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
>> +{
>> + return (dev == DEVICE(bus->bridge));
>> +}
>> +
>> +/*
>> + * Make a native request on the AUX bus.
>> + */
>> +static aux_reply aux_native_request(AUXBus *bus, aux_command cmd,
>> + uint32_t address, uint8_t len,
>> + uint8_t *data)
>> +{
>> + /*
>> + * Transactions on aux address map are 1bytes len time.
>> + */
>> + aux_reply ret = AUX_NACK;
>> + size_t i;
>> +
>> + switch (cmd) {
>> + case READ_AUX:
>> + for (i = 0; i < len; i++) {
>> + if (!address_space_rw(&bus->aux_addr_space, address++,
>> + MEMTXATTRS_UNSPECIFIED, data++, 1, false)) {
> address_space_read. Although ...
>
>> + ret = AUX_I2C_ACK;
>> + } else {
>> + ret = AUX_NACK;
>> + break;
>> + }
>> + }
>> + break;
>> + case WRITE_AUX:
> You can remove the code duplication with:
>
> switch(cmd) {
> case (WRITE_AUX):
> is_write = true;
> /* fallthrough */
> case (READ_AUX):
> for(...) {
> address_space_rw(..., is_write);
>
>> + for (i = 0; i < len; i++) {
>> + if (!address_space_rw(&bus->aux_addr_space, address++,
>> + MEMTXATTRS_UNSPECIFIED, data++, 1, true)) {
>> + ret = AUX_I2C_ACK;
>> + } else {
>> + ret = AUX_NACK;
>> + break;
>> + }
>> + }
>> + break;
>> + default:
>> + abort();
> g_assert_not_reached
>
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
>> + uint8_t len, uint8_t *data)
>> +{
>> + DPRINTF("request at address 0x%5.5X, command %u, len %u\n", address, cmd,
>> + len);
> PRIx32
>
>> +
>> + int temp;
>> + aux_reply ret = AUX_NACK;
>> + I2CBus *i2c_bus = aux_get_i2c_bus(bus);
>> +
> The DRPINTF before the declarations is a C99 mixed code and decls
> which is discouraged. Do the DPRINTF after the decls.
>
>> + switch (cmd) {
>> + /*
>> + * Forward the request on the AUX bus..
>> + */
>> + case WRITE_AUX:
>> + case READ_AUX:
>> + ret = aux_native_request(bus, cmd, address, len, data);
>> + break;
> indentation.
>
>> + /*
>> + * Classic I2C transactions..
>> + */
>> + case READ_I2C:
>> + if (i2c_bus_busy(i2c_bus)) {
>> + i2c_end_transfer(i2c_bus);
>> + }
>> +
>> + if (i2c_start_transfer(i2c_bus, address, 1)) {
>> + ret = AUX_I2C_NACK;
>> + break;
>> + }
>> +
>> + while (len > 0) {
>> + temp = i2c_recv(i2c_bus);
>> +
>> + if (temp < 0) {
>> + ret = AUX_I2C_NACK;
> This nack ...
>
>> + i2c_end_transfer(i2c_bus);
>> + break;
>> + }
>> +
>> + *data++ = temp;
>> + len--;
>> + }
>> + i2c_end_transfer(i2c_bus);
>> + ret = AUX_I2C_ACK;
> ... will get overridden by this ack.
>
>> + break;
> Indentation.
>
>> + case WRITE_I2C:
>> + if (i2c_bus_busy(i2c_bus)) {
>> + i2c_end_transfer(i2c_bus);
>> + }
>> +
>> + if (i2c_start_transfer(i2c_bus, address, 0)) {
>> + ret = AUX_I2C_NACK;
>> + break;
>> + }
>> +
>> + while (len > 0) {
>> + if (!i2c_send(i2c_bus, *data++)) {
>> + ret = AUX_I2C_NACK;
>> + i2c_end_transfer(i2c_bus);
>> + break;
>> + }
>> + len--;
>> + }
>> + i2c_end_transfer(i2c_bus);
>> + ret = AUX_I2C_ACK;
> same. You might be needing a goto from those in-the-loop nacks, but
> the shortest way I can think of is:
>
> ret = AUX_I2C_ACK;
> while (...) {
> if (!i2c_send) {
> ret = NACK;
> break;
> }
> len--;
> }
> i2c_end_transfer(...).
>
>> + break;
>> + /*
>> + * I2C MOT transactions.
>> + *
>> + * Here we send a start when:
>> + * - We didn't start transaction yet.
>> + * - We had a READ and we do a WRITE.
>> + * - We change the address.
> "changed"
>
>> + */
>> + case WRITE_I2C_MOT:
>> + if (!i2c_bus_busy(i2c_bus)) {
>> + /*
>> + * No transactions started..
>> + */
>> + if (i2c_start_transfer(i2c_bus, address, 0)) {
>> + ret = AUX_I2C_NACK;
>> + break;
>> + }
>> + } else if ((address != bus->last_i2c_address) ||
>> + (bus->last_transaction == READ_I2C_MOT)) {
>> + /*
>> + * Transaction started but we need to restart..
>> + */
>> + i2c_end_transfer(i2c_bus);
>> + if (i2c_start_transfer(i2c_bus, address, 0)) {
>> + ret = AUX_I2C_NACK;
>> + break;
>> + }
>> + }
>> +
>> + while (len > 0) {
>> + if (!i2c_send(i2c_bus, *data++)) {
>> + ret = AUX_I2C_NACK;
>> + i2c_end_transfer(i2c_bus);
>> + break;
>> + }
>> + len--;
>> + }
>> + bus->last_transaction = WRITE_I2C_MOT;
>> + bus->last_i2c_address = address;
>> + ret = AUX_I2C_ACK;
>> + break;
>> + case READ_I2C_MOT:
> This read vs write code is very similar from one to the other. It can
> be factored out as such:
>
> case WRITE_I2C_MOT:
> is_write = true;
> /*fallthrough */
> case READ_I2C_MOT:
>
>
>> + if (!i2c_bus_busy(i2c_bus)) {
>> + /*
>> + * No transactions started..
>> + */
>> + if (i2c_start_transfer(i2c_bus, address, 0)) {
>> + ret = AUX_I2C_NACK;
>> + break;
>> + }
>> + } else if (address != bus->last_i2c_address) {
> The restart condition here is different to write. Mainly, you do not
> restart on a change from write to read. Perhaps worth a comment, or
> list-comment the read restart conditions like you did for write.
>
>> + /*
>> + * Transaction started but we need to restart..
>> + */
>> + i2c_end_transfer(i2c_bus);
>> + if (i2c_start_transfer(i2c_bus, address, 0)) {
>> + ret = AUX_I2C_NACK;
>> + break;
>> + }
>> + }
>> +
>> + while (len > 0) {
> if (is_write) {
> i2c_err = i2c_send(...) ? - 1 : 0;
> } else {
>> + temp = i2c_recv(i2c_bus);
> i2c_err = temp < 0;
> }
>
>> +
>> + if (temp < 0) {
>> + ret = AUX_I2C_NACK;
>> + i2c_end_transfer(i2c_bus);
>> + break;
>> + }
>> +
> if (is_write) {
>> + *data++ = temp;
> }
>
>> + len--;
>> + }
>> + bus->last_transaction = READ_I2C_MOT;
>> + bus->last_i2c_address = address;
>> + ret = AUX_I2C_ACK;
>> + break;
>> + default:
>> + DPRINTF("Not implemented!\n");
>> + ret = AUX_NACK;
>> + break;
>> + }
>> +
>> + DPRINTF("reply: %u\n", ret);
>> + return ret;
>> +}
>> +
>> +/*
>> + * AUX to I2C bridge.
>> + */
>> +struct AUXTOI2CState {
> /*< private >*/
>
>> + DeviceState parent_obj;
> /*< public >*/
>
>> + I2CBus *i2c_bus;
>> +};
> Will need to move to the header.
This AUXTOI2C is only used here in aux.c.. I don't think it should be
public?
>
>> +
>> +I2CBus *aux_get_i2c_bus(AUXBus *bus)
>> +{
>> + return bus->bridge->i2c_bus;
>> +}
>> +
>> +static void aux_bridge_init(Object *obj)
>> +{
>> + AUXTOI2CState *s = AUXTOI2C(obj);
>> + /*
>> + * Create the I2C Bus.
>> + */
> self documenting.
>
>> + s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
>> +}
>> +
>> +static const TypeInfo aux_to_i2c_type_info = {
>> + .name = TYPE_AUXTOI2C,
>> + .parent = TYPE_DEVICE,
>> + .instance_size = sizeof(AUXTOI2CState),
>> + .instance_init = aux_bridge_init
>> +};
>> +
>> +/*
>> + * AUX Slave.
>> + */
>> +static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
>> +{
>> + AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
>> + hwaddr size;
>> + AUXSlave *s;
>> +
>> + /*
>> + * Don't print anything if the device is I2C "bridge".
>> + */
>> + if (aux_bus_is_bridge(bus, dev)) {
>> + return;
>> + }
>> +
>> + s = AUX_SLAVE(dev);
>> +
>> + size = memory_region_size(s->mmio);
>> + monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
>> + indent, "", s->address, size);
>> +}
>> +
>> +DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr)
>> +{
>> + DeviceState *dev;
>> +
>> + dev = qdev_create(&bus->qbus, name);
>> + qdev_prop_set_uint64(dev, "address", addr);
>> + qdev_init_nofail(dev);
>> + aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev));
>> + return dev;
>> +}
> qdev_create helpers are depracated. The code should just be inlined
> into the creating machine models or container devs.
>
>> +
>> +void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
>> +{
>> + aux_slave->mmio = mmio;
> Should this assert on repeated calls?
>
>> +}
>> +
>> +static void aux_slave_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *k = DEVICE_CLASS(klass);
>> + set_bit(DEVICE_CATEGORY_MISC, k->categories);
>> + k->bus_type = TYPE_AUX_BUS;
>> + k->props = aux_props;
>> +}
>> +
>> +static const TypeInfo aux_slave_type_info = {
>> + .name = TYPE_AUX_SLAVE,
>> + .parent = TYPE_DEVICE,
>> + .instance_size = sizeof(AUXSlave),
>> + .abstract = true,
>> + .class_init = aux_slave_class_init,
>> +};
>> +
>> +static void aux_slave_register_types(void)
>> +{
>> + type_register_static(&aux_bus_info);
>> + type_register_static(&aux_slave_type_info);
>> + type_register_static(&aux_to_i2c_type_info);
>> +}
>> +
>> +type_init(aux_slave_register_types)
>> diff --git a/include/hw/aux.h b/include/hw/aux.h
>> new file mode 100644
>> index 0000000..7b29ee1
>> --- /dev/null
>> +++ b/include/hw/aux.h
>> @@ -0,0 +1,116 @@
>> +/*
>> + * aux.h
>> + *
>> + * Copyright (C)2014 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option)any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#ifndef QEMU_AUX_H
>> +#define QEMU_AUX_H
>> +
>> +#include "hw/qdev.h"
>> +
>> +enum aux_command {
> AUXCommand.
>
>> + WRITE_I2C = 0,
>> + READ_I2C = 1,
>> + WRITE_I2C_STATUS = 2,
>> + WRITE_I2C_MOT = 4,
>> + READ_I2C_MOT = 5,
>> + WRITE_AUX = 8,
>> + READ_AUX = 9
>> +};
>> +
>> +enum aux_reply {
> AUXReply.
>
>> + AUX_I2C_ACK = 0,
>> + AUX_NACK = 1,
>> + AUX_DEFER = 2,
>> + AUX_I2C_NACK = 4,
>> + AUX_I2C_DEFER = 8
>> +};
>> +
>> +typedef struct AUXBus AUXBus;
>> +typedef struct AUXSlave AUXSlave;
>> +typedef enum aux_command aux_command;
>> +typedef enum aux_reply aux_reply;
>> +
>> +#define TYPE_AUX_SLAVE "aux-slave"
>> +#define AUX_SLAVE(obj) \
>> + OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
>> +
>> +struct AUXSlave {
>> + /* < private > */
>> + DeviceState parent_obj;
>> +
> /*< public >*/
>
>> + /* address of the device on the aux bus. */
>> + hwaddr address;
> Can this be encapsulated by mmio. There is memory_region_get_addr().
>
>> + /* memory region associated. */
>> + MemoryRegion *mmio;
>> +};
>> +
>> +/*
>> + * \func aux_init_bus
>> + * \brief Init an aux bus.
>> + * \param parent The device where this bus is located.
>> + * \param name The name of the bus.
>> + * \return The new aux bus.
> Please use the /** @ style documentation.
>
> Regards,
> Peter
>
>> + */
>> +AUXBus *aux_init_bus(DeviceState *parent, const char *name);
>> +
>> +/*
>> + * \func aux_slave_set_address
>> + * \brief Set the address of the slave on the aux bus.
>> + * \param dev The aux slave device.
>> + * \param address The address to give to the slave.
>> + */
>> +void aux_set_slave_address(AUXSlave *dev, uint32_t address);
>> +
>> +/*
>> + * \func aux_request
>> + * \brief Make a request on the bus.
>> + * \param bus Ths bus where the request happen.
>> + * \param cmd The command requested.
>> + * \param address The 20bits address of the slave.
>> + * \param len The length of the read or write.
>> + * \param data The data array which will be filled or read during transfer.
>> + * \return Return the reply of the request.
>> + */
>> +aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
>> + uint8_t len, uint8_t *data);
>> +
>> +/*
>> + * \func aux_get_i2c_bus
>> + * \brief Get the i2c bus for I2C over AUX command.
>> + * \param bus The aux bus.
>> + * \return Return the i2c bus associated.
>> + */
>> +I2CBus *aux_get_i2c_bus(AUXBus *bus);
>> +
>> +/*
>> + * \func aux_init_mmio
>> + * \brief Init an mmio for an aux slave, must be called after
>> + * memory_region_init_io.
>> + * \param aux_slave The aux slave.
>> + * \param mmio The mmio to be registered.
>> + */
>> +void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
>> +
>> +DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
>> +
>> +#endif /* !QEMU_AUX_H */
>> --
>> 1.9.0
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write.
2015-06-24 6:35 ` Peter Crosthwaite
@ 2015-07-06 16:28 ` Frederic Konrad
2015-07-06 16:54 ` Peter Crosthwaite
0 siblings, 1 reply; 20+ messages in thread
From: Frederic Konrad @ 2015-07-06 16:28 UTC (permalink / raw)
To: Peter Crosthwaite
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On 24/06/2015 08:35, Peter Crosthwaite wrote:
> On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This does a write to every slaves when the I2C bus get a write to address 0.
>>
>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>> ---
>> hw/i2c/core.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 45 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/i2c/core.c b/hw/i2c/core.c
>> index 5a64026..db1cbdd 100644
>> --- a/hw/i2c/core.c
>> +++ b/hw/i2c/core.c
>> @@ -15,6 +15,7 @@ struct I2CBus
>> I2CSlave *current_dev;
>> I2CSlave *dev;
>> uint8_t saved_address;
>> + bool broadcast;
>> };
>>
>> static Property i2c_props[] = {
>> @@ -67,6 +68,8 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
>>
>> bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
>> vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
>> +
>> + bus->broadcast = false;
> 0 initialiser should not be needed for new QOM object.
>
>> return bus;
>> }
>>
>> @@ -89,6 +92,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
>> I2CSlave *slave = NULL;
>> I2CSlaveClass *sc;
>>
>> + if (address == 0x00) {
>> + /*
>> + * This is a broadcast.
>> + */
> One line comment.
>
>> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>> + I2CSlave *dev = I2C_SLAVE(kid->child);
>> + sc = I2C_SLAVE_GET_CLASS(dev);
>> + bus->broadcast = true;
> Move outside loop.
>
>> + if (sc->event) {
>> + sc->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
>> + }
>> + }
>> + return 0;
>> + }
>> +
>> QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>> DeviceState *qdev = kid->child;
>> I2CSlave *candidate = I2C_SLAVE(qdev);
>> @@ -114,9 +132,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
>>
>> void i2c_end_transfer(I2CBus *bus)
>> {
>> + BusChild *kid;
>> I2CSlave *dev = bus->current_dev;
>> I2CSlaveClass *sc;
>>
>> + if (bus->broadcast) {
>> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>> + I2CSlave *dev = I2C_SLAVE(kid->child);
>> + sc = I2C_SLAVE_GET_CLASS(dev);
>> + if (sc->event) {
>> + sc->event(dev, I2C_FINISH);
>> + }
>> + }
>> + bus->broadcast = false;
>> + }
>> +
>> if (!dev) {
>> return;
>> }
>> @@ -131,8 +161,22 @@ void i2c_end_transfer(I2CBus *bus)
>>
>> int i2c_send(I2CBus *bus, uint8_t data)
>> {
>> + BusChild *kid;
>> I2CSlave *dev = bus->current_dev;
>> I2CSlaveClass *sc;
>> + int ret = 0;
>> +
>> + if (bus->broadcast) {
>> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>> + I2CSlave *dev = I2C_SLAVE(kid->child);
>> + sc = I2C_SLAVE_GET_CLASS(dev);
>> + bus->broadcast = true;
>> + if (sc->send) {
>> + ret |= sc->send(dev, data);
>> + }
>> + }
> Still not sure about the duped core functionality of each of these
> APIs. That is, the same code is needed in both a looped form and a 1
> form. Can this be solved by listifying current_dev? That is, ->current
> dev is turned into a list which in the normal case will be populated
> with 1 element by start_transfer() for the current dev. In the
> broadcast case, all qbus.children are added to the list. The broadcast
> bool is then removed. start() send() and end_transfer() then just loop
> through the list unconditionally.
I think better keeping this broadcast as we need it for VMSD anyway?
> Regards,
> Peter
>
>> + return ret;
>> + }
>>
>> if (!dev) {
>> return -1;
>> @@ -151,7 +195,7 @@ int i2c_recv(I2CBus *bus)
>> I2CSlave *dev = bus->current_dev;
>> I2CSlaveClass *sc;
>>
>> - if (!dev) {
>> + if ((!dev) || (bus->broadcast)) {
>> return -1;
>> }
>>
>> --
>> 1.9.0
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 3/7] introduce dpcd module.
2015-06-24 6:44 ` Peter Crosthwaite
@ 2015-07-06 16:30 ` Frederic Konrad
2015-07-06 16:57 ` Peter Crosthwaite
0 siblings, 1 reply; 20+ messages in thread
From: Frederic Konrad @ 2015-07-06 16:30 UTC (permalink / raw)
To: Peter Crosthwaite
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On 24/06/2015 08:44, Peter Crosthwaite wrote:
> On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This introduces a DPCD modules. It wires on a aux-bus and can be accessed by
> "module"
>
>> driver to get lane-speed, etc.
>>
>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>> ---
>> hw/display/Makefile.objs | 1 +
>> hw/display/dpcd.c | 151 +++++++++++++++++++++++++++++++++++++++++++++++
>> hw/display/dpcd.h | 72 ++++++++++++++++++++++
>> 3 files changed, 224 insertions(+)
>> create mode 100644 hw/display/dpcd.c
>> create mode 100644 hw/display/dpcd.h
>>
>> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
>> index 61c80f3..f75094f 100644
>> --- a/hw/display/Makefile.objs
>> +++ b/hw/display/Makefile.objs
>> @@ -36,3 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
>> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
>>
>> obj-$(CONFIG_VIRTIO) += virtio-gpu.o
>> +obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o
> Make a DPCD config and add to aarch64 defconfig.
>
>> diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
>> new file mode 100644
>> index 0000000..b4eeea7
>> --- /dev/null
>> +++ b/hw/display/dpcd.c
>> @@ -0,0 +1,151 @@
>> +/*
>> + * dpcd.c
>> + *
>> + * Copyright (C)2015 : GreenSocs Ltd
> (C) 2015
> (missing space)
>
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option)any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +/*
>> + * This is a simple AUX slave which emulates a connected screen.
>> + */
>> +
>> +#include "hw/aux.h"
>> +#include "dpcd.h"
>> +
>> +#ifndef DEBUG_DPCD
>> +#define DEBUG_DPCD 0
>> +#endif
>> +
>> +#define DPRINTF(fmt, ...) do { \
>> + if (DEBUG_DPCD) { \
>> + qemu_log("dpcd: " fmt, ## __VA_ARGS__); \
>> + } \
>> +} while (0);
>> +
>> +#define DPCD_READABLE_AREA 0x600
>> +
>> +struct DPCDState {
> /*< public >*/
>
>> + AUXSlave parent_obj;
>> +
> /*< private >*/
>
>> + /*
>> + * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
>> + */
>> + uint8_t dpcd_info[DPCD_READABLE_AREA];
>> +
>> + MemoryRegion iomem;
>> +};
>> +
>> +static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
>> +{
>> + uint64_t ret;
> make a uint8_t
>
>> + DPCDState *e = DPCD(opaque);
>> +
>> + if (offset < DPCD_READABLE_AREA) {
>> + ret = e->dpcd_info[offset];
>> + } else {
>> + ret = 0;
>> + }
>> +
>> + DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
> to avoid this cast, and just let the implicit cast on the return
> handle it for you.
>
> PRIx8
> HWADDR_PRIx
>
>> + return ret;
>> +}
>> +
>> +static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
>> + unsigned size)
>> +{
>> + DPCDState *e = DPCD(opaque);
>> +
>> + DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
>> +
> PRIx8
> HWADDR_PRIx
>
>> + if (offset < DPCD_READABLE_AREA) {
>> + e->dpcd_info[offset] = value;
>> + }
> Should there be a else for a guest error?
I think it's fine. Seems it's accessible but just read as 0.
>
>> +}
>> +
>> +static const MemoryRegionOps aux_ops = {
>> + .read = dpcd_read,
>> + .write = dpcd_write,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 1,
>> + },
>> + .impl = {
>> + .min_access_size = 1,
>> + .max_access_size = 1,
>> + },
>> +};
>> +
>> +static void dpcd_reset(DeviceState *dev)
>> +{
>> + DPCDState *s = DPCD(dev);
> blank line.
>
>> + memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
>> +
>> + s->dpcd_info[0x00] = DPCD_REV_1_0;
>> + s->dpcd_info[0x01] = DPCD_5_4GBPS;
>> + s->dpcd_info[0x02] = 0x1;
>> + s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
>> + s->dpcd_info[0x09] = 0xFF;
>> +
>> + /* CR DONE, CE DONE, SYMBOL LOCKED.. */
>> + s->dpcd_info[0x202] = 0x07;
>> + /* INTERLANE_ALIGN_DONE.. */
>> + s->dpcd_info[0x204] = 0x01;
>> + s->dpcd_info[0x205] = 0x01;
> Magic numbers for both offsets and fields should be defined.
>
>> +}
>> +
>> +static void dpcd_init(Object *obj)
>> +{
>> + DPCDState *s = DPCD(obj);
>> +
>> + memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
>> + aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
>> +}
>> +
>> +static const VMStateDescription vmstate_dpcd = {
>> + .name = TYPE_DPCD,
>> + .version_id = 0,
>> + .minimum_version_id = 0,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT8_ARRAY_V(dpcd_info, DPCDState, DPCD_READABLE_AREA, 0),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static void dpcd_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
> blank line.
>
>
> Regards,
> Peter
>
>> + dc->reset = dpcd_reset;
>> + dc->vmsd = &vmstate_dpcd;
>> +}
>> +
>> +static const TypeInfo dpcd_info = {
>> + .name = TYPE_DPCD,
>> + .parent = TYPE_AUX_SLAVE,
>> + .instance_size = sizeof(DPCDState),
>> + .class_init = dpcd_class_init,
>> + .instance_init = dpcd_init,
>> +};
>> +
>> +static void dpcd_register_types(void)
>> +{
>> + type_register_static(&dpcd_info);
>> +}
>> +
>> +type_init(dpcd_register_types)
>> diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
>> new file mode 100644
>> index 0000000..57c393b
>> --- /dev/null
>> +++ b/hw/display/dpcd.h
>> @@ -0,0 +1,72 @@
>> +/*
>> + * dpcd.h
>> + *
>> + * Copyright (C)2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option)any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#ifndef DPCD_H
>> +#define DPCD_H
>> +
>> +typedef struct DPCDState DPCDState;
>> +
>> +#define TYPE_DPCD "dpcd"
>> +#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
>> +
>> +/* DCPD Revision. */
>> +#define DPCD_REV_1_0 0x10
>> +#define DPCD_REV_1_1 0x11
>> +
>> +/* DCPD Max Link Rate. */
>> +#define DPCD_1_62GBPS 0x06
>> +#define DPCD_2_7GBPS 0x0A
>> +#define DPCD_5_4GBPS 0x14
>> +
>> +/* DCPD Max down spread. */
>> +#define DPCD_UP_TO_0_5 0x01
>> +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
>> +
>> +/* DCPD Downstream port type. */
>> +#define DPCD_DISPLAY_PORT 0x00
>> +#define DPCD_ANALOG 0x02
>> +#define DPCD_DVI_HDMI 0x04
>> +#define DPCD_OTHER 0x06
>> +
>> +/* DPCD Format conversion. */
>> +#define DPCD_FORMAT_CONVERSION 0x08
>> +
>> +/* Main link channel coding. */
>> +#define DPCD_ANSI_8B_10B 0x01
>> +
>> +/* Down stream port count. */
>> +#define DPCD_OUI_SUPPORTED 0x80
>> +
>> +/* Receiver port capability. */
>> +#define DPCD_EDID_PRESENT 0x02
>> +#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
>> +
>> +/* Down stream port capability. */
>> +#define DPCD_CAP_DISPLAY_PORT 0x000
>> +#define DPCD_CAP_ANALOG_VGA 0x001
>> +#define DPCD_CAP_DVI 0x002
>> +#define DPCD_CAP_HDMI 0x003
>> +#define DPCD_CAP_OTHER 0x100
>> +
>> +#endif /* !DPCD_H */
>> --
>> 1.9.0
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write.
2015-07-06 16:28 ` Frederic Konrad
@ 2015-07-06 16:54 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-07-06 16:54 UTC (permalink / raw)
To: Frederic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jul 6, 2015 at 9:28 AM, Frederic Konrad
<fred.konrad@greensocs.com> wrote:
> On 24/06/2015 08:35, Peter Crosthwaite wrote:
>>
>> On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
>>>
>>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>>
>>> This does a write to every slaves when the I2C bus get a write to address
>>> 0.
>>>
>>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>>> ---
>>> hw/i2c/core.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 45 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/hw/i2c/core.c b/hw/i2c/core.c
>>> index 5a64026..db1cbdd 100644
>>> --- a/hw/i2c/core.c
>>> +++ b/hw/i2c/core.c
>>> @@ -15,6 +15,7 @@ struct I2CBus
>>> I2CSlave *current_dev;
>>> I2CSlave *dev;
>>> uint8_t saved_address;
>>> + bool broadcast;
>>> };
>>>
>>> static Property i2c_props[] = {
>>> @@ -67,6 +68,8 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char
>>> *name)
>>>
>>> bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
>>> vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
>>> +
>>> + bus->broadcast = false;
>>
>> 0 initialiser should not be needed for new QOM object.
>>
>>> return bus;
>>> }
>>>
>>> @@ -89,6 +92,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address,
>>> int recv)
>>> I2CSlave *slave = NULL;
>>> I2CSlaveClass *sc;
>>>
>>> + if (address == 0x00) {
>>> + /*
>>> + * This is a broadcast.
>>> + */
>>
>> One line comment.
>>
>>> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>>> + I2CSlave *dev = I2C_SLAVE(kid->child);
>>> + sc = I2C_SLAVE_GET_CLASS(dev);
>>> + bus->broadcast = true;
>>
>> Move outside loop.
>>
>>> + if (sc->event) {
>>> + sc->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
>>> + }
>>> + }
>>> + return 0;
>>> + }
>>> +
>>> QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>>> DeviceState *qdev = kid->child;
>>> I2CSlave *candidate = I2C_SLAVE(qdev);
>>> @@ -114,9 +132,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address,
>>> int recv)
>>>
>>> void i2c_end_transfer(I2CBus *bus)
>>> {
>>> + BusChild *kid;
>>> I2CSlave *dev = bus->current_dev;
>>> I2CSlaveClass *sc;
>>>
>>> + if (bus->broadcast) {
>>> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>>> + I2CSlave *dev = I2C_SLAVE(kid->child);
>>> + sc = I2C_SLAVE_GET_CLASS(dev);
>>> + if (sc->event) {
>>> + sc->event(dev, I2C_FINISH);
>>> + }
>>> + }
>>> + bus->broadcast = false;
>>> + }
>>> +
>>> if (!dev) {
>>> return;
>>> }
>>> @@ -131,8 +161,22 @@ void i2c_end_transfer(I2CBus *bus)
>>>
>>> int i2c_send(I2CBus *bus, uint8_t data)
>>> {
>>> + BusChild *kid;
>>> I2CSlave *dev = bus->current_dev;
>>> I2CSlaveClass *sc;
>>> + int ret = 0;
>>> +
>>> + if (bus->broadcast) {
>>> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
>>> + I2CSlave *dev = I2C_SLAVE(kid->child);
>>> + sc = I2C_SLAVE_GET_CLASS(dev);
>>> + bus->broadcast = true;
>>> + if (sc->send) {
>>> + ret |= sc->send(dev, data);
>>> + }
>>> + }
>>
>> Still not sure about the duped core functionality of each of these
>> APIs. That is, the same code is needed in both a looped form and a 1
>> form. Can this be solved by listifying current_dev? That is, ->current
>> dev is turned into a list which in the normal case will be populated
>> with 1 element by start_transfer() for the current dev. In the
>> broadcast case, all qbus.children are added to the list. The broadcast
>> bool is then removed. start() send() and end_transfer() then just loop
>> through the list unconditionally.
>
>
> I think better keeping this broadcast as we need it for VMSD anyway?
>
Ok I see the VMSD issue and can keep the boolean, but I'm more
concerned about the duped code. It's hard to patch this reliably, if
the same core of code is duped.
Regards,
Peter
>
>> Regards,
>> Peter
>>
>>> + return ret;
>>> + }
>>>
>>> if (!dev) {
>>> return -1;
>>> @@ -151,7 +195,7 @@ int i2c_recv(I2CBus *bus)
>>> I2CSlave *dev = bus->current_dev;
>>> I2CSlaveClass *sc;
>>>
>>> - if (!dev) {
>>> + if ((!dev) || (bus->broadcast)) {
>>> return -1;
>>> }
>>>
>>> --
>>> 1.9.0
>>>
>>>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH V2 3/7] introduce dpcd module.
2015-07-06 16:30 ` Frederic Konrad
@ 2015-07-06 16:57 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-07-06 16:57 UTC (permalink / raw)
To: Frederic Konrad
Cc: Peter Maydell, Mark Burton, qemu-devel@nongnu.org Developers,
hyunk, guillaume.delbergue
On Mon, Jul 6, 2015 at 9:30 AM, Frederic Konrad
<fred.konrad@greensocs.com> wrote:
> On 24/06/2015 08:44, Peter Crosthwaite wrote:
>>
>> On Mon, Jun 15, 2015 at 8:15 AM, <fred.konrad@greensocs.com> wrote:
>>>
>>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>>
>>> This introduces a DPCD modules. It wires on a aux-bus and can be accessed
>>> by
>>
>> "module"
>>
>>> driver to get lane-speed, etc.
>>>
>>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>>> ---
>>> hw/display/Makefile.objs | 1 +
>>> hw/display/dpcd.c | 151
>>> +++++++++++++++++++++++++++++++++++++++++++++++
>>> hw/display/dpcd.h | 72 ++++++++++++++++++++++
>>> 3 files changed, 224 insertions(+)
>>> create mode 100644 hw/display/dpcd.c
>>> create mode 100644 hw/display/dpcd.h
>>>
>>> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
>>> index 61c80f3..f75094f 100644
>>> --- a/hw/display/Makefile.objs
>>> +++ b/hw/display/Makefile.objs
>>> @@ -36,3 +36,4 @@ obj-$(CONFIG_VGA) += vga.o
>>> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
>>>
>>> obj-$(CONFIG_VIRTIO) += virtio-gpu.o
>>> +obj-$(CONFIG_XLNX_ZYNQMP) += dpcd.o
>>
>> Make a DPCD config and add to aarch64 defconfig.
>>
>>> diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
>>> new file mode 100644
>>> index 0000000..b4eeea7
>>> --- /dev/null
>>> +++ b/hw/display/dpcd.c
>>> @@ -0,0 +1,151 @@
>>> +/*
>>> + * dpcd.c
>>> + *
>>> + * Copyright (C)2015 : GreenSocs Ltd
>>
>> (C) 2015
>> (missing space)
>>
>>> + * http://www.greensocs.com/ , email: info@greensocs.com
>>> + *
>>> + * Developed by :
>>> + * Frederic Konrad <fred.konrad@greensocs.com>
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License as published by
>>> + * the Free Software Foundation, either version 2 of the License, or
>>> + * (at your option)any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> along
>>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>>> + *
>>> + */
>>> +
>>> +/*
>>> + * This is a simple AUX slave which emulates a connected screen.
>>> + */
>>> +
>>> +#include "hw/aux.h"
>>> +#include "dpcd.h"
>>> +
>>> +#ifndef DEBUG_DPCD
>>> +#define DEBUG_DPCD 0
>>> +#endif
>>> +
>>> +#define DPRINTF(fmt, ...) do {
>>> \
>>> + if (DEBUG_DPCD) {
>>> \
>>> + qemu_log("dpcd: " fmt, ## __VA_ARGS__);
>>> \
>>> + }
>>> \
>>> +} while (0);
>>> +
>>> +#define DPCD_READABLE_AREA 0x600
>>> +
>>> +struct DPCDState {
>>
>> /*< public >*/
>>
>>> + AUXSlave parent_obj;
>>> +
>>
>> /*< private >*/
>>
>>> + /*
>>> + * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
>>> + */
>>> + uint8_t dpcd_info[DPCD_READABLE_AREA];
>>> +
>>> + MemoryRegion iomem;
>>> +};
>>> +
>>> +static uint64_t dpcd_read(void *opaque, hwaddr offset, unsigned size)
>>> +{
>>> + uint64_t ret;
>>
>> make a uint8_t
>>
>>> + DPCDState *e = DPCD(opaque);
>>> +
>>> + if (offset < DPCD_READABLE_AREA) {
>>> + ret = e->dpcd_info[offset];
>>> + } else {
>>> + ret = 0;
>>> + }
>>> +
>>> + DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
>>
>> to avoid this cast, and just let the implicit cast on the return
>> handle it for you.
>>
>> PRIx8
>> HWADDR_PRIx
>>
>>> + return ret;
>>> +}
>>> +
>>> +static void dpcd_write(void *opaque, hwaddr offset, uint64_t value,
>>> + unsigned size)
>>> +{
>>> + DPCDState *e = DPCD(opaque);
>>> +
>>> + DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
>>> +
>>
>> PRIx8
>> HWADDR_PRIx
>>
>>> + if (offset < DPCD_READABLE_AREA) {
>>> + e->dpcd_info[offset] = value;
>>> + }
>>
>> Should there be a else for a guest error?
>
>
> I think it's fine. Seems it's accessible but just read as 0.
>
So guest error is this semantic, it is not limited to only undefs, it
also applied to OOB registers that have a defined background. This
goal is to let the user know "the guest is doing something that
doesn't make sense" rather than trap undef behaviour.
Regards,
Peter
>>
>>> +}
>>> +
>>> +static const MemoryRegionOps aux_ops = {
>>> + .read = dpcd_read,
>>> + .write = dpcd_write,
>>> + .valid = {
>>> + .min_access_size = 1,
>>> + .max_access_size = 1,
>>> + },
>>> + .impl = {
>>> + .min_access_size = 1,
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2015-07-06 16:57 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-15 15:15 [Qemu-devel] [PATCH V2 0/7] Xilinx DisplayPort fred.konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 1/7] Introduce AUX bus fred.konrad
2015-06-24 6:21 ` Peter Crosthwaite
2015-07-06 16:27 ` Frederic Konrad
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 2/7] i2c: implement broadcast write fred.konrad
2015-06-24 6:35 ` Peter Crosthwaite
2015-07-06 16:28 ` Frederic Konrad
2015-07-06 16:54 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 3/7] introduce dpcd module fred.konrad
2015-06-24 6:44 ` Peter Crosthwaite
2015-07-06 16:30 ` Frederic Konrad
2015-07-06 16:57 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 4/7] hw/i2c-ddc.c: Implement DDC I2C slave fred.konrad
2015-06-24 7:03 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 5/7] Introduce xilinx dpdma fred.konrad
2015-06-24 7:41 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 6/7] Introduce xilinx dp fred.konrad
2015-06-24 8:21 ` Peter Crosthwaite
2015-06-15 15:15 ` [Qemu-devel] [PATCH V2 7/7] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
2015-06-24 8:23 ` Peter Crosthwaite
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