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From: Chih-Min Chao <chihmin.chao@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: Frank Chang <frank.chang@sifive.com>,
	Alistair Francis <alistair23@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
Date: Thu, 6 Aug 2020 14:09:13 +0800	[thread overview]
Message-ID: <CAEiOBXXmz2APpmtwPrvikXUt5j_Q=k5ZqK9g2Fe4bdjeAbg_6g@mail.gmail.com> (raw)
In-Reply-To: <ccc72223-d98e-6dd4-6c44-ca30f4e687d5@c-sky.com>

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On Fri, Jul 24, 2020 at 2:06 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:

>
>
> On 2020/7/24 11:55, Richard Henderson wrote:
> > On 7/23/20 7:35 PM, LIU Zhiwei wrote:
> >>
> >> On 2020/7/24 8:28, Richard Henderson wrote:
> >>> Make sure that all results from single-precision scalar helpers
> >>> are properly nan-boxed to 64-bits.
> >>>
> >>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >>> ---
> >>>    target/riscv/internals.h  |  5 +++++
> >>>    target/riscv/fpu_helper.c | 42
> +++++++++++++++++++++------------------
> >>>    2 files changed, 28 insertions(+), 19 deletions(-)
> >>>
> >>> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> >>> index 37d33820ad..9f4ba7d617 100644
> >>> --- a/target/riscv/internals.h
> >>> +++ b/target/riscv/internals.h
> >>> @@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1);
> >>>    #define SEW32 2
> >>>    #define SEW64 3
> >>>    +static inline uint64_t nanbox_s(float32 f)
> >>> +{
> >>> +    return f | MAKE_64BIT_MASK(32, 32);
> >>> +}
> >>> +
> >> If define it here,  we can also define a more general  function with
> flen.
> >>
> >> +static inline uint64_t nanbox_s(float32 f, uint32_t flen)
> >> +{
> >> +    return f | MAKE_64BIT_MASK(flen, 64 - flen);
> >> +}
> >> +
> >>
> >> So we can reuse it in fp16 or bf16 scalar instruction and in vector
> instructions.
> > While we could do that, we will not encounter all possible lengths.  In
> the
> > cover letter, I mentioned defining a second function,
> >
> > static inline uint64_t nanbox_h(float16 f)
> > {
> >     return f | MAKE_64BIT_MASK(16, 48);
> > }
> >
> > Having two separate functions will, I believe, be easier to use in
> practice.
> >
> Get  it. Thanks.
>
> Zhiwei
> >
> > r~
>
>
>
That is what has been implemented in spike.  It fills up the Nan-Box when
value is stored back internal structure and
unbox the value with difference floating type (half/single/double/quad).

By the way,  I prefer to keeping the suffix to tell different floating
type rather than pass arbitrary
since each floating type belong to each extension.

Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>

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WARNING: multiple messages have this Message-ID (diff)
From: Chih-Min Chao <chihmin.chao@sifive.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: Richard Henderson <richard.henderson@linaro.org>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Frank Chang <frank.chang@sifive.com>,
	 Alistair Francis <alistair23@gmail.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>
Subject: Re: [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers
Date: Thu, 6 Aug 2020 14:09:13 +0800	[thread overview]
Message-ID: <CAEiOBXXmz2APpmtwPrvikXUt5j_Q=k5ZqK9g2Fe4bdjeAbg_6g@mail.gmail.com> (raw)
In-Reply-To: <ccc72223-d98e-6dd4-6c44-ca30f4e687d5@c-sky.com>

[-- Attachment #1: Type: text/plain, Size: 2145 bytes --]

On Fri, Jul 24, 2020 at 2:06 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:

>
>
> On 2020/7/24 11:55, Richard Henderson wrote:
> > On 7/23/20 7:35 PM, LIU Zhiwei wrote:
> >>
> >> On 2020/7/24 8:28, Richard Henderson wrote:
> >>> Make sure that all results from single-precision scalar helpers
> >>> are properly nan-boxed to 64-bits.
> >>>
> >>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> >>> ---
> >>>    target/riscv/internals.h  |  5 +++++
> >>>    target/riscv/fpu_helper.c | 42
> +++++++++++++++++++++------------------
> >>>    2 files changed, 28 insertions(+), 19 deletions(-)
> >>>
> >>> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> >>> index 37d33820ad..9f4ba7d617 100644
> >>> --- a/target/riscv/internals.h
> >>> +++ b/target/riscv/internals.h
> >>> @@ -38,4 +38,9 @@ target_ulong fclass_d(uint64_t frs1);
> >>>    #define SEW32 2
> >>>    #define SEW64 3
> >>>    +static inline uint64_t nanbox_s(float32 f)
> >>> +{
> >>> +    return f | MAKE_64BIT_MASK(32, 32);
> >>> +}
> >>> +
> >> If define it here,  we can also define a more general  function with
> flen.
> >>
> >> +static inline uint64_t nanbox_s(float32 f, uint32_t flen)
> >> +{
> >> +    return f | MAKE_64BIT_MASK(flen, 64 - flen);
> >> +}
> >> +
> >>
> >> So we can reuse it in fp16 or bf16 scalar instruction and in vector
> instructions.
> > While we could do that, we will not encounter all possible lengths.  In
> the
> > cover letter, I mentioned defining a second function,
> >
> > static inline uint64_t nanbox_h(float16 f)
> > {
> >     return f | MAKE_64BIT_MASK(16, 48);
> > }
> >
> > Having two separate functions will, I believe, be easier to use in
> practice.
> >
> Get  it. Thanks.
>
> Zhiwei
> >
> > r~
>
>
>
That is what has been implemented in spike.  It fills up the Nan-Box when
value is stored back internal structure and
unbox the value with difference floating type (half/single/double/quad).

By the way,  I prefer to keeping the suffix to tell different floating
type rather than pass arbitrary
since each floating type belong to each extension.

Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>

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  reply	other threads:[~2020-08-06 12:24 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-24  0:28 [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison Richard Henderson
2020-07-24  0:28 ` Richard Henderson
2020-07-24  0:28 ` [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-07-24  2:35   ` LIU Zhiwei
2020-07-24  2:35     ` LIU Zhiwei
2020-07-24  3:55     ` Richard Henderson
2020-07-24  3:55       ` Richard Henderson
2020-07-24  6:05       ` LIU Zhiwei
2020-07-24  6:05         ` LIU Zhiwei
2020-08-06  6:09         ` Chih-Min Chao [this message]
2020-08-06  6:09           ` Chih-Min Chao
2020-08-06  7:05           ` LIU Zhiwei
2020-08-06  7:05             ` LIU Zhiwei
2020-08-06  8:42             ` Chih-Min Chao
2020-08-06  8:42               ` Chih-Min Chao
2020-08-06 10:02               ` LIU Zhiwei
2020-08-06 10:02                 ` LIU Zhiwei
2020-07-24  0:28 ` [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-07-24  2:39   ` LIU Zhiwei
2020-07-24  2:39     ` LIU Zhiwei
2020-08-06  6:24   ` Chih-Min Chao
2020-08-06  6:24     ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-07-24  2:41   ` LIU Zhiwei
2020-07-24  2:41     ` LIU Zhiwei
2020-08-06  6:24   ` Chih-Min Chao
2020-08-06  6:24     ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-07-24  2:47   ` LIU Zhiwei
2020-07-24  2:47     ` LIU Zhiwei
2020-07-24  3:59     ` Richard Henderson
2020-07-24  3:59       ` Richard Henderson
2020-08-06  6:26   ` Chih-Min Chao
2020-08-06  6:26     ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-07-24  6:04   ` LIU Zhiwei
2020-07-24  6:04     ` LIU Zhiwei
2020-08-06  6:27   ` Chih-Min Chao
2020-08-06  6:27     ` Chih-Min Chao
2020-08-07 20:24   ` Chih-Min Chao
2020-08-07 20:24     ` Chih-Min Chao
2020-08-08 14:18     ` LIU Zhiwei
2020-08-08 14:18       ` LIU Zhiwei
2020-08-08 23:06       ` LIU Zhiwei
2020-08-08 23:06         ` LIU Zhiwei
2020-07-24  0:28 ` [PATCH v2 6/7] target/riscv: Clean up fmv.w.x Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-08-06  6:28   ` Chih-Min Chao
2020-08-06  6:28     ` Chih-Min Chao
2020-07-24  0:28 ` [PATCH v2 7/7] target/riscv: check before allocating TCG temps Richard Henderson
2020-07-24  0:28   ` Richard Henderson
2020-08-06  6:28   ` Chih-Min Chao
2020-08-06  6:28     ` Chih-Min Chao
2020-07-24  2:31 ` [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison LIU Zhiwei
2020-07-24  2:31   ` LIU Zhiwei
2020-07-27 23:37 ` Alistair Francis
2020-07-27 23:37   ` Alistair Francis

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