* [PATCH 1/4] PCI: Cache MSI/MSI-X cap in PCI device
2013-04-05 2:54 [PATCH v3 0/5] Retrieve MSI/MSIX cap struct for once on setup Gavin Shan
@ 2013-04-05 2:54 ` Gavin Shan
2013-04-05 2:54 ` [PATCH 2/4] PCI: Remove MSI/MSI-X cap check in pci_msi_check_device() Gavin Shan
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Gavin Shan @ 2013-04-05 2:54 UTC (permalink / raw)
To: linux-pci; +Cc: bhelgaas, Gavin Shan
The patch caches the MSI and MSI-X capability offset in PCI device
(struct pci_dev) so that we needn't poll it from the config space
upon enabling or disabling MSI or MSI-X interrupts. Besides, the
data type of cached PM capability (pm_cap), which is PCI stuff
intead of PCIe stuff, in pci_dev has been changed to "u8" according
to Bjorn's suggestion.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
drivers/pci/msi.c | 43 ++++++++++++++++++++-----------------------
include/linux/pci.h | 4 +++-
2 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 00cc78c..5fdc5d9 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -111,32 +111,26 @@ void default_restore_msi_irqs(struct pci_dev *dev, int irq)
}
#endif
-static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
+static void msi_set_enable(struct pci_dev *dev, int enable)
{
u16 control;
- BUG_ON(!pos);
-
- pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
+ pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
control &= ~PCI_MSI_FLAGS_ENABLE;
if (enable)
control |= PCI_MSI_FLAGS_ENABLE;
- pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
+ pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
}
static void msix_set_enable(struct pci_dev *dev, int enable)
{
- int pos;
u16 control;
- pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
- if (pos) {
- pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
- control &= ~PCI_MSIX_FLAGS_ENABLE;
- if (enable)
- control |= PCI_MSIX_FLAGS_ENABLE;
- pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
- }
+ pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
+ control &= ~PCI_MSIX_FLAGS_ENABLE;
+ if (enable)
+ control |= PCI_MSIX_FLAGS_ENABLE;
+ pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
}
static inline __attribute_const__ u32 msi_mask(unsigned x)
@@ -402,7 +396,7 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
pos = entry->msi_attrib.pos;
pci_intx_for_msi(dev, 0);
- msi_set_enable(dev, pos, 0);
+ msi_set_enable(dev, 0);
arch_restore_msi_irqs(dev, dev->irq);
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
@@ -557,7 +551,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
unsigned mask;
pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
- msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
+ msi_set_enable(dev, 0); /* Disable MSI during set up */
pci_read_config_word(dev, msi_control_reg(pos), &control);
/* MSI Entry Initialization */
@@ -598,7 +592,7 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
/* Set MSI enabled bits */
pci_intx_for_msi(dev, 0);
- msi_set_enable(dev, pos, 1);
+ msi_set_enable(dev, 1);
dev->msi_enabled = 1;
dev->irq = entry->irq;
@@ -885,7 +879,7 @@ void pci_msi_shutdown(struct pci_dev *dev)
desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
pos = desc->msi_attrib.pos;
- msi_set_enable(dev, pos, 0);
+ msi_set_enable(dev, 0);
pci_intx_for_msi(dev, 1);
dev->msi_enabled = 0;
@@ -1048,15 +1042,18 @@ EXPORT_SYMBOL(pci_msi_enabled);
void pci_msi_init_pci_dev(struct pci_dev *dev)
{
- int pos;
INIT_LIST_HEAD(&dev->msi_list);
/* Disable the msi hardware to avoid screaming interrupts
* during boot. This is the power on reset default so
* usually this should be a noop.
*/
- pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
- if (pos)
- msi_set_enable(dev, pos, 0);
- msix_set_enable(dev, 0);
+ dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
+ if (dev->msi_cap)
+ msi_set_enable(dev, 0);
+
+ /* We needn't check if we have valid MSI-X capability here */
+ dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
+ if (dev->msix_cap)
+ msix_set_enable(dev, 0);
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2461033a..3e23895 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -249,7 +249,9 @@ struct pci_dev {
pci_power_t current_state; /* Current operating state. In ACPI-speak,
this is D0-D3, D0 being fully functional,
and D3 being off. */
- int pm_cap; /* PM capability offset in the
+ u8 msi_cap; /* MSI capability offset */
+ u8 msix_cap; /* MSI-X capability offset */
+ u8 pm_cap; /* PM capability offset in the
configuration space */
unsigned int pme_support:5; /* Bitmask of states from which PME#
can be generated */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] PCI: Remove MSI/MSI-X cap check in pci_msi_check_device()
2013-04-05 2:54 [PATCH v3 0/5] Retrieve MSI/MSIX cap struct for once on setup Gavin Shan
2013-04-05 2:54 ` [PATCH 1/4] PCI: Cache MSI/MSI-X cap in PCI device Gavin Shan
@ 2013-04-05 2:54 ` Gavin Shan
2013-04-05 2:54 ` [PATCH 3/4] PCI: Use cached MSI cap while enabling MSI interrupts Gavin Shan
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Gavin Shan @ 2013-04-05 2:54 UTC (permalink / raw)
To: linux-pci; +Cc: bhelgaas, Gavin Shan
The function pci_msi_check_device() is called while enabling MSI
or MSI-X interrupts to make sure the PCI device can support MSI
or MSI-X capability. The patch removes the check on MSI or MSI-X
capability in the function and lets the caller does the check.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
drivers/pci/msi.c | 5 +----
1 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 5fdc5d9..1ec1ba9 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -789,9 +789,6 @@ static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
if (ret)
return ret;
- if (!pci_find_capability(dev, type))
- return -EINVAL;
-
return 0;
}
@@ -942,7 +939,7 @@ int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
int status, nr_entries;
int i, j;
- if (!entries)
+ if (!entries || !dev->msix_cap)
return -EINVAL;
status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/4] PCI: Use cached MSI cap while enabling MSI interrupts
2013-04-05 2:54 [PATCH v3 0/5] Retrieve MSI/MSIX cap struct for once on setup Gavin Shan
2013-04-05 2:54 ` [PATCH 1/4] PCI: Cache MSI/MSI-X cap in PCI device Gavin Shan
2013-04-05 2:54 ` [PATCH 2/4] PCI: Remove MSI/MSI-X cap check in pci_msi_check_device() Gavin Shan
@ 2013-04-05 2:54 ` Gavin Shan
2013-04-05 2:54 ` [PATCH 4/4] PCI: Use cached MSI-X cap while enabling MSI-X Gavin Shan
[not found] ` <5167564e.c628320a.6610.1710SMTPIN_ADDED_BROKEN@mx.google.com>
4 siblings, 0 replies; 6+ messages in thread
From: Gavin Shan @ 2013-04-05 2:54 UTC (permalink / raw)
To: linux-pci; +Cc: bhelgaas, Gavin Shan
The patch intends to use the cached MSI capability offset in
pci_dev instead of polling that from config space when enabling
MSI interrupts.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
drivers/pci/msi.c | 32 +++++++++++++++-----------------
drivers/pci/msi.h | 1 -
2 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 1ec1ba9..449db36 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -299,10 +299,10 @@ void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
int pos = entry->msi_attrib.pos;
u16 msgctl;
- pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
+ pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
msgctl &= ~PCI_MSI_FLAGS_QSIZE;
msgctl |= entry->msi_attrib.multiple << 4;
- pci_write_config_word(dev, msi_control_reg(pos), msgctl);
+ pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
pci_write_config_dword(dev, msi_lower_address_reg(pos),
msg->address_lo);
@@ -546,14 +546,14 @@ out_unroll:
static int msi_capability_init(struct pci_dev *dev, int nvec)
{
struct msi_desc *entry;
- int pos, ret;
+ int ret;
u16 control;
unsigned mask;
- pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
- msi_set_enable(dev, 0); /* Disable MSI during set up */
+ /* Disable MSI during set up */
+ msi_set_enable(dev, 0);
- pci_read_config_word(dev, msi_control_reg(pos), &control);
+ pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
/* MSI Entry Initialization */
entry = alloc_msi_entry(dev);
if (!entry)
@@ -564,9 +564,9 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
entry->msi_attrib.entry_nr = 0;
entry->msi_attrib.maskbit = is_mask_bit_support(control);
entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
- entry->msi_attrib.pos = pos;
+ entry->msi_attrib.pos = dev->msi_cap;
- entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
+ entry->mask_pos = msi_mask_reg(dev->msi_cap, entry->msi_attrib.is_64);
/* All MSIs are unmasked by default, Mask them all */
if (entry->msi_attrib.maskbit)
pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
@@ -807,13 +807,12 @@ static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
*/
int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
{
- int status, pos, maxvec;
+ int status, maxvec;
u16 msgctl;
- pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
- if (!pos)
+ if (!dev->msi_cap)
return -EINVAL;
- pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
+ pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
if (nvec > maxvec)
return maxvec;
@@ -838,14 +837,13 @@ EXPORT_SYMBOL(pci_enable_msi_block);
int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
{
- int ret, pos, nvec;
+ int ret, nvec;
u16 msgctl;
- pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
- if (!pos)
+ if (!dev->msi_cap)
return -EINVAL;
- pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
+ pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
if (maxvec)
@@ -915,7 +913,7 @@ int pci_msix_table_size(struct pci_dev *dev)
if (!pos)
return 0;
- pci_read_config_word(dev, msi_control_reg(pos), &control);
+ pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
return multi_msix_capable(control);
}
diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h
index 65c42f8..6aa7b19 100644
--- a/drivers/pci/msi.h
+++ b/drivers/pci/msi.h
@@ -6,7 +6,6 @@
#ifndef MSI_H
#define MSI_H
-#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
#define msi_data_reg(base, is64bit) \
--
1.7.5.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/4] PCI: Use cached MSI-X cap while enabling MSI-X
2013-04-05 2:54 [PATCH v3 0/5] Retrieve MSI/MSIX cap struct for once on setup Gavin Shan
` (2 preceding siblings ...)
2013-04-05 2:54 ` [PATCH 3/4] PCI: Use cached MSI cap while enabling MSI interrupts Gavin Shan
@ 2013-04-05 2:54 ` Gavin Shan
[not found] ` <5167564e.c628320a.6610.1710SMTPIN_ADDED_BROKEN@mx.google.com>
4 siblings, 0 replies; 6+ messages in thread
From: Gavin Shan @ 2013-04-05 2:54 UTC (permalink / raw)
To: linux-pci; +Cc: bhelgaas, Gavin Shan
The patch intends to use the cached MSI-X capability offset in
pci_dev instead of polling that from config space when enabling
MSI-X interrupts.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
drivers/pci/msi.c | 34 +++++++++++++++-------------------
1 files changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 449db36..212cea3 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -599,14 +599,14 @@ static int msi_capability_init(struct pci_dev *dev, int nvec)
return 0;
}
-static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
- unsigned nr_entries)
+static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
{
resource_size_t phys_addr;
u32 table_offset;
u8 bir;
- pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
+ pci_read_config_dword(dev,
+ msix_table_offset_reg(dev->msix_cap), &table_offset);
bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
phys_addr = pci_resource_start(dev, bir) + table_offset;
@@ -614,9 +614,8 @@ static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
}
-static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
- void __iomem *base, struct msix_entry *entries,
- int nvec)
+static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
+ struct msix_entry *entries, int nvec)
{
struct msi_desc *entry;
int i;
@@ -636,7 +635,7 @@ static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
entry->msi_attrib.is_64 = 1;
entry->msi_attrib.entry_nr = entries[i].entry;
entry->msi_attrib.default_irq = dev->irq;
- entry->msi_attrib.pos = pos;
+ entry->msi_attrib.pos = dev->msix_cap;
entry->mask_base = base;
list_add_tail(&entry->list, &dev->msi_list);
@@ -676,23 +675,22 @@ static void msix_program_entries(struct pci_dev *dev,
static int msix_capability_init(struct pci_dev *dev,
struct msix_entry *entries, int nvec)
{
- int pos, ret;
+ int ret;
u16 control;
void __iomem *base;
- pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
- pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
+ pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
/* Ensure MSI-X is disabled while it is set up */
control &= ~PCI_MSIX_FLAGS_ENABLE;
- pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
+ pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
/* Request & Map MSI-X table region */
- base = msix_map_region(dev, pos, multi_msix_capable(control));
+ base = msix_map_region(dev, multi_msix_capable(control));
if (!base)
return -ENOMEM;
- ret = msix_setup_entries(dev, pos, base, entries, nvec);
+ ret = msix_setup_entries(dev, base, entries, nvec);
if (ret)
return ret;
@@ -706,7 +704,7 @@ static int msix_capability_init(struct pci_dev *dev,
* interrupts coming in before they're fully set up.
*/
control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
- pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
+ pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
msix_program_entries(dev, entries);
@@ -721,7 +719,7 @@ static int msix_capability_init(struct pci_dev *dev,
dev->msix_enabled = 1;
control &= ~PCI_MSIX_FLAGS_MASKALL;
- pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
+ pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
return 0;
@@ -906,14 +904,12 @@ EXPORT_SYMBOL(pci_disable_msi);
*/
int pci_msix_table_size(struct pci_dev *dev)
{
- int pos;
u16 control;
- pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
- if (!pos)
+ if (!dev->msix_cap)
return 0;
- pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
+ pci_read_config_word(dev, dev->msix_cap + PCI_MSI_FLAGS, &control);
return multi_msix_capable(control);
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 6+ messages in thread[parent not found: <5167564e.c628320a.6610.1710SMTPIN_ADDED_BROKEN@mx.google.com>]
* Re: [PATCH v3 0/5] Retrieve MSI/MSIX cap struct for once on setup
[not found] ` <5167564e.c628320a.6610.1710SMTPIN_ADDED_BROKEN@mx.google.com>
@ 2013-04-22 23:11 ` Bjorn Helgaas
0 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2013-04-22 23:11 UTC (permalink / raw)
To: Gavin Shan; +Cc: linux-pci
On Thu, Apr 11, 2013 at 6:33 PM, Gavin Shan <shangw@linux.vnet.ibm.com> wrote:
> On Fri, Apr 05, 2013 at 11:01:18AM +0800, Gavin Shan wrote:
>>On Fri, Apr 05, 2013 at 10:54:29AM +0800, Gavin Shan wrote:
>>
>>The subject should be "[0/4]" instead of "[0/5]". Forgot to change
>>that accordingly. Sorry for the confusion ;-)
>>
>
> Bjorn, did you get change taking a look on this? Please let me know
> if you have more comments :-)
I did look at it; it looks good, and I made some more cleanups, which
I just posted as a "v4" series. Take a look and see if it makes sense
to you.
Bjorn
>>>While we setup MSI or MSI-X for specific PCI device, the address of
>>>MSI or MSI-X capability structure is figured out from the config
>>>space for multiple times. That's unnecessary and the patchset addresses
>>>that. With the patchset applied, the latency for MSI or MSI-X setup
>>>would be decreased hopefully.
>>>
>>>v2 -> v3:
>>> * Remove checking on MSI/MSI-X capability offset in msi_set_enable()
>>> and msix_set_enable(). Let the caller does the check
>>> * Using "u8" for MSI/MSI-X/PM capability
>>> * Let caller of pci_msi_check_device() checks MSI/MSI-X capability
>>> * Replace msi_control_reg() with "pos + PCI_MSI_FLAGS"
>>> * Merge [4/5] to [3/5]
>>>v1 -> v2:
>>> * Cache the MSI/MSI-X capability offset to pci_dev directly according
>>> to Bjorn's suggestion.
>>> * Rebase to 3.9.RC5
>>>
>>>---
>>>
>>>drivers/pci/msi.c | 110 +++++++++++++++++++++++----------------------------
>>>drivers/pci/msi.h | 1 -
>>>include/linux/pci.h | 4 +-
>>>3 files changed, 52 insertions(+), 63 deletions(-)
>>>
>>>Thanks,
>>>Gavin
>>>
>
^ permalink raw reply [flat|nested] 6+ messages in thread