* [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support
@ 2024-03-12 7:03 Sumit Garg
2024-03-12 7:03 ` [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks Sumit Garg
` (11 more replies)
0 siblings, 12 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
rather tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Testing with this patch-set included:
Verdin iMX8MP # pci enum
PCIE-0: Link up (Gen1-x1, Bus0)
Verdin iMX8MP #
Verdin iMX8MP # nvme scan
Verdin iMX8MP #
Verdin iMX8MP # nvme info
Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000000000000000720
Type: Hard Disk
Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
Verdin iMX8MP #
Verdin iMX8MP # load nvme 0 $loadaddr <file-name>
Changes in v3:
- Rebased on top of U-Boot next.
- Incorporated misc. updates to commit messages.
- New patch#2 to refactor reset driver function names.
- Patch#3: Refactored further for better code reuse.
- New patch#4 to fix refcount issue with power domain bus.
- Patch#5: Refactored further for better code reuse.
- Patch#7 & #8: Added dependency on REGMAP and SYSCON. Also, added
support for vpcie-supply regulator.
- Patch#7 & #8: Added error paths and .remove callback.
- New patch#10 to enable PCIe/NVMe for imx8mp_venice*.
Changes in v2:
- Renamed PCIe IMX driver pcie_dw_imx8.c -> pcie_dw_imx.c.
- Added myself as maintainer for PCIe DWC IMX driver support.
- Incorporated various code and commit message improvement suggestions
from Marek, thanks.
- Patch#3: Gate PCIe and USB clocks behind corresponding power domain
IDs.
- Patch#4: Expose HSIO PLL clocks as a regular clock driver instead
similar to what Linux kernel does.
- Patch#7: Picked up tags.
Sumit Garg (10):
clk: imx8mp: Add support for PCIe clocks
reset: imx: Refactor driver to simplify function names
reset: imx: Add support for i.MX8MP reset controller
imx8mp: power-domain: Don't power off pd_bus
imx8mp: power-domain: Add PCIe support
imx8mp: power-domain: Expose high performance PLL clock
phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
pci: Add DW PCIe controller support for iMX8MP SoC
verdin-imx8mp_defconfig: Enable PCIe/NVMe support
MAINTAINERS: Add entry for PCIe DWC IMX driver
Tim Harvey (1):
imx8mp_venice_defconfig: Enable PCIe/NVMe support
MAINTAINERS | 6 +
configs/imx8mp_venice_defconfig | 8 +
configs/verdin-imx8mp_defconfig | 6 +
drivers/clk/imx/clk-imx8mp.c | 6 +
drivers/pci/Kconfig | 11 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx.c | 338 ++++++++++++++++++++++++++
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8m-pcie.c | 283 +++++++++++++++++++++
drivers/power/domain/imx8mp-hsiomix.c | 191 ++++++++++++---
drivers/reset/reset-imx7.c | 125 +++++++++-
12 files changed, 937 insertions(+), 50 deletions(-)
create mode 100644 drivers/pci/pcie_dw_imx.c
create mode 100644 drivers/phy/phy-imx8m-pcie.c
--
2.34.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 3:51 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names Sumit Garg
` (10 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
Add support for PCIe clocks required to enable PCIe support on
iMX8MP SoC.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/clk/imx/clk-imx8mp.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index a21a3ce34bb..7dfc829df2c 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -62,6 +62,10 @@ static const char *imx8mp_dram_apb_sels[] = {"clock-osc-24m", "sys_pll2_200m", "
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", };
+static const char * const imx8mp_pcie_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m",
+ "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
+ "sys_pll1_160m", "sys_pll1_200m", };
+
static const char *imx8mp_i2c5_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m",
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
"audio_pll2_out", "sys_pll1_133m", };
@@ -272,6 +276,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_DRAM_ALT, imx8m_clk_composite("dram_alt", imx8mp_dram_alt_sels, base + 0xa000));
clk_dm(IMX8MP_CLK_DRAM_APB, imx8m_clk_composite_critical("dram_apb", imx8mp_dram_apb_sels, base + 0xa080));
+ clk_dm(IMX8MP_CLK_PCIE_AUX, imx8m_clk_composite("pcie_aux", imx8mp_pcie_aux_sels, base + 0xa400));
clk_dm(IMX8MP_CLK_I2C5, imx8m_clk_composite("i2c5", imx8mp_i2c5_sels, base + 0xa480));
clk_dm(IMX8MP_CLK_I2C6, imx8m_clk_composite("i2c6", imx8mp_i2c6_sels, base + 0xa500));
clk_dm(IMX8MP_CLK_ENET_QOS, imx8m_clk_composite("enet_qos", imx8mp_enet_qos_sels, base + 0xa880));
@@ -322,6 +327,7 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_I2C2_ROOT, imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
clk_dm(IMX8MP_CLK_I2C3_ROOT, imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
clk_dm(IMX8MP_CLK_I2C4_ROOT, imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+ clk_dm(IMX8MP_CLK_PCIE_ROOT, imx_clk_gate4("pcie_root_clk", "pcie_aux", base + 0x4250, 0));
clk_dm(IMX8MP_CLK_PWM1_ROOT, imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
clk_dm(IMX8MP_CLK_PWM2_ROOT, imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
clk_dm(IMX8MP_CLK_PWM3_ROOT, imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
2024-03-12 7:03 ` [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 3:52 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller Sumit Garg
` (9 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
with imx*_reset_{deassert/assert}. So refactor driver to use function
names easier to understand. This shouldn't affect the functionality
though.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/reset/reset-imx7.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index eaef2cc2cdf..4c7fa19d495 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -64,7 +64,7 @@ static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
[IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) },
};
-static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
+static int imx7_reset_deassert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx7_src_signals;
@@ -95,7 +95,7 @@ static int imx7_reset_deassert_imx7(struct reset_ctl *rst)
return 0;
}
-static int imx7_reset_assert_imx7(struct reset_ctl *rst)
+static int imx7_reset_assert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx7_src_signals;
@@ -185,7 +185,7 @@ static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
};
-static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
+static int imx8mq_reset_deassert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx8mq_src_signals;
@@ -223,7 +223,7 @@ static int imx7_reset_deassert_imx8mq(struct reset_ctl *rst)
return 0;
}
-static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
+static int imx8mq_reset_assert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
const struct imx7_src_signal *sig = imx8mq_src_signals;
@@ -252,21 +252,21 @@ static int imx7_reset_assert_imx8mq(struct reset_ctl *rst)
return 0;
}
-static int imx7_reset_assert(struct reset_ctl *rst)
+static int imx_reset_assert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
return priv->ops.rst_assert(rst);
}
-static int imx7_reset_deassert(struct reset_ctl *rst)
+static int imx_reset_deassert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
return priv->ops.rst_deassert(rst);
}
static const struct reset_ops imx7_reset_reset_ops = {
- .rst_assert = imx7_reset_assert,
- .rst_deassert = imx7_reset_deassert,
+ .rst_assert = imx_reset_assert,
+ .rst_deassert = imx_reset_deassert,
};
static const struct udevice_id imx7_reset_ids[] = {
@@ -284,11 +284,11 @@ static int imx7_reset_probe(struct udevice *dev)
return -ENOMEM;
if (device_is_compatible(dev, "fsl,imx8mq-src")) {
- priv->ops.rst_assert = imx7_reset_assert_imx8mq;
- priv->ops.rst_deassert = imx7_reset_deassert_imx8mq;
+ priv->ops.rst_assert = imx8mq_reset_assert;
+ priv->ops.rst_deassert = imx8mq_reset_deassert;
} else if (device_is_compatible(dev, "fsl,imx7d-src")) {
- priv->ops.rst_assert = imx7_reset_assert_imx7;
- priv->ops.rst_deassert = imx7_reset_deassert_imx7;
+ priv->ops.rst_assert = imx7_reset_assert;
+ priv->ops.rst_deassert = imx7_reset_deassert;
}
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
2024-03-12 7:03 ` [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks Sumit Garg
2024-03-12 7:03 ` [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 3:55 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus Sumit Garg
` (8 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
Add support for i.MX8MP reset controller, it has same reset IP inside
as the other iMX7 and iMX8 variants but with different module layout.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/reset/reset-imx7.c | 101 +++++++++++++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
index 4c7fa19d495..90d3d75255e 100644
--- a/drivers/reset/reset-imx7.c
+++ b/drivers/reset/reset-imx7.c
@@ -10,6 +10,7 @@
#include <dm.h>
#include <dt-bindings/reset/imx7-reset.h>
#include <dt-bindings/reset/imx8mq-reset.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
#include <reset-uclass.h>
#include <linux/bitops.h>
#include <linux/delay.h>
@@ -252,6 +253,102 @@ static int imx8mq_reset_assert(struct reset_ctl *rst)
return 0;
}
+enum imx8mp_src_registers {
+ SRC_SUPERMIX_RCR = 0x0018,
+ SRC_AUDIOMIX_RCR = 0x001c,
+ SRC_MLMIX_RCR = 0x0028,
+ SRC_GPU2D_RCR = 0x0038,
+ SRC_GPU3D_RCR = 0x003c,
+ SRC_VPU_G1_RCR = 0x0048,
+ SRC_VPU_G2_RCR = 0x004c,
+ SRC_VPUVC8KE_RCR = 0x0050,
+ SRC_NOC_RCR = 0x0054,
+};
+
+static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
+ [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
+ [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
+ [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
+ [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
+ [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
+ [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
+ [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
+ [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
+ [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
+ [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
+ [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
+ [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
+ [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
+ [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
+ [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
+ [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
+ [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
+ [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
+ [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
+ [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
+ [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
+ [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
+ [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
+ [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
+ [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
+ [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
+ [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
+ [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
+ [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
+};
+
+static int imx8mp_reset_set(struct reset_ctl *rst, bool assert)
+{
+ struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
+ unsigned int bit, value;
+
+ if (rst->id >= IMX8MP_RESET_NUM)
+ return -EINVAL;
+
+ bit = imx8mp_src_signals[rst->id].bit;
+ value = assert ? bit : 0;
+
+ switch (rst->id) {
+ case IMX8MP_RESET_PCIEPHY:
+ /*
+ * wait for more than 10us to release phy g_rst and
+ * btnrst
+ */
+ if (!assert)
+ udelay(10);
+ break;
+
+ case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
+ case IMX8MP_RESET_PCIEPHY_PERST:
+ value = assert ? 0 : bit;
+ break;
+ }
+
+ clrsetbits_le32(priv->base + imx8mp_src_signals[rst->id].offset, bit,
+ value);
+
+ return 0;
+}
+
+static int imx8mp_reset_assert(struct reset_ctl *rst)
+{
+ return imx8mp_reset_set(rst, true);
+}
+
+static int imx8mp_reset_deassert(struct reset_ctl *rst)
+{
+ return imx8mp_reset_set(rst, false);
+}
+
static int imx_reset_assert(struct reset_ctl *rst)
{
struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
@@ -272,6 +369,7 @@ static const struct reset_ops imx7_reset_reset_ops = {
static const struct udevice_id imx7_reset_ids[] = {
{ .compatible = "fsl,imx7d-src" },
{ .compatible = "fsl,imx8mq-src" },
+ { .compatible = "fsl,imx8mp-src" },
{ }
};
@@ -289,6 +387,9 @@ static int imx7_reset_probe(struct udevice *dev)
} else if (device_is_compatible(dev, "fsl,imx7d-src")) {
priv->ops.rst_assert = imx7_reset_assert;
priv->ops.rst_deassert = imx7_reset_deassert;
+ } else if (device_is_compatible(dev, "fsl,imx8mp-src")) {
+ priv->ops.rst_assert = imx8mp_reset_assert;
+ priv->ops.rst_deassert = imx8mp_reset_deassert;
}
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (2 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 3:59 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support Sumit Garg
` (7 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
power_domain_on/off() isn't refcounted and power domain bus shouldn't be
turned off for a single peripheral domain as it would negatively affect
other peripheral domains. So lets just skip turning off bus power
domain.
Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/power/domain/imx8mp-hsiomix.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c5ec7..448746432a2 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
ret = power_domain_on(domain);
if (ret)
- goto err_pd;
+ return ret;
ret = clk_enable(&priv->clk_usb);
if (ret)
@@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
err_clk:
power_domain_off(domain);
-err_pd:
- power_domain_off(&priv->pd_bus);
return ret;
}
@@ -85,8 +83,6 @@ static int imx8mp_hsiomix_off(struct power_domain *power_domain)
else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
power_domain_off(&priv->pd_usb_phy2);
- power_domain_off(&priv->pd_bus);
-
return 0;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (3 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 4:03 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock Sumit Garg
` (6 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
Add support for GPCv2 power domains and clock handling for PCIe and
PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/power/domain/imx8mp-hsiomix.c | 114 ++++++++++++++++++--------
1 file changed, 78 insertions(+), 36 deletions(-)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
index 448746432a2..fb8041749ec 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -16,48 +16,84 @@
#define GPR_REG0 0x0
#define PCIE_CLOCK_MODULE_EN BIT(0)
#define USB_CLOCK_MODULE_EN BIT(1)
+#define PCIE_PHY_APB_RST BIT(4)
+#define PCIE_PHY_INIT_RST BIT(5)
struct imx8mp_hsiomix_priv {
void __iomem *base;
struct clk clk_usb;
+ struct clk clk_pcie;
struct power_domain pd_bus;
struct power_domain pd_usb;
+ struct power_domain pd_pcie;
struct power_domain pd_usb_phy1;
struct power_domain pd_usb_phy2;
+ struct power_domain pd_pcie_phy;
};
-static int imx8mp_hsiomix_on(struct power_domain *power_domain)
+static int imx8mp_hsiomix_set(struct power_domain *power_domain, bool power_on)
{
struct udevice *dev = power_domain->dev;
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
- struct power_domain *domain;
+ struct power_domain *domain = NULL;
+ struct clk *clk = NULL;
+ u32 gpr_reg0_bits = 0;
int ret;
- ret = power_domain_on(&priv->pd_bus);
- if (ret)
- return ret;
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) {
+ switch (power_domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
domain = &priv->pd_usb;
- } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) {
+ clk = &priv->clk_usb;
+ gpr_reg0_bits |= USB_CLOCK_MODULE_EN;
+ break;
+ case IMX8MP_HSIOBLK_PD_USB_PHY1:
domain = &priv->pd_usb_phy1;
- } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) {
+ break;
+ case IMX8MP_HSIOBLK_PD_USB_PHY2:
domain = &priv->pd_usb_phy2;
- } else {
- ret = -EINVAL;
- goto err_pd;
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ domain = &priv->pd_pcie;
+ clk = &priv->clk_pcie;
+ gpr_reg0_bits |= PCIE_CLOCK_MODULE_EN;
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+ domain = &priv->pd_pcie_phy;
+ /* Bits to deassert PCIe PHY reset */
+ gpr_reg0_bits |= PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST;
+ break;
+ default:
+ dev_err(dev, "unknown power domain id: %ld\n",
+ power_domain->id);
+ return -EINVAL;
}
- ret = power_domain_on(domain);
- if (ret)
- return ret;
+ if (power_on) {
+ ret = power_domain_on(&priv->pd_bus);
+ if (ret)
+ return ret;
+
+ ret = power_domain_on(domain);
+ if (ret)
+ return ret;
+
+ if (clk) {
+ ret = clk_enable(clk);
+ if (ret)
+ goto err_clk;
+ }
- ret = clk_enable(&priv->clk_usb);
- if (ret)
- goto err_clk;
+ if (gpr_reg0_bits)
+ setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
+ } else {
+ power_domain_off(domain);
+
+ if (clk)
+ clk_disable(clk);
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
+ if (gpr_reg0_bits)
+ clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
+ }
return 0;
@@ -66,24 +102,14 @@ err_clk:
return ret;
}
-static int imx8mp_hsiomix_off(struct power_domain *power_domain)
+static int imx8mp_hsiomix_on(struct power_domain *power_domain)
{
- struct udevice *dev = power_domain->dev;
- struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN);
-
- clk_disable(&priv->clk_usb);
-
- if (power_domain->id == IMX8MP_HSIOBLK_PD_USB)
- power_domain_off(&priv->pd_usb);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1)
- power_domain_off(&priv->pd_usb_phy1);
- else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2)
- power_domain_off(&priv->pd_usb_phy2);
+ return imx8mp_hsiomix_set(power_domain, true);
+}
- return 0;
+static int imx8mp_hsiomix_off(struct power_domain *power_domain)
+{
+ return imx8mp_hsiomix_set(power_domain, false);
}
static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain,
@@ -105,6 +131,10 @@ static int imx8mp_hsiomix_probe(struct udevice *dev)
if (ret < 0)
return ret;
+ ret = clk_get_by_name(dev, "pcie", &priv->clk_pcie);
+ if (ret < 0)
+ return ret;
+
ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus");
if (ret < 0)
return ret;
@@ -121,8 +151,20 @@ static int imx8mp_hsiomix_probe(struct udevice *dev)
if (ret < 0)
goto err_pd_usb_phy2;
+ ret = power_domain_get_by_name(dev, &priv->pd_pcie, "pcie");
+ if (ret < 0)
+ goto err_pd_pcie;
+
+ ret = power_domain_get_by_name(dev, &priv->pd_pcie_phy, "pcie-phy");
+ if (ret < 0)
+ goto err_pd_pcie_phy;
+
return 0;
+err_pd_pcie_phy:
+ power_domain_free(&priv->pd_pcie);
+err_pd_pcie:
+ power_domain_free(&priv->pd_usb_phy2);
err_pd_usb_phy2:
power_domain_free(&priv->pd_usb_phy1);
err_pd_usb_phy1:
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (4 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 4:05 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY Sumit Garg
` (5 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
Expose the high performance PLL as a regular Linux clock, so the
PCIe PHY can use it when there is no external refclock provided.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
platform remove callback returning void").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/power/domain/imx8mp-hsiomix.c | 77 +++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
index fb8041749ec..5ec79fc948c 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -6,9 +6,15 @@
#include <common.h>
#include <asm/io.h>
#include <clk.h>
+#include <clk-uclass.h>
#include <dm.h>
#include <dm/device.h>
#include <dm/device_compat.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <power-domain-uclass.h>
#include <dt-bindings/power/imx8mp-power.h>
@@ -18,6 +24,15 @@
#define USB_CLOCK_MODULE_EN BIT(1)
#define PCIE_PHY_APB_RST BIT(4)
#define PCIE_PHY_INIT_RST BIT(5)
+#define GPR_REG1 0x4
+#define PLL_LOCK BIT(13)
+#define GPR_REG2 0x8
+#define P_PLL_MASK GENMASK(5, 0)
+#define M_PLL_MASK GENMASK(15, 6)
+#define S_PLL_MASK GENMASK(18, 16)
+#define GPR_REG3 0xc
+#define PLL_CKE BIT(17)
+#define PLL_RST BIT(31)
struct imx8mp_hsiomix_priv {
void __iomem *base;
@@ -120,6 +135,67 @@ static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain,
return 0;
}
+static int hsio_pll_clk_enable(struct clk *clk)
+{
+ void *base = (void *)dev_get_driver_data(clk->dev);
+ u32 val;
+ int ret;
+
+ /* Setup HSIO PLL as 100 MHz output clock */
+ clrsetbits_le32(base + GPR_REG2,
+ P_PLL_MASK | M_PLL_MASK | S_PLL_MASK,
+ FIELD_PREP(P_PLL_MASK, 12) |
+ FIELD_PREP(M_PLL_MASK, 800) |
+ FIELD_PREP(S_PLL_MASK, 4));
+
+ /* de-assert PLL reset */
+ setbits_le32(base + GPR_REG3, PLL_RST);
+
+ /* enable PLL */
+ setbits_le32(base + GPR_REG3, PLL_CKE);
+
+ /* Check if PLL is locked */
+ ret = readl_poll_sleep_timeout(base + GPR_REG1, val,
+ val & PLL_LOCK, 10, 100000);
+ if (ret)
+ dev_err(clk->dev, "failed to lock HSIO PLL\n");
+
+ return ret;
+}
+
+static int hsio_pll_clk_disable(struct clk *clk)
+{
+ void *base = (void *)dev_get_driver_data(clk->dev);
+
+ clrbits_le32(base + GPR_REG3, PLL_CKE | PLL_RST);
+
+ return 0;
+}
+
+static const struct clk_ops hsio_pll_clk_ops = {
+ .enable = hsio_pll_clk_enable,
+ .disable = hsio_pll_clk_disable,
+};
+
+U_BOOT_DRIVER(hsio_pll) = {
+ .name = "hsio-pll",
+ .id = UCLASS_CLK,
+ .ops = &hsio_pll_clk_ops,
+};
+
+int imx8mp_hsiomix_bind(struct udevice *dev)
+{
+ struct driver *drv;
+
+ drv = lists_driver_lookup_name("hsio-pll");
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind_with_driver_data(dev, drv, "hsio-pll",
+ (ulong)dev_read_addr_ptr(dev),
+ dev_ofnode(dev), NULL);
+}
+
static int imx8mp_hsiomix_probe(struct udevice *dev)
{
struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev);
@@ -190,6 +266,7 @@ U_BOOT_DRIVER(imx8mp_hsiomix) = {
.id = UCLASS_POWER_DOMAIN,
.of_match = imx8mp_hsiomix_ids,
.probe = imx8mp_hsiomix_probe,
+ .bind = imx8mp_hsiomix_bind,
.priv_auto = sizeof(struct imx8mp_hsiomix_priv),
.ops = &imx8mp_hsiomix_ops,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (5 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 4:15 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC Sumit Garg
` (4 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.
Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/phy/Kconfig | 11 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-imx8m-pcie.c | 283 +++++++++++++++++++++++++++++++++++
3 files changed, 295 insertions(+)
create mode 100644 drivers/phy/phy-imx8m-pcie.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 60138beca49..8f767877e73 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -284,6 +284,17 @@ config PHY_IMX8MQ_USB
help
Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC
+config PHY_IMX8M_PCIE
+ bool "NXP i.MX8MM/i.MX8MP PCIe PHY Driver"
+ depends on PHY
+ depends on IMX8MM || IMX8MP
+ select REGMAP
+ select SYSCON
+ help
+ Support the PCIe PHY in NXP i.MX8MM or i.MX8MP SoC
+
+ This PHY is found on i.MX8M devices supporting PCIe.
+
config PHY_XILINX_ZYNQMP
tristate "Xilinx ZynqMP PHY driver"
depends on PHY && ARCH_ZYNQMP
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2e8723186c0..7a2b764492b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
obj-$(CONFIG_PHY_NPCM_USB) += phy-npcm-usb.o
obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
+obj-$(CONFIG_PHY_IMX8M_PCIE) += phy-imx8m-pcie.o
obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
obj-y += cadence/
obj-y += ti/
diff --git a/drivers/phy/phy-imx8m-pcie.c b/drivers/phy/phy-imx8m-pcie.c
new file mode 100644
index 00000000000..2418388cb3c
--- /dev/null
+++ b/drivers/phy/phy-imx8m-pcie.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 Linaro Ltd.
+ *
+ * Derived from Linux counterpart driver
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <syscon.h>
+#include <regmap.h>
+#include <reset.h>
+
+#include <dt-bindings/phy/phy-imx8-pcie.h>
+
+#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
+#define IMX8MM_PCIE_PHY_CMN_REG062 0x188
+#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3)
+#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C
+#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6)
+#define IMX8MM_PCIE_PHY_CMN_REG064 0x190
+#define ANA_AUX_RX_TX_SEL_TX BIT(7)
+#define ANA_AUX_RX_TERM_GND_EN BIT(3)
+#define ANA_AUX_TX_TERM BIT(2)
+#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
+#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
+#define ANA_AUX_TX_LVL GENMASK(3, 0)
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
+#define PCIE_PHY_TRSV_REG5 0x414
+#define PCIE_PHY_TRSV_REG6 0x418
+
+#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
+#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
+#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2)
+#define IMX8MM_GPR_PCIE_AUX_EN BIT(19)
+#define IMX8MM_GPR_PCIE_CMN_RST BIT(18)
+#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17)
+#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
+#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+
+#define IOMUXC_GPR14_OFFSET 0x38
+
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ const char *gpr;
+ enum imx8_pcie_phy_type variant;
+};
+
+struct imx8_pcie_phy {
+ ulong base;
+ struct clk hsio_clk;
+ struct regmap *iomuxc_gpr;
+ struct reset_ctl perst;
+ struct reset_ctl reset;
+ u32 refclk_pad_mode;
+ u32 tx_deemph_gen1;
+ u32 tx_deemph_gen2;
+ bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
+};
+
+static int imx8_pcie_phy_power_on(struct phy *phy)
+{
+ int ret;
+ u32 val, pad_mode;
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ pad_mode = imx8_phy->refclk_pad_mode;
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ reset_assert(&imx8_phy->reset);
+
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP: /* Do nothing. */
+ break;
+ }
+
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
+ pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+ /* Configure the pad as input */
+ val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+ writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+ } else {
+ /* Configure the PHY to output the refclock via pad */
+ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+ }
+
+ if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
+ pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+ /* Source clock from SoC internal PLL */
+ writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
+ writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+ val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
+ writel(val | ANA_AUX_RX_TERM_GND_EN,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
+ writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,
+ imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
+ }
+
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ udelay(200);
+
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_deassert(&imx8_phy->perst);
+ fallthrough;
+ case IMX8MM:
+ reset_deassert(&imx8_phy->reset);
+ udelay(500);
+ break;
+ }
+
+ /* Polling to check the phy is ready or not. */
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 20000);
+ return ret;
+}
+
+static int imx8_pcie_phy_init(struct phy *phy)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ return clk_enable(&imx8_phy->hsio_clk);
+}
+
+static int imx8_pcie_phy_exit(struct phy *phy)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(phy->dev);
+
+ return clk_disable(&imx8_phy->hsio_clk);
+}
+
+static const struct phy_ops imx8_pcie_phy_ops = {
+ .init = imx8_pcie_phy_init,
+ .exit = imx8_pcie_phy_exit,
+ .power_on = imx8_pcie_phy_power_on,
+};
+
+static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ .variant = IMX8MM,
+};
+
+static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ .variant = IMX8MP,
+};
+
+static const struct udevice_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = (ulong)&imx8mm_drvdata, },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = (ulong)&imx8mp_drvdata, },
+ { },
+};
+
+static int imx8_pcie_phy_probe(struct udevice *dev)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
+ ofnode gpr;
+ int ret = 0;
+
+ imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
+ imx8_phy->base = dev_read_addr(dev);
+ if (!imx8_phy->base)
+ return -EINVAL;
+
+ /* get PHY refclk pad mode */
+ dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
+
+ imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
+ "fsl,tx-deemph-gen1",
+ 0);
+ imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
+ "fsl,tx-deemph-gen2",
+ 0);
+ imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
+
+ /* Grab GPR config register range */
+ gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
+ if (ofnode_equal(gpr, ofnode_null())) {
+ dev_err(dev, "unable to find GPR node\n");
+ return -ENODEV;
+ }
+
+ imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
+ if (IS_ERR(imx8_phy->iomuxc_gpr)) {
+ dev_err(dev, "unable to find iomuxc registers\n");
+ return PTR_ERR(imx8_phy->iomuxc_gpr);
+ }
+
+ ret = clk_get_by_name(dev, "ref", &imx8_phy->hsio_clk);
+ if (ret) {
+ dev_err(dev, "Failed to get PCIEPHY ref clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "pciephy", &imx8_phy->reset);
+ if (ret) {
+ dev_err(dev, "Failed to get PCIEPHY reset control\n");
+ return ret;
+ }
+
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ ret = reset_get_by_name(dev, "perst", &imx8_phy->perst);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get PCIEPHY PHY PERST control\n");
+ goto err_perst;
+ }
+ }
+
+ return 0;
+
+err_perst:
+ reset_free(&imx8_phy->reset);
+ return ret;
+}
+
+static int imx8_pcie_phy_remove(struct udevice *dev)
+{
+ struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
+
+ if (imx8_phy->drvdata->variant == IMX8MP)
+ reset_free(&imx8_phy->perst);
+
+ reset_free(&imx8_phy->reset);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(nxp_imx8_pcie_phy) = {
+ .name = "nxp_imx8_pcie_phy",
+ .id = UCLASS_PHY,
+ .of_match = imx8_pcie_phy_of_match,
+ .probe = imx8_pcie_phy_probe,
+ .remove = imx8_pcie_phy_remove,
+ .ops = &imx8_pcie_phy_ops,
+ .priv_auto = sizeof(struct imx8_pcie_phy),
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (6 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-14 4:13 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 09/11] verdin-imx8mp_defconfig: Enable PCIe/NVMe support Sumit Garg
` (3 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
tied to quite old port of pcie_designware driver from Linux which
suffices only iMX6 specific needs.
But currently we have the common DWC specific bits which alligns pretty
well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
add support for other iMX8 variants to this driver.
iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
can reuse the generic PHY infrastructure to power on PCIe PHY.
Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/pci/Kconfig | 11 ++
drivers/pci/Makefile | 1 +
drivers/pci/pcie_dw_imx.c | 338 ++++++++++++++++++++++++++++++++++++++
3 files changed, 350 insertions(+)
create mode 100644 drivers/pci/pcie_dw_imx.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 463ec47eb92..8d02ab82ad9 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -413,4 +413,15 @@ config PCIE_STARFIVE_JH7110
Say Y here if you want to enable PLDA XpressRich PCIe controller
support on StarFive JH7110 SoC.
+config PCIE_DW_IMX
+ bool "i.MX DW PCIe controller support"
+ depends on ARCH_IMX8M
+ select PCIE_DW_COMMON
+ select DM_REGULATOR
+ select REGMAP
+ select SYSCON
+ help
+ Say Y here if you want to enable DW PCIe controller support on
+ iMX SoCs.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 72ef8b4bc77..2927c519129 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -53,3 +53,4 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
+obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o
diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
new file mode 100644
index 00000000000..a9e62da69f6
--- /dev/null
+++ b/drivers/pci/pcie_dw_imx.c
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Linaro Ltd.
+ *
+ * Author: Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <log.h>
+#include <pci.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+#include <time.h>
+
+#include "pcie_dw_common.h"
+
+#define PCIE_LINK_CAPABILITY 0x7c
+#define TARGET_LINK_SPEED_MASK 0xf
+#define LINK_SPEED_GEN_1 0x1
+#define LINK_SPEED_GEN_2 0x2
+#define LINK_SPEED_GEN_3 0x3
+
+#define PCIE_MISC_CONTROL_1_OFF 0x8bc
+#define PCIE_DBI_RO_WR_EN BIT(0)
+
+#define PCIE_PORT_DEBUG0 0x728
+#define PCIE_PORT_DEBUG1 0x72c
+#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
+#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
+
+#define PCIE_LINK_UP_TIMEOUT_MS 100
+
+#define IOMUXC_GPR14_OFFSET 0x38
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+
+struct pcie_dw_imx {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+ struct regmap *iomuxc_gpr;
+ struct clk_bulk clks;
+ struct gpio_desc reset_gpio;
+ struct reset_ctl apps_reset;
+ struct phy phy;
+ struct udevice *vpcie;
+};
+
+static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
+{
+ dw_pcie_dbi_write_enable(&priv->dw, true);
+
+ clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY,
+ TARGET_LINK_SPEED_MASK, cap_speed);
+
+ dw_pcie_dbi_write_enable(&priv->dw, false);
+}
+
+static void imx_pcie_ltssm_enable(struct pcie_dw_imx *priv)
+{
+ reset_deassert(&priv->apps_reset);
+}
+
+static void imx_pcie_ltssm_disable(struct pcie_dw_imx *priv)
+{
+ reset_assert(&priv->apps_reset);
+}
+
+static bool is_link_up(u32 val)
+{
+ return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
+ (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
+}
+
+static int wait_link_up(struct pcie_dw_imx *priv)
+{
+ u32 val;
+
+ return readl_poll_sleep_timeout(priv->dw.dbi_base + PCIE_PORT_DEBUG1,
+ val, is_link_up(val), 10000, 100000);
+}
+
+static int pcie_link_up(struct pcie_dw_imx *priv, u32 cap_speed)
+{
+ int ret;
+
+ /* DW pre link configurations */
+ pcie_dw_configure(priv, cap_speed);
+
+ /* Initiate link training */
+ imx_pcie_ltssm_enable(priv);
+
+ /* Check that link was established */
+ ret = wait_link_up(priv);
+ if (ret)
+ imx_pcie_ltssm_disable(priv);
+
+ return ret;
+}
+
+static int imx_pcie_assert_core_reset(struct pcie_dw_imx *priv)
+{
+ if (dm_gpio_is_valid(&priv->reset_gpio)) {
+ dm_gpio_set_value(&priv->reset_gpio, 1);
+ mdelay(20);
+ }
+
+ return reset_assert(&priv->apps_reset);
+}
+
+static int imx_pcie_clk_enable(struct pcie_dw_imx *priv)
+{
+ int ret;
+
+ ret = clk_enable_bulk(&priv->clks);
+ if (ret)
+ return ret;
+
+ /*
+ * Set the over ride low and enabled make sure that
+ * REF_CLK is turned on.
+ */
+ regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE, 0);
+ regmap_update_bits(priv->iomuxc_gpr, IOMUXC_GPR14_OFFSET,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ IMX8M_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
+
+ /* allow the clocks to stabilize */
+ udelay(500);
+
+ return 0;
+}
+
+static void imx_pcie_deassert_core_reset(struct pcie_dw_imx *priv)
+{
+ if (!dm_gpio_is_valid(&priv->reset_gpio))
+ return;
+
+ mdelay(100);
+ dm_gpio_set_value(&priv->reset_gpio, 0);
+ /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */
+ mdelay(100);
+}
+
+static int pcie_dw_imx_probe(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ int ret;
+
+ if (priv->vpcie) {
+ ret = regulator_set_enable(priv->vpcie, true);
+ if (ret) {
+ dev_err(dev, "failed to enable vpcie regulator\n");
+ return ret;
+ }
+ }
+
+ ret = imx_pcie_assert_core_reset(priv);
+ if (ret) {
+ dev_err(dev, "failed to assert core reset\n");
+ return ret;
+ }
+
+ ret = imx_pcie_clk_enable(priv);
+ if (ret) {
+ dev_err(dev, "failed to enable clocks\n");
+ goto err_clk;
+ }
+
+ ret = generic_phy_init(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to initialize PHY\n");
+ goto err_phy_init;
+ }
+
+ ret = generic_phy_power_on(&priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to power on PHY\n");
+ goto err_phy_power;
+ }
+
+ imx_pcie_deassert_core_reset(priv);
+
+ priv->dw.first_busno = dev_seq(dev);
+ priv->dw.dev = dev;
+ pcie_dw_setup_host(&priv->dw);
+
+ if (pcie_link_up(priv, LINK_SPEED_GEN_1)) {
+ printf("PCIE-%d: Link down\n", dev_seq(dev));
+ ret = -ENODEV;
+ goto err_link;
+ }
+
+ printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev_seq(dev),
+ pcie_dw_get_link_speed(&priv->dw),
+ pcie_dw_get_link_width(&priv->dw),
+ hose->first_busno);
+
+ pcie_dw_prog_outbound_atu_unroll(&priv->dw, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_MEM,
+ priv->dw.mem.phys_start,
+ priv->dw.mem.bus_start, priv->dw.mem.size);
+
+ return 0;
+
+err_link:
+ generic_shutdown_phy(&priv->phy);
+err_phy_power:
+ generic_phy_exit(&priv->phy);
+err_phy_init:
+ clk_disable_bulk(&priv->clks);
+err_clk:
+ imx_pcie_deassert_core_reset(priv);
+
+ return ret;
+}
+
+static int pcie_dw_imx_remove(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+
+ generic_shutdown_phy(&priv->phy);
+ dm_gpio_free(dev, &priv->reset_gpio);
+ reset_free(&priv->apps_reset);
+ clk_release_bulk(&priv->clks);
+
+ return 0;
+}
+
+static int pcie_dw_imx_of_to_plat(struct udevice *dev)
+{
+ struct pcie_dw_imx *priv = dev_get_priv(dev);
+ ofnode gpr;
+ int ret;
+
+ /* Get the controller base address */
+ priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
+ if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get dbi_base address\n");
+ return -EINVAL;
+ }
+
+ /* Get the config space base address and size */
+ priv->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config",
+ &priv->dw.cfg_size);
+ if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "failed to get cfg_base address\n");
+ return -EINVAL;
+ }
+
+ ret = clk_get_bulk(dev, &priv->clks);
+ if (ret) {
+ dev_err(dev, "failed to get PCIe clks\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
+ if (ret) {
+ dev_err(dev,
+ "Failed to get PCIe apps reset control\n");
+ goto err_reset;
+ }
+
+ ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
+ (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
+ if (ret) {
+ dev_err(dev, "unable to get reset-gpio\n");
+ goto err_gpio;
+ }
+
+ ret = generic_phy_get_by_name(dev, "pcie-phy", &priv->phy);
+ if (ret) {
+ dev_err(dev, "failed to get pcie phy\n");
+ goto err_phy;
+ }
+
+ gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr");
+ if (ofnode_equal(gpr, ofnode_null())) {
+ dev_err(dev, "unable to find GPR node\n");
+ ret = -ENODEV;
+ goto err_phy;
+ }
+
+ priv->iomuxc_gpr = syscon_node_to_regmap(gpr);
+ if (IS_ERR(priv->iomuxc_gpr)) {
+ dev_err(dev, "unable to find iomuxc registers\n");
+ ret = PTR_ERR(priv->iomuxc_gpr);
+ goto err_phy;
+ }
+
+ /* vpcie-supply regulator is optional */
+ device_get_supply_regulator(dev, "vpcie-supply", &priv->vpcie);
+
+ return 0;
+
+err_phy:
+ dm_gpio_free(dev, &priv->reset_gpio);
+err_gpio:
+ reset_free(&priv->apps_reset);
+err_reset:
+ clk_release_bulk(&priv->clks);
+
+ return ret;
+}
+
+static const struct dm_pci_ops pcie_dw_imx_ops = {
+ .read_config = pcie_dw_read_config,
+ .write_config = pcie_dw_write_config,
+};
+
+static const struct udevice_id pcie_dw_imx_ids[] = {
+ { .compatible = "fsl,imx8mp-pcie" },
+ { }
+};
+
+U_BOOT_DRIVER(pcie_dw_imx) = {
+ .name = "pcie_dw_imx",
+ .id = UCLASS_PCI,
+ .of_match = pcie_dw_imx_ids,
+ .ops = &pcie_dw_imx_ops,
+ .of_to_plat = pcie_dw_imx_of_to_plat,
+ .probe = pcie_dw_imx_probe,
+ .remove = pcie_dw_imx_remove,
+ .priv_auto = sizeof(struct pcie_dw_imx),
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 09/11] verdin-imx8mp_defconfig: Enable PCIe/NVMe support
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (7 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-12 7:03 ` [PATCH v3 10/11] imx8mp_venice_defconfig: " Sumit Garg
` (2 subsequent siblings)
11 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg, Francesco Dolcini
Enable PCIe/NVMe support. Also, enable the reset driver which
is a prerequisite for PCIe support.
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
configs/verdin-imx8mp_defconfig | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig
index 22b8a334dfa..fefadb344f8 100644
--- a/configs/verdin-imx8mp_defconfig
+++ b/configs/verdin-imx8mp_defconfig
@@ -16,6 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mp-verdin-wifi-dev"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_VERDIN_IMX8MP=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -26,6 +27,7 @@ CONFIG_SPL=y
CONFIG_IMX_BOOTAUX=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x48200000
+CONFIG_PCI=y
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_REMAKE_ELF=y
@@ -77,6 +79,7 @@ CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_READ=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
@@ -145,8 +148,11 @@ CONFIG_DWC_ETH_QOS_IMX=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
CONFIG_PHY=y
CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 10/11] imx8mp_venice_defconfig: Enable PCIe/NVMe support
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (8 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 09/11] verdin-imx8mp_defconfig: Enable PCIe/NVMe support Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-12 7:03 ` [PATCH v3 11/11] MAINTAINERS: Add entry for PCIe DWC IMX driver Sumit Garg
2024-03-12 9:43 ` [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Peter Robinson
11 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
From: Tim Harvey <tharvey@gateworks.com>
Enable PCIe/NVMe support. Also, enable the reset, regmap and syscon
drivers which are a prerequisite for PCIe support.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
configs/imx8mp_venice_defconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig
index 11b356b7785..ff7ea9811ed 100644
--- a/configs/imx8mp_venice_defconfig
+++ b/configs/imx8mp_venice_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice"
CONFIG_SPL_TEXT_BASE=0x920000
CONFIG_TARGET_IMX8MP_VENICE=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
CONFIG_SYS_MONITOR_LEN=524288
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
@@ -21,6 +22,7 @@ CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3f8000
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_PCI=y
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x80000000
CONFIG_LTO=y
@@ -65,6 +67,7 @@ CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_SYS_DISABLE_AUTOLOAD=y
CONFIG_CMD_CACHE=y
@@ -86,6 +89,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_IMX8MP=y
CONFIG_GPIO_HOG=y
@@ -114,7 +119,10 @@ CONFIG_FEC_MXC=y
CONFIG_KSZ9477=y
CONFIG_RGMII=y
CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PHY_IMX8M_PCIE=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v3 11/11] MAINTAINERS: Add entry for PCIe DWC IMX driver
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (9 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 10/11] imx8mp_venice_defconfig: " Sumit Garg
@ 2024-03-12 7:03 ` Sumit Garg
2024-03-12 9:43 ` [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Peter Robinson
11 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 7:03 UTC (permalink / raw)
To: u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson, Sumit Garg
Add myself as maintainer for PCIe DWC IMX driver support.
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fbb82b3df5d..e8fd4644fb4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1378,6 +1378,12 @@ M: Simon Glass <sjg@chromium.org>
S: Maintained
F: tools/patman/
+PCIe DWC IMX
+M: Sumit Garg <sumit.garg@linaro.org>
+S: Maintained
+F: drivers/pci/pcie_dw_imx.c
+F: drivers/phy/phy-imx8m-pcie.c
+
PCI Endpoint
M: Ramon Fried <rfried.dev@gmail.com>
S: Maintained
--
2.34.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
` (10 preceding siblings ...)
2024-03-12 7:03 ` [PATCH v3 11/11] MAINTAINERS: Add entry for PCIe DWC IMX driver Sumit Garg
@ 2024-03-12 9:43 ` Peter Robinson
2024-03-12 9:55 ` Sumit Garg
11 siblings, 1 reply; 42+ messages in thread
From: Peter Robinson @ 2024-03-12 9:43 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
Hi Sumit,
> pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> rather tied to quite old port of pcie_designware driver from Linux which
> suffices only iMX6 specific needs.
>
> But currently we have the common DWC specific bits which alligns pretty
> well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> add support for other iMX8 variants to this driver.
The upstream Linux driver is moving towards a single driver [1] for
imx6 -> imx9, would it be possible to add support for all generations
to this driver and then remove the old driver? That would allow this
single modern driver and removing the old imx6 specific driver.
Peter
[1] https://www.spinics.net/lists/linux-pci/msg150359.html
> iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> can reuse the generic PHY infrastructure to power on PCIe PHY.
>
> Testing with this patch-set included:
>
> Verdin iMX8MP # pci enum
> PCIE-0: Link up (Gen1-x1, Bus0)
> Verdin iMX8MP #
> Verdin iMX8MP # nvme scan
> Verdin iMX8MP #
> Verdin iMX8MP # nvme info
> Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000000000000000720
> Type: Hard Disk
> Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
> Verdin iMX8MP #
> Verdin iMX8MP # load nvme 0 $loadaddr <file-name>
>
> Changes in v3:
> - Rebased on top of U-Boot next.
> - Incorporated misc. updates to commit messages.
> - New patch#2 to refactor reset driver function names.
> - Patch#3: Refactored further for better code reuse.
> - New patch#4 to fix refcount issue with power domain bus.
> - Patch#5: Refactored further for better code reuse.
> - Patch#7 & #8: Added dependency on REGMAP and SYSCON. Also, added
> support for vpcie-supply regulator.
> - Patch#7 & #8: Added error paths and .remove callback.
> - New patch#10 to enable PCIe/NVMe for imx8mp_venice*.
>
> Changes in v2:
> - Renamed PCIe IMX driver pcie_dw_imx8.c -> pcie_dw_imx.c.
> - Added myself as maintainer for PCIe DWC IMX driver support.
> - Incorporated various code and commit message improvement suggestions
> from Marek, thanks.
> - Patch#3: Gate PCIe and USB clocks behind corresponding power domain
> IDs.
> - Patch#4: Expose HSIO PLL clocks as a regular clock driver instead
> similar to what Linux kernel does.
> - Patch#7: Picked up tags.
>
> Sumit Garg (10):
> clk: imx8mp: Add support for PCIe clocks
> reset: imx: Refactor driver to simplify function names
> reset: imx: Add support for i.MX8MP reset controller
> imx8mp: power-domain: Don't power off pd_bus
> imx8mp: power-domain: Add PCIe support
> imx8mp: power-domain: Expose high performance PLL clock
> phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
> pci: Add DW PCIe controller support for iMX8MP SoC
> verdin-imx8mp_defconfig: Enable PCIe/NVMe support
> MAINTAINERS: Add entry for PCIe DWC IMX driver
>
> Tim Harvey (1):
> imx8mp_venice_defconfig: Enable PCIe/NVMe support
>
> MAINTAINERS | 6 +
> configs/imx8mp_venice_defconfig | 8 +
> configs/verdin-imx8mp_defconfig | 6 +
> drivers/clk/imx/clk-imx8mp.c | 6 +
> drivers/pci/Kconfig | 11 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_dw_imx.c | 338 ++++++++++++++++++++++++++
> drivers/phy/Kconfig | 11 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-imx8m-pcie.c | 283 +++++++++++++++++++++
> drivers/power/domain/imx8mp-hsiomix.c | 191 ++++++++++++---
> drivers/reset/reset-imx7.c | 125 +++++++++-
> 12 files changed, 937 insertions(+), 50 deletions(-)
> create mode 100644 drivers/pci/pcie_dw_imx.c
> create mode 100644 drivers/phy/phy-imx8m-pcie.c
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support
2024-03-12 9:43 ` [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Peter Robinson
@ 2024-03-12 9:55 ` Sumit Garg
2024-03-12 10:00 ` Peter Robinson
0 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-12 9:55 UTC (permalink / raw)
To: Peter Robinson
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
Hi Peter,
On Tue, 12 Mar 2024 at 15:13, Peter Robinson <pbrobinson@gmail.com> wrote:
>
> Hi Sumit,
>
> > pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> > rather tied to quite old port of pcie_designware driver from Linux which
> > suffices only iMX6 specific needs.
> >
> > But currently we have the common DWC specific bits which alligns pretty
> > well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> > bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> > add support for other iMX8 variants to this driver.
>
> The upstream Linux driver is moving towards a single driver [1] for
> imx6 -> imx9, would it be possible to add support for all generations
> to this driver and then remove the old driver?
Sorry but that's not in scope of this patch-set and neither do I
possess boards with all the imx* SoC variants.
> That would allow this
> single modern driver and removing the old imx6 specific driver.
Folks interested in this can build up on this patch-set and port other
imx* variants and then we could have a single modern driver.
-Sumit
>
> Peter
>
> [1] https://www.spinics.net/lists/linux-pci/msg150359.html
>
> > iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> > can reuse the generic PHY infrastructure to power on PCIe PHY.
> >
> > Testing with this patch-set included:
> >
> > Verdin iMX8MP # pci enum
> > PCIE-0: Link up (Gen1-x1, Bus0)
> > Verdin iMX8MP #
> > Verdin iMX8MP # nvme scan
> > Verdin iMX8MP #
> > Verdin iMX8MP # nvme info
> > Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000000000000000720
> > Type: Hard Disk
> > Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
> > Verdin iMX8MP #
> > Verdin iMX8MP # load nvme 0 $loadaddr <file-name>
> >
> > Changes in v3:
> > - Rebased on top of U-Boot next.
> > - Incorporated misc. updates to commit messages.
> > - New patch#2 to refactor reset driver function names.
> > - Patch#3: Refactored further for better code reuse.
> > - New patch#4 to fix refcount issue with power domain bus.
> > - Patch#5: Refactored further for better code reuse.
> > - Patch#7 & #8: Added dependency on REGMAP and SYSCON. Also, added
> > support for vpcie-supply regulator.
> > - Patch#7 & #8: Added error paths and .remove callback.
> > - New patch#10 to enable PCIe/NVMe for imx8mp_venice*.
> >
> > Changes in v2:
> > - Renamed PCIe IMX driver pcie_dw_imx8.c -> pcie_dw_imx.c.
> > - Added myself as maintainer for PCIe DWC IMX driver support.
> > - Incorporated various code and commit message improvement suggestions
> > from Marek, thanks.
> > - Patch#3: Gate PCIe and USB clocks behind corresponding power domain
> > IDs.
> > - Patch#4: Expose HSIO PLL clocks as a regular clock driver instead
> > similar to what Linux kernel does.
> > - Patch#7: Picked up tags.
> >
> > Sumit Garg (10):
> > clk: imx8mp: Add support for PCIe clocks
> > reset: imx: Refactor driver to simplify function names
> > reset: imx: Add support for i.MX8MP reset controller
> > imx8mp: power-domain: Don't power off pd_bus
> > imx8mp: power-domain: Add PCIe support
> > imx8mp: power-domain: Expose high performance PLL clock
> > phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
> > pci: Add DW PCIe controller support for iMX8MP SoC
> > verdin-imx8mp_defconfig: Enable PCIe/NVMe support
> > MAINTAINERS: Add entry for PCIe DWC IMX driver
> >
> > Tim Harvey (1):
> > imx8mp_venice_defconfig: Enable PCIe/NVMe support
> >
> > MAINTAINERS | 6 +
> > configs/imx8mp_venice_defconfig | 8 +
> > configs/verdin-imx8mp_defconfig | 6 +
> > drivers/clk/imx/clk-imx8mp.c | 6 +
> > drivers/pci/Kconfig | 11 +
> > drivers/pci/Makefile | 1 +
> > drivers/pci/pcie_dw_imx.c | 338 ++++++++++++++++++++++++++
> > drivers/phy/Kconfig | 11 +
> > drivers/phy/Makefile | 1 +
> > drivers/phy/phy-imx8m-pcie.c | 283 +++++++++++++++++++++
> > drivers/power/domain/imx8mp-hsiomix.c | 191 ++++++++++++---
> > drivers/reset/reset-imx7.c | 125 +++++++++-
> > 12 files changed, 937 insertions(+), 50 deletions(-)
> > create mode 100644 drivers/pci/pcie_dw_imx.c
> > create mode 100644 drivers/phy/phy-imx8m-pcie.c
> >
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support
2024-03-12 9:55 ` Sumit Garg
@ 2024-03-12 10:00 ` Peter Robinson
2024-03-13 6:45 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Peter Robinson @ 2024-03-12 10:00 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Tue, 12 Mar 2024 at 09:55, Sumit Garg <sumit.garg@linaro.org> wrote:
>
> Hi Peter,
>
> On Tue, 12 Mar 2024 at 15:13, Peter Robinson <pbrobinson@gmail.com> wrote:
> >
> > Hi Sumit,
> >
> > > pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> > > rather tied to quite old port of pcie_designware driver from Linux which
> > > suffices only iMX6 specific needs.
> > >
> > > But currently we have the common DWC specific bits which alligns pretty
> > > well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> > > bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> > > add support for other iMX8 variants to this driver.
> >
> > The upstream Linux driver is moving towards a single driver [1] for
> > imx6 -> imx9, would it be possible to add support for all generations
> > to this driver and then remove the old driver?
>
> Sorry but that's not in scope of this patch-set and neither do I
> possess boards with all the imx* SoC variants.
>
> > That would allow this
> > single modern driver and removing the old imx6 specific driver.
>
> Folks interested in this can build up on this patch-set and port other
> imx* variants and then we could have a single modern driver.
That's fine but I think you should document that this can be future
because the case is that these devices are clearly related.
> -Sumit
>
> >
> > Peter
> >
> > [1] https://www.spinics.net/lists/linux-pci/msg150359.html
> >
> > > iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> > > can reuse the generic PHY infrastructure to power on PCIe PHY.
> > >
> > > Testing with this patch-set included:
> > >
> > > Verdin iMX8MP # pci enum
> > > PCIE-0: Link up (Gen1-x1, Bus0)
> > > Verdin iMX8MP #
> > > Verdin iMX8MP # nvme scan
> > > Verdin iMX8MP #
> > > Verdin iMX8MP # nvme info
> > > Device 0: Vendor: 0x126f Rev: T0828A0 Prod: AA000000000000000720
> > > Type: Hard Disk
> > > Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
> > > Verdin iMX8MP #
> > > Verdin iMX8MP # load nvme 0 $loadaddr <file-name>
> > >
> > > Changes in v3:
> > > - Rebased on top of U-Boot next.
> > > - Incorporated misc. updates to commit messages.
> > > - New patch#2 to refactor reset driver function names.
> > > - Patch#3: Refactored further for better code reuse.
> > > - New patch#4 to fix refcount issue with power domain bus.
> > > - Patch#5: Refactored further for better code reuse.
> > > - Patch#7 & #8: Added dependency on REGMAP and SYSCON. Also, added
> > > support for vpcie-supply regulator.
> > > - Patch#7 & #8: Added error paths and .remove callback.
> > > - New patch#10 to enable PCIe/NVMe for imx8mp_venice*.
> > >
> > > Changes in v2:
> > > - Renamed PCIe IMX driver pcie_dw_imx8.c -> pcie_dw_imx.c.
> > > - Added myself as maintainer for PCIe DWC IMX driver support.
> > > - Incorporated various code and commit message improvement suggestions
> > > from Marek, thanks.
> > > - Patch#3: Gate PCIe and USB clocks behind corresponding power domain
> > > IDs.
> > > - Patch#4: Expose HSIO PLL clocks as a regular clock driver instead
> > > similar to what Linux kernel does.
> > > - Patch#7: Picked up tags.
> > >
> > > Sumit Garg (10):
> > > clk: imx8mp: Add support for PCIe clocks
> > > reset: imx: Refactor driver to simplify function names
> > > reset: imx: Add support for i.MX8MP reset controller
> > > imx8mp: power-domain: Don't power off pd_bus
> > > imx8mp: power-domain: Add PCIe support
> > > imx8mp: power-domain: Expose high performance PLL clock
> > > phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
> > > pci: Add DW PCIe controller support for iMX8MP SoC
> > > verdin-imx8mp_defconfig: Enable PCIe/NVMe support
> > > MAINTAINERS: Add entry for PCIe DWC IMX driver
> > >
> > > Tim Harvey (1):
> > > imx8mp_venice_defconfig: Enable PCIe/NVMe support
> > >
> > > MAINTAINERS | 6 +
> > > configs/imx8mp_venice_defconfig | 8 +
> > > configs/verdin-imx8mp_defconfig | 6 +
> > > drivers/clk/imx/clk-imx8mp.c | 6 +
> > > drivers/pci/Kconfig | 11 +
> > > drivers/pci/Makefile | 1 +
> > > drivers/pci/pcie_dw_imx.c | 338 ++++++++++++++++++++++++++
> > > drivers/phy/Kconfig | 11 +
> > > drivers/phy/Makefile | 1 +
> > > drivers/phy/phy-imx8m-pcie.c | 283 +++++++++++++++++++++
> > > drivers/power/domain/imx8mp-hsiomix.c | 191 ++++++++++++---
> > > drivers/reset/reset-imx7.c | 125 +++++++++-
> > > 12 files changed, 937 insertions(+), 50 deletions(-)
> > > create mode 100644 drivers/pci/pcie_dw_imx.c
> > > create mode 100644 drivers/phy/phy-imx8m-pcie.c
> > >
> > > --
> > > 2.34.1
> > >
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support
2024-03-12 10:00 ` Peter Robinson
@ 2024-03-13 6:45 ` Sumit Garg
0 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-13 6:45 UTC (permalink / raw)
To: Peter Robinson
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, marex, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Tue, 12 Mar 2024 at 15:30, Peter Robinson <pbrobinson@gmail.com> wrote:
>
> On Tue, 12 Mar 2024 at 09:55, Sumit Garg <sumit.garg@linaro.org> wrote:
> >
> > Hi Peter,
> >
> > On Tue, 12 Mar 2024 at 15:13, Peter Robinson <pbrobinson@gmail.com> wrote:
> > >
> > > Hi Sumit,
> > >
> > > > pcie_imx doesn't seem to share any useful code for iMX8MP SoC and it is
> > > > rather tied to quite old port of pcie_designware driver from Linux which
> > > > suffices only iMX6 specific needs.
> > > >
> > > > But currently we have the common DWC specific bits which alligns pretty
> > > > well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> > > > bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> > > > add support for other iMX8 variants to this driver.
> > >
> > > The upstream Linux driver is moving towards a single driver [1] for
> > > imx6 -> imx9, would it be possible to add support for all generations
> > > to this driver and then remove the old driver?
> >
> > Sorry but that's not in scope of this patch-set and neither do I
> > possess boards with all the imx* SoC variants.
> >
> > > That would allow this
> > > single modern driver and removing the old imx6 specific driver.
> >
> > Folks interested in this can build up on this patch-set and port other
> > imx* variants and then we could have a single modern driver.
>
> That's fine but I think you should document that this can be future
> because the case is that these devices are clearly related.
>
Sure, I suppose it deserves a header comment for the legacy pcie_imx.c
driver. If I don't see any other comments for this series then I can
make that as a follow-up patch. Otherwise I will fold it into this
series.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks
2024-03-12 7:03 ` [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks Sumit Garg
@ 2024-03-14 3:51 ` Marek Vasut
0 siblings, 0 replies; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 3:51 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> Add support for PCIe clocks required to enable PCIe support on
> iMX8MP SoC.
>
> Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names
2024-03-12 7:03 ` [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names Sumit Garg
@ 2024-03-14 3:52 ` Marek Vasut
2024-03-15 5:36 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 3:52 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
> with imx*_reset_{deassert/assert}. So refactor driver to use function
> names easier to understand. This shouldn't affect the functionality
> though.
>
> Suggested-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
> drivers/reset/reset-imx7.c | 24 ++++++++++++------------
You could even rename the driver itself now, but that would be separate
patch.
> 1 file changed, 12 insertions(+), 12 deletions(-)
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller
2024-03-12 7:03 ` [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller Sumit Garg
@ 2024-03-14 3:55 ` Marek Vasut
2024-03-15 5:35 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 3:55 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> Add support for i.MX8MP reset controller, it has same reset IP inside
> as the other iMX7 and iMX8 variants but with different module layout.
iMX8M , iMX8 is a different SoC .
> Inspired from counterpart Linux kernel v6.8-rc3 driver:
> drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
> commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
>
> Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
> drivers/reset/reset-imx7.c | 101 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
>
> diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
> index 4c7fa19d495..90d3d75255e 100644
> --- a/drivers/reset/reset-imx7.c
> +++ b/drivers/reset/reset-imx7.c
> @@ -10,6 +10,7 @@
> #include <dm.h>
> #include <dt-bindings/reset/imx7-reset.h>
> #include <dt-bindings/reset/imx8mq-reset.h>
> +#include <dt-bindings/reset/imx8mp-reset.h>
Keep the list sorted (P is before Q).
> #include <reset-uclass.h>
> #include <linux/bitops.h>
> #include <linux/delay.h>
> @@ -252,6 +253,102 @@ static int imx8mq_reset_assert(struct reset_ctl *rst)
> return 0;
> }
>
> +enum imx8mp_src_registers {
> + SRC_SUPERMIX_RCR = 0x0018,
> + SRC_AUDIOMIX_RCR = 0x001c,
> + SRC_MLMIX_RCR = 0x0028,
> + SRC_GPU2D_RCR = 0x0038,
> + SRC_GPU3D_RCR = 0x003c,
> + SRC_VPU_G1_RCR = 0x0048,
> + SRC_VPU_G2_RCR = 0x004c,
> + SRC_VPUVC8KE_RCR = 0x0050,
> + SRC_NOC_RCR = 0x0054,
> +};
> +
> +static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
> + [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
> + [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
> + [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
> + [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
> + [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
> + [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
> + [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
> + [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
> + [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
> + [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
> + [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
> + [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
> + [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
> + [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
> + [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
> + [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
> + [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
> + [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
> + [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
> + [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
> + [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
> + [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
> + [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
> + [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
> + [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
> + [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
> + [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
> + [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
> + [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
> + [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
> + [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
> + [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
> + [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
> + [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
> + [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
> + [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
> + [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
> + [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
> +};
> +
> +static int imx8mp_reset_set(struct reset_ctl *rst, bool assert)
> +{
> + struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
It wouldn't hurt to rename imx7_reset_priv to imx_reset_priv in 2/11 too.
With the include sorting fixed:
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-12 7:03 ` [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus Sumit Garg
@ 2024-03-14 3:59 ` Marek Vasut
2024-03-15 5:31 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 3:59 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> turned off for a single peripheral domain as it would negatively affect
> other peripheral domains. So lets just skip turning off bus power
> domain.
What exactly is the issue and how did you trigger it ?
Details please.
> Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
> drivers/power/domain/imx8mp-hsiomix.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
> index e2d772c5ec7..448746432a2 100644
> --- a/drivers/power/domain/imx8mp-hsiomix.c
> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
>
> ret = power_domain_on(domain);
> if (ret)
> - goto err_pd;
> + return ret;
>
> ret = clk_enable(&priv->clk_usb);
> if (ret)
> @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
>
> err_clk:
> power_domain_off(domain);
> -err_pd:
> - power_domain_off(&priv->pd_bus);
> return ret;
Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support
2024-03-12 7:03 ` [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support Sumit Garg
@ 2024-03-14 4:03 ` Marek Vasut
0 siblings, 0 replies; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 4:03 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> Add support for GPCv2 power domains and clock handling for PCIe and
> PCIe PHY.
>
> Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock
2024-03-12 7:03 ` [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock Sumit Garg
@ 2024-03-14 4:05 ` Marek Vasut
2024-03-15 5:38 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 4:05 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> Expose the high performance PLL as a regular Linux clock
... as clock framework clock ...
> , so the
> PCIe PHY can use it when there is no external refclock provided.
>
> Inspired from counterpart Linux kernel v6.8-rc3 driver:
> drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
> reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
> platform remove callback returning void").
With that fixed:
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC
2024-03-12 7:03 ` [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC Sumit Garg
@ 2024-03-14 4:13 ` Marek Vasut
2024-03-15 5:39 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 4:13 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
> tied to quite old port of pcie_designware driver from Linux which
> suffices only iMX6 specific needs.
>
> But currently we have the common DWC specific bits which alligns pretty
> well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> add support for other iMX8 variants to this driver.
>
> iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> can reuse the generic PHY infrastructure to power on PCIe PHY.
>
> Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
[...]
> +static int pcie_dw_imx_of_to_plat(struct udevice *dev)
> +{
> + struct pcie_dw_imx *priv = dev_get_priv(dev);
> + ofnode gpr;
> + int ret;
> +
> + /* Get the controller base address */
> + priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
> + if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) {
> + dev_err(dev, "failed to get dbi_base address\n");
> + return -EINVAL;
> + }
> +
> + /* Get the config space base address and size */
> + priv->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config",
> + &priv->dw.cfg_size);
> + if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE) {
> + dev_err(dev, "failed to get cfg_base address\n");
> + return -EINVAL;
> + }
> +
> + ret = clk_get_bulk(dev, &priv->clks);
> + if (ret) {
> + dev_err(dev, "failed to get PCIe clks\n");
> + return ret;
> + }
> +
> + ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
> + if (ret) {
> + dev_err(dev,
> + "Failed to get PCIe apps reset control\n");
> + goto err_reset;
> + }
> +
> + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
> + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
The extra parenthesis () is not needed.
With that fixed:
Reviewed-by: Marek Vasut <marex@denx.de>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-12 7:03 ` [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY Sumit Garg
@ 2024-03-14 4:15 ` Marek Vasut
2024-03-15 5:37 ` Sumit Garg
2024-03-21 12:40 ` Sumit Garg
0 siblings, 2 replies; 42+ messages in thread
From: Marek Vasut @ 2024-03-14 4:15 UTC (permalink / raw)
To: Sumit Garg, u-boot
Cc: trini, tharvey, marcel.ziswiler, francesco, lukma, seanga2,
jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan, aford173,
ilias.apalodimas, sahaj.sarup, fathi.boudra, remi.duraffort,
daniel.thompson
On 3/12/24 8:03 AM, Sumit Garg wrote:
> Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> PHY initialization moved to this standalone PHY driver.
>
> Inspired from counterpart Linux kernel v6.8-rc3 driver:
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
> reference commit 7559e7572c03 ("phy: Explicitly include correct DT
> includes").
[...]
> +static int imx8_pcie_phy_probe(struct udevice *dev)
> +{
> + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
> + ofnode gpr;
> + int ret = 0;
> +
> + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
> + imx8_phy->base = dev_read_addr(dev);
> + if (!imx8_phy->base)
> + return -EINVAL;
> +
> + /* get PHY refclk pad mode */
> + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
> +
> + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
> + "fsl,tx-deemph-gen1",
> + 0);
> + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
> + "fsl,tx-deemph-gen2",
> + 0);
> + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
> +
> + /* Grab GPR config register range */
> + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
> + if (ofnode_equal(gpr, ofnode_null())) {
> + dev_err(dev, "unable to find GPR node\n");
> + return -ENODEV;
> + }
> +
> + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
> + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> + dev_err(dev, "unable to find iomuxc registers\n");
> + return PTR_ERR(imx8_phy->iomuxc_gpr);
> + }
syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
With that fixed:
Reviewed-by: Marek Vasut <marex@denx.de>
[...]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-14 3:59 ` Marek Vasut
@ 2024-03-15 5:31 ` Sumit Garg
2024-03-15 9:13 ` Marek Vasut
0 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 5:31 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> > turned off for a single peripheral domain as it would negatively affect
> > other peripheral domains. So lets just skip turning off bus power
> > domain.
>
> What exactly is the issue and how did you trigger it ?
>
> Details please.
I suppose the issue can be triggered via the "=> usb start => usb
stop" sequence where one of the USB controllers is configured in
peripheral mode.
>
> > Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> > ---
> > drivers/power/domain/imx8mp-hsiomix.c | 6 +-----
> > 1 file changed, 1 insertion(+), 5 deletions(-)
> >
> > diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
> > index e2d772c5ec7..448746432a2 100644
> > --- a/drivers/power/domain/imx8mp-hsiomix.c
> > +++ b/drivers/power/domain/imx8mp-hsiomix.c
> > @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> >
> > ret = power_domain_on(domain);
> > if (ret)
> > - goto err_pd;
> > + return ret;
> >
> > ret = clk_enable(&priv->clk_usb);
> > if (ret)
> > @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> >
> > err_clk:
> > power_domain_off(domain);
> > -err_pd:
> > - power_domain_off(&priv->pd_bus);
> > return ret;
>
> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
Sure I can do that but do you think the current approach can have any
side effects?
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller
2024-03-14 3:55 ` Marek Vasut
@ 2024-03-15 5:35 ` Sumit Garg
0 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 5:35 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > Add support for i.MX8MP reset controller, it has same reset IP inside
> > as the other iMX7 and iMX8 variants but with different module layout.
>
> iMX8M , iMX8 is a different SoC .
Ack.
>
> > Inspired from counterpart Linux kernel v6.8-rc3 driver:
> > drivers/reset/reset-imx7.c. Use last Linux kernel driver reference
> > commit bad8a8afe19f ("reset: Explicitly include correct DT includes").
> >
> > Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
> > Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> > ---
> > drivers/reset/reset-imx7.c | 101 +++++++++++++++++++++++++++++++++++++
> > 1 file changed, 101 insertions(+)
> >
> > diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c
> > index 4c7fa19d495..90d3d75255e 100644
> > --- a/drivers/reset/reset-imx7.c
> > +++ b/drivers/reset/reset-imx7.c
> > @@ -10,6 +10,7 @@
> > #include <dm.h>
> > #include <dt-bindings/reset/imx7-reset.h>
> > #include <dt-bindings/reset/imx8mq-reset.h>
> > +#include <dt-bindings/reset/imx8mp-reset.h>
>
> Keep the list sorted (P is before Q).
Ack.
>
> > #include <reset-uclass.h>
> > #include <linux/bitops.h>
> > #include <linux/delay.h>
> > @@ -252,6 +253,102 @@ static int imx8mq_reset_assert(struct reset_ctl *rst)
> > return 0;
> > }
> >
> > +enum imx8mp_src_registers {
> > + SRC_SUPERMIX_RCR = 0x0018,
> > + SRC_AUDIOMIX_RCR = 0x001c,
> > + SRC_MLMIX_RCR = 0x0028,
> > + SRC_GPU2D_RCR = 0x0038,
> > + SRC_GPU3D_RCR = 0x003c,
> > + SRC_VPU_G1_RCR = 0x0048,
> > + SRC_VPU_G2_RCR = 0x004c,
> > + SRC_VPUVC8KE_RCR = 0x0050,
> > + SRC_NOC_RCR = 0x0054,
> > +};
> > +
> > +static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
> > + [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
> > + [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
> > + [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
> > + [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
> > + [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
> > + [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
> > + [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
> > + [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
> > + [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
> > + [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
> > + [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
> > + [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
> > + [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
> > + [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
> > + [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
> > + [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
> > + [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
> > + [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
> > + [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) },
> > + [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
> > + [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
> > + [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) },
> > + [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) },
> > + [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) },
> > + [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) },
> > + [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
> > + [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
> > + [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
> > + [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
> > + [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) },
> > + [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) },
> > + [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) },
> > + [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
> > + [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
> > + [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) },
> > + [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) },
> > + [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) },
> > + [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) },
> > +};
> > +
> > +static int imx8mp_reset_set(struct reset_ctl *rst, bool assert)
> > +{
> > + struct imx7_reset_priv *priv = dev_get_priv(rst->dev);
>
> It wouldn't hurt to rename imx7_reset_priv to imx_reset_priv in 2/11 too.
>
Ack.
> With the include sorting fixed:
>
> Reviewed-by: Marek Vasut <marex@denx.de>
Thanks.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names
2024-03-14 3:52 ` Marek Vasut
@ 2024-03-15 5:36 ` Sumit Garg
0 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 5:36 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > imx7_reset_{deassert/assert}_imx* are a bit more confusing when compared
> > with imx*_reset_{deassert/assert}. So refactor driver to use function
> > names easier to understand. This shouldn't affect the functionality
> > though.
> >
> > Suggested-by: Marek Vasut <marex@denx.de>
> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> > ---
> > drivers/reset/reset-imx7.c | 24 ++++++++++++------------
>
> You could even rename the driver itself now, but that would be separate
> patch.
That can be done as a followup patch.
>
> > 1 file changed, 12 insertions(+), 12 deletions(-)
> Reviewed-by: Marek Vasut <marex@denx.de>
Thanks.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-14 4:15 ` Marek Vasut
@ 2024-03-15 5:37 ` Sumit Garg
2024-03-21 12:40 ` Sumit Garg
1 sibling, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 5:37 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:46, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> > PHY initialization moved to this standalone PHY driver.
> >
> > Inspired from counterpart Linux kernel v6.8-rc3 driver:
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
> > reference commit 7559e7572c03 ("phy: Explicitly include correct DT
> > includes").
>
> [...]
>
> > +static int imx8_pcie_phy_probe(struct udevice *dev)
> > +{
> > + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
> > + ofnode gpr;
> > + int ret = 0;
> > +
> > + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
> > + imx8_phy->base = dev_read_addr(dev);
> > + if (!imx8_phy->base)
> > + return -EINVAL;
> > +
> > + /* get PHY refclk pad mode */
> > + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
> > +
> > + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
> > + "fsl,tx-deemph-gen1",
> > + 0);
> > + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
> > + "fsl,tx-deemph-gen2",
> > + 0);
> > + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
> > +
> > + /* Grab GPR config register range */
> > + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
> > + if (ofnode_equal(gpr, ofnode_null())) {
> > + dev_err(dev, "unable to find GPR node\n");
> > + return -ENODEV;
> > + }
> > +
> > + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
> > + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > + dev_err(dev, "unable to find iomuxc registers\n");
> > + return PTR_ERR(imx8_phy->iomuxc_gpr);
> > + }
>
> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
>
Ack.
> With that fixed:
>
> Reviewed-by: Marek Vasut <marex@denx.de>
>
Thanks.
-Sumit
> [...]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock
2024-03-14 4:05 ` Marek Vasut
@ 2024-03-15 5:38 ` Sumit Garg
0 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 5:38 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > Expose the high performance PLL as a regular Linux clock
>
> ... as clock framework clock ...
>
Ack.
> > , so the
> > PCIe PHY can use it when there is no external refclock provided.
> >
> > Inspired from counterpart Linux kernel v6.8-rc3 driver:
> > drivers/pmdomain/imx/imx8mp-blk-ctrl.c. Use last Linux kernel driver
> > reference commit 7476ddfd36ac ("pmdomain: imx8mp-blk-ctrl: Convert to
> > platform remove callback returning void").
>
> With that fixed:
>
> Reviewed-by: Marek Vasut <marex@denx.de>
Thanks.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC
2024-03-14 4:13 ` Marek Vasut
@ 2024-03-15 5:39 ` Sumit Garg
0 siblings, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 5:39 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > pcie_imx doesn't seem to share any useful code for iMX8 SoC and it is
> > tied to quite old port of pcie_designware driver from Linux which
> > suffices only iMX6 specific needs.
> >
> > But currently we have the common DWC specific bits which alligns pretty
> > well with DW PCIe controller on iMX8MP SoC. So lets reuse those common
> > bits instead as a new driver for iMX8 SoCs. It should be fairly easy to
> > add support for other iMX8 variants to this driver.
> >
> > iMX8MP SoC also comes up with standalone PCIe PHY support, so hence we
> > can reuse the generic PHY infrastructure to power on PCIe PHY.
> >
> > Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
> > Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
>
> [...]
>
> > +static int pcie_dw_imx_of_to_plat(struct udevice *dev)
> > +{
> > + struct pcie_dw_imx *priv = dev_get_priv(dev);
> > + ofnode gpr;
> > + int ret;
> > +
> > + /* Get the controller base address */
> > + priv->dw.dbi_base = (void *)dev_read_addr_name(dev, "dbi");
> > + if ((fdt_addr_t)priv->dw.dbi_base == FDT_ADDR_T_NONE) {
> > + dev_err(dev, "failed to get dbi_base address\n");
> > + return -EINVAL;
> > + }
> > +
> > + /* Get the config space base address and size */
> > + priv->dw.cfg_base = (void *)dev_read_addr_size_name(dev, "config",
> > + &priv->dw.cfg_size);
> > + if ((fdt_addr_t)priv->dw.cfg_base == FDT_ADDR_T_NONE) {
> > + dev_err(dev, "failed to get cfg_base address\n");
> > + return -EINVAL;
> > + }
> > +
> > + ret = clk_get_bulk(dev, &priv->clks);
> > + if (ret) {
> > + dev_err(dev, "failed to get PCIe clks\n");
> > + return ret;
> > + }
> > +
> > + ret = reset_get_by_name(dev, "apps", &priv->apps_reset);
> > + if (ret) {
> > + dev_err(dev,
> > + "Failed to get PCIe apps reset control\n");
> > + goto err_reset;
> > + }
> > +
> > + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
> > + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
>
> The extra parenthesis () is not needed.
>
Ack.
> With that fixed:
>
> Reviewed-by: Marek Vasut <marex@denx.de>
Thanks.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-15 5:31 ` Sumit Garg
@ 2024-03-15 9:13 ` Marek Vasut
2024-03-15 10:41 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-15 9:13 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On 3/15/24 6:31 AM, Sumit Garg wrote:
> On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>>
>> On 3/12/24 8:03 AM, Sumit Garg wrote:
>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
>>> turned off for a single peripheral domain as it would negatively affect
>>> other peripheral domains. So lets just skip turning off bus power
>>> domain.
>>
>> What exactly is the issue and how did you trigger it ?
>>
>> Details please.
>
> I suppose the issue can be triggered via the "=> usb start => usb
> stop" sequence where one of the USB controllers is configured in
> peripheral mode.
'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
is more extensive ?
Please, write down the necessary steps to reproduce this problem, and
what happens when that problem occurs.
>>> Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
>>> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
>>> ---
>>> drivers/power/domain/imx8mp-hsiomix.c | 6 +-----
>>> 1 file changed, 1 insertion(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
>>> index e2d772c5ec7..448746432a2 100644
>>> --- a/drivers/power/domain/imx8mp-hsiomix.c
>>> +++ b/drivers/power/domain/imx8mp-hsiomix.c
>>> @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
>>>
>>> ret = power_domain_on(domain);
>>> if (ret)
>>> - goto err_pd;
>>> + return ret;
>>>
>>> ret = clk_enable(&priv->clk_usb);
>>> if (ret)
>>> @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
>>>
>>> err_clk:
>>> power_domain_off(domain);
>>> -err_pd:
>>> - power_domain_off(&priv->pd_bus);
>>> return ret;
>>
>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
>
> Sure I can do that but do you think the current approach can have any
> side effects?
Bus domain not getting cycled (which can leave it in some odd state),
and increased power consumption if the next stage doesn't turn the
domain off.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-15 9:13 ` Marek Vasut
@ 2024-03-15 10:41 ` Sumit Garg
2024-03-20 7:16 ` Sumit Garg
2024-03-21 3:52 ` Marek Vasut
0 siblings, 2 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-15 10:41 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Fri, 15 Mar 2024 at 14:53, Marek Vasut <marex@denx.de> wrote:
>
> On 3/15/24 6:31 AM, Sumit Garg wrote:
> > On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> >>> turned off for a single peripheral domain as it would negatively affect
> >>> other peripheral domains. So lets just skip turning off bus power
> >>> domain.
> >>
> >> What exactly is the issue and how did you trigger it ?
> >>
> >> Details please.
> >
> > I suppose the issue can be triggered via the "=> usb start => usb
> > stop" sequence where one of the USB controllers is configured in
> > peripheral mode.
>
> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> is more extensive ?
>
> Please, write down the necessary steps to reproduce this problem, and
> what happens when that problem occurs.
After digging in more, it looks like dev_power_domain_off() is never
(U-Boot life-cycle) invoked for USB controller devices derived from
DT. So this USB power domain sequence is never reachable.
BTW, dev_power_domain_on() is invoked when USB controller devices are
added based on DT.
>
> >>> Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
> >>> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> >>> ---
> >>> drivers/power/domain/imx8mp-hsiomix.c | 6 +-----
> >>> 1 file changed, 1 insertion(+), 5 deletions(-)
> >>>
> >>> diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
> >>> index e2d772c5ec7..448746432a2 100644
> >>> --- a/drivers/power/domain/imx8mp-hsiomix.c
> >>> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> >>> @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> >>>
> >>> ret = power_domain_on(domain);
> >>> if (ret)
> >>> - goto err_pd;
> >>> + return ret;
> >>>
> >>> ret = clk_enable(&priv->clk_usb);
> >>> if (ret)
> >>> @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> >>>
> >>> err_clk:
> >>> power_domain_off(domain);
> >>> -err_pd:
> >>> - power_domain_off(&priv->pd_bus);
> >>> return ret;
> >>
> >> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> >
> > Sure I can do that but do you think the current approach can have any
> > side effects?
>
> Bus domain not getting cycled (which can leave it in some odd state),
> and increased power consumption if the next stage doesn't turn the
> domain off.
Given above, would you like me to drop power domain off path entirely
here? I think if people are concerned about power consumption then it
should be implemented properly in U-Boot to remove all the DT based
devices before passing on control to the next stage.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-15 10:41 ` Sumit Garg
@ 2024-03-20 7:16 ` Sumit Garg
2024-03-21 3:52 ` Marek Vasut
1 sibling, 0 replies; 42+ messages in thread
From: Sumit Garg @ 2024-03-20 7:16 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
Gentle ping..
On Fri, 15 Mar 2024 at 16:11, Sumit Garg <sumit.garg@linaro.org> wrote:
>
> On Fri, 15 Mar 2024 at 14:53, Marek Vasut <marex@denx.de> wrote:
> >
> > On 3/15/24 6:31 AM, Sumit Garg wrote:
> > > On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
> > >>
> > >> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > >>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> > >>> turned off for a single peripheral domain as it would negatively affect
> > >>> other peripheral domains. So lets just skip turning off bus power
> > >>> domain.
> > >>
> > >> What exactly is the issue and how did you trigger it ?
> > >>
> > >> Details please.
> > >
> > > I suppose the issue can be triggered via the "=> usb start => usb
> > > stop" sequence where one of the USB controllers is configured in
> > > peripheral mode.
> >
> > 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> > is more extensive ?
> >
> > Please, write down the necessary steps to reproduce this problem, and
> > what happens when that problem occurs.
>
> After digging in more, it looks like dev_power_domain_off() is never
> (U-Boot life-cycle) invoked for USB controller devices derived from
> DT. So this USB power domain sequence is never reachable.
>
> BTW, dev_power_domain_on() is invoked when USB controller devices are
> added based on DT.
>
> >
> > >>> Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
> > >>> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> > >>> ---
> > >>> drivers/power/domain/imx8mp-hsiomix.c | 6 +-----
> > >>> 1 file changed, 1 insertion(+), 5 deletions(-)
> > >>>
> > >>> diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c
> > >>> index e2d772c5ec7..448746432a2 100644
> > >>> --- a/drivers/power/domain/imx8mp-hsiomix.c
> > >>> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> > >>> @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> > >>>
> > >>> ret = power_domain_on(domain);
> > >>> if (ret)
> > >>> - goto err_pd;
> > >>> + return ret;
> > >>>
> > >>> ret = clk_enable(&priv->clk_usb);
> > >>> if (ret)
> > >>> @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain *power_domain)
> > >>>
> > >>> err_clk:
> > >>> power_domain_off(domain);
> > >>> -err_pd:
> > >>> - power_domain_off(&priv->pd_bus);
> > >>> return ret;
> > >>
> > >> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> > >
> > > Sure I can do that but do you think the current approach can have any
> > > side effects?
> >
> > Bus domain not getting cycled (which can leave it in some odd state),
> > and increased power consumption if the next stage doesn't turn the
> > domain off.
>
> Given above, would you like me to drop power domain off path entirely
> here? I think if people are concerned about power consumption then it
> should be implemented properly in U-Boot to remove all the DT based
> devices before passing on control to the next stage.
How would you like me to proceed here?
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-15 10:41 ` Sumit Garg
2024-03-20 7:16 ` Sumit Garg
@ 2024-03-21 3:52 ` Marek Vasut
2024-03-21 5:46 ` Sumit Garg
1 sibling, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-21 3:52 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On 3/15/24 11:41 AM, Sumit Garg wrote:
> On Fri, 15 Mar 2024 at 14:53, Marek Vasut <marex@denx.de> wrote:
>>
>> On 3/15/24 6:31 AM, Sumit Garg wrote:
>>> On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 3/12/24 8:03 AM, Sumit Garg wrote:
>>>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
>>>>> turned off for a single peripheral domain as it would negatively affect
>>>>> other peripheral domains. So lets just skip turning off bus power
>>>>> domain.
>>>>
>>>> What exactly is the issue and how did you trigger it ?
>>>>
>>>> Details please.
>>>
>>> I suppose the issue can be triggered via the "=> usb start => usb
>>> stop" sequence where one of the USB controllers is configured in
>>> peripheral mode.
>>
>> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
>> is more extensive ?
>>
>> Please, write down the necessary steps to reproduce this problem, and
>> what happens when that problem occurs.
>
> After digging in more, it looks like dev_power_domain_off() is never
> (U-Boot life-cycle) invoked for USB controller devices derived from
> DT. So this USB power domain sequence is never reachable.
The imx8mp_hsiomix_off() is never called on 'usb stop' command ?
But then why would the 'usb start ; usb stop' test break power domain
state here ?
> BTW, dev_power_domain_on() is invoked when USB controller devices are
> added based on DT.
I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
just before Linux boots .
[...]
>>>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
>>>
>>> Sure I can do that but do you think the current approach can have any
>>> side effects?
>>
>> Bus domain not getting cycled (which can leave it in some odd state),
>> and increased power consumption if the next stage doesn't turn the
>> domain off.
>
> Given above, would you like me to drop power domain off path entirely
> here?
Can the series go in without this patch ?
> I think if people are concerned about power consumption then it
> should be implemented properly in U-Boot to remove all the DT based
> devices before passing on control to the next stage.
I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
just before Linux boots (esp. at that point), so if you do not power off
the bus domain before booting Linux, you may hand over a device which
was not fully power cycled.
And sorry for the delay, I was a bit busy.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-21 3:52 ` Marek Vasut
@ 2024-03-21 5:46 ` Sumit Garg
2024-03-21 16:30 ` Marek Vasut
0 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-21 5:46 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 21 Mar 2024 at 11:06, Marek Vasut <marex@denx.de> wrote:
>
> On 3/15/24 11:41 AM, Sumit Garg wrote:
> > On Fri, 15 Mar 2024 at 14:53, Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 3/15/24 6:31 AM, Sumit Garg wrote:
> >>> On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
> >>>>
> >>>> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> >>>>> turned off for a single peripheral domain as it would negatively affect
> >>>>> other peripheral domains. So lets just skip turning off bus power
> >>>>> domain.
> >>>>
> >>>> What exactly is the issue and how did you trigger it ?
> >>>>
> >>>> Details please.
> >>>
> >>> I suppose the issue can be triggered via the "=> usb start => usb
> >>> stop" sequence where one of the USB controllers is configured in
> >>> peripheral mode.
> >>
> >> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> >> is more extensive ?
> >>
> >> Please, write down the necessary steps to reproduce this problem, and
> >> what happens when that problem occurs.
> >
> > After digging in more, it looks like dev_power_domain_off() is never
> > (U-Boot life-cycle) invoked for USB controller devices derived from
> > DT. So this USB power domain sequence is never reachable.
>
> The imx8mp_hsiomix_off() is never called on 'usb stop' command ?
>
Yeah, that's the case.
> But then why would the 'usb start ; usb stop' test break power domain
> state here ?
It won't break with current implementation, earlier I made this
assumption that 'usb stop' turns down the power domain.
>
> > BTW, dev_power_domain_on() is invoked when USB controller devices are
> > added based on DT.
>
> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
> just before Linux boots .
>
> [...]
>
> >>>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> >>>
> >>> Sure I can do that but do you think the current approach can have any
> >>> side effects?
> >>
> >> Bus domain not getting cycled (which can leave it in some odd state),
> >> and increased power consumption if the next stage doesn't turn the
> >> domain off.
> >
> > Given above, would you like me to drop power domain off path entirely
> > here?
>
> Can the series go in without this patch ?
Okay let me drop this patch.
>
> > I think if people are concerned about power consumption then it
> > should be implemented properly in U-Boot to remove all the DT based
> > devices before passing on control to the next stage.
>
> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
> just before Linux boots (esp. at that point), so if you do not power off
> the bus domain before booting Linux, you may hand over a device which
> was not fully power cycled.
Unfortunately that's the current situation I see. IMO, the better
solution would be to just remove all the DT devices before passing on
control to Linux. That should automatically power off devices.
>
> And sorry for the delay, I was a bit busy.
No worries.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-14 4:15 ` Marek Vasut
2024-03-15 5:37 ` Sumit Garg
@ 2024-03-21 12:40 ` Sumit Garg
2024-03-21 16:27 ` Marek Vasut
1 sibling, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-21 12:40 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Thu, 14 Mar 2024 at 09:46, Marek Vasut <marex@denx.de> wrote:
>
> On 3/12/24 8:03 AM, Sumit Garg wrote:
> > Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> > PHY initialization moved to this standalone PHY driver.
> >
> > Inspired from counterpart Linux kernel v6.8-rc3 driver:
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
> > reference commit 7559e7572c03 ("phy: Explicitly include correct DT
> > includes").
>
> [...]
>
> > +static int imx8_pcie_phy_probe(struct udevice *dev)
> > +{
> > + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
> > + ofnode gpr;
> > + int ret = 0;
> > +
> > + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
> > + imx8_phy->base = dev_read_addr(dev);
> > + if (!imx8_phy->base)
> > + return -EINVAL;
> > +
> > + /* get PHY refclk pad mode */
> > + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
> > +
> > + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
> > + "fsl,tx-deemph-gen1",
> > + 0);
> > + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
> > + "fsl,tx-deemph-gen2",
> > + 0);
> > + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
> > +
> > + /* Grab GPR config register range */
> > + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
> > + if (ofnode_equal(gpr, ofnode_null())) {
> > + dev_err(dev, "unable to find GPR node\n");
> > + return -ENODEV;
> > + }
> > +
> > + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
> > + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > + dev_err(dev, "unable to find iomuxc registers\n");
> > + return PTR_ERR(imx8_phy->iomuxc_gpr);
> > + }
>
> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
>
After a close look, that API isn't supported by U-Boot yet. So I will
keep the existing implementation with your review tag. I hope that's
fine with you.
-Sumit
> With that fixed:
>
> Reviewed-by: Marek Vasut <marex@denx.de>
>
> [...]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-21 12:40 ` Sumit Garg
@ 2024-03-21 16:27 ` Marek Vasut
2024-03-22 4:36 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-21 16:27 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On 3/21/24 1:40 PM, Sumit Garg wrote:
> On Thu, 14 Mar 2024 at 09:46, Marek Vasut <marex@denx.de> wrote:
>>
>> On 3/12/24 8:03 AM, Sumit Garg wrote:
>>> Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
>>> PHY initialization moved to this standalone PHY driver.
>>>
>>> Inspired from counterpart Linux kernel v6.8-rc3 driver:
>>> drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
>>> reference commit 7559e7572c03 ("phy: Explicitly include correct DT
>>> includes").
>>
>> [...]
>>
>>> +static int imx8_pcie_phy_probe(struct udevice *dev)
>>> +{
>>> + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
>>> + ofnode gpr;
>>> + int ret = 0;
>>> +
>>> + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
>>> + imx8_phy->base = dev_read_addr(dev);
>>> + if (!imx8_phy->base)
>>> + return -EINVAL;
>>> +
>>> + /* get PHY refclk pad mode */
>>> + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
>>> +
>>> + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
>>> + "fsl,tx-deemph-gen1",
>>> + 0);
>>> + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
>>> + "fsl,tx-deemph-gen2",
>>> + 0);
>>> + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
>>> +
>>> + /* Grab GPR config register range */
>>> + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
>>> + if (ofnode_equal(gpr, ofnode_null())) {
>>> + dev_err(dev, "unable to find GPR node\n");
>>> + return -ENODEV;
>>> + }
>>> +
>>> + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
>>> + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
>>> + dev_err(dev, "unable to find iomuxc registers\n");
>>> + return PTR_ERR(imx8_phy->iomuxc_gpr);
>>> + }
>>
>> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
>>
>
> After a close look, that API isn't supported by U-Boot yet. So I will
> keep the existing implementation with your review tag. I hope that's
> fine with you.
Oh, uh, I had a local patch from previous round of PCIe experiments, I
just sent it out, you are on CC. Can you do a follow up fix once this
series V4 is in ?
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-21 5:46 ` Sumit Garg
@ 2024-03-21 16:30 ` Marek Vasut
2024-03-22 4:55 ` Sumit Garg
0 siblings, 1 reply; 42+ messages in thread
From: Marek Vasut @ 2024-03-21 16:30 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On 3/21/24 6:46 AM, Sumit Garg wrote:
> On Thu, 21 Mar 2024 at 11:06, Marek Vasut <marex@denx.de> wrote:
>>
>> On 3/15/24 11:41 AM, Sumit Garg wrote:
>>> On Fri, 15 Mar 2024 at 14:53, Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 3/15/24 6:31 AM, Sumit Garg wrote:
>>>>> On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
>>>>>>
>>>>>> On 3/12/24 8:03 AM, Sumit Garg wrote:
>>>>>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
>>>>>>> turned off for a single peripheral domain as it would negatively affect
>>>>>>> other peripheral domains. So lets just skip turning off bus power
>>>>>>> domain.
>>>>>>
>>>>>> What exactly is the issue and how did you trigger it ?
>>>>>>
>>>>>> Details please.
>>>>>
>>>>> I suppose the issue can be triggered via the "=> usb start => usb
>>>>> stop" sequence where one of the USB controllers is configured in
>>>>> peripheral mode.
>>>>
>>>> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
>>>> is more extensive ?
>>>>
>>>> Please, write down the necessary steps to reproduce this problem, and
>>>> what happens when that problem occurs.
>>>
>>> After digging in more, it looks like dev_power_domain_off() is never
>>> (U-Boot life-cycle) invoked for USB controller devices derived from
>>> DT. So this USB power domain sequence is never reachable.
>>
>> The imx8mp_hsiomix_off() is never called on 'usb stop' command ?
>>
>
> Yeah, that's the case.
>
>> But then why would the 'usb start ; usb stop' test break power domain
>> state here ?
>
> It won't break with current implementation, earlier I made this
> assumption that 'usb stop' turns down the power domain.
So, maybe I am a little confused, what is this patch solving then ?
>>> BTW, dev_power_domain_on() is invoked when USB controller devices are
>>> added based on DT.
>>
>> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
>> just before Linux boots .
>>
>> [...]
>>
>>>>>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
>>>>>
>>>>> Sure I can do that but do you think the current approach can have any
>>>>> side effects?
>>>>
>>>> Bus domain not getting cycled (which can leave it in some odd state),
>>>> and increased power consumption if the next stage doesn't turn the
>>>> domain off.
>>>
>>> Given above, would you like me to drop power domain off path entirely
>>> here?
>>
>> Can the series go in without this patch ?
>
> Okay let me drop this patch.
We can fix whatever it is that needs to be fixed in a smaller follow up
series.
>>> I think if people are concerned about power consumption then it
>>> should be implemented properly in U-Boot to remove all the DT based
>>> devices before passing on control to the next stage.
>>
>> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
>> just before Linux boots (esp. at that point), so if you do not power off
>> the bus domain before booting Linux, you may hand over a device which
>> was not fully power cycled.
>
> Unfortunately that's the current situation I see. IMO, the better
> solution would be to just remove all the DT devices before passing on
> control to Linux. That should automatically power off devices.
Doesn't CONFIG_DM_DEVICE_REMOVE=y do something like that already ?
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-21 16:27 ` Marek Vasut
@ 2024-03-22 4:36 ` Sumit Garg
2024-03-22 16:30 ` Marek Vasut
0 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-22 4:36 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Fri, 22 Mar 2024 at 00:47, Marek Vasut <marex@denx.de> wrote:
>
> On 3/21/24 1:40 PM, Sumit Garg wrote:
> > On Thu, 14 Mar 2024 at 09:46, Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>> Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
> >>> PHY initialization moved to this standalone PHY driver.
> >>>
> >>> Inspired from counterpart Linux kernel v6.8-rc3 driver:
> >>> drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
> >>> reference commit 7559e7572c03 ("phy: Explicitly include correct DT
> >>> includes").
> >>
> >> [...]
> >>
> >>> +static int imx8_pcie_phy_probe(struct udevice *dev)
> >>> +{
> >>> + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
> >>> + ofnode gpr;
> >>> + int ret = 0;
> >>> +
> >>> + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
> >>> + imx8_phy->base = dev_read_addr(dev);
> >>> + if (!imx8_phy->base)
> >>> + return -EINVAL;
> >>> +
> >>> + /* get PHY refclk pad mode */
> >>> + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
> >>> +
> >>> + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
> >>> + "fsl,tx-deemph-gen1",
> >>> + 0);
> >>> + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
> >>> + "fsl,tx-deemph-gen2",
> >>> + 0);
> >>> + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
> >>> +
> >>> + /* Grab GPR config register range */
> >>> + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
> >>> + if (ofnode_equal(gpr, ofnode_null())) {
> >>> + dev_err(dev, "unable to find GPR node\n");
> >>> + return -ENODEV;
> >>> + }
> >>> +
> >>> + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
> >>> + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> >>> + dev_err(dev, "unable to find iomuxc registers\n");
> >>> + return PTR_ERR(imx8_phy->iomuxc_gpr);
> >>> + }
> >>
> >> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
> >>
> >
> > After a close look, that API isn't supported by U-Boot yet. So I will
> > keep the existing implementation with your review tag. I hope that's
> > fine with you.
>
> Oh, uh, I had a local patch from previous round of PCIe experiments, I
> just sent it out, you are on CC. Can you do a follow up fix once this
> series V4 is in ?
Sure I can do that as a followup once your patch is merged.
-Sumit
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-21 16:30 ` Marek Vasut
@ 2024-03-22 4:55 ` Sumit Garg
2024-03-22 16:39 ` Marek Vasut
0 siblings, 1 reply; 42+ messages in thread
From: Sumit Garg @ 2024-03-22 4:55 UTC (permalink / raw)
To: Marek Vasut
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On Fri, 22 Mar 2024 at 00:47, Marek Vasut <marex@denx.de> wrote:
>
> On 3/21/24 6:46 AM, Sumit Garg wrote:
> > On Thu, 21 Mar 2024 at 11:06, Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 3/15/24 11:41 AM, Sumit Garg wrote:
> >>> On Fri, 15 Mar 2024 at 14:53, Marek Vasut <marex@denx.de> wrote:
> >>>>
> >>>> On 3/15/24 6:31 AM, Sumit Garg wrote:
> >>>>> On Thu, 14 Mar 2024 at 09:45, Marek Vasut <marex@denx.de> wrote:
> >>>>>>
> >>>>>> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>>>>>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> >>>>>>> turned off for a single peripheral domain as it would negatively affect
> >>>>>>> other peripheral domains. So lets just skip turning off bus power
> >>>>>>> domain.
> >>>>>>
> >>>>>> What exactly is the issue and how did you trigger it ?
> >>>>>>
> >>>>>> Details please.
> >>>>>
> >>>>> I suppose the issue can be triggered via the "=> usb start => usb
> >>>>> stop" sequence where one of the USB controllers is configured in
> >>>>> peripheral mode.
> >>>>
> >>>> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> >>>> is more extensive ?
> >>>>
> >>>> Please, write down the necessary steps to reproduce this problem, and
> >>>> what happens when that problem occurs.
> >>>
> >>> After digging in more, it looks like dev_power_domain_off() is never
> >>> (U-Boot life-cycle) invoked for USB controller devices derived from
> >>> DT. So this USB power domain sequence is never reachable.
> >>
> >> The imx8mp_hsiomix_off() is never called on 'usb stop' command ?
> >>
> >
> > Yeah, that's the case.
> >
> >> But then why would the 'usb start ; usb stop' test break power domain
> >> state here ?
> >
> > It won't break with current implementation, earlier I made this
> > assumption that 'usb stop' turns down the power domain.
>
> So, maybe I am a little confused, what is this patch solving then ?
>
It isn't actually solving anything since there isn't a need for
refcount for PD bus since power domain off isn't exercised during the
lifecycle of U-Boot. Hence, I dropped it.
> >>> BTW, dev_power_domain_on() is invoked when USB controller devices are
> >>> added based on DT.
> >>
> >> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
> >> just before Linux boots .
> >>
> >> [...]
> >>
> >>>>>> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> >>>>>
> >>>>> Sure I can do that but do you think the current approach can have any
> >>>>> side effects?
> >>>>
> >>>> Bus domain not getting cycled (which can leave it in some odd state),
> >>>> and increased power consumption if the next stage doesn't turn the
> >>>> domain off.
> >>>
> >>> Given above, would you like me to drop power domain off path entirely
> >>> here?
> >>
> >> Can the series go in without this patch ?
> >
> > Okay let me drop this patch.
>
> We can fix whatever it is that needs to be fixed in a smaller follow up
> series.
Sure, see below.
>
> >>> I think if people are concerned about power consumption then it
> >>> should be implemented properly in U-Boot to remove all the DT based
> >>> devices before passing on control to the next stage.
> >>
> >> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
> >> just before Linux boots (esp. at that point), so if you do not power off
> >> the bus domain before booting Linux, you may hand over a device which
> >> was not fully power cycled.
> >
> > Unfortunately that's the current situation I see. IMO, the better
> > solution would be to just remove all the DT devices before passing on
> > control to Linux. That should automatically power off devices.
>
> Doesn't CONFIG_DM_DEVICE_REMOVE=y do something like that already ?
I just did simple experiment via following diff:
diff --git a/drivers/power/domain/imx8mp-hsiomix.c
b/drivers/power/domain/imx8mp-hsiomix.c
index 6188a04c45e..0ddcd39923a 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -101,6 +101,7 @@ static int imx8mp_hsiomix_set(struct power_domain
*power_domain, bool power_on)
if (gpr_reg0_bits)
setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
} else {
+ while(1);
if (gpr_reg0_bits)
clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
The boot doesn't hang suggesting that CONFIG_DM_DEVICE_REMOVE=y isn't
effective to remove any DT devices. It can for sure be another
followup series to make it effective.
-Sumit
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY
2024-03-22 4:36 ` Sumit Garg
@ 2024-03-22 16:30 ` Marek Vasut
0 siblings, 0 replies; 42+ messages in thread
From: Marek Vasut @ 2024-03-22 16:30 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On 3/22/24 5:36 AM, Sumit Garg wrote:
> On Fri, 22 Mar 2024 at 00:47, Marek Vasut <marex@denx.de> wrote:
>>
>> On 3/21/24 1:40 PM, Sumit Garg wrote:
>>> On Thu, 14 Mar 2024 at 09:46, Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 3/12/24 8:03 AM, Sumit Garg wrote:
>>>>> Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
>>>>> PHY initialization moved to this standalone PHY driver.
>>>>>
>>>>> Inspired from counterpart Linux kernel v6.8-rc3 driver:
>>>>> drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
>>>>> reference commit 7559e7572c03 ("phy: Explicitly include correct DT
>>>>> includes").
>>>>
>>>> [...]
>>>>
>>>>> +static int imx8_pcie_phy_probe(struct udevice *dev)
>>>>> +{
>>>>> + struct imx8_pcie_phy *imx8_phy = dev_get_priv(dev);
>>>>> + ofnode gpr;
>>>>> + int ret = 0;
>>>>> +
>>>>> + imx8_phy->drvdata = (void *)dev_get_driver_data(dev);
>>>>> + imx8_phy->base = dev_read_addr(dev);
>>>>> + if (!imx8_phy->base)
>>>>> + return -EINVAL;
>>>>> +
>>>>> + /* get PHY refclk pad mode */
>>>>> + dev_read_u32(dev, "fsl,refclk-pad-mode", &imx8_phy->refclk_pad_mode);
>>>>> +
>>>>> + imx8_phy->tx_deemph_gen1 = dev_read_u32_default(dev,
>>>>> + "fsl,tx-deemph-gen1",
>>>>> + 0);
>>>>> + imx8_phy->tx_deemph_gen2 = dev_read_u32_default(dev,
>>>>> + "fsl,tx-deemph-gen2",
>>>>> + 0);
>>>>> + imx8_phy->clkreq_unused = dev_read_bool(dev, "fsl,clkreq-unsupported");
>>>>> +
>>>>> + /* Grab GPR config register range */
>>>>> + gpr = ofnode_by_compatible(ofnode_null(), imx8_phy->drvdata->gpr);
>>>>> + if (ofnode_equal(gpr, ofnode_null())) {
>>>>> + dev_err(dev, "unable to find GPR node\n");
>>>>> + return -ENODEV;
>>>>> + }
>>>>> +
>>>>> + imx8_phy->iomuxc_gpr = syscon_node_to_regmap(gpr);
>>>>> + if (IS_ERR(imx8_phy->iomuxc_gpr)) {
>>>>> + dev_err(dev, "unable to find iomuxc registers\n");
>>>>> + return PTR_ERR(imx8_phy->iomuxc_gpr);
>>>>> + }
>>>>
>>>> syscon_regmap_lookup_by_compatible() should simplify these two steps ^ .
>>>>
>>>
>>> After a close look, that API isn't supported by U-Boot yet. So I will
>>> keep the existing implementation with your review tag. I hope that's
>>> fine with you.
>>
>> Oh, uh, I had a local patch from previous round of PCIe experiments, I
>> just sent it out, you are on CC. Can you do a follow up fix once this
>> series V4 is in ?
>
> Sure I can do that as a followup once your patch is merged.
Follow up, yes please. Let's not stuff this series with more stuff
anymore, so it can go in.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus
2024-03-22 4:55 ` Sumit Garg
@ 2024-03-22 16:39 ` Marek Vasut
0 siblings, 0 replies; 42+ messages in thread
From: Marek Vasut @ 2024-03-22 16:39 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, trini, tharvey, marcel.ziswiler, francesco, lukma,
seanga2, jh80.chung, sjg, festevam, andrejs.cainikovs, peng.fan,
aford173, ilias.apalodimas, sahaj.sarup, fathi.boudra,
remi.duraffort, daniel.thompson
On 3/22/24 5:55 AM, Sumit Garg wrote:
Hi,
>>>>> I think if people are concerned about power consumption then it
>>>>> should be implemented properly in U-Boot to remove all the DT based
>>>>> devices before passing on control to the next stage.
>>>>
>>>> I would expect imx8mp_hsiomix_off() to be called either on 'usb stop' or
>>>> just before Linux boots (esp. at that point), so if you do not power off
>>>> the bus domain before booting Linux, you may hand over a device which
>>>> was not fully power cycled.
>>>
>>> Unfortunately that's the current situation I see. IMO, the better
>>> solution would be to just remove all the DT devices before passing on
>>> control to Linux. That should automatically power off devices.
>>
>> Doesn't CONFIG_DM_DEVICE_REMOVE=y do something like that already ?
>
> I just did simple experiment via following diff:
>
> diff --git a/drivers/power/domain/imx8mp-hsiomix.c
> b/drivers/power/domain/imx8mp-hsiomix.c
> index 6188a04c45e..0ddcd39923a 100644
> --- a/drivers/power/domain/imx8mp-hsiomix.c
> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> @@ -101,6 +101,7 @@ static int imx8mp_hsiomix_set(struct power_domain
> *power_domain, bool power_on)
> if (gpr_reg0_bits)
> setbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
> } else {
> + while(1);
> if (gpr_reg0_bits)
> clrbits_le32(priv->base + GPR_REG0, gpr_reg0_bits);
>
> The boot doesn't hang suggesting that CONFIG_DM_DEVICE_REMOVE=y isn't
> effective to remove any DT devices. It can for sure be another
> followup series to make it effective.
That's odd. Please try and edit drivers/core/device-remove.c , look up
device_remove() at the end , and see if the remove is being called on
the hsiomix device . You might need to add some sort of printf() there,
but that's where the removal happens.
The removal before boot is I think called from drivers/core/root.c
dm_remove_devices_flags(), which itself is called from
arch/arm/lib/bootm.c announce_and_cleanup() .
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2024-03-22 16:39 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-12 7:03 [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Sumit Garg
2024-03-12 7:03 ` [PATCH v3 01/11] clk: imx8mp: Add support for PCIe clocks Sumit Garg
2024-03-14 3:51 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 02/11] reset: imx: Refactor driver to simplify function names Sumit Garg
2024-03-14 3:52 ` Marek Vasut
2024-03-15 5:36 ` Sumit Garg
2024-03-12 7:03 ` [PATCH v3 03/11] reset: imx: Add support for i.MX8MP reset controller Sumit Garg
2024-03-14 3:55 ` Marek Vasut
2024-03-15 5:35 ` Sumit Garg
2024-03-12 7:03 ` [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus Sumit Garg
2024-03-14 3:59 ` Marek Vasut
2024-03-15 5:31 ` Sumit Garg
2024-03-15 9:13 ` Marek Vasut
2024-03-15 10:41 ` Sumit Garg
2024-03-20 7:16 ` Sumit Garg
2024-03-21 3:52 ` Marek Vasut
2024-03-21 5:46 ` Sumit Garg
2024-03-21 16:30 ` Marek Vasut
2024-03-22 4:55 ` Sumit Garg
2024-03-22 16:39 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 05/11] imx8mp: power-domain: Add PCIe support Sumit Garg
2024-03-14 4:03 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 06/11] imx8mp: power-domain: Expose high performance PLL clock Sumit Garg
2024-03-14 4:05 ` Marek Vasut
2024-03-15 5:38 ` Sumit Garg
2024-03-12 7:03 ` [PATCH v3 07/11] phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY Sumit Garg
2024-03-14 4:15 ` Marek Vasut
2024-03-15 5:37 ` Sumit Garg
2024-03-21 12:40 ` Sumit Garg
2024-03-21 16:27 ` Marek Vasut
2024-03-22 4:36 ` Sumit Garg
2024-03-22 16:30 ` Marek Vasut
2024-03-12 7:03 ` [PATCH v3 08/11] pci: Add DW PCIe controller support for iMX8MP SoC Sumit Garg
2024-03-14 4:13 ` Marek Vasut
2024-03-15 5:39 ` Sumit Garg
2024-03-12 7:03 ` [PATCH v3 09/11] verdin-imx8mp_defconfig: Enable PCIe/NVMe support Sumit Garg
2024-03-12 7:03 ` [PATCH v3 10/11] imx8mp_venice_defconfig: " Sumit Garg
2024-03-12 7:03 ` [PATCH v3 11/11] MAINTAINERS: Add entry for PCIe DWC IMX driver Sumit Garg
2024-03-12 9:43 ` [PATCH v3 00/11] imx8mp: Enable PCIe/NVMe support Peter Robinson
2024-03-12 9:55 ` Sumit Garg
2024-03-12 10:00 ` Peter Robinson
2024-03-13 6:45 ` Sumit Garg
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