Re: [RFCv1 0/8] Meson-8b and Meson-gxbb USB phy code re-structure

[Martin Blumenstingl <martin.blumenstingl@googlemail.com>]

Hi Anand,

On Fri, Jun 18, 2021 at 3:20 PM Anand Moon <linux.amoon@gmail.com> wrote:
[...]
> (some email id got messed up while sending these changes.)
it happened to me before: don't worry, it's something that can be fixed

[...]
> > > Initially if we connect USB HDD at initial boot it get detected.
> > > but after that usb hotplug of USB HDD is broken.
> > > I did not observe and USB debug events messages to trace the root cause.
> > >
> > > Another issue I observed is increase of USB interrupts event
> > > even if there is not much activity on USB ports.
> > > I tried some clk changes but it did not workout for me.
> > I suggest reporting this to the dwc2 maintainers and asking for advice
> > on how to debug these issues.
> >
> Yes I have enabled the CONFIG_USB_DWC2_DEBUG
> to help debug this issue but could not find much clue on
> why this is happening.
I think CONFIG_USB_DWC2_DEBUG is a good starting point.
For myself I came to the conclusion that the dwc2 IP is too complex to
understand without additional information
Some additional information can be found in public datasheets of other
SoCs which are also using a dwc2 core, see for example RK3128 [0] or
RT3050 [1]
That's why my suggestion is to additionally ask the dwc2 maintainers
(which are not Cc'ed on this mail) for debugging suggestions.


Best regards,
Martin


[0] https://rockchip.fr/RK312X%20TRM/chapter-26-usb-otg-2-0.pdf
[1] http://static6.arrow.com/aropdfconversion/aa9a14376a75e7c5d6daa9f6aaed8411909d2021/rt3050_5x_v2.0_081408_0902.pdf