[PATCH 00/13] MIPS: lantiq: handle RCU register by separate drivers

[PATCH 00/13] MIPS: lantiq: handle RCU register by separate drivers

[Hauke Mehrtens]

The RCU (Reset controller Unit) register block provides many different 
functionalities. Before they were handed by the code in arch/mips/lantiq
/xway/reset.c, now there are separate drivers for the functionality.
This block provides support for reset controller, GPHY firmware 
loading, USB PHY initialization and cross bar configuration. 

These changes are making the old device tree incompatible with the 
current kernel. The upstream Linux kernel supports loading the device 
tree blob from the boot loader since about one year, the latest 
released vendor kernel does not support loading the device tree from a 
bot loader.

I would prefer if this would go through the mips tree.
There are more patches planed which would convert the Lantiq code 
to the common clock framework.

Hauke Mehrtens (4):
  mtd: lantiq-flash: drop check of boot select
  mtd: spi-falcon: drop check of boot select
  watchdog: lantiq: access boot cause register through regmap
  MIPS: lantiq: remove old GPHY loader code

Martin Blumenstingl (9):
  MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses
  MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
  MIPS: lantiq: Convert the xbar driver to a platform_driver
  MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
  reset: Add a reset controller driver for the Lantiq XWAY based SoCs
  MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
  phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
  Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
  MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation

 .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++
 .../devicetree/bindings/mips/lantiq/rcu.txt        |  82 +++++
 .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 ++
 .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
 .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 +++
 MAINTAINERS                                        |   1 +
 arch/mips/include/asm/mach-lantiq/lantiq.h         |   4 -
 arch/mips/lantiq/Kconfig                           |   2 +
 arch/mips/lantiq/falcon/reset.c                    |  22 --
 arch/mips/lantiq/prom.c                            |   3 +-
 arch/mips/lantiq/xway/Makefile                     |   4 +-
 arch/mips/lantiq/xway/reset.c                      | 387 ---------------------
 arch/mips/lantiq/xway/sysctrl.c                    |  69 +---
 arch/mips/lantiq/xway/xrx200_phy_fw.c              | 113 ------
 drivers/mtd/maps/lantiq-flash.c                    |   6 -
 drivers/phy/Kconfig                                |   8 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++
 drivers/reset/Kconfig                              |   6 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-lantiq-rcu.c                   | 231 ++++++++++++
 drivers/soc/Makefile                               |   1 +
 drivers/soc/lantiq/Makefile                        |   2 +
 drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++
 drivers/soc/lantiq/xbar.c                          | 100 ++++++
 drivers/spi/spi-falcon.c                           |   5 -
 drivers/watchdog/lantiq_wdt.c                      |  47 ++-
 include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 +
 28 files changed, 1255 insertions(+), 600 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
 create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
 create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
 delete mode 100644 arch/mips/lantiq/xway/reset.c
 delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
 create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
 create mode 100644 drivers/reset/reset-lantiq-rcu.c
 create mode 100644 drivers/soc/lantiq/Makefile
 create mode 100644 drivers/soc/lantiq/gphy.c
 create mode 100644 drivers/soc/lantiq/xbar.c
 create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h

-- 
2.11.0

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[PATCH 00/13] MIPS: lantiq: handle RCU register by separate drivers

[Hauke Mehrtens]

The RCU (Reset controller Unit) register block provides many different 
functionalities. Before they were handed by the code in arch/mips/lantiq
/xway/reset.c, now there are separate drivers for the functionality.
This block provides support for reset controller, GPHY firmware 
loading, USB PHY initialization and cross bar configuration. 

These changes are making the old device tree incompatible with the 
current kernel. The upstream Linux kernel supports loading the device 
tree blob from the boot loader since about one year, the latest 
released vendor kernel does not support loading the device tree from a 
bot loader.

I would prefer if this would go through the mips tree.
There are more patches planed which would convert the Lantiq code 
to the common clock framework.

Hauke Mehrtens (4):
  mtd: lantiq-flash: drop check of boot select
  mtd: spi-falcon: drop check of boot select
  watchdog: lantiq: access boot cause register through regmap
  MIPS: lantiq: remove old GPHY loader code

Martin Blumenstingl (9):
  MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses
  MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
  MIPS: lantiq: Convert the xbar driver to a platform_driver
  MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
  reset: Add a reset controller driver for the Lantiq XWAY based SoCs
  MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
  phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
  Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
  MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation

 .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++
 .../devicetree/bindings/mips/lantiq/rcu.txt        |  82 +++++
 .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 ++
 .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
 .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 +++
 MAINTAINERS                                        |   1 +
 arch/mips/include/asm/mach-lantiq/lantiq.h         |   4 -
 arch/mips/lantiq/Kconfig                           |   2 +
 arch/mips/lantiq/falcon/reset.c                    |  22 --
 arch/mips/lantiq/prom.c                            |   3 +-
 arch/mips/lantiq/xway/Makefile                     |   4 +-
 arch/mips/lantiq/xway/reset.c                      | 387 ---------------------
 arch/mips/lantiq/xway/sysctrl.c                    |  69 +---
 arch/mips/lantiq/xway/xrx200_phy_fw.c              | 113 ------
 drivers/mtd/maps/lantiq-flash.c                    |   6 -
 drivers/phy/Kconfig                                |   8 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++
 drivers/reset/Kconfig                              |   6 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-lantiq-rcu.c                   | 231 ++++++++++++
 drivers/soc/Makefile                               |   1 +
 drivers/soc/lantiq/Makefile                        |   2 +
 drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++
 drivers/soc/lantiq/xbar.c                          | 100 ++++++
 drivers/spi/spi-falcon.c                           |   5 -
 drivers/watchdog/lantiq_wdt.c                      |  47 ++-
 include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 +
 28 files changed, 1255 insertions(+), 600 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
 create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
 create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
 delete mode 100644 arch/mips/lantiq/xway/reset.c
 delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
 create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
 create mode 100644 drivers/reset/reset-lantiq-rcu.c
 create mode 100644 drivers/soc/lantiq/Makefile
 create mode 100644 drivers/soc/lantiq/gphy.c
 create mode 100644 drivers/soc/lantiq/xbar.c
 create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h

-- 
2.11.0

[PATCH 01/13] MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

This allows populating syscon devices which are using "simple-mfd"
instead of "simple-bus".

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 arch/mips/lantiq/prom.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 96773bed8a8a..72cc12f1b6a5 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -117,7 +117,8 @@ void __init prom_init(void)
 
 int __init plat_of_setup(void)
 {
-	return __dt_register_buses(soc_info.compatible, "simple-bus");
+	return of_platform_populate(NULL, of_default_bus_match_table, NULL,
+				    NULL);
 }
 
 arch_initcall(plat_of_setup);
-- 
2.11.0

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[PATCH 01/13] MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This allows populating syscon devices which are using "simple-mfd"
instead of "simple-bus".

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/lantiq/prom.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 96773bed8a8a..72cc12f1b6a5 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -117,7 +117,8 @@ void __init prom_init(void)
 
 int __init plat_of_setup(void)
 {
-	return __dt_register_buses(soc_info.compatible, "simple-bus");
+	return of_platform_populate(NULL, of_default_bus_match_table, NULL,
+				    NULL);
 }
 
 arch_initcall(plat_of_setup);
-- 
2.11.0

[PATCH 02/13] mtd: lantiq-flash: drop check of boot select

[Hauke Mehrtens]

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 drivers/mtd/maps/lantiq-flash.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 3e33ab66eb24..77b1d8013295 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -114,12 +114,6 @@ ltq_mtd_probe(struct platform_device *pdev)
 	struct cfi_private *cfi;
 	int err;
 
-	if (of_machine_is_compatible("lantiq,falcon") &&
-			(ltq_boot_select() != BS_FLASH)) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
 	if (!ltq_mtd)
 		return -ENOMEM;
-- 
2.11.0

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[PATCH 02/13] mtd: lantiq-flash: drop check of boot select

[Hauke Mehrtens]

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 drivers/mtd/maps/lantiq-flash.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 3e33ab66eb24..77b1d8013295 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -114,12 +114,6 @@ ltq_mtd_probe(struct platform_device *pdev)
 	struct cfi_private *cfi;
 	int err;
 
-	if (of_machine_is_compatible("lantiq,falcon") &&
-			(ltq_boot_select() != BS_FLASH)) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
 	if (!ltq_mtd)
 		return -ENOMEM;
-- 
2.11.0

[PATCH 03/13] mtd: spi-falcon: drop check of boot select

[Hauke Mehrtens]

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	int ret;
 
-	if (ltq_boot_select() != BS_SPI) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 	if (!master)
 		return -ENOMEM;
-- 
2.11.0

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[PATCH 03/13] mtd: spi-falcon: drop check of boot select

[Hauke Mehrtens]

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	int ret;
 
-	if (ltq_boot_select() != BS_SPI) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 	if (!master)
 		return -ENOMEM;
-- 
2.11.0

[PATCH 04/13] watchdog: lantiq: access boot cause register through regmap

[Hauke Mehrtens]

This patch avoids accessing the function ltq_reset_cause() and directly
accesses the register given over the syscon interface. The syscon
interface will be implemented for the xway SoCs for the falcon SoCs the
ltq_reset_cause() function never worked, because a wrong offset was used.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 drivers/watchdog/lantiq_wdt.c | 47 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index e0823677d8c1..0e349ad03fdf 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -17,9 +17,14 @@
 #include <linux/uaccess.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 
 #include <lantiq_soc.h>
 
+#define LTQ_RST_CAUSE_WDT_XRX		BIT(31)
+#define LTQ_RST_CAUSE_WDT_FALCON	0x02
+
 /*
  * Section 3.4 of the datasheet
  * The password sequence protects the WDT control register from unintended
@@ -186,6 +191,40 @@ static struct miscdevice ltq_wdt_miscdev = {
 	.fops	= &ltq_wdt_fops,
 };
 
+static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct regmap *rcu_regmap;
+	u32 status_reg_offset;
+	u32 val;
+	int err;
+
+	rcu_regmap = syscon_regmap_lookup_by_phandle(np,
+						     "lantiq,rcu-syscon");
+	if (IS_ERR_OR_NULL(rcu_regmap))
+		return;
+
+	err = of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+					 &status_reg_offset);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+		return;
+	}
+
+	err = regmap_read(rcu_regmap, status_reg_offset, &val);
+	if (err)
+		return;
+
+	/* find out if the watchdog caused the last reboot */
+	if (of_device_is_compatible(np, "lantiq,wdt-xrx100")) {
+		if (val & LTQ_RST_CAUSE_WDT_XRX)
+			ltq_wdt_bootstatus = WDIOF_CARDRESET;
+	} else if  (of_device_is_compatible(np, "lantiq,wdt-falcon")) {
+		if ((val & 0x7) == LTQ_RST_CAUSE_WDT_FALCON)
+			ltq_wdt_bootstatus = WDIOF_CARDRESET;
+	}
+}
+
 static int
 ltq_wdt_probe(struct platform_device *pdev)
 {
@@ -205,9 +244,7 @@ ltq_wdt_probe(struct platform_device *pdev)
 	ltq_io_region_clk_rate = clk_get_rate(clk);
 	clk_put(clk);
 
-	/* find out if the watchdog caused the last reboot */
-	if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
-		ltq_wdt_bootstatus = WDIOF_CARDRESET;
+	ltq_set_wdt_bootstatus(pdev);
 
 	dev_info(&pdev->dev, "Init done\n");
 	return misc_register(&ltq_wdt_miscdev);
@@ -222,7 +259,9 @@ ltq_wdt_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id ltq_wdt_match[] = {
-	{ .compatible = "lantiq,wdt" },
+	{ .compatible = "lantiq,wdt"},
+	{ .compatible = "lantiq,wdt-xrx100"},
+	{ .compatible = "lantiq,wdt-falcon"},
 	{},
 };
 MODULE_DEVICE_TABLE(of, ltq_wdt_match);
-- 
2.11.0

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[PATCH 04/13] watchdog: lantiq: access boot cause register through regmap

[Hauke Mehrtens]

This patch avoids accessing the function ltq_reset_cause() and directly
accesses the register given over the syscon interface. The syscon
interface will be implemented for the xway SoCs for the falcon SoCs the
ltq_reset_cause() function never worked, because a wrong offset was used.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 drivers/watchdog/lantiq_wdt.c | 47 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index e0823677d8c1..0e349ad03fdf 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -17,9 +17,14 @@
 #include <linux/uaccess.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 
 #include <lantiq_soc.h>
 
+#define LTQ_RST_CAUSE_WDT_XRX		BIT(31)
+#define LTQ_RST_CAUSE_WDT_FALCON	0x02
+
 /*
  * Section 3.4 of the datasheet
  * The password sequence protects the WDT control register from unintended
@@ -186,6 +191,40 @@ static struct miscdevice ltq_wdt_miscdev = {
 	.fops	= &ltq_wdt_fops,
 };
 
+static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
+{
+	struct device_node *np = pdev->dev.of_node;
+	struct regmap *rcu_regmap;
+	u32 status_reg_offset;
+	u32 val;
+	int err;
+
+	rcu_regmap = syscon_regmap_lookup_by_phandle(np,
+						     "lantiq,rcu-syscon");
+	if (IS_ERR_OR_NULL(rcu_regmap))
+		return;
+
+	err = of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+					 &status_reg_offset);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+		return;
+	}
+
+	err = regmap_read(rcu_regmap, status_reg_offset, &val);
+	if (err)
+		return;
+
+	/* find out if the watchdog caused the last reboot */
+	if (of_device_is_compatible(np, "lantiq,wdt-xrx100")) {
+		if (val & LTQ_RST_CAUSE_WDT_XRX)
+			ltq_wdt_bootstatus = WDIOF_CARDRESET;
+	} else if  (of_device_is_compatible(np, "lantiq,wdt-falcon")) {
+		if ((val & 0x7) == LTQ_RST_CAUSE_WDT_FALCON)
+			ltq_wdt_bootstatus = WDIOF_CARDRESET;
+	}
+}
+
 static int
 ltq_wdt_probe(struct platform_device *pdev)
 {
@@ -205,9 +244,7 @@ ltq_wdt_probe(struct platform_device *pdev)
 	ltq_io_region_clk_rate = clk_get_rate(clk);
 	clk_put(clk);
 
-	/* find out if the watchdog caused the last reboot */
-	if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
-		ltq_wdt_bootstatus = WDIOF_CARDRESET;
+	ltq_set_wdt_bootstatus(pdev);
 
 	dev_info(&pdev->dev, "Init done\n");
 	return misc_register(&ltq_wdt_miscdev);
@@ -222,7 +259,9 @@ ltq_wdt_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id ltq_wdt_match[] = {
-	{ .compatible = "lantiq,wdt" },
+	{ .compatible = "lantiq,wdt"},
+	{ .compatible = "lantiq,wdt-xrx100"},
+	{ .compatible = "lantiq,wdt-falcon"},
 	{},
 };
 MODULE_DEVICE_TABLE(of, ltq_wdt_match);
-- 
2.11.0

[PATCH 05/13] MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 arch/mips/lantiq/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 177769dbb0e8..f5db4a426568 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,7 @@ config SOC_XWAY
 	bool "XWAY"
 	select SOC_TYPE_XWAY
 	select HW_HAS_PCI
+	select MFD_SYSCON
 
 config SOC_FALCON
 	bool "FALCON"
-- 
2.11.0

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[PATCH 05/13] MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/lantiq/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 177769dbb0e8..f5db4a426568 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,7 @@ config SOC_XWAY
 	bool "XWAY"
 	select SOC_TYPE_XWAY
 	select HW_HAS_PCI
+	select MFD_SYSCON
 
 config SOC_FALCON
 	bool "FALCON"
-- 
2.11.0

[PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

This allows using the xbar driver on ARX300 based SoCs which require the
same xbar setup as the xRX200 chipsets because the xbar driver
initialization is not guarded by an xRX200 specific
of_machine_is_compatible condition anymore. Additionally the new driver
takes a syscon phandle to configure the XBAR endianness bits in RCU
(before this was done in arch/mips/lantiq/xway/reset.c and also
guarded by an xRX200 specific if-statement).

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
 MAINTAINERS                                        |   1 +
 arch/mips/lantiq/xway/reset.c                      |   4 -
 arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
 drivers/soc/Makefile                               |   1 +
 drivers/soc/lantiq/Makefile                        |   1 +
 drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
 7 files changed, 125 insertions(+), 45 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
 create mode 100644 drivers/soc/lantiq/Makefile
 create mode 100644 drivers/soc/lantiq/xbar.c

diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
new file mode 100644
index 000000000000..86e53ff3b0d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
@@ -0,0 +1,22 @@
+Lantiq XWAY SoC XBAR binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible	: Should be "lantiq,xbar-xway"
+- reg		: The address and length of the XBAR registers
+
+Optional properties:
+- lantiq,rcu-syscon	: A phandle and offset to the endianness configuration
+			  registers in the RCU module
+
+
+-------------------------------------------------------------------------------
+Example for the XBAR on the xRX200 SoCs:
+	xbar0: xbar@400000 {
+		compatible = "lantiq,xbar-xway";
+		reg = <0x400000 0x1000>;
+		big-endian;
+		lantiq,rcu-syscon = <&rcu0 0x4c>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 676c139bc883..7c03776a56e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7321,6 +7321,7 @@ M:	John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
 L:	linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
 S:	Maintained
 F:	arch/mips/lantiq
+F:	drivers/soc/lantiq
 
 LAPB module
 L:	linux-x25-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 83fd65d76e81..b6752c95a600 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
 	    of_machine_is_compatible("lantiq,vr9"))
 		ltq_usb_init();
 
-	if (of_machine_is_compatible("lantiq,vr9"))
-		ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
-			    RCU_AHB_ENDIAN);
-
 	_machine_restart = ltq_machine_restart;
 	_machine_halt = ltq_machine_halt;
 	pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec460b651..706639a343bc 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
 #define pmu_w32(x, y)	ltq_w32((x), pmu_membase + (y))
 #define pmu_r32(x)	ltq_r32(pmu_membase + (x))
 
-#define XBAR_ALWAYS_LAST	0x430
-#define XBAR_FPI_BURST_EN	BIT(1)
-#define XBAR_AHB_BURST_EN	BIT(2)
-
-#define xbar_w32(x, y)	ltq_w32((x), ltq_xbar_membase + (y))
-#define xbar_r32(x)	ltq_r32(ltq_xbar_membase + (x))
-
 static void __iomem *pmu_membase;
-static void __iomem *ltq_xbar_membase;
 void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 
@@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
 	ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 }
 
-static void xbar_fpi_burst_disable(void)
-{
-	u32 reg;
-
-	/* bit 1 as 1 --burst; bit 1 as 0 -- single */
-	reg = xbar_r32(XBAR_ALWAYS_LAST);
-	reg &= ~XBAR_FPI_BURST_EN;
-	xbar_w32(reg, XBAR_ALWAYS_LAST);
-}
-
 /* enable a clockout source */
 static int clkout_enable(struct clk *clk)
 {
@@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
 	if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 		panic("Failed to remap core resources");
 
-	if (of_machine_is_compatible("lantiq,vr9")) {
-		struct resource res_xbar;
-		struct device_node *np_xbar =
-				of_find_compatible_node(NULL, NULL,
-							"lantiq,xbar-xway");
-
-		if (!np_xbar)
-			panic("Failed to load xbar nodes from devicetree");
-		if (of_address_to_resource(np_xbar, 0, &res_xbar))
-			panic("Failed to get xbar resources");
-		if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
-			res_xbar.name))
-			panic("Failed to get xbar resources");
-
-		ltq_xbar_membase = ioremap_nocache(res_xbar.start,
-						   resource_size(&res_xbar));
-		if (!ltq_xbar_membase)
-			panic("Failed to remap xbar resources");
-	}
-
 	/* make sure to unprotect the memory region where flash is located */
 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 
@@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 	}
-
-	if (of_machine_is_compatible("lantiq,vr9"))
-		xbar_fpi_burst_disable();
 }
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 05eae52a30b4..8775d37ac158 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -6,6 +6,7 @@ obj-y				+= bcm/
 obj-$(CONFIG_ARCH_DOVE)		+= dove/
 obj-$(CONFIG_MACH_DOVE)		+= dove/
 obj-y				+= fsl/
+obj-$(CONFIG_SOC_XWAY)		+= lantiq/
 obj-$(CONFIG_ARCH_MEDIATEK)	+= mediatek/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
 obj-$(CONFIG_ARCH_RENESAS)	+= renesas/
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
new file mode 100644
index 000000000000..7411bd23d58e
--- /dev/null
+++ b/drivers/soc/lantiq/Makefile
@@ -0,0 +1 @@
+obj-y				+= xbar.o
diff --git a/drivers/soc/lantiq/xbar.c b/drivers/soc/lantiq/xbar.c
new file mode 100644
index 000000000000..dcd087817435
--- /dev/null
+++ b/drivers/soc/lantiq/xbar.c
@@ -0,0 +1,100 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011-2015 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ */
+
+#include <linux/ioport.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+
+#include <lantiq_soc.h>
+
+#define XBAR_ALWAYS_LAST	0x430
+#define XBAR_FPI_BURST_EN	BIT(1)
+#define XBAR_AHB_BURST_EN	BIT(2)
+
+#define RCU_VR9_BE_AHB1S	0x00000008
+
+static int ltq_xbar_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct resource res_xbar;
+	struct regmap *rcu_regmap;
+	void __iomem *xbar_membase;
+	u32 rcu_ahb_endianness_reg_offset;
+	u32 rcu_ahb_endianness_val;
+	int ret;
+
+	ret = of_address_to_resource(np, 0, &res_xbar);
+	if (ret) {
+		dev_err(dev, "Failed to get xbar resources");
+		return ret;
+	}
+
+	if (!devm_request_mem_region(dev, res_xbar.start,
+				     resource_size(&res_xbar),
+		res_xbar.name)) {
+		dev_err(dev, "Failed to get xbar resources");
+		return -ENODEV;
+	}
+
+	xbar_membase = devm_ioremap_nocache(dev, res_xbar.start,
+						resource_size(&res_xbar));
+	if (!xbar_membase) {
+		dev_err(dev, "Failed to remap xbar resources");
+		return -ENODEV;
+	}
+
+	/* RCU configuration is optional */
+	rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu-syscon");
+	if (!IS_ERR_OR_NULL(rcu_regmap)) {
+		if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+			&rcu_ahb_endianness_reg_offset)) {
+			dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+			return -EINVAL;
+		}
+
+		if (of_device_is_big_endian(np))
+			rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
+		else
+			rcu_ahb_endianness_val = 0;
+
+		if (regmap_update_bits(rcu_regmap,
+					rcu_ahb_endianness_reg_offset,
+					RCU_VR9_BE_AHB1S,
+					rcu_ahb_endianness_val))
+			dev_warn(&pdev->dev,
+				"Failed to configure RCU AHB endianness\n");
+	}
+
+	/* disable fpi burst */
+	ltq_w32_mask(XBAR_FPI_BURST_EN, 0,
+		     xbar_membase + XBAR_ALWAYS_LAST);
+
+	return 0;
+}
+
+static const struct of_device_id xbar_match[] = {
+	{ .compatible = "lantiq,xbar-xway" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, xbar_match);
+
+static struct platform_driver xbar_driver = {
+	.probe = ltq_xbar_probe,
+	.driver = {
+		.name = "xbar-xway",
+		.of_match_table = xbar_match,
+	},
+};
+
+builtin_platform_driver(xbar_driver);
-- 
2.11.0

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[PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This allows using the xbar driver on ARX300 based SoCs which require the
same xbar setup as the xRX200 chipsets because the xbar driver
initialization is not guarded by an xRX200 specific
of_machine_is_compatible condition anymore. Additionally the new driver
takes a syscon phandle to configure the XBAR endianness bits in RCU
(before this was done in arch/mips/lantiq/xway/reset.c and also
guarded by an xRX200 specific if-statement).

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
 MAINTAINERS                                        |   1 +
 arch/mips/lantiq/xway/reset.c                      |   4 -
 arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
 drivers/soc/Makefile                               |   1 +
 drivers/soc/lantiq/Makefile                        |   1 +
 drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
 7 files changed, 125 insertions(+), 45 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
 create mode 100644 drivers/soc/lantiq/Makefile
 create mode 100644 drivers/soc/lantiq/xbar.c

diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
new file mode 100644
index 000000000000..86e53ff3b0d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
@@ -0,0 +1,22 @@
+Lantiq XWAY SoC XBAR binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible	: Should be "lantiq,xbar-xway"
+- reg		: The address and length of the XBAR registers
+
+Optional properties:
+- lantiq,rcu-syscon	: A phandle and offset to the endianness configuration
+			  registers in the RCU module
+
+
+-------------------------------------------------------------------------------
+Example for the XBAR on the xRX200 SoCs:
+	xbar0: xbar@400000 {
+		compatible = "lantiq,xbar-xway";
+		reg = <0x400000 0x1000>;
+		big-endian;
+		lantiq,rcu-syscon = <&rcu0 0x4c>;
+	};
diff --git a/MAINTAINERS b/MAINTAINERS
index 676c139bc883..7c03776a56e9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7321,6 +7321,7 @@ M:	John Crispin <john@phrozen.org>
 L:	linux-mips@linux-mips.org
 S:	Maintained
 F:	arch/mips/lantiq
+F:	drivers/soc/lantiq
 
 LAPB module
 L:	linux-x25@vger.kernel.org
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 83fd65d76e81..b6752c95a600 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
 	    of_machine_is_compatible("lantiq,vr9"))
 		ltq_usb_init();
 
-	if (of_machine_is_compatible("lantiq,vr9"))
-		ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
-			    RCU_AHB_ENDIAN);
-
 	_machine_restart = ltq_machine_restart;
 	_machine_halt = ltq_machine_halt;
 	pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec460b651..706639a343bc 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
 #define pmu_w32(x, y)	ltq_w32((x), pmu_membase + (y))
 #define pmu_r32(x)	ltq_r32(pmu_membase + (x))
 
-#define XBAR_ALWAYS_LAST	0x430
-#define XBAR_FPI_BURST_EN	BIT(1)
-#define XBAR_AHB_BURST_EN	BIT(2)
-
-#define xbar_w32(x, y)	ltq_w32((x), ltq_xbar_membase + (y))
-#define xbar_r32(x)	ltq_r32(ltq_xbar_membase + (x))
-
 static void __iomem *pmu_membase;
-static void __iomem *ltq_xbar_membase;
 void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 
@@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
 	ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 }
 
-static void xbar_fpi_burst_disable(void)
-{
-	u32 reg;
-
-	/* bit 1 as 1 --burst; bit 1 as 0 -- single */
-	reg = xbar_r32(XBAR_ALWAYS_LAST);
-	reg &= ~XBAR_FPI_BURST_EN;
-	xbar_w32(reg, XBAR_ALWAYS_LAST);
-}
-
 /* enable a clockout source */
 static int clkout_enable(struct clk *clk)
 {
@@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
 	if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
 		panic("Failed to remap core resources");
 
-	if (of_machine_is_compatible("lantiq,vr9")) {
-		struct resource res_xbar;
-		struct device_node *np_xbar =
-				of_find_compatible_node(NULL, NULL,
-							"lantiq,xbar-xway");
-
-		if (!np_xbar)
-			panic("Failed to load xbar nodes from devicetree");
-		if (of_address_to_resource(np_xbar, 0, &res_xbar))
-			panic("Failed to get xbar resources");
-		if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
-			res_xbar.name))
-			panic("Failed to get xbar resources");
-
-		ltq_xbar_membase = ioremap_nocache(res_xbar.start,
-						   resource_size(&res_xbar));
-		if (!ltq_xbar_membase)
-			panic("Failed to remap xbar resources");
-	}
-
 	/* make sure to unprotect the memory region where flash is located */
 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 
@@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
 		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
 	}
-
-	if (of_machine_is_compatible("lantiq,vr9"))
-		xbar_fpi_burst_disable();
 }
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 05eae52a30b4..8775d37ac158 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -6,6 +6,7 @@ obj-y				+= bcm/
 obj-$(CONFIG_ARCH_DOVE)		+= dove/
 obj-$(CONFIG_MACH_DOVE)		+= dove/
 obj-y				+= fsl/
+obj-$(CONFIG_SOC_XWAY)		+= lantiq/
 obj-$(CONFIG_ARCH_MEDIATEK)	+= mediatek/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
 obj-$(CONFIG_ARCH_RENESAS)	+= renesas/
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
new file mode 100644
index 000000000000..7411bd23d58e
--- /dev/null
+++ b/drivers/soc/lantiq/Makefile
@@ -0,0 +1 @@
+obj-y				+= xbar.o
diff --git a/drivers/soc/lantiq/xbar.c b/drivers/soc/lantiq/xbar.c
new file mode 100644
index 000000000000..dcd087817435
--- /dev/null
+++ b/drivers/soc/lantiq/xbar.c
@@ -0,0 +1,100 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011-2015 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ */
+
+#include <linux/ioport.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+
+#include <lantiq_soc.h>
+
+#define XBAR_ALWAYS_LAST	0x430
+#define XBAR_FPI_BURST_EN	BIT(1)
+#define XBAR_AHB_BURST_EN	BIT(2)
+
+#define RCU_VR9_BE_AHB1S	0x00000008
+
+static int ltq_xbar_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct resource res_xbar;
+	struct regmap *rcu_regmap;
+	void __iomem *xbar_membase;
+	u32 rcu_ahb_endianness_reg_offset;
+	u32 rcu_ahb_endianness_val;
+	int ret;
+
+	ret = of_address_to_resource(np, 0, &res_xbar);
+	if (ret) {
+		dev_err(dev, "Failed to get xbar resources");
+		return ret;
+	}
+
+	if (!devm_request_mem_region(dev, res_xbar.start,
+				     resource_size(&res_xbar),
+		res_xbar.name)) {
+		dev_err(dev, "Failed to get xbar resources");
+		return -ENODEV;
+	}
+
+	xbar_membase = devm_ioremap_nocache(dev, res_xbar.start,
+						resource_size(&res_xbar));
+	if (!xbar_membase) {
+		dev_err(dev, "Failed to remap xbar resources");
+		return -ENODEV;
+	}
+
+	/* RCU configuration is optional */
+	rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu-syscon");
+	if (!IS_ERR_OR_NULL(rcu_regmap)) {
+		if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+			&rcu_ahb_endianness_reg_offset)) {
+			dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+			return -EINVAL;
+		}
+
+		if (of_device_is_big_endian(np))
+			rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
+		else
+			rcu_ahb_endianness_val = 0;
+
+		if (regmap_update_bits(rcu_regmap,
+					rcu_ahb_endianness_reg_offset,
+					RCU_VR9_BE_AHB1S,
+					rcu_ahb_endianness_val))
+			dev_warn(&pdev->dev,
+				"Failed to configure RCU AHB endianness\n");
+	}
+
+	/* disable fpi burst */
+	ltq_w32_mask(XBAR_FPI_BURST_EN, 0,
+		     xbar_membase + XBAR_ALWAYS_LAST);
+
+	return 0;
+}
+
+static const struct of_device_id xbar_match[] = {
+	{ .compatible = "lantiq,xbar-xway" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, xbar_match);
+
+static struct platform_driver xbar_driver = {
+	.probe = ltq_xbar_probe,
+	.driver = {
+		.name = "xbar-xway",
+		.of_match_table = xbar_match,
+	},
+};
+
+builtin_platform_driver(xbar_driver);
-- 
2.11.0

[PATCH 07/13] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

Do not export the ltq_reset_cause() and ltq_boot_select() function any
more. ltq_reset_cause() was accessed by the watchdog driver before to
see why the last reset happened, this is now done through direct access
of the register over regmap. The bits in this register are anyway
different between the xrx200 and the falcon SoC.
ltq_boot_select() is not used any more and was used by the flash
drivers to check if the system was booted from this flash type, now the
drivers should depend on the device tree only.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 arch/mips/include/asm/mach-lantiq/lantiq.h |  4 ----
 arch/mips/lantiq/falcon/reset.c            | 22 ----------------------
 arch/mips/lantiq/xway/reset.c              | 19 -------------------
 3 files changed, 45 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 8064d7a4b33d..fa045b4c0cdd 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
 extern struct clk *clk_get_io(void);
 extern struct clk *clk_get_ppe(void);
 
-/* find out what bootsource we have */
-extern unsigned char ltq_boot_select(void);
-/* find out what caused the last cpu reset */
-extern int ltq_reset_cause(void);
 /* find out the soc type */
 extern int ltq_soc_type(void);
 
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
index 7a535d72f541..722114d7409d 100644
--- a/arch/mips/lantiq/falcon/reset.c
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -15,28 +15,6 @@
 
 #include <lantiq_soc.h>
 
-/* CPU0 Reset Source Register */
-#define SYS1_CPU0RS		0x0040
-/* reset cause mask */
-#define CPU0RS_MASK		0x0003
-/* CPU0 Boot Mode Register */
-#define SYS1_BM			0x00a0
-/* boot mode mask */
-#define BM_MASK			0x0005
-
-/* allow platform code to find out what surce we booted from */
-unsigned char ltq_boot_select(void)
-{
-	return ltq_sys1_r32(SYS1_BM) & BM_MASK;
-}
-
-/* allow the watchdog driver to find out what the boot reason was */
-int ltq_reset_cause(void)
-{
-	return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
 #define BOOT_REG_BASE	(KSEG1 | 0x1F200000)
 #define BOOT_PW1_REG	(BOOT_REG_BASE | 0x20)
 #define BOOT_PW2_REG	(BOOT_REG_BASE | 0x24)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index b6752c95a600..2dedcf939901 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
 	spin_unlock_irqrestore(&ltq_rcu_lock, flags);
 }
 
-/* This function is used by the watchdog driver */
-int ltq_reset_cause(void)
-{
-	u32 val = ltq_rcu_r32(RCU_RST_STAT);
-	return val >> RCU_STAT_SHIFT;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
-/* allow platform code to find out what source we booted from */
-unsigned char ltq_boot_select(void)
-{
-	u32 val = ltq_rcu_r32(RCU_RST_STAT);
-
-	if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
-		return RCU_BOOT_SEL_XRX200(val);
-
-	return RCU_BOOT_SEL(val);
-}
-
 struct ltq_gphy_reset {
 	u32 rd;
 	u32 addr;
-- 
2.11.0

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[PATCH 07/13] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Do not export the ltq_reset_cause() and ltq_boot_select() function any
more. ltq_reset_cause() was accessed by the watchdog driver before to
see why the last reset happened, this is now done through direct access
of the register over regmap. The bits in this register are anyway
different between the xrx200 and the falcon SoC.
ltq_boot_select() is not used any more and was used by the flash
drivers to check if the system was booted from this flash type, now the
drivers should depend on the device tree only.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/include/asm/mach-lantiq/lantiq.h |  4 ----
 arch/mips/lantiq/falcon/reset.c            | 22 ----------------------
 arch/mips/lantiq/xway/reset.c              | 19 -------------------
 3 files changed, 45 deletions(-)

diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 8064d7a4b33d..fa045b4c0cdd 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
 extern struct clk *clk_get_io(void);
 extern struct clk *clk_get_ppe(void);
 
-/* find out what bootsource we have */
-extern unsigned char ltq_boot_select(void);
-/* find out what caused the last cpu reset */
-extern int ltq_reset_cause(void);
 /* find out the soc type */
 extern int ltq_soc_type(void);
 
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
index 7a535d72f541..722114d7409d 100644
--- a/arch/mips/lantiq/falcon/reset.c
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -15,28 +15,6 @@
 
 #include <lantiq_soc.h>
 
-/* CPU0 Reset Source Register */
-#define SYS1_CPU0RS		0x0040
-/* reset cause mask */
-#define CPU0RS_MASK		0x0003
-/* CPU0 Boot Mode Register */
-#define SYS1_BM			0x00a0
-/* boot mode mask */
-#define BM_MASK			0x0005
-
-/* allow platform code to find out what surce we booted from */
-unsigned char ltq_boot_select(void)
-{
-	return ltq_sys1_r32(SYS1_BM) & BM_MASK;
-}
-
-/* allow the watchdog driver to find out what the boot reason was */
-int ltq_reset_cause(void)
-{
-	return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
 #define BOOT_REG_BASE	(KSEG1 | 0x1F200000)
 #define BOOT_PW1_REG	(BOOT_REG_BASE | 0x20)
 #define BOOT_PW2_REG	(BOOT_REG_BASE | 0x24)
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index b6752c95a600..2dedcf939901 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
 	spin_unlock_irqrestore(&ltq_rcu_lock, flags);
 }
 
-/* This function is used by the watchdog driver */
-int ltq_reset_cause(void)
-{
-	u32 val = ltq_rcu_r32(RCU_RST_STAT);
-	return val >> RCU_STAT_SHIFT;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
-/* allow platform code to find out what source we booted from */
-unsigned char ltq_boot_select(void)
-{
-	u32 val = ltq_rcu_r32(RCU_RST_STAT);
-
-	if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
-		return RCU_BOOT_SEL_XRX200(val);
-
-	return RCU_BOOT_SEL(val);
-}
-
 struct ltq_gphy_reset {
 	u32 rd;
 	u32 addr;
-- 
2.11.0

[PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.

For some devices the request and the status bits are different.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
 arch/mips/lantiq/xway/reset.c                      |  68 ------
 drivers/reset/Kconfig                              |   6 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
 5 files changed, 281 insertions(+), 68 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
 create mode 100644 drivers/reset/reset-lantiq-rcu.c

diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
new file mode 100644
index 000000000000..7f097d16bbb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
@@ -0,0 +1,43 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible		: Should be "lantiq,rcu-reset"
+- lantiq,rcu-syscon	: A phandle to the RCU syscon, the reset register
+			  offset and the status register offset.
+- #reset-cells		: Specifies the number of cells needed to encode the
+			  reset line, should be 1.
+
+Optional properties:
+- reset-status		: The request status bit. For some bits the request bit
+			  and the status bit are different. This is depending
+			  on the SoC. If the reset-status bit does not match
+			  the reset-request bit, put the reset number into the
+			  reset-request property and the status bit at the same
+			  index into the reset-status property. If no
+			  reset-request bit is given here, the driver assume
+			  status and request bit are the same.
+- reset-request		: The reset request bit, to map it to the reset-status
+			  bit.
+
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+	rcu_reset0: rcu_reset {
+		compatible = "lantiq,rcu-reset";
+		lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
+		#reset-cells = <1>;
+		reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
+		reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
+	};
+
+	rcu_reset1: rcu_reset {
+		compatible = "lantiq,rcu-reset";
+		lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
+		#reset-cells = <1>;
+	};
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 2dedcf939901..5cb9309b0047 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
 	return 0;
 }
 
-/* reset a io domain for u micro seconds */
-void ltq_reset_once(unsigned int module, ulong u)
-{
-	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-	udelay(u);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-}
-
-static int ltq_assert_device(struct reset_controller_dev *rcdev,
-				unsigned long id)
-{
-	u32 val;
-
-	if (id < 8)
-		return -1;
-
-	val = ltq_rcu_r32(RCU_RST_REQ);
-	val |= BIT(id);
-	ltq_rcu_w32(val, RCU_RST_REQ);
-
-	return 0;
-}
-
-static int ltq_deassert_device(struct reset_controller_dev *rcdev,
-				  unsigned long id)
-{
-	u32 val;
-
-	if (id < 8)
-		return -1;
-
-	val = ltq_rcu_r32(RCU_RST_REQ);
-	val &= ~BIT(id);
-	ltq_rcu_w32(val, RCU_RST_REQ);
-
-	return 0;
-}
-
-static int ltq_reset_device(struct reset_controller_dev *rcdev,
-			       unsigned long id)
-{
-	ltq_assert_device(rcdev, id);
-	return ltq_deassert_device(rcdev, id);
-}
-
-static const struct reset_control_ops reset_ops = {
-	.reset = ltq_reset_device,
-	.assert = ltq_assert_device,
-	.deassert = ltq_deassert_device,
-};
-
-static struct reset_controller_dev reset_dev = {
-	.ops			= &reset_ops,
-	.owner			= THIS_MODULE,
-	.nr_resets		= 32,
-	.of_reset_n_cells	= 1,
-};
-
-void ltq_rst_init(void)
-{
-	reset_dev.of_node = of_find_compatible_node(NULL, NULL,
-						"lantiq,xway-reset");
-	if (!reset_dev.of_node)
-		pr_err("Failed to find reset controller node");
-	else
-		reset_controller_register(&reset_dev);
-}
-
 static void ltq_machine_restart(char *command)
 {
 	u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index f4cdfe94b9ec..8962ba44248c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -27,6 +27,12 @@ config RESET_BERLIN
 	help
 	  This enables the reset controller driver for Marvell Berlin SoCs.
 
+config RESET_LANTIQ_RCU
+	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
+	default SOC_TYPE_XWAY
+	help
+	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
+
 config RESET_LPC18XX
 	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
 	default ARCH_LPC18XX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 2cd3f6c45165..97b0a844b849 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_RESET_LANTIQ_RCU) += reset-lantiq-rcu.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/reset-lantiq-rcu.c b/drivers/reset/reset-lantiq-rcu.c
new file mode 100644
index 000000000000..6178112ca5b4
--- /dev/null
+++ b/drivers/reset/reset-lantiq-rcu.c
@@ -0,0 +1,231 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_platform.h>
+
+#define LANTIQ_RCU_RESET_TIMEOUT	1000000
+
+struct lantiq_rcu_reset_translation {
+	int request;
+	int status;
+};
+
+struct lantiq_rcu_reset_priv {
+	struct reset_controller_dev rcdev;
+	struct device *dev;
+	struct regmap *regmap;
+	u32 reset_offset;
+	u32 status_offset;
+	int trans_number;
+	struct lantiq_rcu_reset_translation *trans;
+};
+
+static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
+	struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
+}
+
+static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+	u32 val;
+	int ret, i;
+
+	if (id >= rcdev->nr_resets)
+		return -EINVAL;
+
+	for (i = 0; i < priv->trans_number; i++) {
+		if (id == priv->trans[i].request) {
+			id = priv->trans[i].status;
+			break;
+		}
+	}
+
+	ret = regmap_read(priv->regmap, priv->status_offset, &val);
+	if (ret)
+		return ret;
+
+	return !!(val & BIT(id));
+}
+
+static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
+				   unsigned long id, bool assert)
+{
+	struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+	u32 val;
+	int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
+
+	if (id >= rcdev->nr_resets)
+		return -EINVAL;
+
+	if (assert)
+		val = BIT(id);
+	else
+		val = 0;
+
+	ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(id),
+				 val);
+	if (ret) {
+		dev_err(priv->dev, "Failed to set reset bit %lu\n", id);
+		return ret;
+	}
+
+	do {} while (--retry && lantiq_rcu_reset_status(rcdev, id) != assert);
+	if (!retry) {
+		dev_err(priv->dev, "Failed to %s bit %lu\n",
+			assert ? "assert" : "deassert", id);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	return lantiq_rcu_reset_update(rcdev, id, true);
+}
+
+static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	return lantiq_rcu_reset_update(rcdev, id, false);
+}
+
+static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	int ret;
+
+	ret = lantiq_rcu_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
+
+	return lantiq_rcu_reset_deassert(rcdev, id);
+}
+
+static struct reset_control_ops lantiq_rcu_reset_ops = {
+	.assert = lantiq_rcu_reset_assert,
+	.deassert = lantiq_rcu_reset_deassert,
+	.status = lantiq_rcu_reset_status,
+	.reset	= lantiq_rcu_reset_reset,
+};
+
+static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
+			       struct lantiq_rcu_reset_priv *priv)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int cnt, i, ret;
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(np,
+							"lantiq,rcu-syscon");
+	if (IS_ERR(priv->regmap)) {
+		dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+		&priv->reset_offset)) {
+		dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 2,
+		&priv->status_offset)) {
+		dev_err(&pdev->dev, "Failed to get RCU status offset\n");
+		return -EINVAL;
+	}
+
+	cnt = of_property_count_elems_of_size(np, "reset-request", sizeof(u32));
+	if (cnt <= 0)
+		return 0;
+
+	priv->trans = devm_kmalloc_array(&pdev->dev, cnt, sizeof(*priv->trans),
+					 GFP_KERNEL);
+	if (!priv->trans)
+		return -ENOMEM;
+
+	for (i = 0; i < cnt; i++) {
+		ret = of_property_read_u32_index(np, "reset-request", i,
+						 &priv->trans[i].request);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Failed to get reset-request at index %i\n",
+				i);
+			return ret;
+		}
+		ret = of_property_read_u32_index(np, "reset-status", i,
+						 &priv->trans[i].status);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Failed to get reset-status at index %i\n",
+				i);
+			return ret;
+		}
+	}
+	priv->trans_number = cnt;
+
+	return 0;
+}
+
+static int lantiq_rcu_reset_probe(struct platform_device *pdev)
+{
+	struct lantiq_rcu_reset_priv *priv;
+	int err;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+	platform_set_drvdata(pdev, priv);
+
+	err = lantiq_rcu_reset_of_probe(pdev, priv);
+	if (err)
+		return err;
+
+	priv->rcdev.ops = &lantiq_rcu_reset_ops;
+	priv->rcdev.owner = THIS_MODULE;
+	priv->rcdev.of_node = pdev->dev.of_node;
+	priv->rcdev.of_reset_n_cells = 1;
+	priv->rcdev.nr_resets = 32;
+
+	err = reset_controller_register(&priv->rcdev);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
+	{ .compatible = "lantiq,rcu-reset", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
+
+static struct platform_driver lantiq_rcu_reset_driver = {
+	.probe	= lantiq_rcu_reset_probe,
+	.driver = {
+		.name		= "lantiq-rcu-reset",
+		.of_match_table	= lantiq_rcu_reset_dt_ids,
+	},
+};
+module_platform_driver(lantiq_rcu_reset_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
+MODULE_LICENSE("GPL");
-- 
2.11.0

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[PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.

For some devices the request and the status bits are different.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
 arch/mips/lantiq/xway/reset.c                      |  68 ------
 drivers/reset/Kconfig                              |   6 +
 drivers/reset/Makefile                             |   1 +
 drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
 5 files changed, 281 insertions(+), 68 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
 create mode 100644 drivers/reset/reset-lantiq-rcu.c

diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
new file mode 100644
index 000000000000..7f097d16bbb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
@@ -0,0 +1,43 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible		: Should be "lantiq,rcu-reset"
+- lantiq,rcu-syscon	: A phandle to the RCU syscon, the reset register
+			  offset and the status register offset.
+- #reset-cells		: Specifies the number of cells needed to encode the
+			  reset line, should be 1.
+
+Optional properties:
+- reset-status		: The request status bit. For some bits the request bit
+			  and the status bit are different. This is depending
+			  on the SoC. If the reset-status bit does not match
+			  the reset-request bit, put the reset number into the
+			  reset-request property and the status bit at the same
+			  index into the reset-status property. If no
+			  reset-request bit is given here, the driver assume
+			  status and request bit are the same.
+- reset-request		: The reset request bit, to map it to the reset-status
+			  bit.
+
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+	rcu_reset0: rcu_reset {
+		compatible = "lantiq,rcu-reset";
+		lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
+		#reset-cells = <1>;
+		reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
+		reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
+	};
+
+	rcu_reset1: rcu_reset {
+		compatible = "lantiq,rcu-reset";
+		lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
+		#reset-cells = <1>;
+	};
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 2dedcf939901..5cb9309b0047 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
 	return 0;
 }
 
-/* reset a io domain for u micro seconds */
-void ltq_reset_once(unsigned int module, ulong u)
-{
-	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-	udelay(u);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-}
-
-static int ltq_assert_device(struct reset_controller_dev *rcdev,
-				unsigned long id)
-{
-	u32 val;
-
-	if (id < 8)
-		return -1;
-
-	val = ltq_rcu_r32(RCU_RST_REQ);
-	val |= BIT(id);
-	ltq_rcu_w32(val, RCU_RST_REQ);
-
-	return 0;
-}
-
-static int ltq_deassert_device(struct reset_controller_dev *rcdev,
-				  unsigned long id)
-{
-	u32 val;
-
-	if (id < 8)
-		return -1;
-
-	val = ltq_rcu_r32(RCU_RST_REQ);
-	val &= ~BIT(id);
-	ltq_rcu_w32(val, RCU_RST_REQ);
-
-	return 0;
-}
-
-static int ltq_reset_device(struct reset_controller_dev *rcdev,
-			       unsigned long id)
-{
-	ltq_assert_device(rcdev, id);
-	return ltq_deassert_device(rcdev, id);
-}
-
-static const struct reset_control_ops reset_ops = {
-	.reset = ltq_reset_device,
-	.assert = ltq_assert_device,
-	.deassert = ltq_deassert_device,
-};
-
-static struct reset_controller_dev reset_dev = {
-	.ops			= &reset_ops,
-	.owner			= THIS_MODULE,
-	.nr_resets		= 32,
-	.of_reset_n_cells	= 1,
-};
-
-void ltq_rst_init(void)
-{
-	reset_dev.of_node = of_find_compatible_node(NULL, NULL,
-						"lantiq,xway-reset");
-	if (!reset_dev.of_node)
-		pr_err("Failed to find reset controller node");
-	else
-		reset_controller_register(&reset_dev);
-}
-
 static void ltq_machine_restart(char *command)
 {
 	u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index f4cdfe94b9ec..8962ba44248c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -27,6 +27,12 @@ config RESET_BERLIN
 	help
 	  This enables the reset controller driver for Marvell Berlin SoCs.
 
+config RESET_LANTIQ_RCU
+	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
+	default SOC_TYPE_XWAY
+	help
+	  This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
+
 config RESET_LPC18XX
 	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
 	default ARCH_LPC18XX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 2cd3f6c45165..97b0a844b849 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_RESET_LANTIQ_RCU) += reset-lantiq-rcu.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/reset-lantiq-rcu.c b/drivers/reset/reset-lantiq-rcu.c
new file mode 100644
index 000000000000..6178112ca5b4
--- /dev/null
+++ b/drivers/reset/reset-lantiq-rcu.c
@@ -0,0 +1,231 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_platform.h>
+
+#define LANTIQ_RCU_RESET_TIMEOUT	1000000
+
+struct lantiq_rcu_reset_translation {
+	int request;
+	int status;
+};
+
+struct lantiq_rcu_reset_priv {
+	struct reset_controller_dev rcdev;
+	struct device *dev;
+	struct regmap *regmap;
+	u32 reset_offset;
+	u32 status_offset;
+	int trans_number;
+	struct lantiq_rcu_reset_translation *trans;
+};
+
+static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
+	struct reset_controller_dev *rcdev)
+{
+	return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
+}
+
+static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+	u32 val;
+	int ret, i;
+
+	if (id >= rcdev->nr_resets)
+		return -EINVAL;
+
+	for (i = 0; i < priv->trans_number; i++) {
+		if (id == priv->trans[i].request) {
+			id = priv->trans[i].status;
+			break;
+		}
+	}
+
+	ret = regmap_read(priv->regmap, priv->status_offset, &val);
+	if (ret)
+		return ret;
+
+	return !!(val & BIT(id));
+}
+
+static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
+				   unsigned long id, bool assert)
+{
+	struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+	u32 val;
+	int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
+
+	if (id >= rcdev->nr_resets)
+		return -EINVAL;
+
+	if (assert)
+		val = BIT(id);
+	else
+		val = 0;
+
+	ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(id),
+				 val);
+	if (ret) {
+		dev_err(priv->dev, "Failed to set reset bit %lu\n", id);
+		return ret;
+	}
+
+	do {} while (--retry && lantiq_rcu_reset_status(rcdev, id) != assert);
+	if (!retry) {
+		dev_err(priv->dev, "Failed to %s bit %lu\n",
+			assert ? "assert" : "deassert", id);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	return lantiq_rcu_reset_update(rcdev, id, true);
+}
+
+static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	return lantiq_rcu_reset_update(rcdev, id, false);
+}
+
+static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	int ret;
+
+	ret = lantiq_rcu_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
+
+	return lantiq_rcu_reset_deassert(rcdev, id);
+}
+
+static struct reset_control_ops lantiq_rcu_reset_ops = {
+	.assert = lantiq_rcu_reset_assert,
+	.deassert = lantiq_rcu_reset_deassert,
+	.status = lantiq_rcu_reset_status,
+	.reset	= lantiq_rcu_reset_reset,
+};
+
+static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
+			       struct lantiq_rcu_reset_priv *priv)
+{
+	struct device_node *np = pdev->dev.of_node;
+	int cnt, i, ret;
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(np,
+							"lantiq,rcu-syscon");
+	if (IS_ERR(priv->regmap)) {
+		dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+		&priv->reset_offset)) {
+		dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 2,
+		&priv->status_offset)) {
+		dev_err(&pdev->dev, "Failed to get RCU status offset\n");
+		return -EINVAL;
+	}
+
+	cnt = of_property_count_elems_of_size(np, "reset-request", sizeof(u32));
+	if (cnt <= 0)
+		return 0;
+
+	priv->trans = devm_kmalloc_array(&pdev->dev, cnt, sizeof(*priv->trans),
+					 GFP_KERNEL);
+	if (!priv->trans)
+		return -ENOMEM;
+
+	for (i = 0; i < cnt; i++) {
+		ret = of_property_read_u32_index(np, "reset-request", i,
+						 &priv->trans[i].request);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Failed to get reset-request at index %i\n",
+				i);
+			return ret;
+		}
+		ret = of_property_read_u32_index(np, "reset-status", i,
+						 &priv->trans[i].status);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Failed to get reset-status at index %i\n",
+				i);
+			return ret;
+		}
+	}
+	priv->trans_number = cnt;
+
+	return 0;
+}
+
+static int lantiq_rcu_reset_probe(struct platform_device *pdev)
+{
+	struct lantiq_rcu_reset_priv *priv;
+	int err;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+	platform_set_drvdata(pdev, priv);
+
+	err = lantiq_rcu_reset_of_probe(pdev, priv);
+	if (err)
+		return err;
+
+	priv->rcdev.ops = &lantiq_rcu_reset_ops;
+	priv->rcdev.owner = THIS_MODULE;
+	priv->rcdev.of_node = pdev->dev.of_node;
+	priv->rcdev.of_reset_n_cells = 1;
+	priv->rcdev.nr_resets = 32;
+
+	err = reset_controller_register(&priv->rcdev);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
+	{ .compatible = "lantiq,rcu-reset", },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
+
+static struct platform_driver lantiq_rcu_reset_driver = {
+	.probe	= lantiq_rcu_reset_probe,
+	.driver = {
+		.name		= "lantiq-rcu-reset",
+		.of_match_table	= lantiq_rcu_reset_dt_ids,
+	},
+};
+module_platform_driver(lantiq_rcu_reset_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
+MODULE_LICENSE("GPL");
-- 
2.11.0

[PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

Compared to the old xrx200_phy_fw driver the new version has multiple
enhancements. The name of the firmware files does not have to be added
to all .dts files anymore - one now configures the GPHY mode (FE or GE)
instead. Each GPHY can now also boot separate firmware (thus mixing of
GE and FE GPHYs is now possible).
The new implementation is based on the RCU syscon-mfd and uses the
reeset_controller framework instead of raw RCU register reads/writes.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++++
 arch/mips/lantiq/xway/sysctrl.c                    |   4 +-
 drivers/soc/lantiq/Makefile                        |   1 +
 drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++++++++++
 include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 ++
 5 files changed, 314 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
 create mode 100644 drivers/soc/lantiq/gphy.c
 create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h

diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..d525c7ce9f0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,54 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+This depends on binary firmware blobs which must be provided by userspace.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible		: Should be one of
+				"lantiq,xrx200a1x-rcu-gphy"
+				"lantiq,xrx200a2x-rcu-gphy"
+				"lantiq,xrx300-rcu-gphy"
+				"lantiq,xrx330-rcu-gphy"
+- lantiq,rcu-syscon	: A phandle and offset to the GPHY address registers in
+			  the RCU
+- resets		: Must reference the RCU GPHY reset bit
+- reset-names		: One entry, value must be "gphy" or optional "gphy2"
+
+Optional properties (port (child) node):
+- lantiq,gphy-mode	: GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+			  <dt-bindings/mips/lantiq_xway_gphy.h>
+- clocks		: A reference to the (PMU) GPHY clock gate
+- clock-names		: If clocks is given then this must be "gphy"
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+	gphy0: rcu_gphy@0 {
+		compatible = "lantiq,xrx200a2x-rcu-gphy";
+		reg = <0>;
+
+		lantiq,rcu-syscon = <&rcu0 0x20>;
+		resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
+		reset-names = "gphy", "gphy2";
+		lantiq,gphy-mode = <GPHY_MODE_GE>;
+		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+		clock-names = "gphy";
+	};
+
+	gphy1: rcu_gphy@1 {
+		compatible = "lantiq,xrx200a2x-rcu-gphy";
+		reg = <0>;
+
+		lantiq,rcu-syscon = <&rcu0 0x68>;
+		resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
+		reset-names = "gphy", "gphy2";
+		lantiq,gphy-mode = <GPHY_MODE_FE>;
+		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+		clock-names = "gphy";
+	};
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 706639a343bc..5764d3ddce69 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -518,7 +518,7 @@ void __init ltq_soc_init(void)
 		clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
 			       PMU_PPE_DP | PMU_PPE_TC);
 		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
-		clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
+		clkdev_add_pmu("1f203000.rcu:rcu_gphy@0", "gphy", 1, 0, PMU_GPHY);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 		clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -541,7 +541,7 @@ void __init ltq_soc_init(void)
 				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 				PMU_PPE_QSB | PMU_PPE_TOP);
-		clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
+		clkdev_add_pmu("1f203000.rcu:rcu_gphy@0", "gphy", 0, 0, PMU_GPHY);
 		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
index 7411bd23d58e..c5503183740f 100644
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1 +1,2 @@
 obj-y				+= xbar.o
+obj-$(CONFIG_XRX200_PHY_FW)	+= gphy.o
diff --git a/drivers/soc/lantiq/gphy.c b/drivers/soc/lantiq/gphy.c
new file mode 100644
index 000000000000..4218cbd9478e
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,242 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+
+#include <linux/delay.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reboot.h>
+#include <linux/reset.h>
+#include <linux/of_platform.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+
+struct xway_gphy_priv {
+	struct clk *gphy_clk_gate;
+	struct reset_control *gphy_reset;
+	struct reset_control *gphy_reset2;
+	struct regmap *regmap;
+	struct notifier_block gphy_reboot_nb;
+	u32 reg_offset;
+	char *fw_name;
+};
+
+struct xway_gphy_match_data {
+	char *fe_firmware_name;
+	char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+	.fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+	.ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+	.fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+	.ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+	.fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+	.ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+	{ .compatible = "lantiq,xrx200a1x-rcu-gphy", .data = &xrx200a1x_gphy_data },
+	{ .compatible = "lantiq,xrx200a2x-rcu-gphy", .data = &xrx200a2x_gphy_data },
+	{ .compatible = "lantiq,xrx300-rcu-gphy", .data = &xrx300_gphy_data },
+	{ .compatible = "lantiq,xrx330-rcu-gphy", .data = &xrx300_gphy_data },
+	{},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
+{
+	return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
+}
+
+static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
+				   unsigned long code, void *unused)
+{
+	struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
+
+	if (priv) {
+		reset_control_assert(priv->gphy_reset);
+		reset_control_assert(priv->gphy_reset2);
+	}
+
+	return NOTIFY_DONE;
+}
+
+static int xway_gphy_load(struct platform_device *pdev,
+			  const char *fw_name, dma_addr_t *dev_addr)
+{
+	const struct firmware *fw;
+	void *fw_addr;
+	size_t size;
+	int ret;
+
+	dev_info(&pdev->dev, "requesting %s\n", fw_name);
+	ret = request_firmware(&fw, fw_name, &pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to load firmware: %s, error: %i\n",
+			fw_name, ret);
+		return ret;
+	}
+
+	/*
+	 * GPHY cores need the firmware code in a persistent and contiguous
+	 * memory area with a 16 kB boundary aligned start address
+	 */
+	size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+	fw_addr = dma_alloc_coherent(&pdev->dev, size, dev_addr, GFP_KERNEL);
+	if (fw_addr) {
+		fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
+		*dev_addr = ALIGN(*dev_addr, XRX200_GPHY_FW_ALIGN);
+		memcpy(fw_addr, fw->data, fw->size);
+	} else {
+		dev_err(&pdev->dev, "failed to alloc firmware memory\n");
+		ret = -ENOMEM;
+	}
+
+	release_firmware(fw);
+
+	return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+				struct xway_gphy_priv *priv)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *match = of_match_node(xway_gphy_match, np);
+	const struct xway_gphy_match_data *gphy_fw_name_cfg;
+	u32 gphy_mode;
+
+	gphy_fw_name_cfg = match->data;
+
+	/* Ignore all errors since this clock is optional. */
+	priv->gphy_clk_gate = devm_clk_get(&pdev->dev, "gphy");
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(np,
+							"lantiq,rcu-syscon");
+	if (IS_ERR(priv->regmap)) {
+		dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+		&priv->reg_offset)) {
+		dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+		return -EINVAL;
+	}
+
+	priv->gphy_reset = devm_reset_control_get(&pdev->dev, "gphy");
+	if (IS_ERR_OR_NULL(priv->gphy_reset)) {
+		dev_err(&pdev->dev, "Failed to lookup gphy reset\n");
+		return PTR_ERR(priv->gphy_reset);
+	}
+
+	priv->gphy_reset2 = devm_reset_control_get_optional(&pdev->dev, "gphy2");
+	if (IS_ERR(priv->gphy_reset2)) {
+		if (PTR_ERR(priv->gphy_reset2) == -EPROBE_DEFER)
+			return PTR_ERR(priv->gphy_reset2);
+		priv->gphy_reset2 = NULL;
+	}
+
+	if (of_property_read_u32(np, "lantiq,gphy-mode", &gphy_mode))
+		/* Default to GE mode */
+		gphy_mode = GPHY_MODE_GE;
+
+	switch (gphy_mode) {
+	case GPHY_MODE_FE:
+		priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+		break;
+	case GPHY_MODE_GE:
+		priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+		break;
+	default:
+		dev_err(&pdev->dev, "Unknown GPHY mode %d\n", gphy_mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+	struct xway_gphy_priv *priv;
+	dma_addr_t fw_addr = 0;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	ret = xway_gphy_of_probe(pdev, priv);
+	if (ret)
+		return ret;
+
+	if (!IS_ERR_OR_NULL(priv->gphy_clk_gate))
+		clk_prepare_enable(priv->gphy_clk_gate);
+
+	ret = xway_gphy_load(pdev, priv->fw_name, &fw_addr);
+	if (ret)
+		return ret;
+
+	reset_control_assert(priv->gphy_reset);
+	reset_control_assert(priv->gphy_reset2);
+
+	ret = regmap_write(priv->regmap, priv->reg_offset, fw_addr);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to configure FW addr\n");
+		return ret;
+	}
+
+	reset_control_deassert(priv->gphy_reset);
+	reset_control_deassert(priv->gphy_reset2);
+
+	/* assert the gphy reset because it can hang after a reboot: */
+	priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
+	priv->gphy_reboot_nb.priority = -1;
+
+	ret = register_reboot_notifier(&priv->gphy_reboot_nb);
+	if (ret)
+		dev_warn(&pdev->dev, "Failed to register reboot notifier\n");
+
+	platform_set_drvdata(pdev, priv);
+
+	return ret;
+}
+
+static struct platform_driver xway_gphy_driver = {
+	.probe = xway_gphy_probe,
+	.driver = {
+		.name = "xway-rcu-gphy",
+		.of_match_table = xway_gphy_match,
+	},
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/mips/lantiq_rcu_gphy.h b/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 000000000000..fa1a63773342
--- /dev/null
+++ b/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE	1
+#define GPHY_MODE_FE	2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
-- 
2.11.0

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[PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Compared to the old xrx200_phy_fw driver the new version has multiple
enhancements. The name of the firmware files does not have to be added
to all .dts files anymore - one now configures the GPHY mode (FE or GE)
instead. Each GPHY can now also boot separate firmware (thus mixing of
GE and FE GPHYs is now possible).
The new implementation is based on the RCU syscon-mfd and uses the
reeset_controller framework instead of raw RCU register reads/writes.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++++
 arch/mips/lantiq/xway/sysctrl.c                    |   4 +-
 drivers/soc/lantiq/Makefile                        |   1 +
 drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++++++++++
 include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 ++
 5 files changed, 314 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
 create mode 100644 drivers/soc/lantiq/gphy.c
 create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h

diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..d525c7ce9f0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,54 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+This depends on binary firmware blobs which must be provided by userspace.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible		: Should be one of
+				"lantiq,xrx200a1x-rcu-gphy"
+				"lantiq,xrx200a2x-rcu-gphy"
+				"lantiq,xrx300-rcu-gphy"
+				"lantiq,xrx330-rcu-gphy"
+- lantiq,rcu-syscon	: A phandle and offset to the GPHY address registers in
+			  the RCU
+- resets		: Must reference the RCU GPHY reset bit
+- reset-names		: One entry, value must be "gphy" or optional "gphy2"
+
+Optional properties (port (child) node):
+- lantiq,gphy-mode	: GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+			  <dt-bindings/mips/lantiq_xway_gphy.h>
+- clocks		: A reference to the (PMU) GPHY clock gate
+- clock-names		: If clocks is given then this must be "gphy"
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+	gphy0: rcu_gphy@0 {
+		compatible = "lantiq,xrx200a2x-rcu-gphy";
+		reg = <0>;
+
+		lantiq,rcu-syscon = <&rcu0 0x20>;
+		resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
+		reset-names = "gphy", "gphy2";
+		lantiq,gphy-mode = <GPHY_MODE_GE>;
+		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+		clock-names = "gphy";
+	};
+
+	gphy1: rcu_gphy@1 {
+		compatible = "lantiq,xrx200a2x-rcu-gphy";
+		reg = <0>;
+
+		lantiq,rcu-syscon = <&rcu0 0x68>;
+		resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
+		reset-names = "gphy", "gphy2";
+		lantiq,gphy-mode = <GPHY_MODE_FE>;
+		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+		clock-names = "gphy";
+	};
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 706639a343bc..5764d3ddce69 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -518,7 +518,7 @@ void __init ltq_soc_init(void)
 		clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
 			       PMU_PPE_DP | PMU_PPE_TC);
 		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
-		clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
+		clkdev_add_pmu("1f203000.rcu:rcu_gphy@0", "gphy", 1, 0, PMU_GPHY);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 		clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
@@ -541,7 +541,7 @@ void __init ltq_soc_init(void)
 				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
 				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
 				PMU_PPE_QSB | PMU_PPE_TOP);
-		clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
+		clkdev_add_pmu("1f203000.rcu:rcu_gphy@0", "gphy", 0, 0, PMU_GPHY);
 		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
index 7411bd23d58e..c5503183740f 100644
--- a/drivers/soc/lantiq/Makefile
+++ b/drivers/soc/lantiq/Makefile
@@ -1 +1,2 @@
 obj-y				+= xbar.o
+obj-$(CONFIG_XRX200_PHY_FW)	+= gphy.o
diff --git a/drivers/soc/lantiq/gphy.c b/drivers/soc/lantiq/gphy.c
new file mode 100644
index 000000000000..4218cbd9478e
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,242 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/delay.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+#include <linux/firmware.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reboot.h>
+#include <linux/reset.h>
+#include <linux/of_platform.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN	(16 * 1024)
+
+struct xway_gphy_priv {
+	struct clk *gphy_clk_gate;
+	struct reset_control *gphy_reset;
+	struct reset_control *gphy_reset2;
+	struct regmap *regmap;
+	struct notifier_block gphy_reboot_nb;
+	u32 reg_offset;
+	char *fw_name;
+};
+
+struct xway_gphy_match_data {
+	char *fe_firmware_name;
+	char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+	.fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+	.ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+	.fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+	.ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+	.fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+	.ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+	{ .compatible = "lantiq,xrx200a1x-rcu-gphy", .data = &xrx200a1x_gphy_data },
+	{ .compatible = "lantiq,xrx200a2x-rcu-gphy", .data = &xrx200a2x_gphy_data },
+	{ .compatible = "lantiq,xrx300-rcu-gphy", .data = &xrx300_gphy_data },
+	{ .compatible = "lantiq,xrx330-rcu-gphy", .data = &xrx300_gphy_data },
+	{},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
+{
+	return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
+}
+
+static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
+				   unsigned long code, void *unused)
+{
+	struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
+
+	if (priv) {
+		reset_control_assert(priv->gphy_reset);
+		reset_control_assert(priv->gphy_reset2);
+	}
+
+	return NOTIFY_DONE;
+}
+
+static int xway_gphy_load(struct platform_device *pdev,
+			  const char *fw_name, dma_addr_t *dev_addr)
+{
+	const struct firmware *fw;
+	void *fw_addr;
+	size_t size;
+	int ret;
+
+	dev_info(&pdev->dev, "requesting %s\n", fw_name);
+	ret = request_firmware(&fw, fw_name, &pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to load firmware: %s, error: %i\n",
+			fw_name, ret);
+		return ret;
+	}
+
+	/*
+	 * GPHY cores need the firmware code in a persistent and contiguous
+	 * memory area with a 16 kB boundary aligned start address
+	 */
+	size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+	fw_addr = dma_alloc_coherent(&pdev->dev, size, dev_addr, GFP_KERNEL);
+	if (fw_addr) {
+		fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
+		*dev_addr = ALIGN(*dev_addr, XRX200_GPHY_FW_ALIGN);
+		memcpy(fw_addr, fw->data, fw->size);
+	} else {
+		dev_err(&pdev->dev, "failed to alloc firmware memory\n");
+		ret = -ENOMEM;
+	}
+
+	release_firmware(fw);
+
+	return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+				struct xway_gphy_priv *priv)
+{
+	struct device_node *np = pdev->dev.of_node;
+	const struct of_device_id *match = of_match_node(xway_gphy_match, np);
+	const struct xway_gphy_match_data *gphy_fw_name_cfg;
+	u32 gphy_mode;
+
+	gphy_fw_name_cfg = match->data;
+
+	/* Ignore all errors since this clock is optional. */
+	priv->gphy_clk_gate = devm_clk_get(&pdev->dev, "gphy");
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(np,
+							"lantiq,rcu-syscon");
+	if (IS_ERR(priv->regmap)) {
+		dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
+		&priv->reg_offset)) {
+		dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+		return -EINVAL;
+	}
+
+	priv->gphy_reset = devm_reset_control_get(&pdev->dev, "gphy");
+	if (IS_ERR_OR_NULL(priv->gphy_reset)) {
+		dev_err(&pdev->dev, "Failed to lookup gphy reset\n");
+		return PTR_ERR(priv->gphy_reset);
+	}
+
+	priv->gphy_reset2 = devm_reset_control_get_optional(&pdev->dev, "gphy2");
+	if (IS_ERR(priv->gphy_reset2)) {
+		if (PTR_ERR(priv->gphy_reset2) == -EPROBE_DEFER)
+			return PTR_ERR(priv->gphy_reset2);
+		priv->gphy_reset2 = NULL;
+	}
+
+	if (of_property_read_u32(np, "lantiq,gphy-mode", &gphy_mode))
+		/* Default to GE mode */
+		gphy_mode = GPHY_MODE_GE;
+
+	switch (gphy_mode) {
+	case GPHY_MODE_FE:
+		priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+		break;
+	case GPHY_MODE_GE:
+		priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+		break;
+	default:
+		dev_err(&pdev->dev, "Unknown GPHY mode %d\n", gphy_mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+	struct xway_gphy_priv *priv;
+	dma_addr_t fw_addr = 0;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	ret = xway_gphy_of_probe(pdev, priv);
+	if (ret)
+		return ret;
+
+	if (!IS_ERR_OR_NULL(priv->gphy_clk_gate))
+		clk_prepare_enable(priv->gphy_clk_gate);
+
+	ret = xway_gphy_load(pdev, priv->fw_name, &fw_addr);
+	if (ret)
+		return ret;
+
+	reset_control_assert(priv->gphy_reset);
+	reset_control_assert(priv->gphy_reset2);
+
+	ret = regmap_write(priv->regmap, priv->reg_offset, fw_addr);
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to configure FW addr\n");
+		return ret;
+	}
+
+	reset_control_deassert(priv->gphy_reset);
+	reset_control_deassert(priv->gphy_reset2);
+
+	/* assert the gphy reset because it can hang after a reboot: */
+	priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
+	priv->gphy_reboot_nb.priority = -1;
+
+	ret = register_reboot_notifier(&priv->gphy_reboot_nb);
+	if (ret)
+		dev_warn(&pdev->dev, "Failed to register reboot notifier\n");
+
+	platform_set_drvdata(pdev, priv);
+
+	return ret;
+}
+
+static struct platform_driver xway_gphy_driver = {
+	.probe = xway_gphy_probe,
+	.driver = {
+		.name = "xway-rcu-gphy",
+		.of_match_table = xway_gphy_match,
+	},
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");
diff --git a/include/dt-bindings/mips/lantiq_rcu_gphy.h b/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 000000000000..fa1a63773342
--- /dev/null
+++ b/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE	1
+#define GPHY_MODE_FE	2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
-- 
2.11.0

[PATCH 10/13] MIPS: lantiq: remove old GPHY loader code

[Hauke Mehrtens]

The GPHY loader was replaced by a new more flexible driver. Remove the
old driver.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 arch/mips/lantiq/xway/Makefile        |   2 -
 arch/mips/lantiq/xway/reset.c         |  96 -----------------------------
 arch/mips/lantiq/xway/xrx200_phy_fw.c | 113 ----------------------------------
 3 files changed, 211 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c

diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc538f477..6daf3149e7ca 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,3 @@
 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
 
 obj-y += vmmc.o
-
-obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 5cb9309b0047..3f30fb81a50f 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -27,18 +27,6 @@
 #define RCU_RST_REQ		0x0010
 /* reset status register */
 #define RCU_RST_STAT		0x0014
-/* vr9 gphy registers */
-#define RCU_GFS_ADD0_XRX200	0x0020
-#define RCU_GFS_ADD1_XRX200	0x0068
-/* xRX300 gphy registers */
-#define RCU_GFS_ADD0_XRX300	0x0020
-#define RCU_GFS_ADD1_XRX300	0x0058
-#define RCU_GFS_ADD2_XRX300	0x00AC
-/* xRX330 gphy registers */
-#define RCU_GFS_ADD0_XRX330	0x0020
-#define RCU_GFS_ADD1_XRX330	0x0058
-#define RCU_GFS_ADD2_XRX330	0x00AC
-#define RCU_GFS_ADD3_XRX330	0x0264
 
 /* xbar BE flag */
 #define RCU_AHB_ENDIAN          0x004C
@@ -48,15 +36,6 @@
 #define RCU_RD_GPHY0_XRX200	BIT(31)
 #define RCU_RD_SRST		BIT(30)
 #define RCU_RD_GPHY1_XRX200	BIT(29)
-/* xRX300 bits */
-#define RCU_RD_GPHY0_XRX300	BIT(31)
-#define RCU_RD_GPHY1_XRX300	BIT(29)
-#define RCU_RD_GPHY2_XRX300	BIT(28)
-/* xRX330 bits */
-#define RCU_RD_GPHY0_XRX330	BIT(31)
-#define RCU_RD_GPHY1_XRX330	BIT(29)
-#define RCU_RD_GPHY2_XRX330	BIT(28)
-#define RCU_RD_GPHY3_XRX330	BIT(10)
 
 /* reset cause */
 #define RCU_STAT_SHIFT		26
@@ -119,81 +98,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
 	spin_unlock_irqrestore(&ltq_rcu_lock, flags);
 }
 
-struct ltq_gphy_reset {
-	u32 rd;
-	u32 addr;
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx200_gphy[] = {
-	{RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
-	{RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx300_gphy[] = {
-	{RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
-	{RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
-	{RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx330_gphy[] = {
-	{RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
-	{RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
-	{RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
-	{RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
-};
-
-static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
-				  dma_addr_t dev_addr)
-{
-	ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
-	ltq_rcu_w32(dev_addr, phy_regs->addr);
-	ltq_rcu_w32_mask(phy_regs->rd, 0,  RCU_RST_REQ);
-}
-
-/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-{
-	struct clk *clk;
-
-	if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
-		dev_err(dev, "this SoC has no GPHY\n");
-		return -EINVAL;
-	}
-
-	if (of_machine_is_compatible("lantiq,vr9")) {
-		clk = clk_get_sys("1f203000.rcu", "gphy");
-		if (IS_ERR(clk))
-			return PTR_ERR(clk);
-		clk_enable(clk);
-	}
-
-	dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-
-	if (of_machine_is_compatible("lantiq,vr9")) {
-		if (id >= ARRAY_SIZE(xrx200_gphy)) {
-			dev_err(dev, "%u is an invalid gphy id\n", id);
-			return -EINVAL;
-		}
-		xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
-	} else if (of_machine_is_compatible("lantiq,ar10")) {
-		if (id >= ARRAY_SIZE(xrx300_gphy)) {
-			dev_err(dev, "%u is an invalid gphy id\n", id);
-			return -EINVAL;
-		}
-		xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
-	} else if (of_machine_is_compatible("lantiq,grx390")) {
-		if (id >= ARRAY_SIZE(xrx330_gphy)) {
-			dev_err(dev, "%u is an invalid gphy id\n", id);
-			return -EINVAL;
-		}
-		xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
-	}
-	return 0;
-}
-
 static void ltq_machine_restart(char *command)
 {
 	u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/xway/xrx200_phy_fw.c
deleted file mode 100644
index f0a0f2d431b2..000000000000
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Lantiq XRX200 PHY Firmware Loader
- * Author: John Crispin
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2012 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/firmware.h>
-#include <linux/of_platform.h>
-
-#include <lantiq_soc.h>
-
-#define XRX200_GPHY_FW_ALIGN	(16 * 1024)
-
-static dma_addr_t xway_gphy_load(struct platform_device *pdev)
-{
-	const struct firmware *fw;
-	dma_addr_t dev_addr = 0;
-	const char *fw_name;
-	void *fw_addr;
-	size_t size;
-
-	if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
-		of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
-		switch (ltq_soc_type()) {
-		case SOC_TYPE_VR9:
-			if (of_property_read_string(pdev->dev.of_node,
-						    "firmware1", &fw_name)) {
-				dev_err(&pdev->dev,
-					"failed to load firmware filename\n");
-				return 0;
-			}
-			break;
-		case SOC_TYPE_VR9_2:
-			if (of_property_read_string(pdev->dev.of_node,
-						    "firmware2", &fw_name)) {
-				dev_err(&pdev->dev,
-					"failed to load firmware filename\n");
-				return 0;
-			}
-			break;
-		}
-	} else if (of_property_read_string(pdev->dev.of_node,
-					 "firmware", &fw_name)) {
-		dev_err(&pdev->dev, "failed to load firmware filename\n");
-		return 0;
-	}
-
-	dev_info(&pdev->dev, "requesting %s\n", fw_name);
-	if (request_firmware(&fw, fw_name, &pdev->dev)) {
-		dev_err(&pdev->dev, "failed to load firmware: %s\n", fw_name);
-		return 0;
-	}
-
-	/*
-	 * GPHY cores need the firmware code in a persistent and contiguous
-	 * memory area with a 16 kB boundary aligned start address
-	 */
-	size = fw->size + XRX200_GPHY_FW_ALIGN;
-
-	fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
-	if (fw_addr) {
-		fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
-		dev_addr = ALIGN(dev_addr, XRX200_GPHY_FW_ALIGN);
-		memcpy(fw_addr, fw->data, fw->size);
-	} else {
-		dev_err(&pdev->dev, "failed to alloc firmware memory\n");
-	}
-
-	release_firmware(fw);
-	return dev_addr;
-}
-
-static int xway_phy_fw_probe(struct platform_device *pdev)
-{
-	dma_addr_t fw_addr;
-	struct property *pp;
-	unsigned char *phyids;
-	int i, ret = 0;
-
-	fw_addr = xway_gphy_load(pdev);
-	if (!fw_addr)
-		return -EINVAL;
-	pp = of_find_property(pdev->dev.of_node, "phys", NULL);
-	if (!pp)
-		return -ENOENT;
-	phyids = pp->value;
-	for (i = 0; i < pp->length && !ret; i++)
-		ret = xrx200_gphy_boot(&pdev->dev, phyids[i], fw_addr);
-	if (!ret)
-		mdelay(100);
-	return ret;
-}
-
-static const struct of_device_id xway_phy_match[] = {
-	{ .compatible = "lantiq,phy-xrx200" },
-	{},
-};
-
-static struct platform_driver xway_phy_driver = {
-	.probe = xway_phy_fw_probe,
-	.driver = {
-		.name = "phy-xrx200",
-		.of_match_table = xway_phy_match,
-	},
-};
-builtin_platform_driver(xway_phy_driver);
-- 
2.11.0

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[PATCH 10/13] MIPS: lantiq: remove old GPHY loader code

[Hauke Mehrtens]

The GPHY loader was replaced by a new more flexible driver. Remove the
old driver.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/lantiq/xway/Makefile        |   2 -
 arch/mips/lantiq/xway/reset.c         |  96 -----------------------------
 arch/mips/lantiq/xway/xrx200_phy_fw.c | 113 ----------------------------------
 3 files changed, 211 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c

diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc538f477..6daf3149e7ca 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,3 @@
 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
 
 obj-y += vmmc.o
-
-obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 5cb9309b0047..3f30fb81a50f 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -27,18 +27,6 @@
 #define RCU_RST_REQ		0x0010
 /* reset status register */
 #define RCU_RST_STAT		0x0014
-/* vr9 gphy registers */
-#define RCU_GFS_ADD0_XRX200	0x0020
-#define RCU_GFS_ADD1_XRX200	0x0068
-/* xRX300 gphy registers */
-#define RCU_GFS_ADD0_XRX300	0x0020
-#define RCU_GFS_ADD1_XRX300	0x0058
-#define RCU_GFS_ADD2_XRX300	0x00AC
-/* xRX330 gphy registers */
-#define RCU_GFS_ADD0_XRX330	0x0020
-#define RCU_GFS_ADD1_XRX330	0x0058
-#define RCU_GFS_ADD2_XRX330	0x00AC
-#define RCU_GFS_ADD3_XRX330	0x0264
 
 /* xbar BE flag */
 #define RCU_AHB_ENDIAN          0x004C
@@ -48,15 +36,6 @@
 #define RCU_RD_GPHY0_XRX200	BIT(31)
 #define RCU_RD_SRST		BIT(30)
 #define RCU_RD_GPHY1_XRX200	BIT(29)
-/* xRX300 bits */
-#define RCU_RD_GPHY0_XRX300	BIT(31)
-#define RCU_RD_GPHY1_XRX300	BIT(29)
-#define RCU_RD_GPHY2_XRX300	BIT(28)
-/* xRX330 bits */
-#define RCU_RD_GPHY0_XRX330	BIT(31)
-#define RCU_RD_GPHY1_XRX330	BIT(29)
-#define RCU_RD_GPHY2_XRX330	BIT(28)
-#define RCU_RD_GPHY3_XRX330	BIT(10)
 
 /* reset cause */
 #define RCU_STAT_SHIFT		26
@@ -119,81 +98,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
 	spin_unlock_irqrestore(&ltq_rcu_lock, flags);
 }
 
-struct ltq_gphy_reset {
-	u32 rd;
-	u32 addr;
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx200_gphy[] = {
-	{RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
-	{RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx300_gphy[] = {
-	{RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
-	{RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
-	{RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx330_gphy[] = {
-	{RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
-	{RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
-	{RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
-	{RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
-};
-
-static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
-				  dma_addr_t dev_addr)
-{
-	ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
-	ltq_rcu_w32(dev_addr, phy_regs->addr);
-	ltq_rcu_w32_mask(phy_regs->rd, 0,  RCU_RST_REQ);
-}
-
-/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-{
-	struct clk *clk;
-
-	if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
-		dev_err(dev, "this SoC has no GPHY\n");
-		return -EINVAL;
-	}
-
-	if (of_machine_is_compatible("lantiq,vr9")) {
-		clk = clk_get_sys("1f203000.rcu", "gphy");
-		if (IS_ERR(clk))
-			return PTR_ERR(clk);
-		clk_enable(clk);
-	}
-
-	dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-
-	if (of_machine_is_compatible("lantiq,vr9")) {
-		if (id >= ARRAY_SIZE(xrx200_gphy)) {
-			dev_err(dev, "%u is an invalid gphy id\n", id);
-			return -EINVAL;
-		}
-		xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
-	} else if (of_machine_is_compatible("lantiq,ar10")) {
-		if (id >= ARRAY_SIZE(xrx300_gphy)) {
-			dev_err(dev, "%u is an invalid gphy id\n", id);
-			return -EINVAL;
-		}
-		xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
-	} else if (of_machine_is_compatible("lantiq,grx390")) {
-		if (id >= ARRAY_SIZE(xrx330_gphy)) {
-			dev_err(dev, "%u is an invalid gphy id\n", id);
-			return -EINVAL;
-		}
-		xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
-	}
-	return 0;
-}
-
 static void ltq_machine_restart(char *command)
 {
 	u32 val = ltq_rcu_r32(RCU_RST_REQ);
diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/xway/xrx200_phy_fw.c
deleted file mode 100644
index f0a0f2d431b2..000000000000
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Lantiq XRX200 PHY Firmware Loader
- * Author: John Crispin
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2012 John Crispin <john@phrozen.org>
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/firmware.h>
-#include <linux/of_platform.h>
-
-#include <lantiq_soc.h>
-
-#define XRX200_GPHY_FW_ALIGN	(16 * 1024)
-
-static dma_addr_t xway_gphy_load(struct platform_device *pdev)
-{
-	const struct firmware *fw;
-	dma_addr_t dev_addr = 0;
-	const char *fw_name;
-	void *fw_addr;
-	size_t size;
-
-	if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
-		of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
-		switch (ltq_soc_type()) {
-		case SOC_TYPE_VR9:
-			if (of_property_read_string(pdev->dev.of_node,
-						    "firmware1", &fw_name)) {
-				dev_err(&pdev->dev,
-					"failed to load firmware filename\n");
-				return 0;
-			}
-			break;
-		case SOC_TYPE_VR9_2:
-			if (of_property_read_string(pdev->dev.of_node,
-						    "firmware2", &fw_name)) {
-				dev_err(&pdev->dev,
-					"failed to load firmware filename\n");
-				return 0;
-			}
-			break;
-		}
-	} else if (of_property_read_string(pdev->dev.of_node,
-					 "firmware", &fw_name)) {
-		dev_err(&pdev->dev, "failed to load firmware filename\n");
-		return 0;
-	}
-
-	dev_info(&pdev->dev, "requesting %s\n", fw_name);
-	if (request_firmware(&fw, fw_name, &pdev->dev)) {
-		dev_err(&pdev->dev, "failed to load firmware: %s\n", fw_name);
-		return 0;
-	}
-
-	/*
-	 * GPHY cores need the firmware code in a persistent and contiguous
-	 * memory area with a 16 kB boundary aligned start address
-	 */
-	size = fw->size + XRX200_GPHY_FW_ALIGN;
-
-	fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
-	if (fw_addr) {
-		fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
-		dev_addr = ALIGN(dev_addr, XRX200_GPHY_FW_ALIGN);
-		memcpy(fw_addr, fw->data, fw->size);
-	} else {
-		dev_err(&pdev->dev, "failed to alloc firmware memory\n");
-	}
-
-	release_firmware(fw);
-	return dev_addr;
-}
-
-static int xway_phy_fw_probe(struct platform_device *pdev)
-{
-	dma_addr_t fw_addr;
-	struct property *pp;
-	unsigned char *phyids;
-	int i, ret = 0;
-
-	fw_addr = xway_gphy_load(pdev);
-	if (!fw_addr)
-		return -EINVAL;
-	pp = of_find_property(pdev->dev.of_node, "phys", NULL);
-	if (!pp)
-		return -ENOENT;
-	phyids = pp->value;
-	for (i = 0; i < pp->length && !ret; i++)
-		ret = xrx200_gphy_boot(&pdev->dev, phyids[i], fw_addr);
-	if (!ret)
-		mdelay(100);
-	return ret;
-}
-
-static const struct of_device_id xway_phy_match[] = {
-	{ .compatible = "lantiq,phy-xrx200" },
-	{},
-};
-
-static struct platform_driver xway_phy_driver = {
-	.probe = xway_phy_fw_probe,
-	.driver = {
-		.name = "phy-xrx200",
-		.of_match_table = xway_phy_match,
-	},
-};
-builtin_platform_driver(xway_phy_driver);
-- 
2.11.0

[PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
 arch/mips/lantiq/xway/reset.c                      |  43 ---
 arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
 drivers/phy/Kconfig                                |   8 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
 6 files changed, 405 insertions(+), 55 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
 create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c

diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 000000000000..0ec9f790b6e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,59 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible		: Should be one of
+				"lantiq,ase-rcu-usb2-phy"
+				"lantiq,danube-rcu-usb2-phy"
+				"lantiq,xrx100-rcu-usb2-phy"
+				"lantiq,xrx200-rcu-usb2-phy"
+				"lantiq,xrx300-rcu-usb2-phy"
+- lantiq,rcu-syscon	: A phandle to the RCU module and the offsets to the
+			  USB PHY configuration and USB MAC registers.
+- address-cells		: should be 1
+- size-cells		: should be 0
+- phy-cells		: from the generic PHY bindings, must be 1
+
+Optional properties (controller (parent) node):
+- vbus-gpio		: References a GPIO which enables VBUS all given USB
+			  ports.
+
+Required nodes		:  A sub-node is required for each USB PHY port.
+
+
+-------------------------------------------------------------------------------
+Required properties (port (child) node):
+- reg        	: The ID of the USB port, usually 0 or 1.
+- clocks	: References to the (PMU) "ctrl" and "phy" clk gates.
+- clock-names	: Must be one of the following:
+			"ctrl"
+			"phy"
+- resets	: References to the RCU USB configuration reset bits.
+- reset-names	: Must be one of the following:
+			"analog-config" (optional)
+			"statemachine-soft" (optional)
+
+Optional properties (port (child) node):
+- vbus-gpio	: References a GPIO which enables VBUS for the USB port.
+
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+	usb_phys0: rcu-usb2-phy@0 {
+		compatible      = "lantiq,xrx200-rcu-usb2-phy";
+		reg = <0>;
+
+		lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
+		clocks = <&pmu PMU_GATE_USB0_CTRL>,
+			 <&pmu PMU_GATE_USB0_PHY>;
+		clock-names = "ctrl", "phy";
+		vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
+		resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
+		reset-names = "phy", "ctrl";
+		#phy-cells = <0>;
+	};
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 3f30fb81a50f..5aec1f54275b 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
 	unreachable();
 }
 
-static void ltq_usb_init(void)
-{
-	/* Power for USB cores 1 & 2 */
-	ltq_pmu_enable(PMU_AHBM);
-	ltq_pmu_enable(PMU_USB0);
-	ltq_pmu_enable(PMU_USB1);
-
-	ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
-
-	/* Enable USB PHY power for cores 1 & 2 */
-	ltq_pmu_enable(PMU_USB0_P);
-	ltq_pmu_enable(PMU_USB1_P);
-
-	/* Configure cores to host mode */
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
-		RCU_USB1CFG);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
-		RCU_USB2CFG);
-
-	/* Select DMA endianness (Host-endian: big-endian) */
-	ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
-		| RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
-	ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
-		| RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
-	/* Hard reset USB state machines */
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
-	udelay(50 * 1000);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
-	/* Soft reset USB state machines */
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
-		| USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
-	udelay(50 * 1000);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
-		& ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
-}
-
 static int __init mips_reboot_setup(void)
 {
 	struct resource res;
@@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
 	if (!ltq_rcu_membase)
 		panic("Failed to remap core memory");
 
-	if (of_machine_is_compatible("lantiq,ar9") ||
-	    of_machine_is_compatible("lantiq,vr9"))
-		ltq_usb_init();
-
 	_machine_restart = ltq_machine_restart;
 	_machine_halt = ltq_machine_halt;
 	pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 5764d3ddce69..18725f2d5b67 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
 
 	if (of_machine_is_compatible("lantiq,grx390") ||
 	    of_machine_is_compatible("lantiq,ar10")) {
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
-		clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
 		/* rc 0 */
 		clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
 		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
 		else
 			clkdev_add_static(CLOCK_133M, CLOCK_133M,
 						CLOCK_133M, CLOCK_133M);
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 		clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
 	} else if (of_machine_is_compatible("lantiq,vr9")) {
 		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
-		clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
-		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
 		clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
 		clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
 	} else if (of_machine_is_compatible("lantiq,ar9")) {
 		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 				ltq_ar9_fpi_hz(), CLOCK_250M);
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 		clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 		clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
@@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
 	} else {
 		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 005cadb7a3f8..dbb450e3ba04 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
 	  Enable this to support the Broadcom Cygnus PCIe PHY.
 	  If unsure, say N.
 
+config PHY_LANTIQ_RCU_USB2
+	tristate "Lantiq XWAY SoC RCU based USB PHY"
+	depends on SOC_TYPE_XWAY
+	depends on OF
+	select GENERIC_PHY
+	help
+	  Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
+
 source "drivers/phy/tegra/Kconfig"
 
 config PHY_NS2_PCIE
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index dd8f3b5d2918..52631f5ac470 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210)		+= phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCM_SATA)		+= phy-brcm-sata.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
 obj-$(CONFIG_PHY_CYGNUS_PCIE)		+= phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)	+= phy-lantiq-rcu-usb2.o
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_PHY_NS2_PCIE)		+= phy-bcm-ns2-pcie.o
 obj-$(CONFIG_PHY_MESON8B_USB2)		+= phy-meson8b-usb2.o
diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
new file mode 100644
index 000000000000..9bff42afd256
--- /dev/null
+++ b/drivers/phy/phy-lantiq-rcu-usb2.c
@@ -0,0 +1,325 @@
+/*
+ * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define MAX_VBUS_GPIO		2
+
+/* Transmitter HS Pre-Emphasis Enable */
+#define RCU_CFG1_TX_PEE		BIT(0)
+/* Disconnect Threshold */
+#define RCU_CFG1_DIS_THR_MASK	0x00038000
+#define RCU_CFG1_DIS_THR_SHIFT	15
+
+struct ltq_rcu_usb2_bits {
+	u8 hostmode;
+	u8 slave_endianness;
+	u8 host_endianness;
+	bool have_ana_cfg;
+};
+
+struct ltq_rcu_usb2_priv {
+	struct regmap			*regmap;
+	u32				phy_reg_offset;
+	u32				ana_cfg1_reg_offset;
+	const struct ltq_rcu_usb2_bits	*reg_bits;
+	struct device			*dev;
+	struct gpio_desc		*gpiod_vbus[MAX_VBUS_GPIO];
+	struct phy			*phy;
+	struct clk			*ctrl_gate_clk;
+	struct clk			*phy_gate_clk;
+	struct reset_control		*ctrl_reset;
+	struct reset_control		*phy_reset;
+};
+
+static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
+	.hostmode = 11,
+	.slave_endianness = 9,
+	.host_endianness = 10,
+	.have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
+	.hostmode = 11,
+	.slave_endianness = 17,
+	.host_endianness = 10,
+	.have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
+	.hostmode = 11,
+	.slave_endianness = 9,
+	.host_endianness = 10,
+	.have_ana_cfg = true,
+};
+
+static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
+	{
+		.compatible = "lantiq,ase-rcu-usb2-phy",
+		.data = &xway_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,danube-rcu-usb2-phy",
+		.data = &xway_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,xrx100-rcu-usb2-phy",
+		.data = &xrx100_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,xrx200-rcu-usb2-phy",
+		.data = &xrx200_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,xrx300-rcu-usb2-phy",
+		.data = &xrx200_rcu_usb2_reg_bits,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
+
+static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
+						int value)
+{
+	int i;
+
+	for (i = 0; i < MAX_VBUS_GPIO; i++)
+		if (!IS_ERR_OR_NULL(gpiods[i]))
+			gpiod_set_value(gpiods[i], value);
+}
+
+static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
+{
+	struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+	if (priv->phy_reset)
+		reset_control_deassert(priv->phy_reset);
+
+	/* enable the port-specific VBUS GPIOs if available */
+	ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
+
+	return 0;
+}
+
+static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
+{
+	struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+	/*
+	 * only disable the port-specific VBUS GPIO here (if available), the
+	 * shared VBUS GPIO might still be used by another port
+	 */
+	ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
+
+	if (priv->phy_reset)
+		reset_control_assert(priv->phy_reset);
+
+	return 0;
+}
+
+static struct phy_ops ltq_rcu_usb2_phy_ops = {
+	.power_on	= ltq_rcu_usb2_phy_power_on,
+	.power_off	= ltq_rcu_usb2_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
+
+	/* Power on the USB core. */
+	if (clk_prepare_enable(priv->ctrl_gate_clk)) {
+		dev_err(dev, "failed to enable CTRL gate\n");
+		return;
+	}
+
+	/*
+	 * Power on the USB PHY. We have to do it early because
+	 * otherwise the second core won't turn on properly.
+	 */
+	if (clk_prepare_enable(priv->phy_gate_clk)) {
+		dev_err(dev, "failed to enable PHY gate\n");
+		return;
+	}
+
+	if (priv->reg_bits->have_ana_cfg) {
+		regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+			RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
+		regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+			RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
+	}
+
+	/* Configure core to host mode */
+	regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+			   BIT(priv->reg_bits->hostmode), 0);
+
+	/* Select DMA endianness (Host-endian: big-endian) */
+	regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+		BIT(priv->reg_bits->slave_endianness), 0);
+	regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+		BIT(priv->reg_bits->host_endianness),
+		BIT(priv->reg_bits->host_endianness));
+
+	/* Reset USB core throgh reset controller */
+	reset_control_deassert(priv->ctrl_reset);
+
+	if (priv->phy_reset)
+		reset_control_assert(priv->phy_reset);
+}
+
+static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
+					  struct gpio_desc **gpios)
+{
+	int i;
+
+	for (i = 0; i < MAX_VBUS_GPIO; i++) {
+		gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
+							 GPIOD_OUT_LOW);
+		if (IS_ERR(gpios[i]))
+			return PTR_ERR(gpios[i]);
+	}
+
+	return 0;
+}
+
+static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
+				    struct ltq_rcu_usb2_priv *priv)
+{
+	struct device *dev = priv->dev;
+	const struct of_device_id *match =
+		of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
+	int ret;
+
+	if (!match) {
+		dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
+		return -EINVAL;
+	}
+
+	priv->reg_bits = match->data;
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
+						       "lantiq,rcu-syscon");
+	if (IS_ERR(priv->regmap)) {
+		dev_err(dev, "Failed to lookup RCU regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
+	if (ret) {
+		dev_err(dev, "failed to request shared USB VBUS GPIO\n");
+		return ret;
+	}
+
+	priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
+	if (IS_ERR(priv->ctrl_gate_clk)) {
+		dev_err(dev, "Unable to get USB ctrl gate clk\n");
+		return PTR_ERR(priv->ctrl_gate_clk);
+	}
+
+	priv->phy_gate_clk = devm_clk_get(dev, "phy");
+	if (IS_ERR(priv->phy_gate_clk)) {
+		dev_err(dev, "Unable to get USB phy gate clk\n");
+		return PTR_ERR(priv->phy_gate_clk);
+	}
+
+	priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
+	if (IS_ERR(priv->ctrl_reset)) {
+		dev_err(dev, "failed to get 'ctrl' reset\n");
+		return PTR_ERR(priv->ctrl_reset);
+	}
+
+	priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
+	if (IS_ERR(priv->phy_reset)) {
+		if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
+			return PTR_ERR(priv->phy_reset);
+		priv->phy_reset = NULL;
+	}
+
+	ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
+					 &priv->phy_reg_offset);
+	if (ret) {
+		dev_err(dev, "Failed to get RCU PHY reg offset\n");
+		return ret;
+	}
+
+	if (priv->reg_bits->have_ana_cfg) {
+		ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
+						 2, &priv->ana_cfg1_reg_offset);
+		if (ret) {
+			dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
+{
+	struct device_node *child, *np = pdev->dev.of_node;
+	struct ltq_rcu_usb2_priv *priv;
+	struct phy_provider *provider;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
+				       GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+	dev_set_drvdata(priv->dev, priv);
+
+	ret = ltq_rcu_usb2_of_probe(np, priv);
+	if (ret)
+		return ret;
+
+	priv->phy = devm_phy_create(&pdev->dev, child,
+					 &ltq_rcu_usb2_phy_ops);
+	if (IS_ERR(priv->phy)) {
+		dev_err(&pdev->dev, "failed to create PHY\n");
+		return PTR_ERR(priv->phy);
+	}
+
+	phy_set_drvdata(priv->phy, priv);
+
+	ltq_rcu_usb2_start_cores(pdev);
+
+	provider = devm_of_phy_provider_register(&pdev->dev,
+						 of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver ltq_rcu_usb2_phy_driver = {
+	.probe	= ltq_rcu_usb2_phy_probe,
+	.driver = {
+		.name	= "lantiq-rcu-usb2-phy",
+		.of_match_table	= ltq_rcu_usb2_phy_of_match,
+	}
+};
+module_platform_driver(ltq_rcu_usb2_phy_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
+MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

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[PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
the PHY interfaces for each core. The phy instances can be passed to the
dwc2 driver, which already supports the generic phy interface.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
 arch/mips/lantiq/xway/reset.c                      |  43 ---
 arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
 drivers/phy/Kconfig                                |   8 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
 6 files changed, 405 insertions(+), 55 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
 create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c

diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 000000000000..0ec9f790b6e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,59 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible		: Should be one of
+				"lantiq,ase-rcu-usb2-phy"
+				"lantiq,danube-rcu-usb2-phy"
+				"lantiq,xrx100-rcu-usb2-phy"
+				"lantiq,xrx200-rcu-usb2-phy"
+				"lantiq,xrx300-rcu-usb2-phy"
+- lantiq,rcu-syscon	: A phandle to the RCU module and the offsets to the
+			  USB PHY configuration and USB MAC registers.
+- address-cells		: should be 1
+- size-cells		: should be 0
+- phy-cells		: from the generic PHY bindings, must be 1
+
+Optional properties (controller (parent) node):
+- vbus-gpio		: References a GPIO which enables VBUS all given USB
+			  ports.
+
+Required nodes		:  A sub-node is required for each USB PHY port.
+
+
+-------------------------------------------------------------------------------
+Required properties (port (child) node):
+- reg        	: The ID of the USB port, usually 0 or 1.
+- clocks	: References to the (PMU) "ctrl" and "phy" clk gates.
+- clock-names	: Must be one of the following:
+			"ctrl"
+			"phy"
+- resets	: References to the RCU USB configuration reset bits.
+- reset-names	: Must be one of the following:
+			"analog-config" (optional)
+			"statemachine-soft" (optional)
+
+Optional properties (port (child) node):
+- vbus-gpio	: References a GPIO which enables VBUS for the USB port.
+
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+	usb_phys0: rcu-usb2-phy@0 {
+		compatible      = "lantiq,xrx200-rcu-usb2-phy";
+		reg = <0>;
+
+		lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
+		clocks = <&pmu PMU_GATE_USB0_CTRL>,
+			 <&pmu PMU_GATE_USB0_PHY>;
+		clock-names = "ctrl", "phy";
+		vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
+		resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
+		reset-names = "phy", "ctrl";
+		#phy-cells = <0>;
+	};
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 3f30fb81a50f..5aec1f54275b 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
 	unreachable();
 }
 
-static void ltq_usb_init(void)
-{
-	/* Power for USB cores 1 & 2 */
-	ltq_pmu_enable(PMU_AHBM);
-	ltq_pmu_enable(PMU_USB0);
-	ltq_pmu_enable(PMU_USB1);
-
-	ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
-
-	/* Enable USB PHY power for cores 1 & 2 */
-	ltq_pmu_enable(PMU_USB0_P);
-	ltq_pmu_enable(PMU_USB1_P);
-
-	/* Configure cores to host mode */
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
-		RCU_USB1CFG);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
-		RCU_USB2CFG);
-
-	/* Select DMA endianness (Host-endian: big-endian) */
-	ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
-		| RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
-	ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
-		| RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
-	/* Hard reset USB state machines */
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
-	udelay(50 * 1000);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
-	/* Soft reset USB state machines */
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
-		| USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
-	udelay(50 * 1000);
-	ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
-		& ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
-}
-
 static int __init mips_reboot_setup(void)
 {
 	struct resource res;
@@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
 	if (!ltq_rcu_membase)
 		panic("Failed to remap core memory");
 
-	if (of_machine_is_compatible("lantiq,ar9") ||
-	    of_machine_is_compatible("lantiq,vr9"))
-		ltq_usb_init();
-
 	_machine_restart = ltq_machine_restart;
 	_machine_halt = ltq_machine_halt;
 	pm_power_off = ltq_machine_power_off;
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 5764d3ddce69..18725f2d5b67 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
 
 	if (of_machine_is_compatible("lantiq,grx390") ||
 	    of_machine_is_compatible("lantiq,ar10")) {
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
-		clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
 		/* rc 0 */
 		clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
 		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
 		else
 			clkdev_add_static(CLOCK_133M, CLOCK_133M,
 						CLOCK_133M, CLOCK_133M);
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
 		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
 		clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
 	} else if (of_machine_is_compatible("lantiq,vr9")) {
 		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
 				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
-		clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
-		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
 		clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
 		clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
 		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
 	} else if (of_machine_is_compatible("lantiq,ar9")) {
 		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
 				ltq_ar9_fpi_hz(), CLOCK_250M);
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
 		clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
 		clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
@@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
 	} else {
 		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
-		clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-		clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
 		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 005cadb7a3f8..dbb450e3ba04 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
 	  Enable this to support the Broadcom Cygnus PCIe PHY.
 	  If unsure, say N.
 
+config PHY_LANTIQ_RCU_USB2
+	tristate "Lantiq XWAY SoC RCU based USB PHY"
+	depends on SOC_TYPE_XWAY
+	depends on OF
+	select GENERIC_PHY
+	help
+	  Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
+
 source "drivers/phy/tegra/Kconfig"
 
 config PHY_NS2_PCIE
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index dd8f3b5d2918..52631f5ac470 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210)		+= phy-tusb1210.o
 obj-$(CONFIG_PHY_BRCM_SATA)		+= phy-brcm-sata.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
 obj-$(CONFIG_PHY_CYGNUS_PCIE)		+= phy-bcm-cygnus-pcie.o
+obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)	+= phy-lantiq-rcu-usb2.o
 obj-$(CONFIG_ARCH_TEGRA) += tegra/
 obj-$(CONFIG_PHY_NS2_PCIE)		+= phy-bcm-ns2-pcie.o
 obj-$(CONFIG_PHY_MESON8B_USB2)		+= phy-meson8b-usb2.o
diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
new file mode 100644
index 000000000000..9bff42afd256
--- /dev/null
+++ b/drivers/phy/phy-lantiq-rcu-usb2.c
@@ -0,0 +1,325 @@
+/*
+ * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define MAX_VBUS_GPIO		2
+
+/* Transmitter HS Pre-Emphasis Enable */
+#define RCU_CFG1_TX_PEE		BIT(0)
+/* Disconnect Threshold */
+#define RCU_CFG1_DIS_THR_MASK	0x00038000
+#define RCU_CFG1_DIS_THR_SHIFT	15
+
+struct ltq_rcu_usb2_bits {
+	u8 hostmode;
+	u8 slave_endianness;
+	u8 host_endianness;
+	bool have_ana_cfg;
+};
+
+struct ltq_rcu_usb2_priv {
+	struct regmap			*regmap;
+	u32				phy_reg_offset;
+	u32				ana_cfg1_reg_offset;
+	const struct ltq_rcu_usb2_bits	*reg_bits;
+	struct device			*dev;
+	struct gpio_desc		*gpiod_vbus[MAX_VBUS_GPIO];
+	struct phy			*phy;
+	struct clk			*ctrl_gate_clk;
+	struct clk			*phy_gate_clk;
+	struct reset_control		*ctrl_reset;
+	struct reset_control		*phy_reset;
+};
+
+static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
+	.hostmode = 11,
+	.slave_endianness = 9,
+	.host_endianness = 10,
+	.have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
+	.hostmode = 11,
+	.slave_endianness = 17,
+	.host_endianness = 10,
+	.have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
+	.hostmode = 11,
+	.slave_endianness = 9,
+	.host_endianness = 10,
+	.have_ana_cfg = true,
+};
+
+static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
+	{
+		.compatible = "lantiq,ase-rcu-usb2-phy",
+		.data = &xway_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,danube-rcu-usb2-phy",
+		.data = &xway_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,xrx100-rcu-usb2-phy",
+		.data = &xrx100_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,xrx200-rcu-usb2-phy",
+		.data = &xrx200_rcu_usb2_reg_bits,
+	},
+	{
+		.compatible = "lantiq,xrx300-rcu-usb2-phy",
+		.data = &xrx200_rcu_usb2_reg_bits,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
+
+static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
+						int value)
+{
+	int i;
+
+	for (i = 0; i < MAX_VBUS_GPIO; i++)
+		if (!IS_ERR_OR_NULL(gpiods[i]))
+			gpiod_set_value(gpiods[i], value);
+}
+
+static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
+{
+	struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+	if (priv->phy_reset)
+		reset_control_deassert(priv->phy_reset);
+
+	/* enable the port-specific VBUS GPIOs if available */
+	ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
+
+	return 0;
+}
+
+static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
+{
+	struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+	/*
+	 * only disable the port-specific VBUS GPIO here (if available), the
+	 * shared VBUS GPIO might still be used by another port
+	 */
+	ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
+
+	if (priv->phy_reset)
+		reset_control_assert(priv->phy_reset);
+
+	return 0;
+}
+
+static struct phy_ops ltq_rcu_usb2_phy_ops = {
+	.power_on	= ltq_rcu_usb2_phy_power_on,
+	.power_off	= ltq_rcu_usb2_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
+static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
+
+	/* Power on the USB core. */
+	if (clk_prepare_enable(priv->ctrl_gate_clk)) {
+		dev_err(dev, "failed to enable CTRL gate\n");
+		return;
+	}
+
+	/*
+	 * Power on the USB PHY. We have to do it early because
+	 * otherwise the second core won't turn on properly.
+	 */
+	if (clk_prepare_enable(priv->phy_gate_clk)) {
+		dev_err(dev, "failed to enable PHY gate\n");
+		return;
+	}
+
+	if (priv->reg_bits->have_ana_cfg) {
+		regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+			RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
+		regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+			RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
+	}
+
+	/* Configure core to host mode */
+	regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+			   BIT(priv->reg_bits->hostmode), 0);
+
+	/* Select DMA endianness (Host-endian: big-endian) */
+	regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+		BIT(priv->reg_bits->slave_endianness), 0);
+	regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+		BIT(priv->reg_bits->host_endianness),
+		BIT(priv->reg_bits->host_endianness));
+
+	/* Reset USB core throgh reset controller */
+	reset_control_deassert(priv->ctrl_reset);
+
+	if (priv->phy_reset)
+		reset_control_assert(priv->phy_reset);
+}
+
+static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
+					  struct gpio_desc **gpios)
+{
+	int i;
+
+	for (i = 0; i < MAX_VBUS_GPIO; i++) {
+		gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
+							 GPIOD_OUT_LOW);
+		if (IS_ERR(gpios[i]))
+			return PTR_ERR(gpios[i]);
+	}
+
+	return 0;
+}
+
+static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
+				    struct ltq_rcu_usb2_priv *priv)
+{
+	struct device *dev = priv->dev;
+	const struct of_device_id *match =
+		of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
+	int ret;
+
+	if (!match) {
+		dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
+		return -EINVAL;
+	}
+
+	priv->reg_bits = match->data;
+
+	priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
+						       "lantiq,rcu-syscon");
+	if (IS_ERR(priv->regmap)) {
+		dev_err(dev, "Failed to lookup RCU regmap\n");
+		return PTR_ERR(priv->regmap);
+	}
+
+	ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
+	if (ret) {
+		dev_err(dev, "failed to request shared USB VBUS GPIO\n");
+		return ret;
+	}
+
+	priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
+	if (IS_ERR(priv->ctrl_gate_clk)) {
+		dev_err(dev, "Unable to get USB ctrl gate clk\n");
+		return PTR_ERR(priv->ctrl_gate_clk);
+	}
+
+	priv->phy_gate_clk = devm_clk_get(dev, "phy");
+	if (IS_ERR(priv->phy_gate_clk)) {
+		dev_err(dev, "Unable to get USB phy gate clk\n");
+		return PTR_ERR(priv->phy_gate_clk);
+	}
+
+	priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
+	if (IS_ERR(priv->ctrl_reset)) {
+		dev_err(dev, "failed to get 'ctrl' reset\n");
+		return PTR_ERR(priv->ctrl_reset);
+	}
+
+	priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
+	if (IS_ERR(priv->phy_reset)) {
+		if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
+			return PTR_ERR(priv->phy_reset);
+		priv->phy_reset = NULL;
+	}
+
+	ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
+					 &priv->phy_reg_offset);
+	if (ret) {
+		dev_err(dev, "Failed to get RCU PHY reg offset\n");
+		return ret;
+	}
+
+	if (priv->reg_bits->have_ana_cfg) {
+		ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
+						 2, &priv->ana_cfg1_reg_offset);
+		if (ret) {
+			dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
+{
+	struct device_node *child, *np = pdev->dev.of_node;
+	struct ltq_rcu_usb2_priv *priv;
+	struct phy_provider *provider;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
+				       GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+	dev_set_drvdata(priv->dev, priv);
+
+	ret = ltq_rcu_usb2_of_probe(np, priv);
+	if (ret)
+		return ret;
+
+	priv->phy = devm_phy_create(&pdev->dev, child,
+					 &ltq_rcu_usb2_phy_ops);
+	if (IS_ERR(priv->phy)) {
+		dev_err(&pdev->dev, "failed to create PHY\n");
+		return PTR_ERR(priv->phy);
+	}
+
+	phy_set_drvdata(priv->phy, priv);
+
+	ltq_rcu_usb2_start_cores(pdev);
+
+	provider = devm_of_phy_provider_register(&pdev->dev,
+						 of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(provider);
+}
+
+static struct platform_driver ltq_rcu_usb2_phy_driver = {
+	.probe	= ltq_rcu_usb2_phy_probe,
+	.driver = {
+		.name	= "lantiq-rcu-usb2-phy",
+		.of_match_table	= ltq_rcu_usb2_phy_of_match,
+	}
+};
+module_platform_driver(ltq_rcu_usb2_phy_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

[PATCH 12/13] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

This adds the initial documentation for the RCU module (a MFD device
which provides USB PHYs, reset controllers and more).

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 .../devicetree/bindings/mips/lantiq/rcu.txt        | 82 ++++++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt

diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
new file mode 100644
index 000000000000..9e5b1e7493e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,82 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible	: The first and second values must be: "simple-mfd", "syscon"
+- reg		: The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+	rcu0: rcu@203000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x203000 0x100>;
+		big-endian;
+
+		gphy0: rcu_gphy@0 {
+			compatible = "lantiq,xrx200a2x-rcu-gphy";
+			lantiq,rcu-syscon = <&rcu0 0x20>;
+			resets = <&rcu_reset0 31>;
+			reset-names = "gphy";
+			lantiq,gphy-mode = <GPHY_MODE_GE>;
+			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+			clock-names = "gphy";
+		};
+
+		gphy1: rcu_gphy@1 {
+			compatible = "lantiq,xrx200a2x-rcu-gphy";
+			lantiq,rcu-syscon = <&rcu0 0x68>;
+			resets = <&rcu_reset0 29>;
+			reset-names = "gphy";
+			lantiq,gphy-mode = <GPHY_MODE_FE>;
+			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+			clock-names = "gphy";
+		};
+
+		rcu_reset0: rcu_reset@0 {
+			compatible = "lantiq,rcu-reset";
+			lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
+			#reset-cells = <1>;
+			reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
+			reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
+		};
+
+		rcu_reset1: rcu_reset@1 {
+			compatible = "lantiq,rcu-reset";
+			lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
+			#reset-cells = <1>;
+		};
+
+		usb_phys0: rcu-usb2-phy@0 {
+			compatible = "lantiq,xrx200-rcu-usb2-phy";
+
+			lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
+			resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
+			reset-names = "phy", "ctrl";
+			#phy-cells = <0>;
+		};
+
+		usb_phys1: rcu-usb2-phy@1 {
+			compatible = "lantiq,xrx200-rcu-usb2-phy";
+
+			lantiq,rcu-syscon = <&rcu0 0x34 0x3C>;
+			resets = <&rcu_reset1 5>, <&rcu_reset0 4>;
+			reset-names = "phy", "ctrl";
+			#phy-cells = <0>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&rcu0>;
+			offset = <0x10>;
+			mask = <0x40000000>;
+		};
+
+		/* more sub-device nodes (USB PHY, etc.) */
+	};
+
-- 
2.11.0

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[PATCH 12/13] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

This adds the initial documentation for the RCU module (a MFD device
which provides USB PHYs, reset controllers and more).

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 .../devicetree/bindings/mips/lantiq/rcu.txt        | 82 ++++++++++++++++++++++
 1 file changed, 82 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt

diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
new file mode 100644
index 000000000000..9e5b1e7493e4
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,82 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible	: The first and second values must be: "simple-mfd", "syscon"
+- reg		: The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+	rcu0: rcu@203000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x203000 0x100>;
+		big-endian;
+
+		gphy0: rcu_gphy@0 {
+			compatible = "lantiq,xrx200a2x-rcu-gphy";
+			lantiq,rcu-syscon = <&rcu0 0x20>;
+			resets = <&rcu_reset0 31>;
+			reset-names = "gphy";
+			lantiq,gphy-mode = <GPHY_MODE_GE>;
+			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+			clock-names = "gphy";
+		};
+
+		gphy1: rcu_gphy@1 {
+			compatible = "lantiq,xrx200a2x-rcu-gphy";
+			lantiq,rcu-syscon = <&rcu0 0x68>;
+			resets = <&rcu_reset0 29>;
+			reset-names = "gphy";
+			lantiq,gphy-mode = <GPHY_MODE_FE>;
+			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+			clock-names = "gphy";
+		};
+
+		rcu_reset0: rcu_reset@0 {
+			compatible = "lantiq,rcu-reset";
+			lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
+			#reset-cells = <1>;
+			reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
+			reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
+		};
+
+		rcu_reset1: rcu_reset@1 {
+			compatible = "lantiq,rcu-reset";
+			lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
+			#reset-cells = <1>;
+		};
+
+		usb_phys0: rcu-usb2-phy@0 {
+			compatible = "lantiq,xrx200-rcu-usb2-phy";
+
+			lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
+			resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
+			reset-names = "phy", "ctrl";
+			#phy-cells = <0>;
+		};
+
+		usb_phys1: rcu-usb2-phy@1 {
+			compatible = "lantiq,xrx200-rcu-usb2-phy";
+
+			lantiq,rcu-syscon = <&rcu0 0x34 0x3C>;
+			resets = <&rcu_reset1 5>, <&rcu_reset0 4>;
+			reset-names = "phy", "ctrl";
+			#phy-cells = <0>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&rcu0>;
+			offset = <0x10>;
+			mask = <0x40000000>;
+		};
+
+		/* more sub-device nodes (USB PHY, etc.) */
+	};
+
-- 
2.11.0

[PATCH 13/13] MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

The RCU register are now access through separates drivers. remove the
last peaces of the old implementation.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
---
 arch/mips/lantiq/Kconfig       |   1 +
 arch/mips/lantiq/xway/Makefile |   2 +-
 arch/mips/lantiq/xway/reset.c  | 157 -----------------------------------------
 3 files changed, 2 insertions(+), 158 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/reset.c

diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index f5db4a426568..35bc69b78268 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -18,6 +18,7 @@ config SOC_XWAY
 	select SOC_TYPE_XWAY
 	select HW_HAS_PCI
 	select MFD_SYSCON
+	select MFD_CORE
 
 config SOC_FALCON
 	bool "FALCON"
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6daf3149e7ca..fbb0747c70b7 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,3 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
 
 obj-y += vmmc.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
deleted file mode 100644
index 5aec1f54275b..000000000000
--- a/arch/mips/lantiq/xway/reset.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
- *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/export.h>
-#include <linux/delay.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/reset-controller.h>
-
-#include <asm/reboot.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-/* reset request register */
-#define RCU_RST_REQ		0x0010
-/* reset status register */
-#define RCU_RST_STAT		0x0014
-
-/* xbar BE flag */
-#define RCU_AHB_ENDIAN          0x004C
-#define RCU_VR9_BE_AHB1S        0x00000008
-
-/* reboot bit */
-#define RCU_RD_GPHY0_XRX200	BIT(31)
-#define RCU_RD_SRST		BIT(30)
-#define RCU_RD_GPHY1_XRX200	BIT(29)
-
-/* reset cause */
-#define RCU_STAT_SHIFT		26
-/* boot selection */
-#define RCU_BOOT_SEL(x)		((x >> 18) & 0x7)
-#define RCU_BOOT_SEL_XRX200(x)	(((x >> 17) & 0xf) | ((x >> 8) & 0x10))
-
-/* dwc2 USB configuration registers */
-#define RCU_USB1CFG		0x0018
-#define RCU_USB2CFG		0x0034
-
-/* USB DMA endianness bits */
-#define RCU_USBCFG_HDSEL_BIT	BIT(11)
-#define RCU_USBCFG_HOST_END_BIT	BIT(10)
-#define RCU_USBCFG_SLV_END_BIT	BIT(9)
-
-/* USB reset bits */
-#define RCU_USBRESET		0x0010
-
-#define USBRESET_BIT		BIT(4)
-
-#define RCU_USBRESET2		0x0048
-
-#define USB1RESET_BIT		BIT(4)
-#define USB2RESET_BIT		BIT(5)
-
-#define RCU_CFG1A		0x0038
-#define RCU_CFG1B		0x003C
-
-/* USB PMU devices */
-#define PMU_AHBM		BIT(15)
-#define PMU_USB0		BIT(6)
-#define PMU_USB1		BIT(27)
-
-/* USB PHY PMU devices */
-#define PMU_USB0_P		BIT(0)
-#define PMU_USB1_P		BIT(26)
-
-/* remapped base addr of the reset control unit */
-static void __iomem *ltq_rcu_membase;
-static struct device_node *ltq_rcu_np;
-static DEFINE_SPINLOCK(ltq_rcu_lock);
-
-static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
-{
-	ltq_w32(val, ltq_rcu_membase + reg_off);
-}
-
-static uint32_t ltq_rcu_r32(uint32_t reg_off)
-{
-	return ltq_r32(ltq_rcu_membase + reg_off);
-}
-
-static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&ltq_rcu_lock, flags);
-	ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
-	spin_unlock_irqrestore(&ltq_rcu_lock, flags);
-}
-
-static void ltq_machine_restart(char *command)
-{
-	u32 val = ltq_rcu_r32(RCU_RST_REQ);
-
-	if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
-		val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
-
-	val |= RCU_RD_SRST;
-
-	local_irq_disable();
-	ltq_rcu_w32(val, RCU_RST_REQ);
-	unreachable();
-}
-
-static void ltq_machine_halt(void)
-{
-	local_irq_disable();
-	unreachable();
-}
-
-static void ltq_machine_power_off(void)
-{
-	local_irq_disable();
-	unreachable();
-}
-
-static int __init mips_reboot_setup(void)
-{
-	struct resource res;
-
-	ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
-	if (!ltq_rcu_np)
-		ltq_rcu_np = of_find_compatible_node(NULL, NULL,
-							"lantiq,rcu-xrx200");
-
-	/* check if all the reset register range is available */
-	if (!ltq_rcu_np)
-		panic("Failed to load reset resources from devicetree");
-
-	if (of_address_to_resource(ltq_rcu_np, 0, &res))
-		panic("Failed to get rcu memory range");
-
-	if (!request_mem_region(res.start, resource_size(&res), res.name))
-		pr_err("Failed to request rcu memory");
-
-	ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
-	if (!ltq_rcu_membase)
-		panic("Failed to remap core memory");
-
-	_machine_restart = ltq_machine_restart;
-	_machine_halt = ltq_machine_halt;
-	pm_power_off = ltq_machine_power_off;
-
-	return 0;
-}
-
-arch_initcall(mips_reboot_setup);
-- 
2.11.0

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[PATCH 13/13] MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation

[Hauke Mehrtens]

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

The RCU register are now access through separates drivers. remove the
last peaces of the old implementation.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/lantiq/Kconfig       |   1 +
 arch/mips/lantiq/xway/Makefile |   2 +-
 arch/mips/lantiq/xway/reset.c  | 157 -----------------------------------------
 3 files changed, 2 insertions(+), 158 deletions(-)
 delete mode 100644 arch/mips/lantiq/xway/reset.c

diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index f5db4a426568..35bc69b78268 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -18,6 +18,7 @@ config SOC_XWAY
 	select SOC_TYPE_XWAY
 	select HW_HAS_PCI
 	select MFD_SYSCON
+	select MFD_CORE
 
 config SOC_FALCON
 	bool "FALCON"
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index 6daf3149e7ca..fbb0747c70b7 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,3 +1,3 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
 
 obj-y += vmmc.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
deleted file mode 100644
index 5aec1f54275b..000000000000
--- a/arch/mips/lantiq/xway/reset.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <john@phrozen.org>
- *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/export.h>
-#include <linux/delay.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/reset-controller.h>
-
-#include <asm/reboot.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-/* reset request register */
-#define RCU_RST_REQ		0x0010
-/* reset status register */
-#define RCU_RST_STAT		0x0014
-
-/* xbar BE flag */
-#define RCU_AHB_ENDIAN          0x004C
-#define RCU_VR9_BE_AHB1S        0x00000008
-
-/* reboot bit */
-#define RCU_RD_GPHY0_XRX200	BIT(31)
-#define RCU_RD_SRST		BIT(30)
-#define RCU_RD_GPHY1_XRX200	BIT(29)
-
-/* reset cause */
-#define RCU_STAT_SHIFT		26
-/* boot selection */
-#define RCU_BOOT_SEL(x)		((x >> 18) & 0x7)
-#define RCU_BOOT_SEL_XRX200(x)	(((x >> 17) & 0xf) | ((x >> 8) & 0x10))
-
-/* dwc2 USB configuration registers */
-#define RCU_USB1CFG		0x0018
-#define RCU_USB2CFG		0x0034
-
-/* USB DMA endianness bits */
-#define RCU_USBCFG_HDSEL_BIT	BIT(11)
-#define RCU_USBCFG_HOST_END_BIT	BIT(10)
-#define RCU_USBCFG_SLV_END_BIT	BIT(9)
-
-/* USB reset bits */
-#define RCU_USBRESET		0x0010
-
-#define USBRESET_BIT		BIT(4)
-
-#define RCU_USBRESET2		0x0048
-
-#define USB1RESET_BIT		BIT(4)
-#define USB2RESET_BIT		BIT(5)
-
-#define RCU_CFG1A		0x0038
-#define RCU_CFG1B		0x003C
-
-/* USB PMU devices */
-#define PMU_AHBM		BIT(15)
-#define PMU_USB0		BIT(6)
-#define PMU_USB1		BIT(27)
-
-/* USB PHY PMU devices */
-#define PMU_USB0_P		BIT(0)
-#define PMU_USB1_P		BIT(26)
-
-/* remapped base addr of the reset control unit */
-static void __iomem *ltq_rcu_membase;
-static struct device_node *ltq_rcu_np;
-static DEFINE_SPINLOCK(ltq_rcu_lock);
-
-static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
-{
-	ltq_w32(val, ltq_rcu_membase + reg_off);
-}
-
-static uint32_t ltq_rcu_r32(uint32_t reg_off)
-{
-	return ltq_r32(ltq_rcu_membase + reg_off);
-}
-
-static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&ltq_rcu_lock, flags);
-	ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
-	spin_unlock_irqrestore(&ltq_rcu_lock, flags);
-}
-
-static void ltq_machine_restart(char *command)
-{
-	u32 val = ltq_rcu_r32(RCU_RST_REQ);
-
-	if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
-		val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
-
-	val |= RCU_RD_SRST;
-
-	local_irq_disable();
-	ltq_rcu_w32(val, RCU_RST_REQ);
-	unreachable();
-}
-
-static void ltq_machine_halt(void)
-{
-	local_irq_disable();
-	unreachable();
-}
-
-static void ltq_machine_power_off(void)
-{
-	local_irq_disable();
-	unreachable();
-}
-
-static int __init mips_reboot_setup(void)
-{
-	struct resource res;
-
-	ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
-	if (!ltq_rcu_np)
-		ltq_rcu_np = of_find_compatible_node(NULL, NULL,
-							"lantiq,rcu-xrx200");
-
-	/* check if all the reset register range is available */
-	if (!ltq_rcu_np)
-		panic("Failed to load reset resources from devicetree");
-
-	if (of_address_to_resource(ltq_rcu_np, 0, &res))
-		panic("Failed to get rcu memory range");
-
-	if (!request_mem_region(res.start, resource_size(&res), res.name))
-		pr_err("Failed to request rcu memory");
-
-	ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
-	if (!ltq_rcu_membase)
-		panic("Failed to remap core memory");
-
-	_machine_restart = ltq_machine_restart;
-	_machine_halt = ltq_machine_halt;
-	pm_power_off = ltq_machine_power_off;
-
-	return 0;
-}
-
-arch_initcall(mips_reboot_setup);
-- 
2.11.0

Re: [PATCH 00/13] MIPS: lantiq: handle RCU register by separate drivers

[Martin Blumenstingl]

Hi Hauke,

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> The RCU (Reset controller Unit) register block provides many different
> functionalities. Before they were handed by the code in arch/mips/lantiq
> /xway/reset.c, now there are separate drivers for the functionality.
> This block provides support for reset controller, GPHY firmware
> loading, USB PHY initialization and cross bar configuration.
>
> These changes are making the old device tree incompatible with the
> current kernel. The upstream Linux kernel supports loading the device
> tree blob from the boot loader since about one year, the latest
> released vendor kernel does not support loading the device tree from a
> bot loader.
great to see that you could use my work :-)

> I would prefer if this would go through the mips tree.
> There are more patches planed which would convert the Lantiq code
> to the common clock framework.
>
> Hauke Mehrtens (4):
>   mtd: lantiq-flash: drop check of boot select
>   mtd: spi-falcon: drop check of boot select
>   watchdog: lantiq: access boot cause register through regmap
>   MIPS: lantiq: remove old GPHY loader code
>
> Martin Blumenstingl (9):
>   MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses
>   MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
>   MIPS: lantiq: Convert the xbar driver to a platform_driver
>   MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
>   reset: Add a reset controller driver for the Lantiq XWAY based SoCs
>   MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
>   phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
>   Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
>   MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation
if anyone is wondering:
I started porting the lantiq target to the common clock framework
"some" time ago. unfortunately it turned out that some of the
"drivers" are tightly coupled and one cannot simply port the clock
handling to the common clock framework. so I started tackling more
drivers in arch/mips/lantiq/ until I had a huge pile of patches in my
tree but no time to improve them so they were ready to submit. so the
patches from Hauke are roughly based on the ideas of my patches (and
probably a few lines of code here and there).


>  .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++
>  .../devicetree/bindings/mips/lantiq/rcu.txt        |  82 +++++
>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 ++
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 +++
>  MAINTAINERS                                        |   1 +
>  arch/mips/include/asm/mach-lantiq/lantiq.h         |   4 -
>  arch/mips/lantiq/Kconfig                           |   2 +
>  arch/mips/lantiq/falcon/reset.c                    |  22 --
>  arch/mips/lantiq/prom.c                            |   3 +-
>  arch/mips/lantiq/xway/Makefile                     |   4 +-
>  arch/mips/lantiq/xway/reset.c                      | 387 ---------------------
>  arch/mips/lantiq/xway/sysctrl.c                    |  69 +---
>  arch/mips/lantiq/xway/xrx200_phy_fw.c              | 113 ------
>  drivers/mtd/maps/lantiq-flash.c                    |   6 -
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++
>  drivers/reset/Kconfig                              |   6 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-lantiq-rcu.c                   | 231 ++++++++++++
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/lantiq/Makefile                        |   2 +
>  drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++
>  drivers/soc/lantiq/xbar.c                          | 100 ++++++
>  drivers/spi/spi-falcon.c                           |   5 -
>  drivers/watchdog/lantiq_wdt.c                      |  47 ++-
>  include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 +
>  28 files changed, 1255 insertions(+), 600 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>  delete mode 100644 arch/mips/lantiq/xway/reset.c
>  delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>  create mode 100644 drivers/soc/lantiq/Makefile
>  create mode 100644 drivers/soc/lantiq/gphy.c
>  create mode 100644 drivers/soc/lantiq/xbar.c
>  create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
>
> --
> 2.11.0
>
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Re: [PATCH 00/13] MIPS: lantiq: handle RCU register by separate drivers

[Martin Blumenstingl]

Hi Hauke,

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> The RCU (Reset controller Unit) register block provides many different
> functionalities. Before they were handed by the code in arch/mips/lantiq
> /xway/reset.c, now there are separate drivers for the functionality.
> This block provides support for reset controller, GPHY firmware
> loading, USB PHY initialization and cross bar configuration.
>
> These changes are making the old device tree incompatible with the
> current kernel. The upstream Linux kernel supports loading the device
> tree blob from the boot loader since about one year, the latest
> released vendor kernel does not support loading the device tree from a
> bot loader.
great to see that you could use my work :-)

> I would prefer if this would go through the mips tree.
> There are more patches planed which would convert the Lantiq code
> to the common clock framework.
>
> Hauke Mehrtens (4):
>   mtd: lantiq-flash: drop check of boot select
>   mtd: spi-falcon: drop check of boot select
>   watchdog: lantiq: access boot cause register through regmap
>   MIPS: lantiq: remove old GPHY loader code
>
> Martin Blumenstingl (9):
>   MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses
>   MIPS: lantiq: Enable MFD_SYSCON to be able to use it for the RCU MFD
>   MIPS: lantiq: Convert the xbar driver to a platform_driver
>   MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()
>   reset: Add a reset controller driver for the Lantiq XWAY based SoCs
>   MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd
>   phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module
>   Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings
>   MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation
if anyone is wondering:
I started porting the lantiq target to the common clock framework
"some" time ago. unfortunately it turned out that some of the
"drivers" are tightly coupled and one cannot simply port the clock
handling to the common clock framework. so I started tackling more
drivers in arch/mips/lantiq/ until I had a huge pile of patches in my
tree but no time to improve them so they were ready to submit. so the
patches from Hauke are roughly based on the ideas of my patches (and
probably a few lines of code here and there).


>  .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++
>  .../devicetree/bindings/mips/lantiq/rcu.txt        |  82 +++++
>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 ++
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 +++
>  MAINTAINERS                                        |   1 +
>  arch/mips/include/asm/mach-lantiq/lantiq.h         |   4 -
>  arch/mips/lantiq/Kconfig                           |   2 +
>  arch/mips/lantiq/falcon/reset.c                    |  22 --
>  arch/mips/lantiq/prom.c                            |   3 +-
>  arch/mips/lantiq/xway/Makefile                     |   4 +-
>  arch/mips/lantiq/xway/reset.c                      | 387 ---------------------
>  arch/mips/lantiq/xway/sysctrl.c                    |  69 +---
>  arch/mips/lantiq/xway/xrx200_phy_fw.c              | 113 ------
>  drivers/mtd/maps/lantiq-flash.c                    |   6 -
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++
>  drivers/reset/Kconfig                              |   6 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-lantiq-rcu.c                   | 231 ++++++++++++
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/lantiq/Makefile                        |   2 +
>  drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++
>  drivers/soc/lantiq/xbar.c                          | 100 ++++++
>  drivers/spi/spi-falcon.c                           |   5 -
>  drivers/watchdog/lantiq_wdt.c                      |  47 ++-
>  include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 +
>  28 files changed, 1255 insertions(+), 600 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>  delete mode 100644 arch/mips/lantiq/xway/reset.c
>  delete mode 100644 arch/mips/lantiq/xway/xrx200_phy_fw.c
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>  create mode 100644 drivers/soc/lantiq/Makefile
>  create mode 100644 drivers/soc/lantiq/gphy.c
>  create mode 100644 drivers/soc/lantiq/xbar.c
>  create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
>
> --
> 2.11.0
>

Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> The reset controllers (on xRX200 and newer SoCs have two of them) are
> provided by the RCU module. This was initially implemented as a simple
> reset controller. However, the RCU module provides more functionality
> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
> The old reset controller driver implementation from
> arch/mips/lantiq/xway/reset.c did not honor this fact.
>
> For some devices the request and the status bits are different.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
I think you should CC the reset controller framework maintainer
(Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>) as well

> ---
>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>  drivers/reset/Kconfig                              |   6 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>  5 files changed, 281 insertions(+), 68 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>
> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> new file mode 100644
> index 000000000000..7f097d16bbb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> @@ -0,0 +1,43 @@
> +Lantiq XWAY SoC RCU reset controller binding
> +============================================
> +
> +This binding describes a reset-controller found on the RCU module on Lantiq
> +XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible           : Should be "lantiq,rcu-reset"
> +- lantiq,rcu-syscon    : A phandle to the RCU syscon, the reset register
> +                         offset and the status register offset.
> +- #reset-cells         : Specifies the number of cells needed to encode the
> +                         reset line, should be 1.
> +
> +Optional properties:
> +- reset-status         : The request status bit. For some bits the request bit
> +                         and the status bit are different. This is depending
> +                         on the SoC. If the reset-status bit does not match
> +                         the reset-request bit, put the reset number into the
> +                         reset-request property and the status bit at the same
> +                         index into the reset-status property. If no
> +                         reset-request bit is given here, the driver assume
> +                         status and request bit are the same.
> +- reset-request                : The reset request bit, to map it to the reset-status
> +                         bit.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the reset-controllers on the xRX200 SoCs:
> +       rcu_reset0: rcu_reset {
> +               compatible = "lantiq,rcu-reset";
> +               lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
> +               #reset-cells = <1>;
> +               reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
> +               reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
> +       };
> +
> +       rcu_reset1: rcu_reset {
> +               compatible = "lantiq,rcu-reset";
> +               lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
> +               #reset-cells = <1>;
> +       };
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 2dedcf939901..5cb9309b0047 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
probably a left-over of my patch: can't this
arch/mips/lantiq/xway/reset.c change go into PATCH #13 as well?

> @@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
>         return 0;
>  }
>
> -/* reset a io domain for u micro seconds */
> -void ltq_reset_once(unsigned int module, ulong u)
> -{
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
> -       udelay(u);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
> -}
> -
> -static int ltq_assert_device(struct reset_controller_dev *rcdev,
> -                               unsigned long id)
> -{
> -       u32 val;
> -
> -       if (id < 8)
> -               return -1;
> -
> -       val = ltq_rcu_r32(RCU_RST_REQ);
> -       val |= BIT(id);
> -       ltq_rcu_w32(val, RCU_RST_REQ);
> -
> -       return 0;
> -}
> -
> -static int ltq_deassert_device(struct reset_controller_dev *rcdev,
> -                                 unsigned long id)
> -{
> -       u32 val;
> -
> -       if (id < 8)
> -               return -1;
> -
> -       val = ltq_rcu_r32(RCU_RST_REQ);
> -       val &= ~BIT(id);
> -       ltq_rcu_w32(val, RCU_RST_REQ);
> -
> -       return 0;
> -}
> -
> -static int ltq_reset_device(struct reset_controller_dev *rcdev,
> -                              unsigned long id)
> -{
> -       ltq_assert_device(rcdev, id);
> -       return ltq_deassert_device(rcdev, id);
> -}
> -
> -static const struct reset_control_ops reset_ops = {
> -       .reset = ltq_reset_device,
> -       .assert = ltq_assert_device,
> -       .deassert = ltq_deassert_device,
> -};
> -
> -static struct reset_controller_dev reset_dev = {
> -       .ops                    = &reset_ops,
> -       .owner                  = THIS_MODULE,
> -       .nr_resets              = 32,
> -       .of_reset_n_cells       = 1,
> -};
> -
> -void ltq_rst_init(void)
> -{
> -       reset_dev.of_node = of_find_compatible_node(NULL, NULL,
> -                                               "lantiq,xway-reset");
> -       if (!reset_dev.of_node)
> -               pr_err("Failed to find reset controller node");
> -       else
> -               reset_controller_register(&reset_dev);
> -}
> -
>  static void ltq_machine_restart(char *command)
>  {
>         u32 val = ltq_rcu_r32(RCU_RST_REQ);
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index f4cdfe94b9ec..8962ba44248c 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -27,6 +27,12 @@ config RESET_BERLIN
>         help
>           This enables the reset controller driver for Marvell Berlin SoCs.
>
> +config RESET_LANTIQ_RCU
> +       bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
> +       default SOC_TYPE_XWAY
> +       help
> +         This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
> +
>  config RESET_LPC18XX
>         bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
>         default ARCH_LPC18XX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 2cd3f6c45165..97b0a844b849 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>  obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
>  obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
> +obj-$(CONFIG_RESET_LANTIQ_RCU) += reset-lantiq-rcu.o
>  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>  obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> diff --git a/drivers/reset/reset-lantiq-rcu.c b/drivers/reset/reset-lantiq-rcu.c
> new file mode 100644
> index 000000000000..6178112ca5b4
> --- /dev/null
> +++ b/drivers/reset/reset-lantiq-rcu.c
> @@ -0,0 +1,231 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2010 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> + *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
> + *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> + *  Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
> +#include <linux/of_platform.h>
> +
> +#define LANTIQ_RCU_RESET_TIMEOUT       1000000
> +
> +struct lantiq_rcu_reset_translation {
> +       int request;
> +       int status;
> +};
> +
> +struct lantiq_rcu_reset_priv {
> +       struct reset_controller_dev rcdev;
> +       struct device *dev;
> +       struct regmap *regmap;
> +       u32 reset_offset;
> +       u32 status_offset;
> +       int trans_number;
> +       struct lantiq_rcu_reset_translation *trans;
> +};
> +
> +static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
> +       struct reset_controller_dev *rcdev)
> +{
> +       return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
> +}
> +
> +static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
> +                            unsigned long id)
> +{
> +       struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
> +       u32 val;
> +       int ret, i;
> +
> +       if (id >= rcdev->nr_resets)
> +               return -EINVAL;
> +
> +       for (i = 0; i < priv->trans_number; i++) {
> +               if (id == priv->trans[i].request) {
> +                       id = priv->trans[i].status;
> +                       break;
> +               }
> +       }
> +
> +       ret = regmap_read(priv->regmap, priv->status_offset, &val);
> +       if (ret)
> +               return ret;
> +
> +       return !!(val & BIT(id));
> +}
> +
> +static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
> +                                  unsigned long id, bool assert)
> +{
> +       struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
> +       u32 val;
> +       int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
> +
> +       if (id >= rcdev->nr_resets)
> +               return -EINVAL;
> +
> +       if (assert)
> +               val = BIT(id);
> +       else
> +               val = 0;
> +
> +       ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(id),
> +                                val);
> +       if (ret) {
> +               dev_err(priv->dev, "Failed to set reset bit %lu\n", id);
> +               return ret;
> +       }
> +
> +       do {} while (--retry && lantiq_rcu_reset_status(rcdev, id) != assert);
> +       if (!retry) {
> +               dev_err(priv->dev, "Failed to %s bit %lu\n",
> +                       assert ? "assert" : "deassert", id);
> +               return -EIO;
> +       }
> +
> +       return 0;
> +}
> +
> +static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
> +                            unsigned long id)
> +{
> +       return lantiq_rcu_reset_update(rcdev, id, true);
> +}
> +
> +static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
> +                              unsigned long id)
> +{
> +       return lantiq_rcu_reset_update(rcdev, id, false);
> +}
> +
> +static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
> +                           unsigned long id)
> +{
> +       int ret;
> +
> +       ret = lantiq_rcu_reset_assert(rcdev, id);
> +       if (ret)
> +               return ret;
> +
> +       return lantiq_rcu_reset_deassert(rcdev, id);
> +}
> +
> +static struct reset_control_ops lantiq_rcu_reset_ops = {
> +       .assert = lantiq_rcu_reset_assert,
> +       .deassert = lantiq_rcu_reset_deassert,
> +       .status = lantiq_rcu_reset_status,
> +       .reset  = lantiq_rcu_reset_reset,
> +};
> +
> +static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
> +                              struct lantiq_rcu_reset_priv *priv)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       int cnt, i, ret;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(np,
> +                                                       "lantiq,rcu-syscon");
> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
> +               return PTR_ERR(priv->regmap);
> +       }
> +
> +       if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
> +               &priv->reset_offset)) {
> +               dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
> +               return -EINVAL;
> +       }
> +
> +       if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 2,
> +               &priv->status_offset)) {
> +               dev_err(&pdev->dev, "Failed to get RCU status offset\n");
> +               return -EINVAL;
> +       }
> +
> +       cnt = of_property_count_elems_of_size(np, "reset-request", sizeof(u32));
> +       if (cnt <= 0)
> +               return 0;
> +
> +       priv->trans = devm_kmalloc_array(&pdev->dev, cnt, sizeof(*priv->trans),
> +                                        GFP_KERNEL);
> +       if (!priv->trans)
> +               return -ENOMEM;
> +
> +       for (i = 0; i < cnt; i++) {
> +               ret = of_property_read_u32_index(np, "reset-request", i,
> +                                                &priv->trans[i].request);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Failed to get reset-request at index %i\n",
> +                               i);
> +                       return ret;
> +               }
> +               ret = of_property_read_u32_index(np, "reset-status", i,
> +                                                &priv->trans[i].status);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Failed to get reset-status at index %i\n",
> +                               i);
> +                       return ret;
> +               }
> +       }
> +       priv->trans_number = cnt;
> +
> +       return 0;
> +}
> +
> +static int lantiq_rcu_reset_probe(struct platform_device *pdev)
> +{
> +       struct lantiq_rcu_reset_priv *priv;
> +       int err;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = &pdev->dev;
> +       platform_set_drvdata(pdev, priv);
> +
> +       err = lantiq_rcu_reset_of_probe(pdev, priv);
> +       if (err)
> +               return err;
> +
> +       priv->rcdev.ops = &lantiq_rcu_reset_ops;
> +       priv->rcdev.owner = THIS_MODULE;
> +       priv->rcdev.of_node = pdev->dev.of_node;
> +       priv->rcdev.of_reset_n_cells = 1;
> +       priv->rcdev.nr_resets = 32;
> +
> +       err = reset_controller_register(&priv->rcdev);
> +       if (err)
> +               return err;
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
> +       { .compatible = "lantiq,rcu-reset", },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
> +
> +static struct platform_driver lantiq_rcu_reset_driver = {
> +       .probe  = lantiq_rcu_reset_probe,
> +       .driver = {
> +               .name           = "lantiq-rcu-reset",
> +               .of_match_table = lantiq_rcu_reset_dt_ids,
> +       },
> +};
> +module_platform_driver(lantiq_rcu_reset_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
> +MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.11.0
>
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Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> The reset controllers (on xRX200 and newer SoCs have two of them) are
> provided by the RCU module. This was initially implemented as a simple
> reset controller. However, the RCU module provides more functionality
> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
> The old reset controller driver implementation from
> arch/mips/lantiq/xway/reset.c did not honor this fact.
>
> For some devices the request and the status bits are different.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
I think you should CC the reset controller framework maintainer
(Philipp Zabel <p.zabel@pengutronix.de>) as well

> ---
>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>  drivers/reset/Kconfig                              |   6 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>  5 files changed, 281 insertions(+), 68 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>
> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> new file mode 100644
> index 000000000000..7f097d16bbb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> @@ -0,0 +1,43 @@
> +Lantiq XWAY SoC RCU reset controller binding
> +============================================
> +
> +This binding describes a reset-controller found on the RCU module on Lantiq
> +XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible           : Should be "lantiq,rcu-reset"
> +- lantiq,rcu-syscon    : A phandle to the RCU syscon, the reset register
> +                         offset and the status register offset.
> +- #reset-cells         : Specifies the number of cells needed to encode the
> +                         reset line, should be 1.
> +
> +Optional properties:
> +- reset-status         : The request status bit. For some bits the request bit
> +                         and the status bit are different. This is depending
> +                         on the SoC. If the reset-status bit does not match
> +                         the reset-request bit, put the reset number into the
> +                         reset-request property and the status bit at the same
> +                         index into the reset-status property. If no
> +                         reset-request bit is given here, the driver assume
> +                         status and request bit are the same.
> +- reset-request                : The reset request bit, to map it to the reset-status
> +                         bit.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the reset-controllers on the xRX200 SoCs:
> +       rcu_reset0: rcu_reset {
> +               compatible = "lantiq,rcu-reset";
> +               lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
> +               #reset-cells = <1>;
> +               reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
> +               reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
> +       };
> +
> +       rcu_reset1: rcu_reset {
> +               compatible = "lantiq,rcu-reset";
> +               lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
> +               #reset-cells = <1>;
> +       };
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 2dedcf939901..5cb9309b0047 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
probably a left-over of my patch: can't this
arch/mips/lantiq/xway/reset.c change go into PATCH #13 as well?

> @@ -194,74 +194,6 @@ int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
>         return 0;
>  }
>
> -/* reset a io domain for u micro seconds */
> -void ltq_reset_once(unsigned int module, ulong u)
> -{
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
> -       udelay(u);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
> -}
> -
> -static int ltq_assert_device(struct reset_controller_dev *rcdev,
> -                               unsigned long id)
> -{
> -       u32 val;
> -
> -       if (id < 8)
> -               return -1;
> -
> -       val = ltq_rcu_r32(RCU_RST_REQ);
> -       val |= BIT(id);
> -       ltq_rcu_w32(val, RCU_RST_REQ);
> -
> -       return 0;
> -}
> -
> -static int ltq_deassert_device(struct reset_controller_dev *rcdev,
> -                                 unsigned long id)
> -{
> -       u32 val;
> -
> -       if (id < 8)
> -               return -1;
> -
> -       val = ltq_rcu_r32(RCU_RST_REQ);
> -       val &= ~BIT(id);
> -       ltq_rcu_w32(val, RCU_RST_REQ);
> -
> -       return 0;
> -}
> -
> -static int ltq_reset_device(struct reset_controller_dev *rcdev,
> -                              unsigned long id)
> -{
> -       ltq_assert_device(rcdev, id);
> -       return ltq_deassert_device(rcdev, id);
> -}
> -
> -static const struct reset_control_ops reset_ops = {
> -       .reset = ltq_reset_device,
> -       .assert = ltq_assert_device,
> -       .deassert = ltq_deassert_device,
> -};
> -
> -static struct reset_controller_dev reset_dev = {
> -       .ops                    = &reset_ops,
> -       .owner                  = THIS_MODULE,
> -       .nr_resets              = 32,
> -       .of_reset_n_cells       = 1,
> -};
> -
> -void ltq_rst_init(void)
> -{
> -       reset_dev.of_node = of_find_compatible_node(NULL, NULL,
> -                                               "lantiq,xway-reset");
> -       if (!reset_dev.of_node)
> -               pr_err("Failed to find reset controller node");
> -       else
> -               reset_controller_register(&reset_dev);
> -}
> -
>  static void ltq_machine_restart(char *command)
>  {
>         u32 val = ltq_rcu_r32(RCU_RST_REQ);
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index f4cdfe94b9ec..8962ba44248c 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -27,6 +27,12 @@ config RESET_BERLIN
>         help
>           This enables the reset controller driver for Marvell Berlin SoCs.
>
> +config RESET_LANTIQ_RCU
> +       bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
> +       default SOC_TYPE_XWAY
> +       help
> +         This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
> +
>  config RESET_LPC18XX
>         bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
>         default ARCH_LPC18XX
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 2cd3f6c45165..97b0a844b849 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>  obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
>  obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
> +obj-$(CONFIG_RESET_LANTIQ_RCU) += reset-lantiq-rcu.o
>  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>  obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> diff --git a/drivers/reset/reset-lantiq-rcu.c b/drivers/reset/reset-lantiq-rcu.c
> new file mode 100644
> index 000000000000..6178112ca5b4
> --- /dev/null
> +++ b/drivers/reset/reset-lantiq-rcu.c
> @@ -0,0 +1,231 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
> + *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
> + *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
> +#include <linux/of_platform.h>
> +
> +#define LANTIQ_RCU_RESET_TIMEOUT       1000000
> +
> +struct lantiq_rcu_reset_translation {
> +       int request;
> +       int status;
> +};
> +
> +struct lantiq_rcu_reset_priv {
> +       struct reset_controller_dev rcdev;
> +       struct device *dev;
> +       struct regmap *regmap;
> +       u32 reset_offset;
> +       u32 status_offset;
> +       int trans_number;
> +       struct lantiq_rcu_reset_translation *trans;
> +};
> +
> +static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
> +       struct reset_controller_dev *rcdev)
> +{
> +       return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
> +}
> +
> +static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
> +                            unsigned long id)
> +{
> +       struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
> +       u32 val;
> +       int ret, i;
> +
> +       if (id >= rcdev->nr_resets)
> +               return -EINVAL;
> +
> +       for (i = 0; i < priv->trans_number; i++) {
> +               if (id == priv->trans[i].request) {
> +                       id = priv->trans[i].status;
> +                       break;
> +               }
> +       }
> +
> +       ret = regmap_read(priv->regmap, priv->status_offset, &val);
> +       if (ret)
> +               return ret;
> +
> +       return !!(val & BIT(id));
> +}
> +
> +static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
> +                                  unsigned long id, bool assert)
> +{
> +       struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
> +       u32 val;
> +       int ret, retry = LANTIQ_RCU_RESET_TIMEOUT;
> +
> +       if (id >= rcdev->nr_resets)
> +               return -EINVAL;
> +
> +       if (assert)
> +               val = BIT(id);
> +       else
> +               val = 0;
> +
> +       ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(id),
> +                                val);
> +       if (ret) {
> +               dev_err(priv->dev, "Failed to set reset bit %lu\n", id);
> +               return ret;
> +       }
> +
> +       do {} while (--retry && lantiq_rcu_reset_status(rcdev, id) != assert);
> +       if (!retry) {
> +               dev_err(priv->dev, "Failed to %s bit %lu\n",
> +                       assert ? "assert" : "deassert", id);
> +               return -EIO;
> +       }
> +
> +       return 0;
> +}
> +
> +static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
> +                            unsigned long id)
> +{
> +       return lantiq_rcu_reset_update(rcdev, id, true);
> +}
> +
> +static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
> +                              unsigned long id)
> +{
> +       return lantiq_rcu_reset_update(rcdev, id, false);
> +}
> +
> +static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
> +                           unsigned long id)
> +{
> +       int ret;
> +
> +       ret = lantiq_rcu_reset_assert(rcdev, id);
> +       if (ret)
> +               return ret;
> +
> +       return lantiq_rcu_reset_deassert(rcdev, id);
> +}
> +
> +static struct reset_control_ops lantiq_rcu_reset_ops = {
> +       .assert = lantiq_rcu_reset_assert,
> +       .deassert = lantiq_rcu_reset_deassert,
> +       .status = lantiq_rcu_reset_status,
> +       .reset  = lantiq_rcu_reset_reset,
> +};
> +
> +static int lantiq_rcu_reset_of_probe(struct platform_device *pdev,
> +                              struct lantiq_rcu_reset_priv *priv)
> +{
> +       struct device_node *np = pdev->dev.of_node;
> +       int cnt, i, ret;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(np,
> +                                                       "lantiq,rcu-syscon");
> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
> +               return PTR_ERR(priv->regmap);
> +       }
> +
> +       if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
> +               &priv->reset_offset)) {
> +               dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
> +               return -EINVAL;
> +       }
> +
> +       if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 2,
> +               &priv->status_offset)) {
> +               dev_err(&pdev->dev, "Failed to get RCU status offset\n");
> +               return -EINVAL;
> +       }
> +
> +       cnt = of_property_count_elems_of_size(np, "reset-request", sizeof(u32));
> +       if (cnt <= 0)
> +               return 0;
> +
> +       priv->trans = devm_kmalloc_array(&pdev->dev, cnt, sizeof(*priv->trans),
> +                                        GFP_KERNEL);
> +       if (!priv->trans)
> +               return -ENOMEM;
> +
> +       for (i = 0; i < cnt; i++) {
> +               ret = of_property_read_u32_index(np, "reset-request", i,
> +                                                &priv->trans[i].request);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Failed to get reset-request at index %i\n",
> +                               i);
> +                       return ret;
> +               }
> +               ret = of_property_read_u32_index(np, "reset-status", i,
> +                                                &priv->trans[i].status);
> +               if (ret) {
> +                       dev_err(&pdev->dev,
> +                               "Failed to get reset-status at index %i\n",
> +                               i);
> +                       return ret;
> +               }
> +       }
> +       priv->trans_number = cnt;
> +
> +       return 0;
> +}
> +
> +static int lantiq_rcu_reset_probe(struct platform_device *pdev)
> +{
> +       struct lantiq_rcu_reset_priv *priv;
> +       int err;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = &pdev->dev;
> +       platform_set_drvdata(pdev, priv);
> +
> +       err = lantiq_rcu_reset_of_probe(pdev, priv);
> +       if (err)
> +               return err;
> +
> +       priv->rcdev.ops = &lantiq_rcu_reset_ops;
> +       priv->rcdev.owner = THIS_MODULE;
> +       priv->rcdev.of_node = pdev->dev.of_node;
> +       priv->rcdev.of_reset_n_cells = 1;
> +       priv->rcdev.nr_resets = 32;
> +
> +       err = reset_controller_register(&priv->rcdev);
> +       if (err)
> +               return err;
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
> +       { .compatible = "lantiq,rcu-reset", },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
> +
> +static struct platform_driver lantiq_rcu_reset_driver = {
> +       .probe  = lantiq_rcu_reset_probe,
> +       .driver = {
> +               .name           = "lantiq-rcu-reset",
> +               .of_match_table = lantiq_rcu_reset_dt_ids,
> +       },
> +};
> +module_platform_driver(lantiq_rcu_reset_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.11.0
>

Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
you should probably send this patch to the PHY maintainer as well
(Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>)

> ---
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>  6 files changed, 405 insertions(+), 55 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> new file mode 100644
> index 000000000000..0ec9f790b6e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> @@ -0,0 +1,59 @@
> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
> +===========================================
> +
> +This binding describes the USB PHY hardware provided by the RCU module on the
> +Lantiq XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible           : Should be one of
> +                               "lantiq,ase-rcu-usb2-phy"
> +                               "lantiq,danube-rcu-usb2-phy"
> +                               "lantiq,xrx100-rcu-usb2-phy"
> +                               "lantiq,xrx200-rcu-usb2-phy"
> +                               "lantiq,xrx300-rcu-usb2-phy"
> +- lantiq,rcu-syscon    : A phandle to the RCU module and the offsets to the
> +                         USB PHY configuration and USB MAC registers.
> +- address-cells                : should be 1
> +- size-cells           : should be 0
> +- phy-cells            : from the generic PHY bindings, must be 1
> +
> +Optional properties (controller (parent) node):
> +- vbus-gpio            : References a GPIO which enables VBUS all given USB
> +                         ports.
the PHY framework already handles this if you wrap the GPIO in a
"regulator-fixed" node, see [0] how to define a fixed regulator with a
GPIO (the regulator in this example has two states: off = 0V and on =
5V, probably exactly what you need) and [1] how to pass it to the PHY
(phy-core.c handles this already, no driver specific code needed)

> +
> +Required nodes         :  A sub-node is required for each USB PHY port.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (port (child) node):
> +- reg          : The ID of the USB port, usually 0 or 1.
> +- clocks       : References to the (PMU) "ctrl" and "phy" clk gates.
> +- clock-names  : Must be one of the following:
> +                       "ctrl"
> +                       "phy"
> +- resets       : References to the RCU USB configuration reset bits.
> +- reset-names  : Must be one of the following:
> +                       "analog-config" (optional)
> +                       "statemachine-soft" (optional)
> +
> +Optional properties (port (child) node):
> +- vbus-gpio    : References a GPIO which enables VBUS for the USB port.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the USB PHYs on an xRX200 SoC:
> +       usb_phys0: rcu-usb2-phy@0 {
> +               compatible      = "lantiq,xrx200-rcu-usb2-phy";
> +               reg = <0>;
> +
> +               lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +               clocks = <&pmu PMU_GATE_USB0_CTRL>,
> +                        <&pmu PMU_GATE_USB0_PHY>;
> +               clock-names = "ctrl", "phy";
> +               vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
> +               resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +               reset-names = "phy", "ctrl";
> +               #phy-cells = <0>;
> +       };
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 3f30fb81a50f..5aec1f54275b 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
could these arch/mips/lantiq/xway/reset.c changes to into PATCH #3 as well?

> @@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
>         unreachable();
>  }
>
> -static void ltq_usb_init(void)
> -{
> -       /* Power for USB cores 1 & 2 */
> -       ltq_pmu_enable(PMU_AHBM);
> -       ltq_pmu_enable(PMU_USB0);
> -       ltq_pmu_enable(PMU_USB1);
> -
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
> -
> -       /* Enable USB PHY power for cores 1 & 2 */
> -       ltq_pmu_enable(PMU_USB0_P);
> -       ltq_pmu_enable(PMU_USB1_P);
> -
> -       /* Configure cores to host mode */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB2CFG);
> -
> -       /* Select DMA endianness (Host-endian: big-endian) */
> -       ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
> -
> -       /* Hard reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
> -
> -       /* Soft reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
> -}
> -
>  static int __init mips_reboot_setup(void)
>  {
>         struct resource res;
> @@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
>         if (!ltq_rcu_membase)
>                 panic("Failed to remap core memory");
>
> -       if (of_machine_is_compatible("lantiq,ar9") ||
> -           of_machine_is_compatible("lantiq,vr9"))
> -               ltq_usb_init();
> -
>         _machine_restart = ltq_machine_restart;
>         _machine_halt = ltq_machine_halt;
>         pm_power_off = ltq_machine_power_off;
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 5764d3ddce69..18725f2d5b67 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
>
>         if (of_machine_is_compatible("lantiq,grx390") ||
>             of_machine_is_compatible("lantiq,ar10")) {
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
>                 /* rc 0 */
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
>                 else
>                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
>                                                 CLOCK_133M, CLOCK_133M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
>                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
>                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
> @@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,vr9")) {
>                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
>                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
> -               clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
>                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,ar9")) {
>                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
>                                 ltq_ar9_fpi_hz(), CLOCK_250M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
>                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
>                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
> @@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
>         } else {
>                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
>                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
>                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
>                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 005cadb7a3f8..dbb450e3ba04 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
>           Enable this to support the Broadcom Cygnus PCIe PHY.
>           If unsure, say N.
>
> +config PHY_LANTIQ_RCU_USB2
> +       tristate "Lantiq XWAY SoC RCU based USB PHY"
> +       depends on SOC_TYPE_XWAY
> +       depends on OF
> +       select GENERIC_PHY
> +       help
> +         Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
> +
>  source "drivers/phy/tegra/Kconfig"
>
>  config PHY_NS2_PCIE
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index dd8f3b5d2918..52631f5ac470 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210)            += phy-tusb1210.o
>  obj-$(CONFIG_PHY_BRCM_SATA)            += phy-brcm-sata.o
>  obj-$(CONFIG_PHY_PISTACHIO_USB)                += phy-pistachio-usb.o
>  obj-$(CONFIG_PHY_CYGNUS_PCIE)          += phy-bcm-cygnus-pcie.o
> +obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)      += phy-lantiq-rcu-usb2.o
>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>  obj-$(CONFIG_PHY_NS2_PCIE)             += phy-bcm-ns2-pcie.o
>  obj-$(CONFIG_PHY_MESON8B_USB2)         += phy-meson8b-usb2.o
> diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
> new file mode 100644
> index 000000000000..9bff42afd256
> --- /dev/null
> +++ b/drivers/phy/phy-lantiq-rcu-usb2.c
> @@ -0,0 +1,325 @@
> +/*
> + * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
> + *
> + * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> + * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#define MAX_VBUS_GPIO          2
> +
> +/* Transmitter HS Pre-Emphasis Enable */
> +#define RCU_CFG1_TX_PEE                BIT(0)
> +/* Disconnect Threshold */
> +#define RCU_CFG1_DIS_THR_MASK  0x00038000
> +#define RCU_CFG1_DIS_THR_SHIFT 15
> +
> +struct ltq_rcu_usb2_bits {
> +       u8 hostmode;
> +       u8 slave_endianness;
> +       u8 host_endianness;
> +       bool have_ana_cfg;
> +};
> +
> +struct ltq_rcu_usb2_priv {
> +       struct regmap                   *regmap;
> +       u32                             phy_reg_offset;
> +       u32                             ana_cfg1_reg_offset;
> +       const struct ltq_rcu_usb2_bits  *reg_bits;
> +       struct device                   *dev;
> +       struct gpio_desc                *gpiod_vbus[MAX_VBUS_GPIO];
> +       struct phy                      *phy;
> +       struct clk                      *ctrl_gate_clk;
> +       struct clk                      *phy_gate_clk;
> +       struct reset_control            *ctrl_reset;
> +       struct reset_control            *phy_reset;
> +};
> +
> +static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 17,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = true,
> +};
> +
> +static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
> +       {
> +               .compatible = "lantiq,ase-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,danube-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx100-rcu-usb2-phy",
> +               .data = &xrx100_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx200-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx300-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
> +
> +static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
> +                                               int value)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++)
> +               if (!IS_ERR_OR_NULL(gpiods[i]))
> +                       gpiod_set_value(gpiods[i], value);
> +}
> +
> +static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       if (priv->phy_reset)
> +               reset_control_deassert(priv->phy_reset);
> +
> +       /* enable the port-specific VBUS GPIOs if available */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       /*
> +        * only disable the port-specific VBUS GPIO here (if available), the
> +        * shared VBUS GPIO might still be used by another port
> +        */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +
> +       return 0;
> +}
> +
> +static struct phy_ops ltq_rcu_usb2_phy_ops = {
> +       .power_on       = ltq_rcu_usb2_phy_power_on,
> +       .power_off      = ltq_rcu_usb2_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
> +
> +       /* Power on the USB core. */
> +       if (clk_prepare_enable(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "failed to enable CTRL gate\n");
> +               return;
> +       }
> +
> +       /*
> +        * Power on the USB PHY. We have to do it early because
> +        * otherwise the second core won't turn on properly.
> +        */
> +       if (clk_prepare_enable(priv->phy_gate_clk)) {
> +               dev_err(dev, "failed to enable PHY gate\n");
> +               return;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
> +       }
> +
> +       /* Configure core to host mode */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +                          BIT(priv->reg_bits->hostmode), 0);
> +
> +       /* Select DMA endianness (Host-endian: big-endian) */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->slave_endianness), 0);
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->host_endianness),
> +               BIT(priv->reg_bits->host_endianness));
> +
> +       /* Reset USB core throgh reset controller */
> +       reset_control_deassert(priv->ctrl_reset);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +}
> +
> +static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
> +                                         struct gpio_desc **gpios)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++) {
> +               gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
> +                                                        GPIOD_OUT_LOW);
> +               if (IS_ERR(gpios[i]))
> +                       return PTR_ERR(gpios[i]);
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
> +                                   struct ltq_rcu_usb2_priv *priv)
> +{
> +       struct device *dev = priv->dev;
> +       const struct of_device_id *match =
> +               of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
> +       int ret;
> +
> +       if (!match) {
> +               dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->reg_bits = match->data;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
> +                                                      "lantiq,rcu-syscon");
> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(dev, "Failed to lookup RCU regmap\n");
> +               return PTR_ERR(priv->regmap);
> +       }
> +
> +       ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
> +       if (ret) {
> +               dev_err(dev, "failed to request shared USB VBUS GPIO\n");
> +               return ret;
> +       }
> +
> +       priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "Unable to get USB ctrl gate clk\n");
> +               return PTR_ERR(priv->ctrl_gate_clk);
> +       }
> +
> +       priv->phy_gate_clk = devm_clk_get(dev, "phy");
> +       if (IS_ERR(priv->phy_gate_clk)) {
> +               dev_err(dev, "Unable to get USB phy gate clk\n");
> +               return PTR_ERR(priv->phy_gate_clk);
> +       }
> +
> +       priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_reset)) {
> +               dev_err(dev, "failed to get 'ctrl' reset\n");
> +               return PTR_ERR(priv->ctrl_reset);
> +       }
> +
> +       priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
> +       if (IS_ERR(priv->phy_reset)) {
> +               if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
> +                       return PTR_ERR(priv->phy_reset);
> +               priv->phy_reset = NULL;
> +       }
> +
> +       ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
> +                                        &priv->phy_reg_offset);
> +       if (ret) {
> +               dev_err(dev, "Failed to get RCU PHY reg offset\n");
> +               return ret;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
> +                                                2, &priv->ana_cfg1_reg_offset);
> +               if (ret) {
> +                       dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
> +{
> +       struct device_node *child, *np = pdev->dev.of_node;
> +       struct ltq_rcu_usb2_priv *priv;
> +       struct phy_provider *provider;
> +       int ret;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
> +                                      GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = &pdev->dev;
> +       dev_set_drvdata(priv->dev, priv);
> +
> +       ret = ltq_rcu_usb2_of_probe(np, priv);
> +       if (ret)
> +               return ret;
> +
> +       priv->phy = devm_phy_create(&pdev->dev, child,
> +                                        &ltq_rcu_usb2_phy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(&pdev->dev, "failed to create PHY\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       ltq_rcu_usb2_start_cores(pdev);
> +
> +       provider = devm_of_phy_provider_register(&pdev->dev,
> +                                                of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver ltq_rcu_usb2_phy_driver = {
> +       .probe  = ltq_rcu_usb2_phy_probe,
> +       .driver = {
> +               .name   = "lantiq-rcu-usb2-phy",
> +               .of_match_table = ltq_rcu_usb2_phy_of_match,
> +       }
> +};
> +module_platform_driver(ltq_rcu_usb2_phy_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
> +MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.11.0
>

[0] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L67
[1] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L133
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Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
you should probably send this patch to the PHY maintainer as well
(Kishon Vijay Abraham I <kishon@ti.com>)

> ---
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>  6 files changed, 405 insertions(+), 55 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> new file mode 100644
> index 000000000000..0ec9f790b6e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> @@ -0,0 +1,59 @@
> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
> +===========================================
> +
> +This binding describes the USB PHY hardware provided by the RCU module on the
> +Lantiq XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible           : Should be one of
> +                               "lantiq,ase-rcu-usb2-phy"
> +                               "lantiq,danube-rcu-usb2-phy"
> +                               "lantiq,xrx100-rcu-usb2-phy"
> +                               "lantiq,xrx200-rcu-usb2-phy"
> +                               "lantiq,xrx300-rcu-usb2-phy"
> +- lantiq,rcu-syscon    : A phandle to the RCU module and the offsets to the
> +                         USB PHY configuration and USB MAC registers.
> +- address-cells                : should be 1
> +- size-cells           : should be 0
> +- phy-cells            : from the generic PHY bindings, must be 1
> +
> +Optional properties (controller (parent) node):
> +- vbus-gpio            : References a GPIO which enables VBUS all given USB
> +                         ports.
the PHY framework already handles this if you wrap the GPIO in a
"regulator-fixed" node, see [0] how to define a fixed regulator with a
GPIO (the regulator in this example has two states: off = 0V and on =
5V, probably exactly what you need) and [1] how to pass it to the PHY
(phy-core.c handles this already, no driver specific code needed)

> +
> +Required nodes         :  A sub-node is required for each USB PHY port.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (port (child) node):
> +- reg          : The ID of the USB port, usually 0 or 1.
> +- clocks       : References to the (PMU) "ctrl" and "phy" clk gates.
> +- clock-names  : Must be one of the following:
> +                       "ctrl"
> +                       "phy"
> +- resets       : References to the RCU USB configuration reset bits.
> +- reset-names  : Must be one of the following:
> +                       "analog-config" (optional)
> +                       "statemachine-soft" (optional)
> +
> +Optional properties (port (child) node):
> +- vbus-gpio    : References a GPIO which enables VBUS for the USB port.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the USB PHYs on an xRX200 SoC:
> +       usb_phys0: rcu-usb2-phy@0 {
> +               compatible      = "lantiq,xrx200-rcu-usb2-phy";
> +               reg = <0>;
> +
> +               lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +               clocks = <&pmu PMU_GATE_USB0_CTRL>,
> +                        <&pmu PMU_GATE_USB0_PHY>;
> +               clock-names = "ctrl", "phy";
> +               vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
> +               resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +               reset-names = "phy", "ctrl";
> +               #phy-cells = <0>;
> +       };
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 3f30fb81a50f..5aec1f54275b 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
could these arch/mips/lantiq/xway/reset.c changes to into PATCH #3 as well?

> @@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
>         unreachable();
>  }
>
> -static void ltq_usb_init(void)
> -{
> -       /* Power for USB cores 1 & 2 */
> -       ltq_pmu_enable(PMU_AHBM);
> -       ltq_pmu_enable(PMU_USB0);
> -       ltq_pmu_enable(PMU_USB1);
> -
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
> -
> -       /* Enable USB PHY power for cores 1 & 2 */
> -       ltq_pmu_enable(PMU_USB0_P);
> -       ltq_pmu_enable(PMU_USB1_P);
> -
> -       /* Configure cores to host mode */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB2CFG);
> -
> -       /* Select DMA endianness (Host-endian: big-endian) */
> -       ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
> -
> -       /* Hard reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
> -
> -       /* Soft reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
> -}
> -
>  static int __init mips_reboot_setup(void)
>  {
>         struct resource res;
> @@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
>         if (!ltq_rcu_membase)
>                 panic("Failed to remap core memory");
>
> -       if (of_machine_is_compatible("lantiq,ar9") ||
> -           of_machine_is_compatible("lantiq,vr9"))
> -               ltq_usb_init();
> -
>         _machine_restart = ltq_machine_restart;
>         _machine_halt = ltq_machine_halt;
>         pm_power_off = ltq_machine_power_off;
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 5764d3ddce69..18725f2d5b67 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
>
>         if (of_machine_is_compatible("lantiq,grx390") ||
>             of_machine_is_compatible("lantiq,ar10")) {
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
>                 /* rc 0 */
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
>                 else
>                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
>                                                 CLOCK_133M, CLOCK_133M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
>                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
>                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
> @@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,vr9")) {
>                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
>                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
> -               clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
>                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,ar9")) {
>                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
>                                 ltq_ar9_fpi_hz(), CLOCK_250M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
>                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
>                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
> @@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
>         } else {
>                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
>                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
>                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
>                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 005cadb7a3f8..dbb450e3ba04 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
>           Enable this to support the Broadcom Cygnus PCIe PHY.
>           If unsure, say N.
>
> +config PHY_LANTIQ_RCU_USB2
> +       tristate "Lantiq XWAY SoC RCU based USB PHY"
> +       depends on SOC_TYPE_XWAY
> +       depends on OF
> +       select GENERIC_PHY
> +       help
> +         Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
> +
>  source "drivers/phy/tegra/Kconfig"
>
>  config PHY_NS2_PCIE
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index dd8f3b5d2918..52631f5ac470 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210)            += phy-tusb1210.o
>  obj-$(CONFIG_PHY_BRCM_SATA)            += phy-brcm-sata.o
>  obj-$(CONFIG_PHY_PISTACHIO_USB)                += phy-pistachio-usb.o
>  obj-$(CONFIG_PHY_CYGNUS_PCIE)          += phy-bcm-cygnus-pcie.o
> +obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)      += phy-lantiq-rcu-usb2.o
>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>  obj-$(CONFIG_PHY_NS2_PCIE)             += phy-bcm-ns2-pcie.o
>  obj-$(CONFIG_PHY_MESON8B_USB2)         += phy-meson8b-usb2.o
> diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
> new file mode 100644
> index 000000000000..9bff42afd256
> --- /dev/null
> +++ b/drivers/phy/phy-lantiq-rcu-usb2.c
> @@ -0,0 +1,325 @@
> +/*
> + * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
> + *
> + * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#define MAX_VBUS_GPIO          2
> +
> +/* Transmitter HS Pre-Emphasis Enable */
> +#define RCU_CFG1_TX_PEE                BIT(0)
> +/* Disconnect Threshold */
> +#define RCU_CFG1_DIS_THR_MASK  0x00038000
> +#define RCU_CFG1_DIS_THR_SHIFT 15
> +
> +struct ltq_rcu_usb2_bits {
> +       u8 hostmode;
> +       u8 slave_endianness;
> +       u8 host_endianness;
> +       bool have_ana_cfg;
> +};
> +
> +struct ltq_rcu_usb2_priv {
> +       struct regmap                   *regmap;
> +       u32                             phy_reg_offset;
> +       u32                             ana_cfg1_reg_offset;
> +       const struct ltq_rcu_usb2_bits  *reg_bits;
> +       struct device                   *dev;
> +       struct gpio_desc                *gpiod_vbus[MAX_VBUS_GPIO];
> +       struct phy                      *phy;
> +       struct clk                      *ctrl_gate_clk;
> +       struct clk                      *phy_gate_clk;
> +       struct reset_control            *ctrl_reset;
> +       struct reset_control            *phy_reset;
> +};
> +
> +static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 17,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = true,
> +};
> +
> +static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
> +       {
> +               .compatible = "lantiq,ase-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,danube-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx100-rcu-usb2-phy",
> +               .data = &xrx100_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx200-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx300-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
> +
> +static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
> +                                               int value)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++)
> +               if (!IS_ERR_OR_NULL(gpiods[i]))
> +                       gpiod_set_value(gpiods[i], value);
> +}
> +
> +static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       if (priv->phy_reset)
> +               reset_control_deassert(priv->phy_reset);
> +
> +       /* enable the port-specific VBUS GPIOs if available */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       /*
> +        * only disable the port-specific VBUS GPIO here (if available), the
> +        * shared VBUS GPIO might still be used by another port
> +        */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +
> +       return 0;
> +}
> +
> +static struct phy_ops ltq_rcu_usb2_phy_ops = {
> +       .power_on       = ltq_rcu_usb2_phy_power_on,
> +       .power_off      = ltq_rcu_usb2_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
> +
> +       /* Power on the USB core. */
> +       if (clk_prepare_enable(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "failed to enable CTRL gate\n");
> +               return;
> +       }
> +
> +       /*
> +        * Power on the USB PHY. We have to do it early because
> +        * otherwise the second core won't turn on properly.
> +        */
> +       if (clk_prepare_enable(priv->phy_gate_clk)) {
> +               dev_err(dev, "failed to enable PHY gate\n");
> +               return;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
> +       }
> +
> +       /* Configure core to host mode */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +                          BIT(priv->reg_bits->hostmode), 0);
> +
> +       /* Select DMA endianness (Host-endian: big-endian) */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->slave_endianness), 0);
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->host_endianness),
> +               BIT(priv->reg_bits->host_endianness));
> +
> +       /* Reset USB core throgh reset controller */
> +       reset_control_deassert(priv->ctrl_reset);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +}
> +
> +static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
> +                                         struct gpio_desc **gpios)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++) {
> +               gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
> +                                                        GPIOD_OUT_LOW);
> +               if (IS_ERR(gpios[i]))
> +                       return PTR_ERR(gpios[i]);
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
> +                                   struct ltq_rcu_usb2_priv *priv)
> +{
> +       struct device *dev = priv->dev;
> +       const struct of_device_id *match =
> +               of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
> +       int ret;
> +
> +       if (!match) {
> +               dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->reg_bits = match->data;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
> +                                                      "lantiq,rcu-syscon");
> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(dev, "Failed to lookup RCU regmap\n");
> +               return PTR_ERR(priv->regmap);
> +       }
> +
> +       ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
> +       if (ret) {
> +               dev_err(dev, "failed to request shared USB VBUS GPIO\n");
> +               return ret;
> +       }
> +
> +       priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "Unable to get USB ctrl gate clk\n");
> +               return PTR_ERR(priv->ctrl_gate_clk);
> +       }
> +
> +       priv->phy_gate_clk = devm_clk_get(dev, "phy");
> +       if (IS_ERR(priv->phy_gate_clk)) {
> +               dev_err(dev, "Unable to get USB phy gate clk\n");
> +               return PTR_ERR(priv->phy_gate_clk);
> +       }
> +
> +       priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_reset)) {
> +               dev_err(dev, "failed to get 'ctrl' reset\n");
> +               return PTR_ERR(priv->ctrl_reset);
> +       }
> +
> +       priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
> +       if (IS_ERR(priv->phy_reset)) {
> +               if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
> +                       return PTR_ERR(priv->phy_reset);
> +               priv->phy_reset = NULL;
> +       }
> +
> +       ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
> +                                        &priv->phy_reg_offset);
> +       if (ret) {
> +               dev_err(dev, "Failed to get RCU PHY reg offset\n");
> +               return ret;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
> +                                                2, &priv->ana_cfg1_reg_offset);
> +               if (ret) {
> +                       dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
> +{
> +       struct device_node *child, *np = pdev->dev.of_node;
> +       struct ltq_rcu_usb2_priv *priv;
> +       struct phy_provider *provider;
> +       int ret;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
> +                                      GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = &pdev->dev;
> +       dev_set_drvdata(priv->dev, priv);
> +
> +       ret = ltq_rcu_usb2_of_probe(np, priv);
> +       if (ret)
> +               return ret;
> +
> +       priv->phy = devm_phy_create(&pdev->dev, child,
> +                                        &ltq_rcu_usb2_phy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(&pdev->dev, "failed to create PHY\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       ltq_rcu_usb2_start_cores(pdev);
> +
> +       provider = devm_of_phy_provider_register(&pdev->dev,
> +                                                of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver ltq_rcu_usb2_phy_driver = {
> +       .probe  = ltq_rcu_usb2_phy_probe,
> +       .driver = {
> +               .name   = "lantiq-rcu-usb2-phy",
> +               .of_match_table = ltq_rcu_usb2_phy_of_match,
> +       }
> +};
> +module_platform_driver(ltq_rcu_usb2_phy_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.11.0
>

[0] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L67
[1] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L133

Re: [PATCH 13/13] MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> The RCU register are now access through separates drivers. remove the
> last peaces of the old implementation.
s/peaces/pieces/

you should probably mention that arch/mips/kernel/reset.c handles the
ltq_machine_halt and ltq_machine_power_off code, while
ltq_machine_restart (setting some reset bits) can be replaced with
"syscon-reboot"

apart from that: great to see that this gets some love! :)

> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  arch/mips/lantiq/Kconfig       |   1 +
>  arch/mips/lantiq/xway/Makefile |   2 +-
>  arch/mips/lantiq/xway/reset.c  | 157 -----------------------------------------
>  3 files changed, 2 insertions(+), 158 deletions(-)
>  delete mode 100644 arch/mips/lantiq/xway/reset.c
>
> diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
> index f5db4a426568..35bc69b78268 100644
> --- a/arch/mips/lantiq/Kconfig
> +++ b/arch/mips/lantiq/Kconfig
> @@ -18,6 +18,7 @@ config SOC_XWAY
>         select SOC_TYPE_XWAY
>         select HW_HAS_PCI
>         select MFD_SYSCON
> +       select MFD_CORE
>
>  config SOC_FALCON
>         bool "FALCON"
> diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
> index 6daf3149e7ca..fbb0747c70b7 100644
> --- a/arch/mips/lantiq/xway/Makefile
> +++ b/arch/mips/lantiq/xway/Makefile
> @@ -1,3 +1,3 @@
> -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
> +obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
>
>  obj-y += vmmc.o
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> deleted file mode 100644
> index 5aec1f54275b..000000000000
> --- a/arch/mips/lantiq/xway/reset.c
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -/*
> - *  This program is free software; you can redistribute it and/or modify it
> - *  under the terms of the GNU General Public License version 2 as published
> - *  by the Free Software Foundation.
> - *
> - *  Copyright (C) 2010 John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
> - *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
> - */
> -
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/ioport.h>
> -#include <linux/pm.h>
> -#include <linux/export.h>
> -#include <linux/delay.h>
> -#include <linux/of_address.h>
> -#include <linux/of_platform.h>
> -#include <linux/reset-controller.h>
> -
> -#include <asm/reboot.h>
> -
> -#include <lantiq_soc.h>
> -
> -#include "../prom.h"
> -
> -/* reset request register */
> -#define RCU_RST_REQ            0x0010
> -/* reset status register */
> -#define RCU_RST_STAT           0x0014
> -
> -/* xbar BE flag */
> -#define RCU_AHB_ENDIAN          0x004C
> -#define RCU_VR9_BE_AHB1S        0x00000008
> -
> -/* reboot bit */
> -#define RCU_RD_GPHY0_XRX200    BIT(31)
> -#define RCU_RD_SRST            BIT(30)
> -#define RCU_RD_GPHY1_XRX200    BIT(29)
> -
> -/* reset cause */
> -#define RCU_STAT_SHIFT         26
> -/* boot selection */
> -#define RCU_BOOT_SEL(x)                ((x >> 18) & 0x7)
> -#define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
> -
> -/* dwc2 USB configuration registers */
> -#define RCU_USB1CFG            0x0018
> -#define RCU_USB2CFG            0x0034
> -
> -/* USB DMA endianness bits */
> -#define RCU_USBCFG_HDSEL_BIT   BIT(11)
> -#define RCU_USBCFG_HOST_END_BIT        BIT(10)
> -#define RCU_USBCFG_SLV_END_BIT BIT(9)
> -
> -/* USB reset bits */
> -#define RCU_USBRESET           0x0010
> -
> -#define USBRESET_BIT           BIT(4)
> -
> -#define RCU_USBRESET2          0x0048
> -
> -#define USB1RESET_BIT          BIT(4)
> -#define USB2RESET_BIT          BIT(5)
> -
> -#define RCU_CFG1A              0x0038
> -#define RCU_CFG1B              0x003C
> -
> -/* USB PMU devices */
> -#define PMU_AHBM               BIT(15)
> -#define PMU_USB0               BIT(6)
> -#define PMU_USB1               BIT(27)
> -
> -/* USB PHY PMU devices */
> -#define PMU_USB0_P             BIT(0)
> -#define PMU_USB1_P             BIT(26)
> -
> -/* remapped base addr of the reset control unit */
> -static void __iomem *ltq_rcu_membase;
> -static struct device_node *ltq_rcu_np;
> -static DEFINE_SPINLOCK(ltq_rcu_lock);
> -
> -static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
> -{
> -       ltq_w32(val, ltq_rcu_membase + reg_off);
> -}
> -
> -static uint32_t ltq_rcu_r32(uint32_t reg_off)
> -{
> -       return ltq_r32(ltq_rcu_membase + reg_off);
> -}
> -
> -static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
> -{
> -       unsigned long flags;
> -
> -       spin_lock_irqsave(&ltq_rcu_lock, flags);
> -       ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
> -       spin_unlock_irqrestore(&ltq_rcu_lock, flags);
> -}
> -
> -static void ltq_machine_restart(char *command)
> -{
> -       u32 val = ltq_rcu_r32(RCU_RST_REQ);
> -
> -       if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
> -               val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
> -
> -       val |= RCU_RD_SRST;
> -
> -       local_irq_disable();
> -       ltq_rcu_w32(val, RCU_RST_REQ);
> -       unreachable();
> -}
> -
> -static void ltq_machine_halt(void)
> -{
> -       local_irq_disable();
> -       unreachable();
> -}
> -
> -static void ltq_machine_power_off(void)
> -{
> -       local_irq_disable();
> -       unreachable();
> -}
> -
> -static int __init mips_reboot_setup(void)
> -{
> -       struct resource res;
> -
> -       ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
> -       if (!ltq_rcu_np)
> -               ltq_rcu_np = of_find_compatible_node(NULL, NULL,
> -                                                       "lantiq,rcu-xrx200");
> -
> -       /* check if all the reset register range is available */
> -       if (!ltq_rcu_np)
> -               panic("Failed to load reset resources from devicetree");
> -
> -       if (of_address_to_resource(ltq_rcu_np, 0, &res))
> -               panic("Failed to get rcu memory range");
> -
> -       if (!request_mem_region(res.start, resource_size(&res), res.name))
> -               pr_err("Failed to request rcu memory");
> -
> -       ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
> -       if (!ltq_rcu_membase)
> -               panic("Failed to remap core memory");
> -
> -       _machine_restart = ltq_machine_restart;
> -       _machine_halt = ltq_machine_halt;
> -       pm_power_off = ltq_machine_power_off;
> -
> -       return 0;
> -}
> -
> -arch_initcall(mips_reboot_setup);
> --
> 2.11.0
>
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Re: [PATCH 13/13] MIPS: lantiq: Remove the arch/mips/lantiq/xway/reset.c implementation

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> The RCU register are now access through separates drivers. remove the
> last peaces of the old implementation.
s/peaces/pieces/

you should probably mention that arch/mips/kernel/reset.c handles the
ltq_machine_halt and ltq_machine_power_off code, while
ltq_machine_restart (setting some reset bits) can be replaced with
"syscon-reboot"

apart from that: great to see that this gets some love! :)

> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  arch/mips/lantiq/Kconfig       |   1 +
>  arch/mips/lantiq/xway/Makefile |   2 +-
>  arch/mips/lantiq/xway/reset.c  | 157 -----------------------------------------
>  3 files changed, 2 insertions(+), 158 deletions(-)
>  delete mode 100644 arch/mips/lantiq/xway/reset.c
>
> diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
> index f5db4a426568..35bc69b78268 100644
> --- a/arch/mips/lantiq/Kconfig
> +++ b/arch/mips/lantiq/Kconfig
> @@ -18,6 +18,7 @@ config SOC_XWAY
>         select SOC_TYPE_XWAY
>         select HW_HAS_PCI
>         select MFD_SYSCON
> +       select MFD_CORE
>
>  config SOC_FALCON
>         bool "FALCON"
> diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
> index 6daf3149e7ca..fbb0747c70b7 100644
> --- a/arch/mips/lantiq/xway/Makefile
> +++ b/arch/mips/lantiq/xway/Makefile
> @@ -1,3 +1,3 @@
> -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
> +obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
>
>  obj-y += vmmc.o
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> deleted file mode 100644
> index 5aec1f54275b..000000000000
> --- a/arch/mips/lantiq/xway/reset.c
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -/*
> - *  This program is free software; you can redistribute it and/or modify it
> - *  under the terms of the GNU General Public License version 2 as published
> - *  by the Free Software Foundation.
> - *
> - *  Copyright (C) 2010 John Crispin <john@phrozen.org>
> - *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
> - */
> -
> -#include <linux/init.h>
> -#include <linux/io.h>
> -#include <linux/ioport.h>
> -#include <linux/pm.h>
> -#include <linux/export.h>
> -#include <linux/delay.h>
> -#include <linux/of_address.h>
> -#include <linux/of_platform.h>
> -#include <linux/reset-controller.h>
> -
> -#include <asm/reboot.h>
> -
> -#include <lantiq_soc.h>
> -
> -#include "../prom.h"
> -
> -/* reset request register */
> -#define RCU_RST_REQ            0x0010
> -/* reset status register */
> -#define RCU_RST_STAT           0x0014
> -
> -/* xbar BE flag */
> -#define RCU_AHB_ENDIAN          0x004C
> -#define RCU_VR9_BE_AHB1S        0x00000008
> -
> -/* reboot bit */
> -#define RCU_RD_GPHY0_XRX200    BIT(31)
> -#define RCU_RD_SRST            BIT(30)
> -#define RCU_RD_GPHY1_XRX200    BIT(29)
> -
> -/* reset cause */
> -#define RCU_STAT_SHIFT         26
> -/* boot selection */
> -#define RCU_BOOT_SEL(x)                ((x >> 18) & 0x7)
> -#define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
> -
> -/* dwc2 USB configuration registers */
> -#define RCU_USB1CFG            0x0018
> -#define RCU_USB2CFG            0x0034
> -
> -/* USB DMA endianness bits */
> -#define RCU_USBCFG_HDSEL_BIT   BIT(11)
> -#define RCU_USBCFG_HOST_END_BIT        BIT(10)
> -#define RCU_USBCFG_SLV_END_BIT BIT(9)
> -
> -/* USB reset bits */
> -#define RCU_USBRESET           0x0010
> -
> -#define USBRESET_BIT           BIT(4)
> -
> -#define RCU_USBRESET2          0x0048
> -
> -#define USB1RESET_BIT          BIT(4)
> -#define USB2RESET_BIT          BIT(5)
> -
> -#define RCU_CFG1A              0x0038
> -#define RCU_CFG1B              0x003C
> -
> -/* USB PMU devices */
> -#define PMU_AHBM               BIT(15)
> -#define PMU_USB0               BIT(6)
> -#define PMU_USB1               BIT(27)
> -
> -/* USB PHY PMU devices */
> -#define PMU_USB0_P             BIT(0)
> -#define PMU_USB1_P             BIT(26)
> -
> -/* remapped base addr of the reset control unit */
> -static void __iomem *ltq_rcu_membase;
> -static struct device_node *ltq_rcu_np;
> -static DEFINE_SPINLOCK(ltq_rcu_lock);
> -
> -static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
> -{
> -       ltq_w32(val, ltq_rcu_membase + reg_off);
> -}
> -
> -static uint32_t ltq_rcu_r32(uint32_t reg_off)
> -{
> -       return ltq_r32(ltq_rcu_membase + reg_off);
> -}
> -
> -static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
> -{
> -       unsigned long flags;
> -
> -       spin_lock_irqsave(&ltq_rcu_lock, flags);
> -       ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
> -       spin_unlock_irqrestore(&ltq_rcu_lock, flags);
> -}
> -
> -static void ltq_machine_restart(char *command)
> -{
> -       u32 val = ltq_rcu_r32(RCU_RST_REQ);
> -
> -       if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
> -               val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
> -
> -       val |= RCU_RD_SRST;
> -
> -       local_irq_disable();
> -       ltq_rcu_w32(val, RCU_RST_REQ);
> -       unreachable();
> -}
> -
> -static void ltq_machine_halt(void)
> -{
> -       local_irq_disable();
> -       unreachable();
> -}
> -
> -static void ltq_machine_power_off(void)
> -{
> -       local_irq_disable();
> -       unreachable();
> -}
> -
> -static int __init mips_reboot_setup(void)
> -{
> -       struct resource res;
> -
> -       ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
> -       if (!ltq_rcu_np)
> -               ltq_rcu_np = of_find_compatible_node(NULL, NULL,
> -                                                       "lantiq,rcu-xrx200");
> -
> -       /* check if all the reset register range is available */
> -       if (!ltq_rcu_np)
> -               panic("Failed to load reset resources from devicetree");
> -
> -       if (of_address_to_resource(ltq_rcu_np, 0, &res))
> -               panic("Failed to get rcu memory range");
> -
> -       if (!request_mem_region(res.start, resource_size(&res), res.name))
> -               pr_err("Failed to request rcu memory");
> -
> -       ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
> -       if (!ltq_rcu_membase)
> -               panic("Failed to remap core memory");
> -
> -       _machine_restart = ltq_machine_restart;
> -       _machine_halt = ltq_machine_halt;
> -       pm_power_off = ltq_machine_power_off;
> -
> -       return 0;
> -}
> -
> -arch_initcall(mips_reboot_setup);
> --
> 2.11.0
>

Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:35PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> 
> This allows using the xbar driver on ARX300 based SoCs which require the
> same xbar setup as the xRX200 chipsets because the xbar driver
> initialization is not guarded by an xRX200 specific
> of_machine_is_compatible condition anymore. Additionally the new driver
> takes a syscon phandle to configure the XBAR endianness bits in RCU
> (before this was done in arch/mips/lantiq/xway/reset.c and also
> guarded by an xRX200 specific if-statement).
> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>  MAINTAINERS                                        |   1 +
>  arch/mips/lantiq/xway/reset.c                      |   4 -
>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/lantiq/Makefile                        |   1 +
>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>  7 files changed, 125 insertions(+), 45 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>  create mode 100644 drivers/soc/lantiq/Makefile
>  create mode 100644 drivers/soc/lantiq/xbar.c
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> new file mode 100644
> index 000000000000..86e53ff3b0d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> @@ -0,0 +1,22 @@
> +Lantiq XWAY SoC XBAR binding
> +============================
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible	: Should be "lantiq,xbar-xway"

This compatible is already in use so it is fine, but you should also 
have per SoC compatible strings.

> +- reg		: The address and length of the XBAR registers
> +
> +Optional properties:
> +- lantiq,rcu-syscon	: A phandle and offset to the endianness configuration
> +			  registers in the RCU module
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the XBAR on the xRX200 SoCs:
> +	xbar0: xbar@400000 {
> +		compatible = "lantiq,xbar-xway";
> +		reg = <0x400000 0x1000>;
> +		big-endian;
> +		lantiq,rcu-syscon = <&rcu0 0x4c>;
> +	};
--
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Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:35PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> This allows using the xbar driver on ARX300 based SoCs which require the
> same xbar setup as the xRX200 chipsets because the xbar driver
> initialization is not guarded by an xRX200 specific
> of_machine_is_compatible condition anymore. Additionally the new driver
> takes a syscon phandle to configure the XBAR endianness bits in RCU
> (before this was done in arch/mips/lantiq/xway/reset.c and also
> guarded by an xRX200 specific if-statement).
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>  MAINTAINERS                                        |   1 +
>  arch/mips/lantiq/xway/reset.c                      |   4 -
>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/lantiq/Makefile                        |   1 +
>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>  7 files changed, 125 insertions(+), 45 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>  create mode 100644 drivers/soc/lantiq/Makefile
>  create mode 100644 drivers/soc/lantiq/xbar.c
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> new file mode 100644
> index 000000000000..86e53ff3b0d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> @@ -0,0 +1,22 @@
> +Lantiq XWAY SoC XBAR binding
> +============================
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible	: Should be "lantiq,xbar-xway"

This compatible is already in use so it is fine, but you should also 
have per SoC compatible strings.

> +- reg		: The address and length of the XBAR registers
> +
> +Optional properties:
> +- lantiq,rcu-syscon	: A phandle and offset to the endianness configuration
> +			  registers in the RCU module
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the XBAR on the xRX200 SoCs:
> +	xbar0: xbar@400000 {
> +		compatible = "lantiq,xbar-xway";
> +		reg = <0x400000 0x1000>;
> +		big-endian;
> +		lantiq,rcu-syscon = <&rcu0 0x4c>;
> +	};

Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:37PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> 
> The reset controllers (on xRX200 and newer SoCs have two of them) are
> provided by the RCU module. This was initially implemented as a simple
> reset controller. However, the RCU module provides more functionality
> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
> The old reset controller driver implementation from
> arch/mips/lantiq/xway/reset.c did not honor this fact.
> 
> For some devices the request and the status bits are different.
> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>  drivers/reset/Kconfig                              |   6 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>  5 files changed, 281 insertions(+), 68 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
> 
> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> new file mode 100644
> index 000000000000..7f097d16bbb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> @@ -0,0 +1,43 @@
> +Lantiq XWAY SoC RCU reset controller binding
> +============================================
> +
> +This binding describes a reset-controller found on the RCU module on Lantiq
> +XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible		: Should be "lantiq,rcu-reset"
> +- lantiq,rcu-syscon	: A phandle to the RCU syscon, the reset register
> +			  offset and the status register offset.
> +- #reset-cells		: Specifies the number of cells needed to encode the
> +			  reset line, should be 1.
> +
> +Optional properties:
> +- reset-status		: The request status bit. For some bits the request bit
> +			  and the status bit are different. This is depending
> +			  on the SoC. If the reset-status bit does not match
> +			  the reset-request bit, put the reset number into the
> +			  reset-request property and the status bit at the same
> +			  index into the reset-status property. If no
> +			  reset-request bit is given here, the driver assume
> +			  status and request bit are the same.
> +- reset-request		: The reset request bit, to map it to the reset-status
> +			  bit.

These should either be implied by SoC specific compatible or be made 
part of the reset cells. In the latter case, you still need the SoC 
specific compatible.

> +-------------------------------------------------------------------------------
> +Example for the reset-controllers on the xRX200 SoCs:
> +	rcu_reset0: rcu_reset {
> +		compatible = "lantiq,rcu-reset";
> +		lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
> +		#reset-cells = <1>;
> +		reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
> +		reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
> +	};
> +
> +	rcu_reset1: rcu_reset {
> +		compatible = "lantiq,rcu-reset";

These 2 blocks are identical? Given different registers sizes, I'd say 
not. So they should have different compatible strings.

> +		lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
> +		#reset-cells = <1>;
> +	};
--
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Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:37PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> The reset controllers (on xRX200 and newer SoCs have two of them) are
> provided by the RCU module. This was initially implemented as a simple
> reset controller. However, the RCU module provides more functionality
> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
> The old reset controller driver implementation from
> arch/mips/lantiq/xway/reset.c did not honor this fact.
> 
> For some devices the request and the status bits are different.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>  drivers/reset/Kconfig                              |   6 +
>  drivers/reset/Makefile                             |   1 +
>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>  5 files changed, 281 insertions(+), 68 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
> 
> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> new file mode 100644
> index 000000000000..7f097d16bbb7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
> @@ -0,0 +1,43 @@
> +Lantiq XWAY SoC RCU reset controller binding
> +============================================
> +
> +This binding describes a reset-controller found on the RCU module on Lantiq
> +XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible		: Should be "lantiq,rcu-reset"
> +- lantiq,rcu-syscon	: A phandle to the RCU syscon, the reset register
> +			  offset and the status register offset.
> +- #reset-cells		: Specifies the number of cells needed to encode the
> +			  reset line, should be 1.
> +
> +Optional properties:
> +- reset-status		: The request status bit. For some bits the request bit
> +			  and the status bit are different. This is depending
> +			  on the SoC. If the reset-status bit does not match
> +			  the reset-request bit, put the reset number into the
> +			  reset-request property and the status bit at the same
> +			  index into the reset-status property. If no
> +			  reset-request bit is given here, the driver assume
> +			  status and request bit are the same.
> +- reset-request		: The reset request bit, to map it to the reset-status
> +			  bit.

These should either be implied by SoC specific compatible or be made 
part of the reset cells. In the latter case, you still need the SoC 
specific compatible.

> +-------------------------------------------------------------------------------
> +Example for the reset-controllers on the xRX200 SoCs:
> +	rcu_reset0: rcu_reset {
> +		compatible = "lantiq,rcu-reset";
> +		lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
> +		#reset-cells = <1>;
> +		reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
> +		reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
> +	};
> +
> +	rcu_reset1: rcu_reset {
> +		compatible = "lantiq,rcu-reset";

These 2 blocks are identical? Given different registers sizes, I'd say 
not. So they should have different compatible strings.

> +		lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
> +		#reset-cells = <1>;
> +	};

Re: [PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:38PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> 
> Compared to the old xrx200_phy_fw driver the new version has multiple
> enhancements. The name of the firmware files does not have to be added
> to all .dts files anymore - one now configures the GPHY mode (FE or GE)
> instead. Each GPHY can now also boot separate firmware (thus mixing of
> GE and FE GPHYs is now possible).
> The new implementation is based on the RCU syscon-mfd and uses the
> reeset_controller framework instead of raw RCU register reads/writes.
> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++++
>  arch/mips/lantiq/xway/sysctrl.c                    |   4 +-
>  drivers/soc/lantiq/Makefile                        |   1 +
>  drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++++++++++
>  include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 ++
>  5 files changed, 314 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>  create mode 100644 drivers/soc/lantiq/gphy.c
>  create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
> new file mode 100644
> index 000000000000..d525c7ce9f0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
> @@ -0,0 +1,54 @@
> +Lantiq XWAY SoC GPHY binding
> +============================
> +
> +This binding describes a software-defined ethernet PHY, provided by the RCU
> +module on newer Lantiq XWAY SoCs (xRX200 and newer).
> +This depends on binary firmware blobs which must be provided by userspace.

Where the blobs come from is not relevant. 

> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible		: Should be one of
> +				"lantiq,xrx200a1x-rcu-gphy"
> +				"lantiq,xrx200a2x-rcu-gphy"
> +				"lantiq,xrx300-rcu-gphy"
> +				"lantiq,xrx330-rcu-gphy"
> +- lantiq,rcu-syscon	: A phandle and offset to the GPHY address registers in
> +			  the RCU
> +- resets		: Must reference the RCU GPHY reset bit
> +- reset-names		: One entry, value must be "gphy" or optional "gphy2"
> +
> +Optional properties (port (child) node):
> +- lantiq,gphy-mode	: GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
> +			  <dt-bindings/mips/lantiq_xway_gphy.h>
> +- clocks		: A reference to the (PMU) GPHY clock gate
> +- clock-names		: If clocks is given then this must be "gphy"

Kind of pointless to have a name for a single clock.

> +
> +
> +-------------------------------------------------------------------------------
> +Example for the GPHys on the xRX200 SoCs:
> +
> +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
> +	gphy0: rcu_gphy@0 {

Use generic node names: phy@...

> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
> +		reg = <0>;
> +
> +		lantiq,rcu-syscon = <&rcu0 0x20>;

Could the phy just be a child of the rcu? Then you don't need a phandle 
here and 0x20 becomes the reg address.

> +		resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
> +		reset-names = "gphy", "gphy2";
> +		lantiq,gphy-mode = <GPHY_MODE_GE>;
> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +		clock-names = "gphy";
> +	};
> +
> +	gphy1: rcu_gphy@1 {
> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
> +		reg = <0>;
> +
> +		lantiq,rcu-syscon = <&rcu0 0x68>;
> +		resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
> +		reset-names = "gphy", "gphy2";
> +		lantiq,gphy-mode = <GPHY_MODE_FE>;
> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +		clock-names = "gphy";
> +	};
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Re: [PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:38PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> Compared to the old xrx200_phy_fw driver the new version has multiple
> enhancements. The name of the firmware files does not have to be added
> to all .dts files anymore - one now configures the GPHY mode (FE or GE)
> instead. Each GPHY can now also boot separate firmware (thus mixing of
> GE and FE GPHYs is now possible).
> The new implementation is based on the RCU syscon-mfd and uses the
> reeset_controller framework instead of raw RCU register reads/writes.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++++
>  arch/mips/lantiq/xway/sysctrl.c                    |   4 +-
>  drivers/soc/lantiq/Makefile                        |   1 +
>  drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++++++++++
>  include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 ++
>  5 files changed, 314 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>  create mode 100644 drivers/soc/lantiq/gphy.c
>  create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
> new file mode 100644
> index 000000000000..d525c7ce9f0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
> @@ -0,0 +1,54 @@
> +Lantiq XWAY SoC GPHY binding
> +============================
> +
> +This binding describes a software-defined ethernet PHY, provided by the RCU
> +module on newer Lantiq XWAY SoCs (xRX200 and newer).
> +This depends on binary firmware blobs which must be provided by userspace.

Where the blobs come from is not relevant. 

> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible		: Should be one of
> +				"lantiq,xrx200a1x-rcu-gphy"
> +				"lantiq,xrx200a2x-rcu-gphy"
> +				"lantiq,xrx300-rcu-gphy"
> +				"lantiq,xrx330-rcu-gphy"
> +- lantiq,rcu-syscon	: A phandle and offset to the GPHY address registers in
> +			  the RCU
> +- resets		: Must reference the RCU GPHY reset bit
> +- reset-names		: One entry, value must be "gphy" or optional "gphy2"
> +
> +Optional properties (port (child) node):
> +- lantiq,gphy-mode	: GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
> +			  <dt-bindings/mips/lantiq_xway_gphy.h>
> +- clocks		: A reference to the (PMU) GPHY clock gate
> +- clock-names		: If clocks is given then this must be "gphy"

Kind of pointless to have a name for a single clock.

> +
> +
> +-------------------------------------------------------------------------------
> +Example for the GPHys on the xRX200 SoCs:
> +
> +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
> +	gphy0: rcu_gphy@0 {

Use generic node names: phy@...

> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
> +		reg = <0>;
> +
> +		lantiq,rcu-syscon = <&rcu0 0x20>;

Could the phy just be a child of the rcu? Then you don't need a phandle 
here and 0x20 becomes the reg address.

> +		resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
> +		reset-names = "gphy", "gphy2";
> +		lantiq,gphy-mode = <GPHY_MODE_GE>;
> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +		clock-names = "gphy";
> +	};
> +
> +	gphy1: rcu_gphy@1 {
> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
> +		reg = <0>;
> +
> +		lantiq,rcu-syscon = <&rcu0 0x68>;
> +		resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
> +		reset-names = "gphy", "gphy2";
> +		lantiq,gphy-mode = <GPHY_MODE_FE>;
> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +		clock-names = "gphy";
> +	};

Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:40PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> 
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>  6 files changed, 405 insertions(+), 55 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> new file mode 100644
> index 000000000000..0ec9f790b6e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> @@ -0,0 +1,59 @@
> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
> +===========================================
> +
> +This binding describes the USB PHY hardware provided by the RCU module on the
> +Lantiq XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible		: Should be one of
> +				"lantiq,ase-rcu-usb2-phy"
> +				"lantiq,danube-rcu-usb2-phy"
> +				"lantiq,xrx100-rcu-usb2-phy"
> +				"lantiq,xrx200-rcu-usb2-phy"
> +				"lantiq,xrx300-rcu-usb2-phy"

The first x in xrx seems to be a wildcard. Don't use wildcards in 
compatible strings.

> +- lantiq,rcu-syscon	: A phandle to the RCU module and the offsets to the
> +			  USB PHY configuration and USB MAC registers.

Same comment as gphy.

> +- address-cells		: should be 1
> +- size-cells		: should be 0
> +- phy-cells		: from the generic PHY bindings, must be 1

Missing the '#'

> +
> +Optional properties (controller (parent) node):
> +- vbus-gpio		: References a GPIO which enables VBUS all given USB
> +			  ports.

-gpios is preferred form.

> +
> +Required nodes		:  A sub-node is required for each USB PHY port.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (port (child) node):

Where's the sub nodes in the example?

> +- reg        	: The ID of the USB port, usually 0 or 1.
> +- clocks	: References to the (PMU) "ctrl" and "phy" clk gates.
> +- clock-names	: Must be one of the following:
> +			"ctrl"
> +			"phy"
> +- resets	: References to the RCU USB configuration reset bits.
> +- reset-names	: Must be one of the following:
> +			"analog-config" (optional)
> +			"statemachine-soft" (optional)
> +
> +Optional properties (port (child) node):
> +- vbus-gpio	: References a GPIO which enables VBUS for the USB port.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the USB PHYs on an xRX200 SoC:
> +	usb_phys0: rcu-usb2-phy@0 {

usb-phy@...

> +		compatible      = "lantiq,xrx200-rcu-usb2-phy";

Extra spaces.

> +		reg = <0>;
> +
> +		lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +		clocks = <&pmu PMU_GATE_USB0_CTRL>,
> +			 <&pmu PMU_GATE_USB0_PHY>;
> +		clock-names = "ctrl", "phy";
> +		vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
> +		resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +		reset-names = "phy", "ctrl";
> +		#phy-cells = <0>;
> +	};
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Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:40PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>  6 files changed, 405 insertions(+), 55 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> new file mode 100644
> index 000000000000..0ec9f790b6e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> @@ -0,0 +1,59 @@
> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
> +===========================================
> +
> +This binding describes the USB PHY hardware provided by the RCU module on the
> +Lantiq XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible		: Should be one of
> +				"lantiq,ase-rcu-usb2-phy"
> +				"lantiq,danube-rcu-usb2-phy"
> +				"lantiq,xrx100-rcu-usb2-phy"
> +				"lantiq,xrx200-rcu-usb2-phy"
> +				"lantiq,xrx300-rcu-usb2-phy"

The first x in xrx seems to be a wildcard. Don't use wildcards in 
compatible strings.

> +- lantiq,rcu-syscon	: A phandle to the RCU module and the offsets to the
> +			  USB PHY configuration and USB MAC registers.

Same comment as gphy.

> +- address-cells		: should be 1
> +- size-cells		: should be 0
> +- phy-cells		: from the generic PHY bindings, must be 1

Missing the '#'

> +
> +Optional properties (controller (parent) node):
> +- vbus-gpio		: References a GPIO which enables VBUS all given USB
> +			  ports.

-gpios is preferred form.

> +
> +Required nodes		:  A sub-node is required for each USB PHY port.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (port (child) node):

Where's the sub nodes in the example?

> +- reg        	: The ID of the USB port, usually 0 or 1.
> +- clocks	: References to the (PMU) "ctrl" and "phy" clk gates.
> +- clock-names	: Must be one of the following:
> +			"ctrl"
> +			"phy"
> +- resets	: References to the RCU USB configuration reset bits.
> +- reset-names	: Must be one of the following:
> +			"analog-config" (optional)
> +			"statemachine-soft" (optional)
> +
> +Optional properties (port (child) node):
> +- vbus-gpio	: References a GPIO which enables VBUS for the USB port.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the USB PHYs on an xRX200 SoC:
> +	usb_phys0: rcu-usb2-phy@0 {

usb-phy@...

> +		compatible      = "lantiq,xrx200-rcu-usb2-phy";

Extra spaces.

> +		reg = <0>;
> +
> +		lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +		clocks = <&pmu PMU_GATE_USB0_CTRL>,
> +			 <&pmu PMU_GATE_USB0_PHY>;
> +		clock-names = "ctrl", "phy";
> +		vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
> +		resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +		reset-names = "phy", "ctrl";
> +		#phy-cells = <0>;
> +	};

Re: [PATCH 12/13] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:41PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> 
> This adds the initial documentation for the RCU module (a MFD device
> which provides USB PHYs, reset controllers and more).

This should come before the other patches.

> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../devicetree/bindings/mips/lantiq/rcu.txt        | 82 ++++++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> new file mode 100644
> index 000000000000..9e5b1e7493e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> @@ -0,0 +1,82 @@
> +Lantiq XWAY SoC RCU binding
> +===========================
> +
> +This binding describes the RCU (reset controller unit) multifunction device,
> +where each sub-device has it's own set of registers.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible	: The first and second values must be: "simple-mfd", "syscon"
> +- reg		: The address and length of the system control registers
> +
> +
> +-------------------------------------------------------------------------------
> +Example of the RCU bindings on a xRX200 SoC:
> +	rcu0: rcu@203000 {
> +		compatible = "simple-mfd", "syscon";

Needs an SoC specific compatible string here.

> +		reg = <0x203000 0x100>;
> +		big-endian;
> +
> +		gphy0: rcu_gphy@0 {
> +			compatible = "lantiq,xrx200a2x-rcu-gphy";
> +			lantiq,rcu-syscon = <&rcu0 0x20>;

So these are already child nodes. You can get rid of this and use 
reg/ranges instead.

> +			resets = <&rcu_reset0 31>;
> +			reset-names = "gphy";
> +			lantiq,gphy-mode = <GPHY_MODE_GE>;
> +			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +			clock-names = "gphy";
> +		};
> +
> +		gphy1: rcu_gphy@1 {
> +			compatible = "lantiq,xrx200a2x-rcu-gphy";
> +			lantiq,rcu-syscon = <&rcu0 0x68>;
> +			resets = <&rcu_reset0 29>;
> +			reset-names = "gphy";
> +			lantiq,gphy-mode = <GPHY_MODE_FE>;
> +			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +			clock-names = "gphy";
> +		};
> +
> +		rcu_reset0: rcu_reset@0 {
> +			compatible = "lantiq,rcu-reset";
> +			lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
> +			#reset-cells = <1>;
> +			reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
> +			reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
> +		};
> +
> +		rcu_reset1: rcu_reset@1 {
> +			compatible = "lantiq,rcu-reset";
> +			lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
> +			#reset-cells = <1>;
> +		};
> +
> +		usb_phys0: rcu-usb2-phy@0 {
> +			compatible = "lantiq,xrx200-rcu-usb2-phy";
> +
> +			lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +			resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +			reset-names = "phy", "ctrl";
> +			#phy-cells = <0>;
> +		};
> +
> +		usb_phys1: rcu-usb2-phy@1 {
> +			compatible = "lantiq,xrx200-rcu-usb2-phy";
> +
> +			lantiq,rcu-syscon = <&rcu0 0x34 0x3C>;
> +			resets = <&rcu_reset1 5>, <&rcu_reset0 4>;
> +			reset-names = "phy", "ctrl";
> +			#phy-cells = <0>;
> +		};
> +
> +		reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&rcu0>;
> +			offset = <0x10>;
> +			mask = <0x40000000>;
> +		};
> +
> +		/* more sub-device nodes (USB PHY, etc.) */
> +	};
> +
> -- 
> 2.11.0
> 
> --
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Re: [PATCH 12/13] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings

[Rob Herring]

On Mon, Apr 17, 2017 at 09:29:41PM +0200, Hauke Mehrtens wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> This adds the initial documentation for the RCU module (a MFD device
> which provides USB PHYs, reset controllers and more).

This should come before the other patches.

> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../devicetree/bindings/mips/lantiq/rcu.txt        | 82 ++++++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> 
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> new file mode 100644
> index 000000000000..9e5b1e7493e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
> @@ -0,0 +1,82 @@
> +Lantiq XWAY SoC RCU binding
> +===========================
> +
> +This binding describes the RCU (reset controller unit) multifunction device,
> +where each sub-device has it's own set of registers.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible	: The first and second values must be: "simple-mfd", "syscon"
> +- reg		: The address and length of the system control registers
> +
> +
> +-------------------------------------------------------------------------------
> +Example of the RCU bindings on a xRX200 SoC:
> +	rcu0: rcu@203000 {
> +		compatible = "simple-mfd", "syscon";

Needs an SoC specific compatible string here.

> +		reg = <0x203000 0x100>;
> +		big-endian;
> +
> +		gphy0: rcu_gphy@0 {
> +			compatible = "lantiq,xrx200a2x-rcu-gphy";
> +			lantiq,rcu-syscon = <&rcu0 0x20>;

So these are already child nodes. You can get rid of this and use 
reg/ranges instead.

> +			resets = <&rcu_reset0 31>;
> +			reset-names = "gphy";
> +			lantiq,gphy-mode = <GPHY_MODE_GE>;
> +			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +			clock-names = "gphy";
> +		};
> +
> +		gphy1: rcu_gphy@1 {
> +			compatible = "lantiq,xrx200a2x-rcu-gphy";
> +			lantiq,rcu-syscon = <&rcu0 0x68>;
> +			resets = <&rcu_reset0 29>;
> +			reset-names = "gphy";
> +			lantiq,gphy-mode = <GPHY_MODE_FE>;
> +			clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
> +			clock-names = "gphy";
> +		};
> +
> +		rcu_reset0: rcu_reset@0 {
> +			compatible = "lantiq,rcu-reset";
> +			lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
> +			#reset-cells = <1>;
> +			reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
> +			reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
> +		};
> +
> +		rcu_reset1: rcu_reset@1 {
> +			compatible = "lantiq,rcu-reset";
> +			lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
> +			#reset-cells = <1>;
> +		};
> +
> +		usb_phys0: rcu-usb2-phy@0 {
> +			compatible = "lantiq,xrx200-rcu-usb2-phy";
> +
> +			lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +			resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +			reset-names = "phy", "ctrl";
> +			#phy-cells = <0>;
> +		};
> +
> +		usb_phys1: rcu-usb2-phy@1 {
> +			compatible = "lantiq,xrx200-rcu-usb2-phy";
> +
> +			lantiq,rcu-syscon = <&rcu0 0x34 0x3C>;
> +			resets = <&rcu_reset1 5>, <&rcu_reset0 4>;
> +			reset-names = "phy", "ctrl";
> +			#phy-cells = <0>;
> +		};
> +
> +		reboot {
> +			compatible = "syscon-reboot";
> +			regmap = <&rcu0>;
> +			offset = <0x10>;
> +			mask = <0x40000000>;
> +		};
> +
> +		/* more sub-device nodes (USB PHY, etc.) */
> +	};
> +
> -- 
> 2.11.0
> 
> --
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Re: [PATCH 02/13] mtd: lantiq-flash: drop check of boot select

[Brian Norris]

On Mon, Apr 17, 2017 at 09:29:31PM +0200, Hauke Mehrtens wrote:
> Do not check which flash type the SoC was booted from before
> using this driver. Assume that the device tree is correct and use this
> driver when it was added to device tree. This also removes a build
> dependency to the SoC code.
> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>

Presuming you get the platform details right (i.e., device tree), I'm
happy with this. It's not really this driver's job to check your boot
strappings.

Acked-by: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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Re: [PATCH 02/13] mtd: lantiq-flash: drop check of boot select

[Brian Norris]

On Mon, Apr 17, 2017 at 09:29:31PM +0200, Hauke Mehrtens wrote:
> Do not check which flash type the SoC was booted from before
> using this driver. Assume that the device tree is correct and use this
> driver when it was added to device tree. This also removes a build
> dependency to the SoC code.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

Presuming you get the platform details right (i.e., device tree), I'm
happy with this. It's not really this driver's job to check your boot
strappings.

Acked-by: Brian Norris <computersforpeace@gmail.com>

Re: [PATCH 01/13] MIPS: lantiq: Use of_platform_populate instead of __dt_register_buses

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This allows populating syscon devices which are using "simple-mfd"
> instead of "simple-bus".
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

> ---
>  arch/mips/lantiq/prom.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
> index 96773bed8a8a..72cc12f1b6a5 100644
> --- a/arch/mips/lantiq/prom.c
> +++ b/arch/mips/lantiq/prom.c
> @@ -117,7 +117,8 @@ void __init prom_init(void)
>
>  int __init plat_of_setup(void)
>  {
> -       return __dt_register_buses(soc_info.compatible, "simple-bus");
> +       return of_platform_populate(NULL, of_default_bus_match_table, NULL,
> +                                   NULL);
>  }
>
>  arch_initcall(plat_of_setup);
> --
> 2.11.0
>

Re: [PATCH 07/13] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> Do not export the ltq_reset_cause() and ltq_boot_select() function any
> more. ltq_reset_cause() was accessed by the watchdog driver before to
> see why the last reset happened, this is now done through direct access
> of the register over regmap. The bits in this register are anyway
> different between the xrx200 and the falcon SoC.
> ltq_boot_select() is not used any more and was used by the flash
> drivers to check if the system was booted from this flash type, now the
> drivers should depend on the device tree only.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Acked-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

(you could make yourself the author of this patch as I didn't touch
this - but I think that this is a good thing to do!)

> ---
>  arch/mips/include/asm/mach-lantiq/lantiq.h |  4 ----
>  arch/mips/lantiq/falcon/reset.c            | 22 ----------------------
>  arch/mips/lantiq/xway/reset.c              | 19 -------------------
>  3 files changed, 45 deletions(-)
>
> diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
> index 8064d7a4b33d..fa045b4c0cdd 100644
> --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
> +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
> @@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
>  extern struct clk *clk_get_io(void);
>  extern struct clk *clk_get_ppe(void);
>
> -/* find out what bootsource we have */
> -extern unsigned char ltq_boot_select(void);
> -/* find out what caused the last cpu reset */
> -extern int ltq_reset_cause(void);
>  /* find out the soc type */
>  extern int ltq_soc_type(void);
>
> diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
> index 7a535d72f541..722114d7409d 100644
> --- a/arch/mips/lantiq/falcon/reset.c
> +++ b/arch/mips/lantiq/falcon/reset.c
> @@ -15,28 +15,6 @@
>
>  #include <lantiq_soc.h>
>
> -/* CPU0 Reset Source Register */
> -#define SYS1_CPU0RS            0x0040
> -/* reset cause mask */
> -#define CPU0RS_MASK            0x0003
> -/* CPU0 Boot Mode Register */
> -#define SYS1_BM                        0x00a0
> -/* boot mode mask */
> -#define BM_MASK                        0x0005
> -
> -/* allow platform code to find out what surce we booted from */
> -unsigned char ltq_boot_select(void)
> -{
> -       return ltq_sys1_r32(SYS1_BM) & BM_MASK;
> -}
> -
> -/* allow the watchdog driver to find out what the boot reason was */
> -int ltq_reset_cause(void)
> -{
> -       return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
> -}
> -EXPORT_SYMBOL_GPL(ltq_reset_cause);
> -
>  #define BOOT_REG_BASE  (KSEG1 | 0x1F200000)
>  #define BOOT_PW1_REG   (BOOT_REG_BASE | 0x20)
>  #define BOOT_PW2_REG   (BOOT_REG_BASE | 0x24)
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index b6752c95a600..2dedcf939901 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
> @@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
>         spin_unlock_irqrestore(&ltq_rcu_lock, flags);
>  }
>
> -/* This function is used by the watchdog driver */
> -int ltq_reset_cause(void)
> -{
> -       u32 val = ltq_rcu_r32(RCU_RST_STAT);
> -       return val >> RCU_STAT_SHIFT;
> -}
> -EXPORT_SYMBOL_GPL(ltq_reset_cause);
> -
> -/* allow platform code to find out what source we booted from */
> -unsigned char ltq_boot_select(void)
> -{
> -       u32 val = ltq_rcu_r32(RCU_RST_STAT);
> -
> -       if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
> -               return RCU_BOOT_SEL_XRX200(val);
> -
> -       return RCU_BOOT_SEL(val);
> -}
> -
>  struct ltq_gphy_reset {
>         u32 rd;
>         u32 addr;
> --
> 2.11.0
>
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Re: [PATCH 07/13] MIPS: lantiq: remove ltq_reset_cause() and ltq_boot_select()

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> Do not export the ltq_reset_cause() and ltq_boot_select() function any
> more. ltq_reset_cause() was accessed by the watchdog driver before to
> see why the last reset happened, this is now done through direct access
> of the register over regmap. The bits in this register are anyway
> different between the xrx200 and the falcon SoC.
> ltq_boot_select() is not used any more and was used by the flash
> drivers to check if the system was booted from this flash type, now the
> drivers should depend on the device tree only.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

(you could make yourself the author of this patch as I didn't touch
this - but I think that this is a good thing to do!)

> ---
>  arch/mips/include/asm/mach-lantiq/lantiq.h |  4 ----
>  arch/mips/lantiq/falcon/reset.c            | 22 ----------------------
>  arch/mips/lantiq/xway/reset.c              | 19 -------------------
>  3 files changed, 45 deletions(-)
>
> diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
> index 8064d7a4b33d..fa045b4c0cdd 100644
> --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
> +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
> @@ -44,10 +44,6 @@ extern struct clk *clk_get_fpi(void);
>  extern struct clk *clk_get_io(void);
>  extern struct clk *clk_get_ppe(void);
>
> -/* find out what bootsource we have */
> -extern unsigned char ltq_boot_select(void);
> -/* find out what caused the last cpu reset */
> -extern int ltq_reset_cause(void);
>  /* find out the soc type */
>  extern int ltq_soc_type(void);
>
> diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
> index 7a535d72f541..722114d7409d 100644
> --- a/arch/mips/lantiq/falcon/reset.c
> +++ b/arch/mips/lantiq/falcon/reset.c
> @@ -15,28 +15,6 @@
>
>  #include <lantiq_soc.h>
>
> -/* CPU0 Reset Source Register */
> -#define SYS1_CPU0RS            0x0040
> -/* reset cause mask */
> -#define CPU0RS_MASK            0x0003
> -/* CPU0 Boot Mode Register */
> -#define SYS1_BM                        0x00a0
> -/* boot mode mask */
> -#define BM_MASK                        0x0005
> -
> -/* allow platform code to find out what surce we booted from */
> -unsigned char ltq_boot_select(void)
> -{
> -       return ltq_sys1_r32(SYS1_BM) & BM_MASK;
> -}
> -
> -/* allow the watchdog driver to find out what the boot reason was */
> -int ltq_reset_cause(void)
> -{
> -       return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
> -}
> -EXPORT_SYMBOL_GPL(ltq_reset_cause);
> -
>  #define BOOT_REG_BASE  (KSEG1 | 0x1F200000)
>  #define BOOT_PW1_REG   (BOOT_REG_BASE | 0x20)
>  #define BOOT_PW2_REG   (BOOT_REG_BASE | 0x24)
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index b6752c95a600..2dedcf939901 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
> @@ -119,25 +119,6 @@ static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
>         spin_unlock_irqrestore(&ltq_rcu_lock, flags);
>  }
>
> -/* This function is used by the watchdog driver */
> -int ltq_reset_cause(void)
> -{
> -       u32 val = ltq_rcu_r32(RCU_RST_STAT);
> -       return val >> RCU_STAT_SHIFT;
> -}
> -EXPORT_SYMBOL_GPL(ltq_reset_cause);
> -
> -/* allow platform code to find out what source we booted from */
> -unsigned char ltq_boot_select(void)
> -{
> -       u32 val = ltq_rcu_r32(RCU_RST_STAT);
> -
> -       if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
> -               return RCU_BOOT_SEL_XRX200(val);
> -
> -       return RCU_BOOT_SEL(val);
> -}
> -
>  struct ltq_gphy_reset {
>         u32 rd;
>         u32 addr;
> --
> 2.11.0
>

Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> This allows using the xbar driver on ARX300 based SoCs which require the
> same xbar setup as the xRX200 chipsets because the xbar driver
> initialization is not guarded by an xRX200 specific
> of_machine_is_compatible condition anymore. Additionally the new driver
> takes a syscon phandle to configure the XBAR endianness bits in RCU
> (before this was done in arch/mips/lantiq/xway/reset.c and also
> guarded by an xRX200 specific if-statement).
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>  MAINTAINERS                                        |   1 +
>  arch/mips/lantiq/xway/reset.c                      |   4 -
>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/lantiq/Makefile                        |   1 +
>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>  7 files changed, 125 insertions(+), 45 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>  create mode 100644 drivers/soc/lantiq/Makefile
>  create mode 100644 drivers/soc/lantiq/xbar.c
>
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> new file mode 100644
> index 000000000000..86e53ff3b0d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> @@ -0,0 +1,22 @@
> +Lantiq XWAY SoC XBAR binding
> +============================
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible   : Should be "lantiq,xbar-xway"
> +- reg          : The address and length of the XBAR registers
> +
> +Optional properties:
> +- lantiq,rcu-syscon    : A phandle and offset to the endianness configuration
> +                         registers in the RCU module
is the xbar module really coupled with the RCU mdoule? if it is then:

Signed-off-by: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>

> +
> +
> +-------------------------------------------------------------------------------
> +Example for the XBAR on the xRX200 SoCs:
> +       xbar0: xbar@400000 {
> +               compatible = "lantiq,xbar-xway";
> +               reg = <0x400000 0x1000>;
> +               big-endian;
> +               lantiq,rcu-syscon = <&rcu0 0x4c>;
> +       };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 676c139bc883..7c03776a56e9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7321,6 +7321,7 @@ M:        John Crispin <john-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
>  L:     linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
>  S:     Maintained
>  F:     arch/mips/lantiq
> +F:     drivers/soc/lantiq
>
>  LAPB module
>  L:     linux-x25-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 83fd65d76e81..b6752c95a600 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
> @@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
>             of_machine_is_compatible("lantiq,vr9"))
>                 ltq_usb_init();
>
> -       if (of_machine_is_compatible("lantiq,vr9"))
> -               ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
> -                           RCU_AHB_ENDIAN);
> -
>         _machine_restart = ltq_machine_restart;
>         _machine_halt = ltq_machine_halt;
>         pm_power_off = ltq_machine_power_off;
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 95bec460b651..706639a343bc 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
>  #define pmu_w32(x, y)  ltq_w32((x), pmu_membase + (y))
>  #define pmu_r32(x)     ltq_r32(pmu_membase + (x))
>
> -#define XBAR_ALWAYS_LAST       0x430
> -#define XBAR_FPI_BURST_EN      BIT(1)
> -#define XBAR_AHB_BURST_EN      BIT(2)
> -
> -#define xbar_w32(x, y) ltq_w32((x), ltq_xbar_membase + (y))
> -#define xbar_r32(x)    ltq_r32(ltq_xbar_membase + (x))
> -
>  static void __iomem *pmu_membase;
> -static void __iomem *ltq_xbar_membase;
>  void __iomem *ltq_cgu_membase;
>  void __iomem *ltq_ebu_membase;
>
> @@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
>         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
>  }
>
> -static void xbar_fpi_burst_disable(void)
> -{
> -       u32 reg;
> -
> -       /* bit 1 as 1 --burst; bit 1 as 0 -- single */
> -       reg = xbar_r32(XBAR_ALWAYS_LAST);
> -       reg &= ~XBAR_FPI_BURST_EN;
> -       xbar_w32(reg, XBAR_ALWAYS_LAST);
> -}
> -
>  /* enable a clockout source */
>  static int clkout_enable(struct clk *clk)
>  {
> @@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
>         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
>                 panic("Failed to remap core resources");
>
> -       if (of_machine_is_compatible("lantiq,vr9")) {
> -               struct resource res_xbar;
> -               struct device_node *np_xbar =
> -                               of_find_compatible_node(NULL, NULL,
> -                                                       "lantiq,xbar-xway");
> -
> -               if (!np_xbar)
> -                       panic("Failed to load xbar nodes from devicetree");
> -               if (of_address_to_resource(np_xbar, 0, &res_xbar))
> -                       panic("Failed to get xbar resources");
> -               if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
> -                       res_xbar.name))
> -                       panic("Failed to get xbar resources");
> -
> -               ltq_xbar_membase = ioremap_nocache(res_xbar.start,
> -                                                  resource_size(&res_xbar));
> -               if (!ltq_xbar_membase)
> -                       panic("Failed to remap xbar resources");
> -       }
> -
>         /* make sure to unprotect the memory region where flash is located */
>         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
>
> @@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
>                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
>                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
>         }
> -
> -       if (of_machine_is_compatible("lantiq,vr9"))
> -               xbar_fpi_burst_disable();
>  }
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 05eae52a30b4..8775d37ac158 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -6,6 +6,7 @@ obj-y                           += bcm/
>  obj-$(CONFIG_ARCH_DOVE)                += dove/
>  obj-$(CONFIG_MACH_DOVE)                += dove/
>  obj-y                          += fsl/
> +obj-$(CONFIG_SOC_XWAY)         += lantiq/
>  obj-$(CONFIG_ARCH_MEDIATEK)    += mediatek/
>  obj-$(CONFIG_ARCH_QCOM)                += qcom/
>  obj-$(CONFIG_ARCH_RENESAS)     += renesas/
> diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
> new file mode 100644
> index 000000000000..7411bd23d58e
> --- /dev/null
> +++ b/drivers/soc/lantiq/Makefile
> @@ -0,0 +1 @@
> +obj-y                          += xbar.o
> diff --git a/drivers/soc/lantiq/xbar.c b/drivers/soc/lantiq/xbar.c
> new file mode 100644
> index 000000000000..dcd087817435
> --- /dev/null
> +++ b/drivers/soc/lantiq/xbar.c
> @@ -0,0 +1,100 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2011-2015 John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> + *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> + */
> +
> +#include <linux/ioport.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/regmap.h>
> +
> +#include <lantiq_soc.h>
> +
> +#define XBAR_ALWAYS_LAST       0x430
> +#define XBAR_FPI_BURST_EN      BIT(1)
> +#define XBAR_AHB_BURST_EN      BIT(2)
> +
> +#define RCU_VR9_BE_AHB1S       0x00000008
> +
> +static int ltq_xbar_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct resource res_xbar;
> +       struct regmap *rcu_regmap;
> +       void __iomem *xbar_membase;
> +       u32 rcu_ahb_endianness_reg_offset;
> +       u32 rcu_ahb_endianness_val;
> +       int ret;
> +
> +       ret = of_address_to_resource(np, 0, &res_xbar);
> +       if (ret) {
> +               dev_err(dev, "Failed to get xbar resources");
> +               return ret;
> +       }
> +
> +       if (!devm_request_mem_region(dev, res_xbar.start,
> +                                    resource_size(&res_xbar),
> +               res_xbar.name)) {
> +               dev_err(dev, "Failed to get xbar resources");
> +               return -ENODEV;
> +       }
> +
> +       xbar_membase = devm_ioremap_nocache(dev, res_xbar.start,
> +                                               resource_size(&res_xbar));
> +       if (!xbar_membase) {
> +               dev_err(dev, "Failed to remap xbar resources");
> +               return -ENODEV;
> +       }
> +
> +       /* RCU configuration is optional */
> +       rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu-syscon");
> +       if (!IS_ERR_OR_NULL(rcu_regmap)) {
> +               if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
> +                       &rcu_ahb_endianness_reg_offset)) {
> +                       dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
> +                       return -EINVAL;
> +               }
> +
> +               if (of_device_is_big_endian(np))
> +                       rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
> +               else
> +                       rcu_ahb_endianness_val = 0;
> +
> +               if (regmap_update_bits(rcu_regmap,
> +                                       rcu_ahb_endianness_reg_offset,
> +                                       RCU_VR9_BE_AHB1S,
> +                                       rcu_ahb_endianness_val))
> +                       dev_warn(&pdev->dev,
> +                               "Failed to configure RCU AHB endianness\n");
> +       }
> +
> +       /* disable fpi burst */
> +       ltq_w32_mask(XBAR_FPI_BURST_EN, 0,
> +                    xbar_membase + XBAR_ALWAYS_LAST);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id xbar_match[] = {
> +       { .compatible = "lantiq,xbar-xway" },
> +       {},
> +};
> +MODULE_DEVICE_TABLE(of, xbar_match);
> +
> +static struct platform_driver xbar_driver = {
> +       .probe = ltq_xbar_probe,
> +       .driver = {
> +               .name = "xbar-xway",
> +               .of_match_table = xbar_match,
> +       },
> +};
> +
> +builtin_platform_driver(xbar_driver);
> --
> 2.11.0
>
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Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This allows using the xbar driver on ARX300 based SoCs which require the
> same xbar setup as the xRX200 chipsets because the xbar driver
> initialization is not guarded by an xRX200 specific
> of_machine_is_compatible condition anymore. Additionally the new driver
> takes a syscon phandle to configure the XBAR endianness bits in RCU
> (before this was done in arch/mips/lantiq/xway/reset.c and also
> guarded by an xRX200 specific if-statement).
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>  MAINTAINERS                                        |   1 +
>  arch/mips/lantiq/xway/reset.c                      |   4 -
>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/lantiq/Makefile                        |   1 +
>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>  7 files changed, 125 insertions(+), 45 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>  create mode 100644 drivers/soc/lantiq/Makefile
>  create mode 100644 drivers/soc/lantiq/xbar.c
>
> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> new file mode 100644
> index 000000000000..86e53ff3b0d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
> @@ -0,0 +1,22 @@
> +Lantiq XWAY SoC XBAR binding
> +============================
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties:
> +- compatible   : Should be "lantiq,xbar-xway"
> +- reg          : The address and length of the XBAR registers
> +
> +Optional properties:
> +- lantiq,rcu-syscon    : A phandle and offset to the endianness configuration
> +                         registers in the RCU module
is the xbar module really coupled with the RCU mdoule? if it is then:

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

> +
> +
> +-------------------------------------------------------------------------------
> +Example for the XBAR on the xRX200 SoCs:
> +       xbar0: xbar@400000 {
> +               compatible = "lantiq,xbar-xway";
> +               reg = <0x400000 0x1000>;
> +               big-endian;
> +               lantiq,rcu-syscon = <&rcu0 0x4c>;
> +       };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 676c139bc883..7c03776a56e9 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7321,6 +7321,7 @@ M:        John Crispin <john@phrozen.org>
>  L:     linux-mips@linux-mips.org
>  S:     Maintained
>  F:     arch/mips/lantiq
> +F:     drivers/soc/lantiq
>
>  LAPB module
>  L:     linux-x25@vger.kernel.org
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 83fd65d76e81..b6752c95a600 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
> @@ -373,10 +373,6 @@ static int __init mips_reboot_setup(void)
>             of_machine_is_compatible("lantiq,vr9"))
>                 ltq_usb_init();
>
> -       if (of_machine_is_compatible("lantiq,vr9"))
> -               ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
> -                           RCU_AHB_ENDIAN);
> -
>         _machine_restart = ltq_machine_restart;
>         _machine_halt = ltq_machine_halt;
>         pm_power_off = ltq_machine_power_off;
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 95bec460b651..706639a343bc 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
>  #define pmu_w32(x, y)  ltq_w32((x), pmu_membase + (y))
>  #define pmu_r32(x)     ltq_r32(pmu_membase + (x))
>
> -#define XBAR_ALWAYS_LAST       0x430
> -#define XBAR_FPI_BURST_EN      BIT(1)
> -#define XBAR_AHB_BURST_EN      BIT(2)
> -
> -#define xbar_w32(x, y) ltq_w32((x), ltq_xbar_membase + (y))
> -#define xbar_r32(x)    ltq_r32(ltq_xbar_membase + (x))
> -
>  static void __iomem *pmu_membase;
> -static void __iomem *ltq_xbar_membase;
>  void __iomem *ltq_cgu_membase;
>  void __iomem *ltq_ebu_membase;
>
> @@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
>         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
>  }
>
> -static void xbar_fpi_burst_disable(void)
> -{
> -       u32 reg;
> -
> -       /* bit 1 as 1 --burst; bit 1 as 0 -- single */
> -       reg = xbar_r32(XBAR_ALWAYS_LAST);
> -       reg &= ~XBAR_FPI_BURST_EN;
> -       xbar_w32(reg, XBAR_ALWAYS_LAST);
> -}
> -
>  /* enable a clockout source */
>  static int clkout_enable(struct clk *clk)
>  {
> @@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
>         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
>                 panic("Failed to remap core resources");
>
> -       if (of_machine_is_compatible("lantiq,vr9")) {
> -               struct resource res_xbar;
> -               struct device_node *np_xbar =
> -                               of_find_compatible_node(NULL, NULL,
> -                                                       "lantiq,xbar-xway");
> -
> -               if (!np_xbar)
> -                       panic("Failed to load xbar nodes from devicetree");
> -               if (of_address_to_resource(np_xbar, 0, &res_xbar))
> -                       panic("Failed to get xbar resources");
> -               if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
> -                       res_xbar.name))
> -                       panic("Failed to get xbar resources");
> -
> -               ltq_xbar_membase = ioremap_nocache(res_xbar.start,
> -                                                  resource_size(&res_xbar));
> -               if (!ltq_xbar_membase)
> -                       panic("Failed to remap xbar resources");
> -       }
> -
>         /* make sure to unprotect the memory region where flash is located */
>         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
>
> @@ -605,7 +567,4 @@ void __init ltq_soc_init(void)
>                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
>                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
>         }
> -
> -       if (of_machine_is_compatible("lantiq,vr9"))
> -               xbar_fpi_burst_disable();
>  }
> diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
> index 05eae52a30b4..8775d37ac158 100644
> --- a/drivers/soc/Makefile
> +++ b/drivers/soc/Makefile
> @@ -6,6 +6,7 @@ obj-y                           += bcm/
>  obj-$(CONFIG_ARCH_DOVE)                += dove/
>  obj-$(CONFIG_MACH_DOVE)                += dove/
>  obj-y                          += fsl/
> +obj-$(CONFIG_SOC_XWAY)         += lantiq/
>  obj-$(CONFIG_ARCH_MEDIATEK)    += mediatek/
>  obj-$(CONFIG_ARCH_QCOM)                += qcom/
>  obj-$(CONFIG_ARCH_RENESAS)     += renesas/
> diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
> new file mode 100644
> index 000000000000..7411bd23d58e
> --- /dev/null
> +++ b/drivers/soc/lantiq/Makefile
> @@ -0,0 +1 @@
> +obj-y                          += xbar.o
> diff --git a/drivers/soc/lantiq/xbar.c b/drivers/soc/lantiq/xbar.c
> new file mode 100644
> index 000000000000..dcd087817435
> --- /dev/null
> +++ b/drivers/soc/lantiq/xbar.c
> @@ -0,0 +1,100 @@
> +/*
> + *  This program is free software; you can redistribute it and/or modify it
> + *  under the terms of the GNU General Public License version 2 as published
> + *  by the Free Software Foundation.
> + *
> + *  Copyright (C) 2011-2015 John Crispin <blogic@openwrt.org>
> + *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + */
> +
> +#include <linux/ioport.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/regmap.h>
> +
> +#include <lantiq_soc.h>
> +
> +#define XBAR_ALWAYS_LAST       0x430
> +#define XBAR_FPI_BURST_EN      BIT(1)
> +#define XBAR_AHB_BURST_EN      BIT(2)
> +
> +#define RCU_VR9_BE_AHB1S       0x00000008
> +
> +static int ltq_xbar_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct resource res_xbar;
> +       struct regmap *rcu_regmap;
> +       void __iomem *xbar_membase;
> +       u32 rcu_ahb_endianness_reg_offset;
> +       u32 rcu_ahb_endianness_val;
> +       int ret;
> +
> +       ret = of_address_to_resource(np, 0, &res_xbar);
> +       if (ret) {
> +               dev_err(dev, "Failed to get xbar resources");
> +               return ret;
> +       }
> +
> +       if (!devm_request_mem_region(dev, res_xbar.start,
> +                                    resource_size(&res_xbar),
> +               res_xbar.name)) {
> +               dev_err(dev, "Failed to get xbar resources");
> +               return -ENODEV;
> +       }
> +
> +       xbar_membase = devm_ioremap_nocache(dev, res_xbar.start,
> +                                               resource_size(&res_xbar));
> +       if (!xbar_membase) {
> +               dev_err(dev, "Failed to remap xbar resources");
> +               return -ENODEV;
> +       }
> +
> +       /* RCU configuration is optional */
> +       rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu-syscon");
> +       if (!IS_ERR_OR_NULL(rcu_regmap)) {
> +               if (of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
> +                       &rcu_ahb_endianness_reg_offset)) {
> +                       dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
> +                       return -EINVAL;
> +               }
> +
> +               if (of_device_is_big_endian(np))
> +                       rcu_ahb_endianness_val = RCU_VR9_BE_AHB1S;
> +               else
> +                       rcu_ahb_endianness_val = 0;
> +
> +               if (regmap_update_bits(rcu_regmap,
> +                                       rcu_ahb_endianness_reg_offset,
> +                                       RCU_VR9_BE_AHB1S,
> +                                       rcu_ahb_endianness_val))
> +                       dev_warn(&pdev->dev,
> +                               "Failed to configure RCU AHB endianness\n");
> +       }
> +
> +       /* disable fpi burst */
> +       ltq_w32_mask(XBAR_FPI_BURST_EN, 0,
> +                    xbar_membase + XBAR_ALWAYS_LAST);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id xbar_match[] = {
> +       { .compatible = "lantiq,xbar-xway" },
> +       {},
> +};
> +MODULE_DEVICE_TABLE(of, xbar_match);
> +
> +static struct platform_driver xbar_driver = {
> +       .probe = ltq_xbar_probe,
> +       .driver = {
> +               .name = "xbar-xway",
> +               .of_match_table = xbar_match,
> +       },
> +};
> +
> +builtin_platform_driver(xbar_driver);
> --
> 2.11.0
>

Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
>
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> ---
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>  6 files changed, 405 insertions(+), 55 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> new file mode 100644
> index 000000000000..0ec9f790b6e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> @@ -0,0 +1,59 @@
> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
> +===========================================
> +
> +This binding describes the USB PHY hardware provided by the RCU module on the
> +Lantiq XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible           : Should be one of
> +                               "lantiq,ase-rcu-usb2-phy"
> +                               "lantiq,danube-rcu-usb2-phy"
> +                               "lantiq,xrx100-rcu-usb2-phy"
> +                               "lantiq,xrx200-rcu-usb2-phy"
> +                               "lantiq,xrx300-rcu-usb2-phy"
> +- lantiq,rcu-syscon    : A phandle to the RCU module and the offsets to the
> +                         USB PHY configuration and USB MAC registers.
> +- address-cells                : should be 1
> +- size-cells           : should be 0
> +- phy-cells            : from the generic PHY bindings, must be 1
> +
> +Optional properties (controller (parent) node):
> +- vbus-gpio            : References a GPIO which enables VBUS all given USB
> +                         ports.
> +
> +Required nodes         :  A sub-node is required for each USB PHY port.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (port (child) node):
> +- reg          : The ID of the USB port, usually 0 or 1.
> +- clocks       : References to the (PMU) "ctrl" and "phy" clk gates.
> +- clock-names  : Must be one of the following:
> +                       "ctrl"
> +                       "phy"
> +- resets       : References to the RCU USB configuration reset bits.
> +- reset-names  : Must be one of the following:
> +                       "analog-config" (optional)
> +                       "statemachine-soft" (optional)
> +
> +Optional properties (port (child) node):
> +- vbus-gpio    : References a GPIO which enables VBUS for the USB port.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the USB PHYs on an xRX200 SoC:
> +       usb_phys0: rcu-usb2-phy@0 {
> +               compatible      = "lantiq,xrx200-rcu-usb2-phy";
> +               reg = <0>;
> +
> +               lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +               clocks = <&pmu PMU_GATE_USB0_CTRL>,
> +                        <&pmu PMU_GATE_USB0_PHY>;
> +               clock-names = "ctrl", "phy";
> +               vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
> +               resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +               reset-names = "phy", "ctrl";
> +               #phy-cells = <0>;
> +       };
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 3f30fb81a50f..5aec1f54275b 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
> @@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
>         unreachable();
>  }
>
> -static void ltq_usb_init(void)
> -{
> -       /* Power for USB cores 1 & 2 */
> -       ltq_pmu_enable(PMU_AHBM);
> -       ltq_pmu_enable(PMU_USB0);
> -       ltq_pmu_enable(PMU_USB1);
> -
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
> -
> -       /* Enable USB PHY power for cores 1 & 2 */
> -       ltq_pmu_enable(PMU_USB0_P);
> -       ltq_pmu_enable(PMU_USB1_P);
> -
> -       /* Configure cores to host mode */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB2CFG);
> -
> -       /* Select DMA endianness (Host-endian: big-endian) */
> -       ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
> -
> -       /* Hard reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
> -
> -       /* Soft reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
> -}
> -
>  static int __init mips_reboot_setup(void)
>  {
>         struct resource res;
> @@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
>         if (!ltq_rcu_membase)
>                 panic("Failed to remap core memory");
>
> -       if (of_machine_is_compatible("lantiq,ar9") ||
> -           of_machine_is_compatible("lantiq,vr9"))
> -               ltq_usb_init();
> -
>         _machine_restart = ltq_machine_restart;
>         _machine_halt = ltq_machine_halt;
>         pm_power_off = ltq_machine_power_off;
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 5764d3ddce69..18725f2d5b67 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
>
>         if (of_machine_is_compatible("lantiq,grx390") ||
>             of_machine_is_compatible("lantiq,ar10")) {
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
>                 /* rc 0 */
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
>                 else
>                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
>                                                 CLOCK_133M, CLOCK_133M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
>                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
>                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
> @@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,vr9")) {
>                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
>                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
> -               clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
>                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,ar9")) {
>                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
>                                 ltq_ar9_fpi_hz(), CLOCK_250M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
>                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
>                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
> @@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
>         } else {
>                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
>                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
>                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
>                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 005cadb7a3f8..dbb450e3ba04 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
>           Enable this to support the Broadcom Cygnus PCIe PHY.
>           If unsure, say N.
>
> +config PHY_LANTIQ_RCU_USB2
> +       tristate "Lantiq XWAY SoC RCU based USB PHY"
> +       depends on SOC_TYPE_XWAY
> +       depends on OF
> +       select GENERIC_PHY
> +       help
> +         Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
> +
>  source "drivers/phy/tegra/Kconfig"
>
>  config PHY_NS2_PCIE
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index dd8f3b5d2918..52631f5ac470 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210)            += phy-tusb1210.o
>  obj-$(CONFIG_PHY_BRCM_SATA)            += phy-brcm-sata.o
>  obj-$(CONFIG_PHY_PISTACHIO_USB)                += phy-pistachio-usb.o
>  obj-$(CONFIG_PHY_CYGNUS_PCIE)          += phy-bcm-cygnus-pcie.o
> +obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)      += phy-lantiq-rcu-usb2.o
>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>  obj-$(CONFIG_PHY_NS2_PCIE)             += phy-bcm-ns2-pcie.o
>  obj-$(CONFIG_PHY_MESON8B_USB2)         += phy-meson8b-usb2.o
> diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
> new file mode 100644
> index 000000000000..9bff42afd256
> --- /dev/null
> +++ b/drivers/phy/phy-lantiq-rcu-usb2.c
> @@ -0,0 +1,325 @@
> +/*
> + * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
> + *
> + * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
> + * Copyright (C) 2017 Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#define MAX_VBUS_GPIO          2
> +
> +/* Transmitter HS Pre-Emphasis Enable */
> +#define RCU_CFG1_TX_PEE                BIT(0)
> +/* Disconnect Threshold */
> +#define RCU_CFG1_DIS_THR_MASK  0x00038000
> +#define RCU_CFG1_DIS_THR_SHIFT 15
> +
> +struct ltq_rcu_usb2_bits {
> +       u8 hostmode;
> +       u8 slave_endianness;
> +       u8 host_endianness;
> +       bool have_ana_cfg;
> +};
> +
> +struct ltq_rcu_usb2_priv {
> +       struct regmap                   *regmap;
> +       u32                             phy_reg_offset;
> +       u32                             ana_cfg1_reg_offset;
> +       const struct ltq_rcu_usb2_bits  *reg_bits;
> +       struct device                   *dev;
> +       struct gpio_desc                *gpiod_vbus[MAX_VBUS_GPIO];
> +       struct phy                      *phy;
> +       struct clk                      *ctrl_gate_clk;
> +       struct clk                      *phy_gate_clk;
> +       struct reset_control            *ctrl_reset;
> +       struct reset_control            *phy_reset;
> +};
> +
> +static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 17,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = true,
> +};
> +
> +static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
> +       {
> +               .compatible = "lantiq,ase-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,danube-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx100-rcu-usb2-phy",
> +               .data = &xrx100_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx200-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx300-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
> +
> +static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
> +                                               int value)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++)
> +               if (!IS_ERR_OR_NULL(gpiods[i]))
> +                       gpiod_set_value(gpiods[i], value);
> +}
> +
> +static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       if (priv->phy_reset)
> +               reset_control_deassert(priv->phy_reset);
> +
> +       /* enable the port-specific VBUS GPIOs if available */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
as I mentioned in my previous mail, if you pass a fixed regulator then
the PHY framework handles this, see [1] (regulator_enable is called
right before .phy_power_on and regulator_disable is called right after
.phy_power_off)

> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       /*
> +        * only disable the port-specific VBUS GPIO here (if available), the
> +        * shared VBUS GPIO might still be used by another port
> +        */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +
> +       return 0;
> +}
> +
> +static struct phy_ops ltq_rcu_usb2_phy_ops = {
> +       .power_on       = ltq_rcu_usb2_phy_power_on,
> +       .power_off      = ltq_rcu_usb2_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
> +
> +       /* Power on the USB core. */
> +       if (clk_prepare_enable(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "failed to enable CTRL gate\n");
> +               return;
> +       }
> +
> +       /*
> +        * Power on the USB PHY. We have to do it early because
> +        * otherwise the second core won't turn on properly.
> +        */
> +       if (clk_prepare_enable(priv->phy_gate_clk)) {
> +               dev_err(dev, "failed to enable PHY gate\n");
> +               return;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
> +       }
> +
> +       /* Configure core to host mode */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +                          BIT(priv->reg_bits->hostmode), 0);
> +
> +       /* Select DMA endianness (Host-endian: big-endian) */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->slave_endianness), 0);
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->host_endianness),
> +               BIT(priv->reg_bits->host_endianness));
> +
> +       /* Reset USB core throgh reset controller */
> +       reset_control_deassert(priv->ctrl_reset);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +}
> +
> +static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
> +                                         struct gpio_desc **gpios)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++) {
> +               gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
> +                                                        GPIOD_OUT_LOW);
> +               if (IS_ERR(gpios[i]))
> +                       return PTR_ERR(gpios[i]);
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
> +                                   struct ltq_rcu_usb2_priv *priv)
> +{
> +       struct device *dev = priv->dev;
> +       const struct of_device_id *match =
> +               of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
> +       int ret;
> +
> +       if (!match) {
> +               dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->reg_bits = match->data;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
> +                                                      "lantiq,rcu-syscon");
> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(dev, "Failed to lookup RCU regmap\n");
> +               return PTR_ERR(priv->regmap);
> +       }
> +
> +       ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
> +       if (ret) {
> +               dev_err(dev, "failed to request shared USB VBUS GPIO\n");
> +               return ret;
> +       }
> +
> +       priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "Unable to get USB ctrl gate clk\n");
> +               return PTR_ERR(priv->ctrl_gate_clk);
> +       }
> +
> +       priv->phy_gate_clk = devm_clk_get(dev, "phy");
> +       if (IS_ERR(priv->phy_gate_clk)) {
> +               dev_err(dev, "Unable to get USB phy gate clk\n");
> +               return PTR_ERR(priv->phy_gate_clk);
> +       }
> +
> +       priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_reset)) {
> +               dev_err(dev, "failed to get 'ctrl' reset\n");
> +               return PTR_ERR(priv->ctrl_reset);
> +       }
> +
> +       priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
> +       if (IS_ERR(priv->phy_reset)) {
> +               if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
> +                       return PTR_ERR(priv->phy_reset);
> +               priv->phy_reset = NULL;
> +       }
a recent reset controller framework improvement allows us to make this
much easier as:
"As of commit bb475230b8e5 ("reset: make optional functions really
optional"), the reset framework API calls use NULL pointers to describe
optional, non-present reset controls." (see [0])
so we can basically turn this into IS_ERR() then return PTR_ERR()

> +       ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
> +                                        &priv->phy_reg_offset);
> +       if (ret) {
> +               dev_err(dev, "Failed to get RCU PHY reg offset\n");
> +               return ret;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
> +                                                2, &priv->ana_cfg1_reg_offset);
> +               if (ret) {
> +                       dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
> +{
> +       struct device_node *child, *np = pdev->dev.of_node;
> +       struct ltq_rcu_usb2_priv *priv;
> +       struct phy_provider *provider;
> +       int ret;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
> +                                      GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = &pdev->dev;
> +       dev_set_drvdata(priv->dev, priv);
> +
> +       ret = ltq_rcu_usb2_of_probe(np, priv);
> +       if (ret)
> +               return ret;
> +
> +       priv->phy = devm_phy_create(&pdev->dev, child,
> +                                        &ltq_rcu_usb2_phy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(&pdev->dev, "failed to create PHY\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       ltq_rcu_usb2_start_cores(pdev);
> +
> +       provider = devm_of_phy_provider_register(&pdev->dev,
> +                                                of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver ltq_rcu_usb2_phy_driver = {
> +       .probe  = ltq_rcu_usb2_phy_probe,
> +       .driver = {
> +               .name   = "lantiq-rcu-usb2-phy",
> +               .of_match_table = ltq_rcu_usb2_phy_of_match,
> +       }
> +};
> +module_platform_driver(ltq_rcu_usb2_phy_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>");
> +MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.11.0
>

[0] https://patchwork.kernel.org/patch/9545031/
[1] http://lxr.free-electrons.com/source/drivers/phy/phy-core.c#L276
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Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Martin Blumenstingl]

On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>
> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
> the PHY interfaces for each core. The phy instances can be passed to the
> dwc2 driver, which already supports the generic phy interface.
>
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> ---
>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>  6 files changed, 405 insertions(+), 55 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> new file mode 100644
> index 000000000000..0ec9f790b6e0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
> @@ -0,0 +1,59 @@
> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
> +===========================================
> +
> +This binding describes the USB PHY hardware provided by the RCU module on the
> +Lantiq XWAY SoCs.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (controller (parent) node):
> +- compatible           : Should be one of
> +                               "lantiq,ase-rcu-usb2-phy"
> +                               "lantiq,danube-rcu-usb2-phy"
> +                               "lantiq,xrx100-rcu-usb2-phy"
> +                               "lantiq,xrx200-rcu-usb2-phy"
> +                               "lantiq,xrx300-rcu-usb2-phy"
> +- lantiq,rcu-syscon    : A phandle to the RCU module and the offsets to the
> +                         USB PHY configuration and USB MAC registers.
> +- address-cells                : should be 1
> +- size-cells           : should be 0
> +- phy-cells            : from the generic PHY bindings, must be 1
> +
> +Optional properties (controller (parent) node):
> +- vbus-gpio            : References a GPIO which enables VBUS all given USB
> +                         ports.
> +
> +Required nodes         :  A sub-node is required for each USB PHY port.
> +
> +
> +-------------------------------------------------------------------------------
> +Required properties (port (child) node):
> +- reg          : The ID of the USB port, usually 0 or 1.
> +- clocks       : References to the (PMU) "ctrl" and "phy" clk gates.
> +- clock-names  : Must be one of the following:
> +                       "ctrl"
> +                       "phy"
> +- resets       : References to the RCU USB configuration reset bits.
> +- reset-names  : Must be one of the following:
> +                       "analog-config" (optional)
> +                       "statemachine-soft" (optional)
> +
> +Optional properties (port (child) node):
> +- vbus-gpio    : References a GPIO which enables VBUS for the USB port.
> +
> +
> +-------------------------------------------------------------------------------
> +Example for the USB PHYs on an xRX200 SoC:
> +       usb_phys0: rcu-usb2-phy@0 {
> +               compatible      = "lantiq,xrx200-rcu-usb2-phy";
> +               reg = <0>;
> +
> +               lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
> +               clocks = <&pmu PMU_GATE_USB0_CTRL>,
> +                        <&pmu PMU_GATE_USB0_PHY>;
> +               clock-names = "ctrl", "phy";
> +               vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
> +               resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
> +               reset-names = "phy", "ctrl";
> +               #phy-cells = <0>;
> +       };
> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
> index 3f30fb81a50f..5aec1f54275b 100644
> --- a/arch/mips/lantiq/xway/reset.c
> +++ b/arch/mips/lantiq/xway/reset.c
> @@ -124,45 +124,6 @@ static void ltq_machine_power_off(void)
>         unreachable();
>  }
>
> -static void ltq_usb_init(void)
> -{
> -       /* Power for USB cores 1 & 2 */
> -       ltq_pmu_enable(PMU_AHBM);
> -       ltq_pmu_enable(PMU_USB0);
> -       ltq_pmu_enable(PMU_USB1);
> -
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
> -
> -       /* Enable USB PHY power for cores 1 & 2 */
> -       ltq_pmu_enable(PMU_USB0_P);
> -       ltq_pmu_enable(PMU_USB1_P);
> -
> -       /* Configure cores to host mode */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
> -               RCU_USB2CFG);
> -
> -       /* Select DMA endianness (Host-endian: big-endian) */
> -       ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
> -       ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
> -               | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
> -
> -       /* Hard reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
> -
> -       /* Soft reset USB state machines */
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
> -       udelay(50 * 1000);
> -       ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
> -               & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
> -}
> -
>  static int __init mips_reboot_setup(void)
>  {
>         struct resource res;
> @@ -186,10 +147,6 @@ static int __init mips_reboot_setup(void)
>         if (!ltq_rcu_membase)
>                 panic("Failed to remap core memory");
>
> -       if (of_machine_is_compatible("lantiq,ar9") ||
> -           of_machine_is_compatible("lantiq,vr9"))
> -               ltq_usb_init();
> -
>         _machine_restart = ltq_machine_restart;
>         _machine_halt = ltq_machine_halt;
>         pm_power_off = ltq_machine_power_off;
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 5764d3ddce69..18725f2d5b67 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -469,8 +469,8 @@ void __init ltq_soc_init(void)
>
>         if (of_machine_is_compatible("lantiq,grx390") ||
>             of_machine_is_compatible("lantiq,ar10")) {
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 2, PMU_ANALOG_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 2, PMU_ANALOG_USB1_P);
>                 /* rc 0 */
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -490,8 +490,8 @@ void __init ltq_soc_init(void)
>                 else
>                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
>                                                 CLOCK_133M, CLOCK_133M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
>                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
>                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
> @@ -525,10 +525,10 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,vr9")) {
>                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
>                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
> -               clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
> -               clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0 | PMU_AHBM);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "phy", 1, 0, PMU_USB1_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@1", "ctrl", 1, 0, PMU_USB1 | PMU_AHBM);
>                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
>                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
>                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
> @@ -548,8 +548,8 @@ void __init ltq_soc_init(void)
>         } else if (of_machine_is_compatible("lantiq,ar9")) {
>                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
>                                 ltq_ar9_fpi_hz(), CLOCK_250M);
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
>                 clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
>                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
> @@ -560,8 +560,8 @@ void __init ltq_soc_init(void)
>         } else {
>                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
>                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
> -               clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
> -               clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "ctrl", 1, 0, PMU_USB0);
> +               clkdev_add_pmu("1f203000.rcu:rcu-usb2-phy@0", "phy", 1, 0, PMU_USB0_P);
>                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
>                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
>                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 005cadb7a3f8..dbb450e3ba04 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -488,6 +488,14 @@ config PHY_CYGNUS_PCIE
>           Enable this to support the Broadcom Cygnus PCIe PHY.
>           If unsure, say N.
>
> +config PHY_LANTIQ_RCU_USB2
> +       tristate "Lantiq XWAY SoC RCU based USB PHY"
> +       depends on SOC_TYPE_XWAY
> +       depends on OF
> +       select GENERIC_PHY
> +       help
> +         Support for the USB PHY(s) on the Lantiq XWAY family SoCs.
> +
>  source "drivers/phy/tegra/Kconfig"
>
>  config PHY_NS2_PCIE
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index dd8f3b5d2918..52631f5ac470 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_PHY_TUSB1210)            += phy-tusb1210.o
>  obj-$(CONFIG_PHY_BRCM_SATA)            += phy-brcm-sata.o
>  obj-$(CONFIG_PHY_PISTACHIO_USB)                += phy-pistachio-usb.o
>  obj-$(CONFIG_PHY_CYGNUS_PCIE)          += phy-bcm-cygnus-pcie.o
> +obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)      += phy-lantiq-rcu-usb2.o
>  obj-$(CONFIG_ARCH_TEGRA) += tegra/
>  obj-$(CONFIG_PHY_NS2_PCIE)             += phy-bcm-ns2-pcie.o
>  obj-$(CONFIG_PHY_MESON8B_USB2)         += phy-meson8b-usb2.o
> diff --git a/drivers/phy/phy-lantiq-rcu-usb2.c b/drivers/phy/phy-lantiq-rcu-usb2.c
> new file mode 100644
> index 000000000000..9bff42afd256
> --- /dev/null
> +++ b/drivers/phy/phy-lantiq-rcu-usb2.c
> @@ -0,0 +1,325 @@
> +/*
> + * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
> + *
> + * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> + * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +
> +#define MAX_VBUS_GPIO          2
> +
> +/* Transmitter HS Pre-Emphasis Enable */
> +#define RCU_CFG1_TX_PEE                BIT(0)
> +/* Disconnect Threshold */
> +#define RCU_CFG1_DIS_THR_MASK  0x00038000
> +#define RCU_CFG1_DIS_THR_SHIFT 15
> +
> +struct ltq_rcu_usb2_bits {
> +       u8 hostmode;
> +       u8 slave_endianness;
> +       u8 host_endianness;
> +       bool have_ana_cfg;
> +};
> +
> +struct ltq_rcu_usb2_priv {
> +       struct regmap                   *regmap;
> +       u32                             phy_reg_offset;
> +       u32                             ana_cfg1_reg_offset;
> +       const struct ltq_rcu_usb2_bits  *reg_bits;
> +       struct device                   *dev;
> +       struct gpio_desc                *gpiod_vbus[MAX_VBUS_GPIO];
> +       struct phy                      *phy;
> +       struct clk                      *ctrl_gate_clk;
> +       struct clk                      *phy_gate_clk;
> +       struct reset_control            *ctrl_reset;
> +       struct reset_control            *phy_reset;
> +};
> +
> +static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 17,
> +       .host_endianness = 10,
> +       .have_ana_cfg = false,
> +};
> +
> +static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
> +       .hostmode = 11,
> +       .slave_endianness = 9,
> +       .host_endianness = 10,
> +       .have_ana_cfg = true,
> +};
> +
> +static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
> +       {
> +               .compatible = "lantiq,ase-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,danube-rcu-usb2-phy",
> +               .data = &xway_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx100-rcu-usb2-phy",
> +               .data = &xrx100_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx200-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       {
> +               .compatible = "lantiq,xrx300-rcu-usb2-phy",
> +               .data = &xrx200_rcu_usb2_reg_bits,
> +       },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
> +
> +static void ltq_rcu_usb2_set_vbus_gpio_value(struct gpio_desc **gpiods,
> +                                               int value)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++)
> +               if (!IS_ERR_OR_NULL(gpiods[i]))
> +                       gpiod_set_value(gpiods[i], value);
> +}
> +
> +static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       if (priv->phy_reset)
> +               reset_control_deassert(priv->phy_reset);
> +
> +       /* enable the port-specific VBUS GPIOs if available */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 1);
as I mentioned in my previous mail, if you pass a fixed regulator then
the PHY framework handles this, see [1] (regulator_enable is called
right before .phy_power_on and regulator_disable is called right after
.phy_power_off)

> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
> +{
> +       struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
> +
> +       /*
> +        * only disable the port-specific VBUS GPIO here (if available), the
> +        * shared VBUS GPIO might still be used by another port
> +        */
> +       ltq_rcu_usb2_set_vbus_gpio_value(priv->gpiod_vbus, 0);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +
> +       return 0;
> +}
> +
> +static struct phy_ops ltq_rcu_usb2_phy_ops = {
> +       .power_on       = ltq_rcu_usb2_phy_power_on,
> +       .power_off      = ltq_rcu_usb2_phy_power_off,
> +       .owner          = THIS_MODULE,
> +};
> +
> +static void ltq_rcu_usb2_start_cores(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct ltq_rcu_usb2_priv *priv = dev_get_drvdata(dev);
> +
> +       /* Power on the USB core. */
> +       if (clk_prepare_enable(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "failed to enable CTRL gate\n");
> +               return;
> +       }
> +
> +       /*
> +        * Power on the USB PHY. We have to do it early because
> +        * otherwise the second core won't turn on properly.
> +        */
> +       if (clk_prepare_enable(priv->phy_gate_clk)) {
> +               dev_err(dev, "failed to enable PHY gate\n");
> +               return;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
> +               regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
> +                       RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
> +       }
> +
> +       /* Configure core to host mode */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +                          BIT(priv->reg_bits->hostmode), 0);
> +
> +       /* Select DMA endianness (Host-endian: big-endian) */
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->slave_endianness), 0);
> +       regmap_update_bits(priv->regmap, priv->phy_reg_offset,
> +               BIT(priv->reg_bits->host_endianness),
> +               BIT(priv->reg_bits->host_endianness));
> +
> +       /* Reset USB core throgh reset controller */
> +       reset_control_deassert(priv->ctrl_reset);
> +
> +       if (priv->phy_reset)
> +               reset_control_assert(priv->phy_reset);
> +}
> +
> +static int ltq_rcu_usb2_get_vbus_gpios(struct device *dev,
> +                                         struct gpio_desc **gpios)
> +{
> +       int i;
> +
> +       for (i = 0; i < MAX_VBUS_GPIO; i++) {
> +               gpios[i] = devm_gpiod_get_index_optional(dev, "vbus", i,
> +                                                        GPIOD_OUT_LOW);
> +               if (IS_ERR(gpios[i]))
> +                       return PTR_ERR(gpios[i]);
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_of_probe(struct device_node *phynode,
> +                                   struct ltq_rcu_usb2_priv *priv)
> +{
> +       struct device *dev = priv->dev;
> +       const struct of_device_id *match =
> +               of_match_node(ltq_rcu_usb2_phy_of_match, phynode);
> +       int ret;
> +
> +       if (!match) {
> +               dev_err(dev, "Not a compatible Lantiq RCU USB PHY\n");
> +               return -EINVAL;
> +       }
> +
> +       priv->reg_bits = match->data;
> +
> +       priv->regmap = syscon_regmap_lookup_by_phandle(phynode,
> +                                                      "lantiq,rcu-syscon");
> +       if (IS_ERR(priv->regmap)) {
> +               dev_err(dev, "Failed to lookup RCU regmap\n");
> +               return PTR_ERR(priv->regmap);
> +       }
> +
> +       ret = ltq_rcu_usb2_get_vbus_gpios(dev, priv->gpiod_vbus);
> +       if (ret) {
> +               dev_err(dev, "failed to request shared USB VBUS GPIO\n");
> +               return ret;
> +       }
> +
> +       priv->ctrl_gate_clk = devm_clk_get(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_gate_clk)) {
> +               dev_err(dev, "Unable to get USB ctrl gate clk\n");
> +               return PTR_ERR(priv->ctrl_gate_clk);
> +       }
> +
> +       priv->phy_gate_clk = devm_clk_get(dev, "phy");
> +       if (IS_ERR(priv->phy_gate_clk)) {
> +               dev_err(dev, "Unable to get USB phy gate clk\n");
> +               return PTR_ERR(priv->phy_gate_clk);
> +       }
> +
> +       priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
> +       if (IS_ERR(priv->ctrl_reset)) {
> +               dev_err(dev, "failed to get 'ctrl' reset\n");
> +               return PTR_ERR(priv->ctrl_reset);
> +       }
> +
> +       priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
> +       if (IS_ERR(priv->phy_reset)) {
> +               if (PTR_ERR(priv->phy_reset) == -EPROBE_DEFER)
> +                       return PTR_ERR(priv->phy_reset);
> +               priv->phy_reset = NULL;
> +       }
a recent reset controller framework improvement allows us to make this
much easier as:
"As of commit bb475230b8e5 ("reset: make optional functions really
optional"), the reset framework API calls use NULL pointers to describe
optional, non-present reset controls." (see [0])
so we can basically turn this into IS_ERR() then return PTR_ERR()

> +       ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon", 1,
> +                                        &priv->phy_reg_offset);
> +       if (ret) {
> +               dev_err(dev, "Failed to get RCU PHY reg offset\n");
> +               return ret;
> +       }
> +
> +       if (priv->reg_bits->have_ana_cfg) {
> +               ret = of_property_read_u32_index(phynode, "lantiq,rcu-syscon",
> +                                                2, &priv->ana_cfg1_reg_offset);
> +               if (ret) {
> +                       dev_dbg(dev, "Failed to get RCU ANA CFG1 reg offset\n");
> +                       return ret;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
> +{
> +       struct device_node *child, *np = pdev->dev.of_node;
> +       struct ltq_rcu_usb2_priv *priv;
> +       struct phy_provider *provider;
> +       int ret;
> +
> +       priv = devm_kzalloc(&pdev->dev, sizeof(*priv),
> +                                      GFP_KERNEL);
> +       if (!priv)
> +               return -ENOMEM;
> +
> +       priv->dev = &pdev->dev;
> +       dev_set_drvdata(priv->dev, priv);
> +
> +       ret = ltq_rcu_usb2_of_probe(np, priv);
> +       if (ret)
> +               return ret;
> +
> +       priv->phy = devm_phy_create(&pdev->dev, child,
> +                                        &ltq_rcu_usb2_phy_ops);
> +       if (IS_ERR(priv->phy)) {
> +               dev_err(&pdev->dev, "failed to create PHY\n");
> +               return PTR_ERR(priv->phy);
> +       }
> +
> +       phy_set_drvdata(priv->phy, priv);
> +
> +       ltq_rcu_usb2_start_cores(pdev);
> +
> +       provider = devm_of_phy_provider_register(&pdev->dev,
> +                                                of_phy_simple_xlate);
> +
> +       return PTR_ERR_OR_ZERO(provider);
> +}
> +
> +static struct platform_driver ltq_rcu_usb2_phy_driver = {
> +       .probe  = ltq_rcu_usb2_phy_probe,
> +       .driver = {
> +               .name   = "lantiq-rcu-usb2-phy",
> +               .of_match_table = ltq_rcu_usb2_phy_of_match,
> +       }
> +};
> +module_platform_driver(ltq_rcu_usb2_phy_driver);
> +
> +MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
> +MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.11.0
>

[0] https://patchwork.kernel.org/patch/9545031/
[1] http://lxr.free-electrons.com/source/drivers/phy/phy-core.c#L276

Re: [04/13] watchdog: lantiq: access boot cause register through regmap

[Guenter Roeck]

On Mon, Apr 17, 2017 at 09:29:33PM +0200, Hauke Mehrtens wrote:
> This patch avoids accessing the function ltq_reset_cause() and directly
> accesses the register given over the syscon interface. The syscon
> interface will be implemented for the xway SoCs for the falcon SoCs the
> ltq_reset_cause() function never worked, because a wrong offset was used.
> 
> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>

Acked-by: Guenter Roeck <linux-cYGBoTPqujPR7s880joybQ@public.gmane.org>

> ---
>  drivers/watchdog/lantiq_wdt.c | 47 +++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
> index e0823677d8c1..0e349ad03fdf 100644
> --- a/drivers/watchdog/lantiq_wdt.c
> +++ b/drivers/watchdog/lantiq_wdt.c
> @@ -17,9 +17,14 @@
>  #include <linux/uaccess.h>
>  #include <linux/clk.h>
>  #include <linux/io.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
>  
>  #include <lantiq_soc.h>
>  
> +#define LTQ_RST_CAUSE_WDT_XRX		BIT(31)
> +#define LTQ_RST_CAUSE_WDT_FALCON	0x02
> +
>  /*
>   * Section 3.4 of the datasheet
>   * The password sequence protects the WDT control register from unintended
> @@ -186,6 +191,40 @@ static struct miscdevice ltq_wdt_miscdev = {
>  	.fops	= &ltq_wdt_fops,
>  };
>  
> +static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct regmap *rcu_regmap;
> +	u32 status_reg_offset;
> +	u32 val;
> +	int err;
> +
> +	rcu_regmap = syscon_regmap_lookup_by_phandle(np,
> +						     "lantiq,rcu-syscon");
> +	if (IS_ERR_OR_NULL(rcu_regmap))
> +		return;
> +
> +	err = of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
> +					 &status_reg_offset);
> +	if (err) {
> +		dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
> +		return;
> +	}
> +
> +	err = regmap_read(rcu_regmap, status_reg_offset, &val);
> +	if (err)
> +		return;
> +
> +	/* find out if the watchdog caused the last reboot */
> +	if (of_device_is_compatible(np, "lantiq,wdt-xrx100")) {
> +		if (val & LTQ_RST_CAUSE_WDT_XRX)
> +			ltq_wdt_bootstatus = WDIOF_CARDRESET;
> +	} else if  (of_device_is_compatible(np, "lantiq,wdt-falcon")) {
> +		if ((val & 0x7) == LTQ_RST_CAUSE_WDT_FALCON)
> +			ltq_wdt_bootstatus = WDIOF_CARDRESET;
> +	}
> +}
> +
>  static int
>  ltq_wdt_probe(struct platform_device *pdev)
>  {
> @@ -205,9 +244,7 @@ ltq_wdt_probe(struct platform_device *pdev)
>  	ltq_io_region_clk_rate = clk_get_rate(clk);
>  	clk_put(clk);
>  
> -	/* find out if the watchdog caused the last reboot */
> -	if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
> -		ltq_wdt_bootstatus = WDIOF_CARDRESET;
> +	ltq_set_wdt_bootstatus(pdev);
>  
>  	dev_info(&pdev->dev, "Init done\n");
>  	return misc_register(&ltq_wdt_miscdev);
> @@ -222,7 +259,9 @@ ltq_wdt_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id ltq_wdt_match[] = {
> -	{ .compatible = "lantiq,wdt" },
> +	{ .compatible = "lantiq,wdt"},
> +	{ .compatible = "lantiq,wdt-xrx100"},
> +	{ .compatible = "lantiq,wdt-falcon"},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, ltq_wdt_match);
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Re: [04/13] watchdog: lantiq: access boot cause register through regmap

[Guenter Roeck]

On Mon, Apr 17, 2017 at 09:29:33PM +0200, Hauke Mehrtens wrote:
> This patch avoids accessing the function ltq_reset_cause() and directly
> accesses the register given over the syscon interface. The syscon
> interface will be implemented for the xway SoCs for the falcon SoCs the
> ltq_reset_cause() function never worked, because a wrong offset was used.
> 
> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

Acked-by: Guenter Roeck <linux@reck-us.net>

> ---
>  drivers/watchdog/lantiq_wdt.c | 47 +++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
> index e0823677d8c1..0e349ad03fdf 100644
> --- a/drivers/watchdog/lantiq_wdt.c
> +++ b/drivers/watchdog/lantiq_wdt.c
> @@ -17,9 +17,14 @@
>  #include <linux/uaccess.h>
>  #include <linux/clk.h>
>  #include <linux/io.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
>  
>  #include <lantiq_soc.h>
>  
> +#define LTQ_RST_CAUSE_WDT_XRX		BIT(31)
> +#define LTQ_RST_CAUSE_WDT_FALCON	0x02
> +
>  /*
>   * Section 3.4 of the datasheet
>   * The password sequence protects the WDT control register from unintended
> @@ -186,6 +191,40 @@ static struct miscdevice ltq_wdt_miscdev = {
>  	.fops	= &ltq_wdt_fops,
>  };
>  
> +static void ltq_set_wdt_bootstatus(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct regmap *rcu_regmap;
> +	u32 status_reg_offset;
> +	u32 val;
> +	int err;
> +
> +	rcu_regmap = syscon_regmap_lookup_by_phandle(np,
> +						     "lantiq,rcu-syscon");
> +	if (IS_ERR_OR_NULL(rcu_regmap))
> +		return;
> +
> +	err = of_property_read_u32_index(np, "lantiq,rcu-syscon", 1,
> +					 &status_reg_offset);
> +	if (err) {
> +		dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
> +		return;
> +	}
> +
> +	err = regmap_read(rcu_regmap, status_reg_offset, &val);
> +	if (err)
> +		return;
> +
> +	/* find out if the watchdog caused the last reboot */
> +	if (of_device_is_compatible(np, "lantiq,wdt-xrx100")) {
> +		if (val & LTQ_RST_CAUSE_WDT_XRX)
> +			ltq_wdt_bootstatus = WDIOF_CARDRESET;
> +	} else if  (of_device_is_compatible(np, "lantiq,wdt-falcon")) {
> +		if ((val & 0x7) == LTQ_RST_CAUSE_WDT_FALCON)
> +			ltq_wdt_bootstatus = WDIOF_CARDRESET;
> +	}
> +}
> +
>  static int
>  ltq_wdt_probe(struct platform_device *pdev)
>  {
> @@ -205,9 +244,7 @@ ltq_wdt_probe(struct platform_device *pdev)
>  	ltq_io_region_clk_rate = clk_get_rate(clk);
>  	clk_put(clk);
>  
> -	/* find out if the watchdog caused the last reboot */
> -	if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
> -		ltq_wdt_bootstatus = WDIOF_CARDRESET;
> +	ltq_set_wdt_bootstatus(pdev);
>  
>  	dev_info(&pdev->dev, "Init done\n");
>  	return misc_register(&ltq_wdt_miscdev);
> @@ -222,7 +259,9 @@ ltq_wdt_remove(struct platform_device *pdev)
>  }
>  
>  static const struct of_device_id ltq_wdt_match[] = {
> -	{ .compatible = "lantiq,wdt" },
> +	{ .compatible = "lantiq,wdt"},
> +	{ .compatible = "lantiq,wdt-xrx100"},
> +	{ .compatible = "lantiq,wdt-falcon"},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, ltq_wdt_match);

Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Hauke Mehrtens]

On 04/17/2017 11:23 PM, Martin Blumenstingl wrote:
> On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
> you should probably send this patch to the PHY maintainer as well
> (Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>)
> 
>> ---
>>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>>  drivers/phy/Kconfig                                |   8 +
>>  drivers/phy/Makefile                               |   1 +
>>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>>  6 files changed, 405 insertions(+), 55 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> new file mode 100644
>> index 000000000000..0ec9f790b6e0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> @@ -0,0 +1,59 @@
>> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
>> +===========================================
>> +
>> +This binding describes the USB PHY hardware provided by the RCU module on the
>> +Lantiq XWAY SoCs.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible           : Should be one of
>> +                               "lantiq,ase-rcu-usb2-phy"
>> +                               "lantiq,danube-rcu-usb2-phy"
>> +                               "lantiq,xrx100-rcu-usb2-phy"
>> +                               "lantiq,xrx200-rcu-usb2-phy"
>> +                               "lantiq,xrx300-rcu-usb2-phy"
>> +- lantiq,rcu-syscon    : A phandle to the RCU module and the offsets to the
>> +                         USB PHY configuration and USB MAC registers.
>> +- address-cells                : should be 1
>> +- size-cells           : should be 0
>> +- phy-cells            : from the generic PHY bindings, must be 1
>> +
>> +Optional properties (controller (parent) node):
>> +- vbus-gpio            : References a GPIO which enables VBUS all given USB
>> +                         ports.
> the PHY framework already handles this if you wrap the GPIO in a
> "regulator-fixed" node, see [0] how to define a fixed regulator with a
> GPIO (the regulator in this example has two states: off = 0V and on =
> 5V, probably exactly what you need) and [1] how to pass it to the PHY
> (phy-core.c handles this already, no driver specific code needed)

Thanksy, I will change the code and use a regulator.

......

>> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
>> index 3f30fb81a50f..5aec1f54275b 100644
>> --- a/arch/mips/lantiq/xway/reset.c
>> +++ b/arch/mips/lantiq/xway/reset.c
> could these arch/mips/lantiq/xway/reset.c changes to into PATCH #3 as well?

I do not get this.

......

> [0] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L67
> [1] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L133
> 
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Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Hauke Mehrtens]

On 04/17/2017 11:23 PM, Martin Blumenstingl wrote:
> On Mon, Apr 17, 2017 at 9:29 PM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
> you should probably send this patch to the PHY maintainer as well
> (Kishon Vijay Abraham I <kishon@ti.com>)
> 
>> ---
>>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>>  drivers/phy/Kconfig                                |   8 +
>>  drivers/phy/Makefile                               |   1 +
>>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>>  6 files changed, 405 insertions(+), 55 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> new file mode 100644
>> index 000000000000..0ec9f790b6e0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> @@ -0,0 +1,59 @@
>> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
>> +===========================================
>> +
>> +This binding describes the USB PHY hardware provided by the RCU module on the
>> +Lantiq XWAY SoCs.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible           : Should be one of
>> +                               "lantiq,ase-rcu-usb2-phy"
>> +                               "lantiq,danube-rcu-usb2-phy"
>> +                               "lantiq,xrx100-rcu-usb2-phy"
>> +                               "lantiq,xrx200-rcu-usb2-phy"
>> +                               "lantiq,xrx300-rcu-usb2-phy"
>> +- lantiq,rcu-syscon    : A phandle to the RCU module and the offsets to the
>> +                         USB PHY configuration and USB MAC registers.
>> +- address-cells                : should be 1
>> +- size-cells           : should be 0
>> +- phy-cells            : from the generic PHY bindings, must be 1
>> +
>> +Optional properties (controller (parent) node):
>> +- vbus-gpio            : References a GPIO which enables VBUS all given USB
>> +                         ports.
> the PHY framework already handles this if you wrap the GPIO in a
> "regulator-fixed" node, see [0] how to define a fixed regulator with a
> GPIO (the regulator in this example has two states: off = 0V and on =
> 5V, probably exactly what you need) and [1] how to pass it to the PHY
> (phy-core.c handles this already, no driver specific code needed)

Thanksy, I will change the code and use a regulator.

......

>> diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
>> index 3f30fb81a50f..5aec1f54275b 100644
>> --- a/arch/mips/lantiq/xway/reset.c
>> +++ b/arch/mips/lantiq/xway/reset.c
> could these arch/mips/lantiq/xway/reset.c changes to into PATCH #3 as well?

I do not get this.

......

> [0] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L67
> [1] https://github.com/torvalds/linux/blob/2fbbc4bf69f293df317559a267f4120f290b8fc4/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi#L133
> 

Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Hauke Mehrtens]

On 04/20/2017 04:48 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:35PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> This allows using the xbar driver on ARX300 based SoCs which require the
>> same xbar setup as the xRX200 chipsets because the xbar driver
>> initialization is not guarded by an xRX200 specific
>> of_machine_is_compatible condition anymore. Additionally the new driver
>> takes a syscon phandle to configure the XBAR endianness bits in RCU
>> (before this was done in arch/mips/lantiq/xway/reset.c and also
>> guarded by an xRX200 specific if-statement).
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> ---
>>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>>  MAINTAINERS                                        |   1 +
>>  arch/mips/lantiq/xway/reset.c                      |   4 -
>>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>>  drivers/soc/Makefile                               |   1 +
>>  drivers/soc/lantiq/Makefile                        |   1 +
>>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>>  7 files changed, 125 insertions(+), 45 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>  create mode 100644 drivers/soc/lantiq/Makefile
>>  create mode 100644 drivers/soc/lantiq/xbar.c
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>> new file mode 100644
>> index 000000000000..86e53ff3b0d5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>> @@ -0,0 +1,22 @@
>> +Lantiq XWAY SoC XBAR binding
>> +============================
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties:
>> +- compatible	: Should be "lantiq,xbar-xway"
> 
> This compatible is already in use so it is fine, but you should also 
> have per SoC compatible strings.

I will add a new SoC specific one.
What does per SoC device tree mean? Does it mean for the same silicon,
for the same silicon revision, for the same fusing of a silicon or for
the same marketing name?

I would like to make it per silicon or per silicon revision for the IP
cores which I know are different.

Hauke
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Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Hauke Mehrtens]

On 04/20/2017 04:48 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:35PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This allows using the xbar driver on ARX300 based SoCs which require the
>> same xbar setup as the xRX200 chipsets because the xbar driver
>> initialization is not guarded by an xRX200 specific
>> of_machine_is_compatible condition anymore. Additionally the new driver
>> takes a syscon phandle to configure the XBAR endianness bits in RCU
>> (before this was done in arch/mips/lantiq/xway/reset.c and also
>> guarded by an xRX200 specific if-statement).
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>> ---
>>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>>  MAINTAINERS                                        |   1 +
>>  arch/mips/lantiq/xway/reset.c                      |   4 -
>>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>>  drivers/soc/Makefile                               |   1 +
>>  drivers/soc/lantiq/Makefile                        |   1 +
>>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>>  7 files changed, 125 insertions(+), 45 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>  create mode 100644 drivers/soc/lantiq/Makefile
>>  create mode 100644 drivers/soc/lantiq/xbar.c
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>> new file mode 100644
>> index 000000000000..86e53ff3b0d5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>> @@ -0,0 +1,22 @@
>> +Lantiq XWAY SoC XBAR binding
>> +============================
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties:
>> +- compatible	: Should be "lantiq,xbar-xway"
> 
> This compatible is already in use so it is fine, but you should also 
> have per SoC compatible strings.

I will add a new SoC specific one.
What does per SoC device tree mean? Does it mean for the same silicon,
for the same silicon revision, for the same fusing of a silicon or for
the same marketing name?

I would like to make it per silicon or per silicon revision for the IP
cores which I know are different.

Hauke

Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Hauke Mehrtens]

On 04/20/2017 04:54 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:37PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> The reset controllers (on xRX200 and newer SoCs have two of them) are
>> provided by the RCU module. This was initially implemented as a simple
>> reset controller. However, the RCU module provides more functionality
>> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
>> The old reset controller driver implementation from
>> arch/mips/lantiq/xway/reset.c did not honor this fact.
>>
>> For some devices the request and the status bits are different.
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> ---
>>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>>  drivers/reset/Kconfig                              |   6 +
>>  drivers/reset/Makefile                             |   1 +
>>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>>  5 files changed, 281 insertions(+), 68 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>>
>> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>> new file mode 100644
>> index 000000000000..7f097d16bbb7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>> @@ -0,0 +1,43 @@
>> +Lantiq XWAY SoC RCU reset controller binding
>> +============================================
>> +
>> +This binding describes a reset-controller found on the RCU module on Lantiq
>> +XWAY SoCs.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible		: Should be "lantiq,rcu-reset"
>> +- lantiq,rcu-syscon	: A phandle to the RCU syscon, the reset register
>> +			  offset and the status register offset.
>> +- #reset-cells		: Specifies the number of cells needed to encode the
>> +			  reset line, should be 1.
>> +
>> +Optional properties:
>> +- reset-status		: The request status bit. For some bits the request bit
>> +			  and the status bit are different. This is depending
>> +			  on the SoC. If the reset-status bit does not match
>> +			  the reset-request bit, put the reset number into the
>> +			  reset-request property and the status bit at the same
>> +			  index into the reset-status property. If no
>> +			  reset-request bit is given here, the driver assume
>> +			  status and request bit are the same.
>> +- reset-request		: The reset request bit, to map it to the reset-status
>> +			  bit.
> 
> These should either be implied by SoC specific compatible or be made 
> part of the reset cells. In the latter case, you still need the SoC 
> specific compatible.

Currently the reset framework only supports a single reset cell to my
knowledge, but I haven't looked into the details, I could extend it to
make it support two.

The SoC which needs this has two reset control register sets and the
bits are specific for each register set. Would a specific compatible
string for each register set ok?

> 
>> +-------------------------------------------------------------------------------
>> +Example for the reset-controllers on the xRX200 SoCs:
>> +	rcu_reset0: rcu_reset {
>> +		compatible = "lantiq,rcu-reset";
>> +		lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
>> +		#reset-cells = <1>;
>> +		reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
>> +		reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
>> +	};
>> +
>> +	rcu_reset1: rcu_reset {
>> +		compatible = "lantiq,rcu-reset";
> 
> These 2 blocks are identical? Given different registers sizes, I'd say 
> not. So they should have different compatible strings.

I will remove the second one.

> 
>> +		lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
>> +		#reset-cells = <1>;
>> +	};
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Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Hauke Mehrtens]

On 04/20/2017 04:54 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:37PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> The reset controllers (on xRX200 and newer SoCs have two of them) are
>> provided by the RCU module. This was initially implemented as a simple
>> reset controller. However, the RCU module provides more functionality
>> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
>> The old reset controller driver implementation from
>> arch/mips/lantiq/xway/reset.c did not honor this fact.
>>
>> For some devices the request and the status bits are different.
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>> ---
>>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>>  drivers/reset/Kconfig                              |   6 +
>>  drivers/reset/Makefile                             |   1 +
>>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>>  5 files changed, 281 insertions(+), 68 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>>
>> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>> new file mode 100644
>> index 000000000000..7f097d16bbb7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>> @@ -0,0 +1,43 @@
>> +Lantiq XWAY SoC RCU reset controller binding
>> +============================================
>> +
>> +This binding describes a reset-controller found on the RCU module on Lantiq
>> +XWAY SoCs.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible		: Should be "lantiq,rcu-reset"
>> +- lantiq,rcu-syscon	: A phandle to the RCU syscon, the reset register
>> +			  offset and the status register offset.
>> +- #reset-cells		: Specifies the number of cells needed to encode the
>> +			  reset line, should be 1.
>> +
>> +Optional properties:
>> +- reset-status		: The request status bit. For some bits the request bit
>> +			  and the status bit are different. This is depending
>> +			  on the SoC. If the reset-status bit does not match
>> +			  the reset-request bit, put the reset number into the
>> +			  reset-request property and the status bit at the same
>> +			  index into the reset-status property. If no
>> +			  reset-request bit is given here, the driver assume
>> +			  status and request bit are the same.
>> +- reset-request		: The reset request bit, to map it to the reset-status
>> +			  bit.
> 
> These should either be implied by SoC specific compatible or be made 
> part of the reset cells. In the latter case, you still need the SoC 
> specific compatible.

Currently the reset framework only supports a single reset cell to my
knowledge, but I haven't looked into the details, I could extend it to
make it support two.

The SoC which needs this has two reset control register sets and the
bits are specific for each register set. Would a specific compatible
string for each register set ok?

> 
>> +-------------------------------------------------------------------------------
>> +Example for the reset-controllers on the xRX200 SoCs:
>> +	rcu_reset0: rcu_reset {
>> +		compatible = "lantiq,rcu-reset";
>> +		lantiq,rcu-syscon = <&rcu0 0x10 0x14>;
>> +		#reset-cells = <1>;
>> +		reset-request = <31>, <29>, <21>, <19>, <16>, <12>;
>> +		reset-status  = <30>, <28>, <16>, <25>, <5>,  <24>;
>> +	};
>> +
>> +	rcu_reset1: rcu_reset {
>> +		compatible = "lantiq,rcu-reset";
> 
> These 2 blocks are identical? Given different registers sizes, I'd say 
> not. So they should have different compatible strings.

I will remove the second one.

> 
>> +		lantiq,rcu-syscon = <&rcu0 0x48 0x24>;
>> +		#reset-cells = <1>;
>> +	};

Re: [PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd

[Hauke Mehrtens]

On 04/20/2017 05:27 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:38PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> Compared to the old xrx200_phy_fw driver the new version has multiple
>> enhancements. The name of the firmware files does not have to be added
>> to all .dts files anymore - one now configures the GPHY mode (FE or GE)
>> instead. Each GPHY can now also boot separate firmware (thus mixing of
>> GE and FE GPHYs is now possible).
>> The new implementation is based on the RCU syscon-mfd and uses the
>> reeset_controller framework instead of raw RCU register reads/writes.
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> ---
>>  .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++++
>>  arch/mips/lantiq/xway/sysctrl.c                    |   4 +-
>>  drivers/soc/lantiq/Makefile                        |   1 +
>>  drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++++++++++
>>  include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 ++
>>  5 files changed, 314 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>>  create mode 100644 drivers/soc/lantiq/gphy.c
>>  create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>> new file mode 100644
>> index 000000000000..d525c7ce9f0b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>> @@ -0,0 +1,54 @@
>> +Lantiq XWAY SoC GPHY binding
>> +============================
>> +
>> +This binding describes a software-defined ethernet PHY, provided by the RCU
>> +module on newer Lantiq XWAY SoCs (xRX200 and newer).
>> +This depends on binary firmware blobs which must be provided by userspace.
> 
> Where the blobs come from is not relevant. 
> 
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible		: Should be one of
>> +				"lantiq,xrx200a1x-rcu-gphy"
>> +				"lantiq,xrx200a2x-rcu-gphy"
>> +				"lantiq,xrx300-rcu-gphy"
>> +				"lantiq,xrx330-rcu-gphy"
>> +- lantiq,rcu-syscon	: A phandle and offset to the GPHY address registers in
>> +			  the RCU
>> +- resets		: Must reference the RCU GPHY reset bit
>> +- reset-names		: One entry, value must be "gphy" or optional "gphy2"
>> +
>> +Optional properties (port (child) node):
>> +- lantiq,gphy-mode	: GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
>> +			  <dt-bindings/mips/lantiq_xway_gphy.h>
>> +- clocks		: A reference to the (PMU) GPHY clock gate
>> +- clock-names		: If clocks is given then this must be "gphy"
> 
> Kind of pointless to have a name for a single clock.

The documentation misses the 2. clock. ;-) Will add it.
> 
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example for the GPHys on the xRX200 SoCs:
>> +
>> +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
>> +	gphy0: rcu_gphy@0 {
> 
> Use generic node names: phy@...

I will change this

> 
>> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +		reg = <0>;
>> +
>> +		lantiq,rcu-syscon = <&rcu0 0x20>;
> 
> Could the phy just be a child of the rcu? Then you don't need a phandle 
> here and 0x20 becomes the reg address.

The RCU is a register block which does many things. This register is
specific to this ghpy, but there are some register in the RCU block
which are shared between multiple drivers. Can I support both, provide
some parts of this block as syscon and some as direct register blocks?

> 
>> +		resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
>> +		reset-names = "gphy", "gphy2";
>> +		lantiq,gphy-mode = <GPHY_MODE_GE>;
>> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
>> +		clock-names = "gphy";
>> +	};
>> +
>> +	gphy1: rcu_gphy@1 {
>> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +		reg = <0>;
>> +
>> +		lantiq,rcu-syscon = <&rcu0 0x68>;
>> +		resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
>> +		reset-names = "gphy", "gphy2";
>> +		lantiq,gphy-mode = <GPHY_MODE_FE>;
>> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
>> +		clock-names = "gphy";
>> +	};
--
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Re: [PATCH 09/13] MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfd

[Hauke Mehrtens]

On 04/20/2017 05:27 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:38PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> Compared to the old xrx200_phy_fw driver the new version has multiple
>> enhancements. The name of the firmware files does not have to be added
>> to all .dts files anymore - one now configures the GPHY mode (FE or GE)
>> instead. Each GPHY can now also boot separate firmware (thus mixing of
>> GE and FE GPHYs is now possible).
>> The new implementation is based on the RCU syscon-mfd and uses the
>> reeset_controller framework instead of raw RCU register reads/writes.
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>> ---
>>  .../devicetree/bindings/mips/lantiq/rcu-gphy.txt   |  54 +++++
>>  arch/mips/lantiq/xway/sysctrl.c                    |   4 +-
>>  drivers/soc/lantiq/Makefile                        |   1 +
>>  drivers/soc/lantiq/gphy.c                          | 242 +++++++++++++++++++++
>>  include/dt-bindings/mips/lantiq_rcu_gphy.h         |  15 ++
>>  5 files changed, 314 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>>  create mode 100644 drivers/soc/lantiq/gphy.c
>>  create mode 100644 include/dt-bindings/mips/lantiq_rcu_gphy.h
>>
>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>> new file mode 100644
>> index 000000000000..d525c7ce9f0b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
>> @@ -0,0 +1,54 @@
>> +Lantiq XWAY SoC GPHY binding
>> +============================
>> +
>> +This binding describes a software-defined ethernet PHY, provided by the RCU
>> +module on newer Lantiq XWAY SoCs (xRX200 and newer).
>> +This depends on binary firmware blobs which must be provided by userspace.
> 
> Where the blobs come from is not relevant. 
> 
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible		: Should be one of
>> +				"lantiq,xrx200a1x-rcu-gphy"
>> +				"lantiq,xrx200a2x-rcu-gphy"
>> +				"lantiq,xrx300-rcu-gphy"
>> +				"lantiq,xrx330-rcu-gphy"
>> +- lantiq,rcu-syscon	: A phandle and offset to the GPHY address registers in
>> +			  the RCU
>> +- resets		: Must reference the RCU GPHY reset bit
>> +- reset-names		: One entry, value must be "gphy" or optional "gphy2"
>> +
>> +Optional properties (port (child) node):
>> +- lantiq,gphy-mode	: GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
>> +			  <dt-bindings/mips/lantiq_xway_gphy.h>
>> +- clocks		: A reference to the (PMU) GPHY clock gate
>> +- clock-names		: If clocks is given then this must be "gphy"
> 
> Kind of pointless to have a name for a single clock.

The documentation misses the 2. clock. ;-) Will add it.
> 
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example for the GPHys on the xRX200 SoCs:
>> +
>> +#include <dt-bindings/mips/lantiq_rcu_gphy.h>
>> +	gphy0: rcu_gphy@0 {
> 
> Use generic node names: phy@...

I will change this

> 
>> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +		reg = <0>;
>> +
>> +		lantiq,rcu-syscon = <&rcu0 0x20>;
> 
> Could the phy just be a child of the rcu? Then you don't need a phandle 
> here and 0x20 becomes the reg address.

The RCU is a register block which does many things. This register is
specific to this ghpy, but there are some register in the RCU block
which are shared between multiple drivers. Can I support both, provide
some parts of this block as syscon and some as direct register blocks?

> 
>> +		resets = <&rcu_reset0 31>, <&rcu_reset1 7>;
>> +		reset-names = "gphy", "gphy2";
>> +		lantiq,gphy-mode = <GPHY_MODE_GE>;
>> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
>> +		clock-names = "gphy";
>> +	};
>> +
>> +	gphy1: rcu_gphy@1 {
>> +		compatible = "lantiq,xrx200a2x-rcu-gphy";
>> +		reg = <0>;
>> +
>> +		lantiq,rcu-syscon = <&rcu0 0x68>;
>> +		resets = <&rcu_reset0 29>, <&rcu_reset1 6>;
>> +		reset-names = "gphy", "gphy2";
>> +		lantiq,gphy-mode = <GPHY_MODE_FE>;
>> +		clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
>> +		clock-names = "gphy";
>> +	};

Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Hauke Mehrtens]

On 04/20/2017 05:36 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:40PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>>
>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>> ---
>>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>>  drivers/phy/Kconfig                                |   8 +
>>  drivers/phy/Makefile                               |   1 +
>>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>>  6 files changed, 405 insertions(+), 55 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> new file mode 100644
>> index 000000000000..0ec9f790b6e0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> @@ -0,0 +1,59 @@
>> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
>> +===========================================
>> +
>> +This binding describes the USB PHY hardware provided by the RCU module on the
>> +Lantiq XWAY SoCs.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible		: Should be one of
>> +				"lantiq,ase-rcu-usb2-phy"
>> +				"lantiq,danube-rcu-usb2-phy"
>> +				"lantiq,xrx100-rcu-usb2-phy"
>> +				"lantiq,xrx200-rcu-usb2-phy"
>> +				"lantiq,xrx300-rcu-usb2-phy"
> 
> The first x in xrx seems to be a wildcard. Don't use wildcards in 
> compatible strings.

Yes that is correct, I will replace it in the newly introduced
compatible strings with the full names without wild cards.

> 
>> +- lantiq,rcu-syscon	: A phandle to the RCU module and the offsets to the
>> +			  USB PHY configuration and USB MAC registers.
> 
> Same comment as gphy.
> 
>> +- address-cells		: should be 1
>> +- size-cells		: should be 0
>> +- phy-cells		: from the generic PHY bindings, must be 1
> 
> Missing the '#'
> 
>> +
>> +Optional properties (controller (parent) node):
>> +- vbus-gpio		: References a GPIO which enables VBUS all given USB
>> +			  ports.
> 
> -gpios is preferred form.
> 
>> +
>> +Required nodes		:  A sub-node is required for each USB PHY port.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (port (child) node):
> 
> Where's the sub nodes in the example?

Sorry, this was from an older version, I will update this.

> 
>> +- reg        	: The ID of the USB port, usually 0 or 1.
>> +- clocks	: References to the (PMU) "ctrl" and "phy" clk gates.
>> +- clock-names	: Must be one of the following:
>> +			"ctrl"
>> +			"phy"
>> +- resets	: References to the RCU USB configuration reset bits.
>> +- reset-names	: Must be one of the following:
>> +			"analog-config" (optional)
>> +			"statemachine-soft" (optional)
>> +
>> +Optional properties (port (child) node):
>> +- vbus-gpio	: References a GPIO which enables VBUS for the USB port.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example for the USB PHYs on an xRX200 SoC:
>> +	usb_phys0: rcu-usb2-phy@0 {
> 
> usb-phy@...
> 
>> +		compatible      = "lantiq,xrx200-rcu-usb2-phy";
> 
> Extra spaces.
> 
>> +		reg = <0>;
>> +
>> +		lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
>> +		clocks = <&pmu PMU_GATE_USB0_CTRL>,
>> +			 <&pmu PMU_GATE_USB0_PHY>;
>> +		clock-names = "ctrl", "phy";
>> +		vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
>> +		resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
>> +		reset-names = "phy", "ctrl";
>> +		#phy-cells = <0>;
>> +	};
--
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Re: [PATCH 11/13] phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module

[Hauke Mehrtens]

On 04/20/2017 05:36 PM, Rob Herring wrote:
> On Mon, Apr 17, 2017 at 09:29:40PM +0200, Hauke Mehrtens wrote:
>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>
>> This driver starts the DWC2 core(s) built into the XWAY SoCs and provides
>> the PHY interfaces for each core. The phy instances can be passed to the
>> dwc2 driver, which already supports the generic phy interface.
>>
>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>> ---
>>  .../bindings/phy/phy-lantiq-rcu-usb2.txt           |  59 ++++
>>  arch/mips/lantiq/xway/reset.c                      |  43 ---
>>  arch/mips/lantiq/xway/sysctrl.c                    |  24 +-
>>  drivers/phy/Kconfig                                |   8 +
>>  drivers/phy/Makefile                               |   1 +
>>  drivers/phy/phy-lantiq-rcu-usb2.c                  | 325 +++++++++++++++++++++
>>  6 files changed, 405 insertions(+), 55 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>>  create mode 100644 drivers/phy/phy-lantiq-rcu-usb2.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> new file mode 100644
>> index 000000000000..0ec9f790b6e0
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
>> @@ -0,0 +1,59 @@
>> +Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
>> +===========================================
>> +
>> +This binding describes the USB PHY hardware provided by the RCU module on the
>> +Lantiq XWAY SoCs.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (controller (parent) node):
>> +- compatible		: Should be one of
>> +				"lantiq,ase-rcu-usb2-phy"
>> +				"lantiq,danube-rcu-usb2-phy"
>> +				"lantiq,xrx100-rcu-usb2-phy"
>> +				"lantiq,xrx200-rcu-usb2-phy"
>> +				"lantiq,xrx300-rcu-usb2-phy"
> 
> The first x in xrx seems to be a wildcard. Don't use wildcards in 
> compatible strings.

Yes that is correct, I will replace it in the newly introduced
compatible strings with the full names without wild cards.

> 
>> +- lantiq,rcu-syscon	: A phandle to the RCU module and the offsets to the
>> +			  USB PHY configuration and USB MAC registers.
> 
> Same comment as gphy.
> 
>> +- address-cells		: should be 1
>> +- size-cells		: should be 0
>> +- phy-cells		: from the generic PHY bindings, must be 1
> 
> Missing the '#'
> 
>> +
>> +Optional properties (controller (parent) node):
>> +- vbus-gpio		: References a GPIO which enables VBUS all given USB
>> +			  ports.
> 
> -gpios is preferred form.
> 
>> +
>> +Required nodes		:  A sub-node is required for each USB PHY port.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Required properties (port (child) node):
> 
> Where's the sub nodes in the example?

Sorry, this was from an older version, I will update this.

> 
>> +- reg        	: The ID of the USB port, usually 0 or 1.
>> +- clocks	: References to the (PMU) "ctrl" and "phy" clk gates.
>> +- clock-names	: Must be one of the following:
>> +			"ctrl"
>> +			"phy"
>> +- resets	: References to the RCU USB configuration reset bits.
>> +- reset-names	: Must be one of the following:
>> +			"analog-config" (optional)
>> +			"statemachine-soft" (optional)
>> +
>> +Optional properties (port (child) node):
>> +- vbus-gpio	: References a GPIO which enables VBUS for the USB port.
>> +
>> +
>> +-------------------------------------------------------------------------------
>> +Example for the USB PHYs on an xRX200 SoC:
>> +	usb_phys0: rcu-usb2-phy@0 {
> 
> usb-phy@...
> 
>> +		compatible      = "lantiq,xrx200-rcu-usb2-phy";
> 
> Extra spaces.
> 
>> +		reg = <0>;
>> +
>> +		lantiq,rcu-syscon = <&rcu0 0x18 0x38>;
>> +		clocks = <&pmu PMU_GATE_USB0_CTRL>,
>> +			 <&pmu PMU_GATE_USB0_PHY>;
>> +		clock-names = "ctrl", "phy";
>> +		vbus-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
>> +		resets = <&rcu_reset1 4>, <&rcu_reset0 4>;
>> +		reset-names = "phy", "ctrl";
>> +		#phy-cells = <0>;
>> +	};

Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Rob Herring]

On Tue, Apr 25, 2017 at 1:56 AM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
>
>
> On 04/20/2017 04:48 PM, Rob Herring wrote:
>> On Mon, Apr 17, 2017 at 09:29:35PM +0200, Hauke Mehrtens wrote:
>>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>>
>>> This allows using the xbar driver on ARX300 based SoCs which require the
>>> same xbar setup as the xRX200 chipsets because the xbar driver
>>> initialization is not guarded by an xRX200 specific
>>> of_machine_is_compatible condition anymore. Additionally the new driver
>>> takes a syscon phandle to configure the XBAR endianness bits in RCU
>>> (before this was done in arch/mips/lantiq/xway/reset.c and also
>>> guarded by an xRX200 specific if-statement).
>>>
>>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>>> ---
>>>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>>>  MAINTAINERS                                        |   1 +
>>>  arch/mips/lantiq/xway/reset.c                      |   4 -
>>>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>>>  drivers/soc/Makefile                               |   1 +
>>>  drivers/soc/lantiq/Makefile                        |   1 +
>>>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>>>  7 files changed, 125 insertions(+), 45 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>>  create mode 100644 drivers/soc/lantiq/Makefile
>>>  create mode 100644 drivers/soc/lantiq/xbar.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>> new file mode 100644
>>> index 000000000000..86e53ff3b0d5
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>> @@ -0,0 +1,22 @@
>>> +Lantiq XWAY SoC XBAR binding
>>> +============================
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Required properties:
>>> +- compatible        : Should be "lantiq,xbar-xway"
>>
>> This compatible is already in use so it is fine, but you should also
>> have per SoC compatible strings.
>
> I will add a new SoC specific one.
> What does per SoC device tree mean? Does it mean for the same silicon,
> for the same silicon revision, for the same fusing of a silicon or for
> the same marketing name?

Depends how specific you need to some extent. For fusing, packaging,
metal fixes, speed grading, etc. probably use the same compatible.
Different design and dies from the start, then they should have
different compatibles.

> I would like to make it per silicon or per silicon revision for the IP
> cores which I know are different.

Being "the same IP" doesn't really matter. The errata can be different
and often there is no visibility into what h/w designers may have
changed. On some IP you can rely on revision/feature registers though
forgetting to rev revision registers is not uncommon. You need to have
sufficient information that you can work-around a problem in the
future without requiring a new dtb.

Rob
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Re: [PATCH 06/13] MIPS: lantiq: Convert the xbar driver to a platform_driver

[Rob Herring]

On Tue, Apr 25, 2017 at 1:56 AM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>
>
> On 04/20/2017 04:48 PM, Rob Herring wrote:
>> On Mon, Apr 17, 2017 at 09:29:35PM +0200, Hauke Mehrtens wrote:
>>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>>
>>> This allows using the xbar driver on ARX300 based SoCs which require the
>>> same xbar setup as the xRX200 chipsets because the xbar driver
>>> initialization is not guarded by an xRX200 specific
>>> of_machine_is_compatible condition anymore. Additionally the new driver
>>> takes a syscon phandle to configure the XBAR endianness bits in RCU
>>> (before this was done in arch/mips/lantiq/xway/reset.c and also
>>> guarded by an xRX200 specific if-statement).
>>>
>>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> ---
>>>  .../devicetree/bindings/mips/lantiq/xbar.txt       |  22 +++++
>>>  MAINTAINERS                                        |   1 +
>>>  arch/mips/lantiq/xway/reset.c                      |   4 -
>>>  arch/mips/lantiq/xway/sysctrl.c                    |  41 ---------
>>>  drivers/soc/Makefile                               |   1 +
>>>  drivers/soc/lantiq/Makefile                        |   1 +
>>>  drivers/soc/lantiq/xbar.c                          | 100 +++++++++++++++++++++
>>>  7 files changed, 125 insertions(+), 45 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>>  create mode 100644 drivers/soc/lantiq/Makefile
>>>  create mode 100644 drivers/soc/lantiq/xbar.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/mips/lantiq/xbar.txt b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>> new file mode 100644
>>> index 000000000000..86e53ff3b0d5
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mips/lantiq/xbar.txt
>>> @@ -0,0 +1,22 @@
>>> +Lantiq XWAY SoC XBAR binding
>>> +============================
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Required properties:
>>> +- compatible        : Should be "lantiq,xbar-xway"
>>
>> This compatible is already in use so it is fine, but you should also
>> have per SoC compatible strings.
>
> I will add a new SoC specific one.
> What does per SoC device tree mean? Does it mean for the same silicon,
> for the same silicon revision, for the same fusing of a silicon or for
> the same marketing name?

Depends how specific you need to some extent. For fusing, packaging,
metal fixes, speed grading, etc. probably use the same compatible.
Different design and dies from the start, then they should have
different compatibles.

> I would like to make it per silicon or per silicon revision for the IP
> cores which I know are different.

Being "the same IP" doesn't really matter. The errata can be different
and often there is no visibility into what h/w designers may have
changed. On some IP you can rely on revision/feature registers though
forgetting to rev revision registers is not uncommon. You need to have
sufficient information that you can work-around a problem in the
future without requiring a new dtb.

Rob

Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Rob Herring]

On Tue, Apr 25, 2017 at 2:00 AM, Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org> wrote:
>
>
> On 04/20/2017 04:54 PM, Rob Herring wrote:
>> On Mon, Apr 17, 2017 at 09:29:37PM +0200, Hauke Mehrtens wrote:
>>> From: Martin Blumenstingl <martin.blumenstingl-gM/Ye1E23mwN+BqQ9rBEUg@public.gmane.org>
>>>
>>> The reset controllers (on xRX200 and newer SoCs have two of them) are
>>> provided by the RCU module. This was initially implemented as a simple
>>> reset controller. However, the RCU module provides more functionality
>>> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
>>> The old reset controller driver implementation from
>>> arch/mips/lantiq/xway/reset.c did not honor this fact.
>>>
>>> For some devices the request and the status bits are different.
>>>
>>> Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
>>> ---
>>>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>>>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>>>  drivers/reset/Kconfig                              |   6 +
>>>  drivers/reset/Makefile                             |   1 +
>>>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>>>  5 files changed, 281 insertions(+), 68 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>> new file mode 100644
>>> index 000000000000..7f097d16bbb7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>> @@ -0,0 +1,43 @@
>>> +Lantiq XWAY SoC RCU reset controller binding
>>> +============================================
>>> +
>>> +This binding describes a reset-controller found on the RCU module on Lantiq
>>> +XWAY SoCs.
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Required properties (controller (parent) node):
>>> +- compatible                : Should be "lantiq,rcu-reset"
>>> +- lantiq,rcu-syscon : A phandle to the RCU syscon, the reset register
>>> +                      offset and the status register offset.
>>> +- #reset-cells              : Specifies the number of cells needed to encode the
>>> +                      reset line, should be 1.
>>> +
>>> +Optional properties:
>>> +- reset-status              : The request status bit. For some bits the request bit
>>> +                      and the status bit are different. This is depending
>>> +                      on the SoC. If the reset-status bit does not match
>>> +                      the reset-request bit, put the reset number into the
>>> +                      reset-request property and the status bit at the same
>>> +                      index into the reset-status property. If no
>>> +                      reset-request bit is given here, the driver assume
>>> +                      status and request bit are the same.
>>> +- reset-request             : The reset request bit, to map it to the reset-status
>>> +                      bit.
>>
>> These should either be implied by SoC specific compatible or be made
>> part of the reset cells. In the latter case, you still need the SoC
>> specific compatible.
>
> Currently the reset framework only supports a single reset cell to my
> knowledge, but I haven't looked into the details, I could extend it to
> make it support two.

I thought we had cases already, but maybe I'm thinking of something
else. In any case, driver limitations shouldn't define binding design.

> The SoC which needs this has two reset control register sets and the
> bits are specific for each register set. Would a specific compatible
> string for each register set ok?

Yes. You should have that.

Rob
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Re: [PATCH 08/13] reset: Add a reset controller driver for the Lantiq XWAY based SoCs

[Rob Herring]

On Tue, Apr 25, 2017 at 2:00 AM, Hauke Mehrtens <hauke@hauke-m.de> wrote:
>
>
> On 04/20/2017 04:54 PM, Rob Herring wrote:
>> On Mon, Apr 17, 2017 at 09:29:37PM +0200, Hauke Mehrtens wrote:
>>> From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>>
>>> The reset controllers (on xRX200 and newer SoCs have two of them) are
>>> provided by the RCU module. This was initially implemented as a simple
>>> reset controller. However, the RCU module provides more functionality
>>> (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
>>> The old reset controller driver implementation from
>>> arch/mips/lantiq/xway/reset.c did not honor this fact.
>>>
>>> For some devices the request and the status bits are different.
>>>
>>> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
>>> ---
>>>  .../devicetree/bindings/reset/lantiq,rcu-reset.txt |  43 ++++
>>>  arch/mips/lantiq/xway/reset.c                      |  68 ------
>>>  drivers/reset/Kconfig                              |   6 +
>>>  drivers/reset/Makefile                             |   1 +
>>>  drivers/reset/reset-lantiq-rcu.c                   | 231 +++++++++++++++++++++
>>>  5 files changed, 281 insertions(+), 68 deletions(-)
>>>  create mode 100644 Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>>  create mode 100644 drivers/reset/reset-lantiq-rcu.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>> new file mode 100644
>>> index 000000000000..7f097d16bbb7
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/reset/lantiq,rcu-reset.txt
>>> @@ -0,0 +1,43 @@
>>> +Lantiq XWAY SoC RCU reset controller binding
>>> +============================================
>>> +
>>> +This binding describes a reset-controller found on the RCU module on Lantiq
>>> +XWAY SoCs.
>>> +
>>> +
>>> +-------------------------------------------------------------------------------
>>> +Required properties (controller (parent) node):
>>> +- compatible                : Should be "lantiq,rcu-reset"
>>> +- lantiq,rcu-syscon : A phandle to the RCU syscon, the reset register
>>> +                      offset and the status register offset.
>>> +- #reset-cells              : Specifies the number of cells needed to encode the
>>> +                      reset line, should be 1.
>>> +
>>> +Optional properties:
>>> +- reset-status              : The request status bit. For some bits the request bit
>>> +                      and the status bit are different. This is depending
>>> +                      on the SoC. If the reset-status bit does not match
>>> +                      the reset-request bit, put the reset number into the
>>> +                      reset-request property and the status bit at the same
>>> +                      index into the reset-status property. If no
>>> +                      reset-request bit is given here, the driver assume
>>> +                      status and request bit are the same.
>>> +- reset-request             : The reset request bit, to map it to the reset-status
>>> +                      bit.
>>
>> These should either be implied by SoC specific compatible or be made
>> part of the reset cells. In the latter case, you still need the SoC
>> specific compatible.
>
> Currently the reset framework only supports a single reset cell to my
> knowledge, but I haven't looked into the details, I could extend it to
> make it support two.

I thought we had cases already, but maybe I'm thinking of something
else. In any case, driver limitations shouldn't define binding design.

> The SoC which needs this has two reset control register sets and the
> bits are specific for each register set. Would a specific compatible
> string for each register set ok?

Yes. You should have that.

Rob

Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

The patch

   spi: spi-falcon: drop check of boot select

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 1a41aa1376df9e24d0c760df1a6f59765316c457 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Date: Sun, 20 Aug 2017 00:18:10 +0200
Subject: [PATCH] spi: spi-falcon: drop check of boot select

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

All device trees I am aware of only have one correct flash device entry
in it. The device tree is anyway bundled with the kernel in all systems
using device tree I know of.

The boot mode can be specified with some pin straps and will select the
flash type the rom code will boot from. One SPI, NOR or NAND flash chip
can be connect to the EBU and used to load the first stage boot loader
from.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	int ret;
 
-	if (ltq_boot_select() != BS_SPI) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 	if (!master)
 		return -ENOMEM;
-- 
2.14.1

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Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

The patch

   spi: spi-falcon: drop check of boot select

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 1a41aa1376df9e24d0c760df1a6f59765316c457 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sun, 20 Aug 2017 00:18:10 +0200
Subject: [PATCH] spi: spi-falcon: drop check of boot select

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

All device trees I am aware of only have one correct flash device entry
in it. The device tree is anyway bundled with the kernel in all systems
using device tree I know of.

The boot mode can be specified with some pin straps and will select the
flash type the rom code will boot from. One SPI, NOR or NAND flash chip
can be connect to the EBU and used to load the first stage boot loader
from.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-spi@vger.kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	int ret;
 
-	if (ltq_boot_select() != BS_SPI) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 	if (!master)
 		return -ENOMEM;
-- 
2.14.1

Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

The patch

   spi: spi-falcon: drop check of boot select

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 1a41aa1376df9e24d0c760df1a6f59765316c457 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Date: Sun, 20 Aug 2017 00:18:10 +0200
Subject: [PATCH] spi: spi-falcon: drop check of boot select

Do not check which flash type the SoC was booted from before
using this driver. Assume that the device tree is correct and use this
driver when it was added to device tree. This also removes a build
dependency to the SoC code.

All device trees I am aware of only have one correct flash device entry
in it. The device tree is anyway bundled with the kernel in all systems
using device tree I know of.

The boot mode can be specified with some pin straps and will select the
flash type the rom code will boot from. One SPI, NOR or NAND flash chip
can be connect to the EBU and used to load the first stage boot loader
from.

Signed-off-by: Hauke Mehrtens <hauke-5/S+JYg5SzeELgA04lAiVw@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
index 286b2c81fc6b..f8638e82e5db 100644
--- a/drivers/spi/spi-falcon.c
+++ b/drivers/spi/spi-falcon.c
@@ -395,11 +395,6 @@ static int falcon_sflash_probe(struct platform_device *pdev)
 	struct spi_master *master;
 	int ret;
 
-	if (ltq_boot_select() != BS_SPI) {
-		dev_err(&pdev->dev, "invalid bootstrap options\n");
-		return -ENODEV;
-	}
-
 	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 	if (!master)
 		return -ENOMEM;
-- 
2.14.1

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Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

The patch

   spi: spi-falcon: drop check of boot select

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

The patch

   spi: spi-falcon: drop check of boot select

has been applied to the spi tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Ralf Baechle]

On Fri, Sep 01, 2017 at 11:47:26AM +0100, Mark Brown wrote:

> The patch
> 
>    spi: spi-falcon: drop check of boot select
> 
> has been applied to the spi tree at
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

Thanks Mark - but there are some ordering dependencies in Hauke's
patch series so it would be great if I could have an Acked-by to merge
this patch through the MIPS tree along with the rest of Hauke's series.

  Ralf
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Re: Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Ralf Baechle]

On Fri, Sep 01, 2017 at 11:47:26AM +0100, Mark Brown wrote:

> The patch
> 
>    spi: spi-falcon: drop check of boot select
> 
> has been applied to the spi tree at
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

Thanks Mark - but there are some ordering dependencies in Hauke's
patch series so it would be great if I could have an Acked-by to merge
this patch through the MIPS tree along with the rest of Hauke's series.

  Ralf

Re: Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1173 bytes --]

On Fri, Sep 01, 2017 at 04:23:55PM +0200, Ralf Baechle wrote:

> Thanks Mark - but there are some ordering dependencies in Hauke's
> patch series so it would be great if I could have an Acked-by to merge
> this patch through the MIPS tree along with the rest of Hauke's series.

Ah, I see - I wasn't copied on the cover letter so I didn't know about
this.  Here's a pull request:

The following changes since commit 5771a8c08880cdca3bfb4a3fc6d309d6bba20877:

  Linux v4.13-rc1 (2017-07-15 15:22:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git tags/spi-falcon-no-board-check

for you to fetch changes up to 1a41aa1376df9e24d0c760df1a6f59765316c457:

  spi: spi-falcon: drop check of boot select (2017-09-01 11:33:22 +0100)

----------------------------------------------------------------
spi: Remove board check from the Falcon driver

MIPS is removing this board check so support a cross tree merge.

----------------------------------------------------------------
Hauke Mehrtens (1):
      spi: spi-falcon: drop check of boot select

 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

[-- Attachment #2: signature.asc --]
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Re: Applied "spi: spi-falcon: drop check of boot select" to the spi tree

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 1173 bytes --]

On Fri, Sep 01, 2017 at 04:23:55PM +0200, Ralf Baechle wrote:

> Thanks Mark - but there are some ordering dependencies in Hauke's
> patch series so it would be great if I could have an Acked-by to merge
> this patch through the MIPS tree along with the rest of Hauke's series.

Ah, I see - I wasn't copied on the cover letter so I didn't know about
this.  Here's a pull request:

The following changes since commit 5771a8c08880cdca3bfb4a3fc6d309d6bba20877:

  Linux v4.13-rc1 (2017-07-15 15:22:10 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git tags/spi-falcon-no-board-check

for you to fetch changes up to 1a41aa1376df9e24d0c760df1a6f59765316c457:

  spi: spi-falcon: drop check of boot select (2017-09-01 11:33:22 +0100)

----------------------------------------------------------------
spi: Remove board check from the Falcon driver

MIPS is removing this board check so support a cross tree merge.

----------------------------------------------------------------
Hauke Mehrtens (1):
      spi: spi-falcon: drop check of boot select

 drivers/spi/spi-falcon.c | 5 -----
 1 file changed, 5 deletions(-)

[-- Attachment #2: signature.asc --]
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