* [PULL 00/20] MIPS queue for June 9th, 2020
@ 2020-06-09 16:28 Aleksandar Markovic
2020-06-09 16:28 ` [PULL 01/20] mailmap: Change email address of Filip Bozuta Aleksandar Markovic
` (20 more replies)
0 siblings, 21 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
The following changes since commit 49ee11555262a256afec592dfed7c5902d5eefd2:
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-request' into staging (2020-06-08 11:04:57 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qemu tags/mips-queue-jun-09-2020
for you to fetch changes up to 6db06115d246ea6d24755657a98c185ed2a50210:
target/mips: Enable hardware page table walker and CMGCR features for P5600 (2020-06-09 17:32:45 +0200)
----------------------------------------------------------------
MIPS queue for June 9th, 2020
Highlights:
- Registring change of email address for two contributors
- Cleanup and improvements of FPU helpers
- Enabling some features of P5600
- Adding two Loongson-3A CPU definitions
- A checkpatch warning is known and should be ignored
----------------------------------------------------------------
Aleksandar Markovic (18):
mailmap: Change email address of Filip Bozuta
mailmap: Change email address of Stefan Brankovic
target/mips: fpu: Demacro ADD.<D|S|PS>
target/mips: fpu: Demacro SUB.<D|S|PS>
target/mips: fpu: Demacro MUL.<D|S|PS>
target/mips: fpu: Demacro DIV.<D|S|PS>
target/mips: fpu: Remove now unused macro FLOAT_BINOP
target/mips: fpu: Demacro MADD.<D|S|PS>
target/mips: fpu: Demacro MSUB.<D|S|PS>
target/mips: fpu: Demacro NMADD.<D|S|PS>
target/mips: fpu: Demacro NMSUB.<D|S|PS>
target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros
target/mips: fpu: Demacro CLASS.<D|S>
target/mips: fpu: Remove now unused FLOAT_CLASS macro
target/mips: fpu: Demacro RINT.<D|S>
target/mips: fpu: Remove now unused FLOAT_RINT macro
target/mips: fpu: Name better paired-single variables
target/mips: fpu: Refactor conversion from ieee to mips exception
flags
Andrea Oliveri (1):
target/mips: Enable hardware page table walker and CMGCR features for
P5600
Huacai Chen (1):
target/mips: Add Loongson-3 CPU definition
target/mips/cpu.h | 32 +-
target/mips/internal.h | 3 +-
target/mips/mips-defs.h | 45 +-
target/mips/fpu_helper.c | 658 +++++++++++++++++++---------
target/mips/{lmi_helper.c => lmmi_helper.c} | 0
target/mips/msa_helper.c | 77 ++--
target/mips/translate.c | 2 +
target/mips/translate_init.inc.c | 95 +++-
.mailmap | 2 +
target/mips/Makefile.objs | 2 +-
10 files changed, 658 insertions(+), 258 deletions(-)
rename target/mips/{lmi_helper.c => lmmi_helper.c} (100%)
--
2.7.4
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 01/20] mailmap: Change email address of Filip Bozuta
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 02/20] mailmap: Change email address of Stefan Brankovic Aleksandar Markovic
` (19 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
Filip Bozuta wants to use his new email address for his future
work in QEMU.
CC: Filip Bozuta <filip.bozuta@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Filip Bozuta <filip.bozuta@syrmia.com>
Message-Id: <20200602085215.12585-2-aleksandar.qemu.devel@gmail.com>
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index e3628c7..9f2a3a5 100644
--- a/.mailmap
+++ b/.mailmap
@@ -45,6 +45,7 @@ Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <arikalo@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <aleksandar.rikalo@rt-rk.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
+Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>
Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 02/20] mailmap: Change email address of Stefan Brankovic
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
2020-06-09 16:28 ` [PULL 01/20] mailmap: Change email address of Filip Bozuta Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 03/20] target/mips: fpu: Demacro ADD.<D|S|PS> Aleksandar Markovic
` (18 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
Stefan Brankovic wants to use his new email address for his future
work in QEMU.
CC: Stefan Brankovic <stefan.brankovic@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Reviewed-by: Stefan Brankovic <stefan.brankovic@syrmia.com>
Message-Id: <20200602085215.12585-3-aleksandar.qemu.devel@gmail.com>
---
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.mailmap
index 9f2a3a5..84f3659 100644
--- a/.mailmap
+++ b/.mailmap
@@ -52,6 +52,7 @@ Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
Philippe Mathieu-Daudé <philmd@redhat.com> <f4bug@amsat.org>
+Stefan Brankovic <stefan.brankovic@syrmia.com> <stefan.brankovic@rt-rk.com.com>
Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>
# Also list preferred name forms where people have changed their
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 03/20] target/mips: fpu: Demacro ADD.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
2020-06-09 16:28 ` [PULL 01/20] mailmap: Change email address of Filip Bozuta Aleksandar Markovic
2020-06-09 16:28 ` [PULL 02/20] mailmap: Change email address of Stefan Brankovic Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 04/20] target/mips: fpu: Demacro SUB.<D|S|PS> Aleksandar Markovic
` (17 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-2-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 38 +++++++++++++++++++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 5287c86..984f3f4 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,12 +1208,48 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(add)
FLOAT_BINOP(sub)
FLOAT_BINOP(mul)
FLOAT_BINOP(div)
#undef FLOAT_BINOP
+uint64_t helper_float_add_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_add(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_add_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_add_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_add(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_add(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 04/20] target/mips: fpu: Demacro SUB.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (2 preceding siblings ...)
2020-06-09 16:28 ` [PULL 03/20] target/mips: fpu: Demacro ADD.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 05/20] target/mips: fpu: Demacro MUL.<D|S|PS> Aleksandar Markovic
` (16 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-3-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 984f3f4..715a872 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(sub)
FLOAT_BINOP(mul)
FLOAT_BINOP(div)
#undef FLOAT_BINOP
@@ -1249,6 +1248,42 @@ uint64_t helper_float_add_ps(CPUMIPSState *env,
return ((uint64_t)wth2 << 32) | wtl2;
}
+uint64_t helper_float_sub_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_sub(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_sub_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_sub_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_sub(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_sub(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 05/20] target/mips: fpu: Demacro MUL.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (3 preceding siblings ...)
2020-06-09 16:28 ` [PULL 04/20] target/mips: fpu: Demacro SUB.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 06/20] target/mips: fpu: Demacro DIV.<D|S|PS> Aleksandar Markovic
` (15 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-4-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 715a872..449e945 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(mul)
FLOAT_BINOP(div)
#undef FLOAT_BINOP
@@ -1284,6 +1283,42 @@ uint64_t helper_float_sub_ps(CPUMIPSState *env,
return ((uint64_t)wth2 << 32) | wtl2;
}
+uint64_t helper_float_mul_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_mul(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_mul_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_mul_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 06/20] target/mips: fpu: Demacro DIV.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (4 preceding siblings ...)
2020-06-09 16:28 ` [PULL 05/20] target/mips: fpu: Demacro MUL.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 07/20] target/mips: fpu: Remove now unused macro FLOAT_BINOP Aleksandar Markovic
` (14 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-5-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 37 ++++++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 449e945..2759c99 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1208,7 +1208,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
return ((uint64_t)wth2 << 32) | wt2; \
}
-FLOAT_BINOP(div)
#undef FLOAT_BINOP
uint64_t helper_float_add_d(CPUMIPSState *env,
@@ -1319,6 +1318,42 @@ uint64_t helper_float_mul_ps(CPUMIPSState *env,
return ((uint64_t)wth2 << 32) | wtl2;
}
+uint64_t helper_float_div_d(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint64_t dt2;
+
+ dt2 = float64_div(fdt0, fdt1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return dt2;
+}
+
+uint32_t helper_float_div_s(CPUMIPSState *env,
+ uint32_t fst0, uint32_t fst1)
+{
+ uint32_t wt2;
+
+ wt2 = float32_div(fst0, fst1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return wt2;
+}
+
+uint64_t helper_float_div_ps(CPUMIPSState *env,
+ uint64_t fdt0, uint64_t fdt1)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t wtl2;
+ uint32_t wth2;
+
+ wtl2 = float32_div(fstl0, fstl1, &env->active_fpu.fp_status);
+ wth2 = float32_div(fsth0, fsth1, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return ((uint64_t)wth2 << 32) | wtl2;
+}
+
/* MIPS specific binary operations */
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 07/20] target/mips: fpu: Remove now unused macro FLOAT_BINOP
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (5 preceding siblings ...)
2020-06-09 16:28 ` [PULL 06/20] target/mips: fpu: Demacro DIV.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 08/20] target/mips: fpu: Demacro MADD.<D|S|PS> Aleksandar Markovic
` (13 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
After demacroing <ADD|SUB|MUL|DIV>.<D|S|PS>, this macro is not
needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-6-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 39 ---------------------------------------
1 file changed, 39 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 2759c99..a3a3968 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1170,45 +1170,6 @@ FLOAT_CLASS(class_d, 64)
#undef FLOAT_CLASS
/* binary operations */
-#define FLOAT_BINOP(name) \
-uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1) \
-{ \
- uint64_t dt2; \
- \
- dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\
- update_fcr31(env, GETPC()); \
- return dt2; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
- uint32_t fst0, uint32_t fst1) \
-{ \
- uint32_t wt2; \
- \
- wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\
- update_fcr31(env, GETPC()); \
- return wt2; \
-} \
- \
-uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
- uint64_t fdt0, \
- uint64_t fdt1) \
-{ \
- uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
- uint32_t fsth0 = fdt0 >> 32; \
- uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
- uint32_t fsth1 = fdt1 >> 32; \
- uint32_t wt2; \
- uint32_t wth2; \
- \
- wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \
- wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \
- update_fcr31(env, GETPC()); \
- return ((uint64_t)wth2 << 32) | wt2; \
-}
-
-#undef FLOAT_BINOP
uint64_t helper_float_add_d(CPUMIPSState *env,
uint64_t fdt0, uint64_t fdt1)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 08/20] target/mips: fpu: Demacro MADD.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (6 preceding siblings ...)
2020-06-09 16:28 ` [PULL 07/20] target/mips: fpu: Remove now unused macro FLOAT_BINOP Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 09/20] target/mips: fpu: Demacro MSUB.<D|S|PS> Aleksandar Markovic
` (12 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-7-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 41 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index a3a3968..c070081 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,12 +1495,51 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(madd, 0)
FLOAT_FMA(msub, float_muladd_negate_c)
FLOAT_FMA(nmadd, float_muladd_negate_result)
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
+uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_madd_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
uint ## bits ## _t fs, \
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 09/20] target/mips: fpu: Demacro MSUB.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (7 preceding siblings ...)
2020-06-09 16:28 ` [PULL 08/20] target/mips: fpu: Demacro MADD.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 10/20] target/mips: fpu: Demacro NMADD.<D|S|PS> Aleksandar Markovic
` (11 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-8-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 40 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index c070081..e37fc40 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(msub, float_muladd_negate_c)
FLOAT_FMA(nmadd, float_muladd_negate_result)
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
@@ -1539,6 +1538,45 @@ uint64_t helper_float_madd_ps(CPUMIPSState *env, uint64_t fdt0,
return ((uint64_t)fsth0 << 32) | fstl0;
}
+uint64_t helper_float_msub_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_msub_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 10/20] target/mips: fpu: Demacro NMADD.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (8 preceding siblings ...)
2020-06-09 16:28 ` [PULL 09/20] target/mips: fpu: Demacro MSUB.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 11/20] target/mips: fpu: Demacro NMSUB.<D|S|PS> Aleksandar Markovic
` (10 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-9-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 44 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index e37fc40..d4c065f 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(nmadd, float_muladd_negate_result)
FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
@@ -1577,6 +1576,49 @@ uint64_t helper_float_msub_ps(CPUMIPSState *env, uint64_t fdt0,
return ((uint64_t)fsth0 << 32) | fstl0;
}
+uint64_t helper_float_nmadd_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_add(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float64_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_nmadd_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_add(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float32_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_add(fstl0, fstl2, &env->active_fpu.fp_status);
+ fstl0 = float32_chs(fstl0);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_add(fsth0, fsth2, &env->active_fpu.fp_status);
+ fsth0 = float32_chs(fsth0);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 11/20] target/mips: fpu: Demacro NMSUB.<D|S|PS>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (9 preceding siblings ...)
2020-06-09 16:28 ` [PULL 10/20] target/mips: fpu: Demacro NMADD.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 12/20] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros Aleksandar Markovic
` (9 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-10-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 44 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index d4c065f..927bac2 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1495,7 +1495,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
update_fcr31(env, GETPC()); \
return ((uint64_t)fsth0 << 32) | fst0; \
}
-FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
@@ -1619,6 +1618,49 @@ uint64_t helper_float_nmadd_ps(CPUMIPSState *env, uint64_t fdt0,
return ((uint64_t)fsth0 << 32) | fstl0;
}
+uint64_t helper_float_nmsub_d(CPUMIPSState *env, uint64_t fst0,
+ uint64_t fst1, uint64_t fst2)
+{
+ fst0 = float64_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float64_sub(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float64_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint32_t helper_float_nmsub_s(CPUMIPSState *env, uint32_t fst0,
+ uint32_t fst1, uint32_t fst2)
+{
+ fst0 = float32_mul(fst0, fst1, &env->active_fpu.fp_status);
+ fst0 = float32_sub(fst0, fst2, &env->active_fpu.fp_status);
+ fst0 = float32_chs(fst0);
+
+ update_fcr31(env, GETPC());
+ return fst0;
+}
+
+uint64_t helper_float_nmsub_ps(CPUMIPSState *env, uint64_t fdt0,
+ uint64_t fdt1, uint64_t fdt2)
+{
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fsth0 = fdt0 >> 32;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fsth1 = fdt1 >> 32;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fsth2 = fdt2 >> 32;
+
+ fstl0 = float32_mul(fstl0, fstl1, &env->active_fpu.fp_status);
+ fstl0 = float32_sub(fstl0, fstl2, &env->active_fpu.fp_status);
+ fstl0 = float32_chs(fstl0);
+ fsth0 = float32_mul(fsth0, fsth1, &env->active_fpu.fp_status);
+ fsth0 = float32_sub(fsth0, fsth2, &env->active_fpu.fp_status);
+ fsth0 = float32_chs(fsth0);
+
+ update_fcr31(env, GETPC());
+ return ((uint64_t)fsth0 << 32) | fstl0;
+}
+
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 12/20] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (10 preceding siblings ...)
2020-06-09 16:28 ` [PULL 11/20] target/mips: fpu: Demacro NMSUB.<D|S|PS> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 13/20] target/mips: fpu: Demacro CLASS.<D|S> Aleksandar Markovic
` (8 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
After demacroing <MADD|MSUB|NMADD|NMSUB>.<D|S|PS>, these macros
are not needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-11-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 50 ------------------------------------------------
1 file changed, 50 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 927bac2..e8e50e4 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1446,56 +1446,6 @@ FLOAT_MINMAX(mina_d, 64, minnummag)
#undef FLOAT_MINMAX
/* ternary operations */
-#define UNFUSED_FMA(prefix, a, b, c, flags) \
-{ \
- a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
- if ((flags) & float_muladd_negate_c) { \
- a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
- } else { \
- a = prefix##_add(a, c, &env->active_fpu.fp_status); \
- } \
- if ((flags) & float_muladd_negate_result) { \
- a = prefix##_chs(a); \
- } \
-}
-
-/* FMA based operations */
-#define FLOAT_FMA(name, type) \
-uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
-{ \
- UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
- update_fcr31(env, GETPC()); \
- return fdt0; \
-} \
- \
-uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
- uint32_t fst0, uint32_t fst1, \
- uint32_t fst2) \
-{ \
- UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
- update_fcr31(env, GETPC()); \
- return fst0; \
-} \
- \
-uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
- uint64_t fdt0, uint64_t fdt1, \
- uint64_t fdt2) \
-{ \
- uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
- uint32_t fsth0 = fdt0 >> 32; \
- uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
- uint32_t fsth1 = fdt1 >> 32; \
- uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
- uint32_t fsth2 = fdt2 >> 32; \
- \
- UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
- UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
- update_fcr31(env, GETPC()); \
- return ((uint64_t)fsth0 << 32) | fst0; \
-}
-#undef FLOAT_FMA
uint64_t helper_float_madd_d(CPUMIPSState *env, uint64_t fst0,
uint64_t fst1, uint64_t fst2)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 13/20] target/mips: fpu: Demacro CLASS.<D|S>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (11 preceding siblings ...)
2020-06-09 16:28 ` [PULL 12/20] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 14/20] target/mips: fpu: Remove now unused FLOAT_CLASS macro Aleksandar Markovic
` (7 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-12-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 68 insertions(+), 2 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index e8e50e4..b3903f5 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1165,10 +1165,76 @@ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
return float_ ## name(arg, &env->active_fpu.fp_status); \
}
-FLOAT_CLASS(class_s, 32)
-FLOAT_CLASS(class_d, 64)
#undef FLOAT_CLASS
+uint64_t float_class_d(uint64_t arg, float_status *status)
+{
+ if (float64_is_signaling_nan(arg, status)) {
+ return FLOAT_CLASS_SIGNALING_NAN;
+ } else if (float64_is_quiet_nan(arg, status)) {
+ return FLOAT_CLASS_QUIET_NAN;
+ } else if (float64_is_neg(arg)) {
+ if (float64_is_infinity(arg)) {
+ return FLOAT_CLASS_NEGATIVE_INFINITY;
+ } else if (float64_is_zero(arg)) {
+ return FLOAT_CLASS_NEGATIVE_ZERO;
+ } else if (float64_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_NEGATIVE_NORMAL;
+ }
+ } else {
+ if (float64_is_infinity(arg)) {
+ return FLOAT_CLASS_POSITIVE_INFINITY;
+ } else if (float64_is_zero(arg)) {
+ return FLOAT_CLASS_POSITIVE_ZERO;
+ } else if (float64_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_POSITIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_POSITIVE_NORMAL;
+ }
+ }
+}
+
+uint64_t helper_float_class_d(CPUMIPSState *env, uint64_t arg)
+{
+ return float_class_d(arg, &env->active_fpu.fp_status);
+}
+
+uint32_t float_class_s(uint32_t arg, float_status *status)
+{
+ if (float32_is_signaling_nan(arg, status)) {
+ return FLOAT_CLASS_SIGNALING_NAN;
+ } else if (float32_is_quiet_nan(arg, status)) {
+ return FLOAT_CLASS_QUIET_NAN;
+ } else if (float32_is_neg(arg)) {
+ if (float32_is_infinity(arg)) {
+ return FLOAT_CLASS_NEGATIVE_INFINITY;
+ } else if (float32_is_zero(arg)) {
+ return FLOAT_CLASS_NEGATIVE_ZERO;
+ } else if (float32_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_NEGATIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_NEGATIVE_NORMAL;
+ }
+ } else {
+ if (float32_is_infinity(arg)) {
+ return FLOAT_CLASS_POSITIVE_INFINITY;
+ } else if (float32_is_zero(arg)) {
+ return FLOAT_CLASS_POSITIVE_ZERO;
+ } else if (float32_is_zero_or_denormal(arg)) {
+ return FLOAT_CLASS_POSITIVE_SUBNORMAL;
+ } else {
+ return FLOAT_CLASS_POSITIVE_NORMAL;
+ }
+ }
+}
+
+uint32_t helper_float_class_s(CPUMIPSState *env, uint32_t arg)
+{
+ return float_class_s(arg, &env->active_fpu.fp_status);
+}
+
/* binary operations */
uint64_t helper_float_add_d(CPUMIPSState *env,
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 14/20] target/mips: fpu: Remove now unused FLOAT_CLASS macro
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (12 preceding siblings ...)
2020-06-09 16:28 ` [PULL 13/20] target/mips: fpu: Demacro CLASS.<D|S> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 15/20] target/mips: fpu: Demacro RINT.<D|S> Aleksandar Markovic
` (6 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
After demacroing CLASS.<D|S>, this macro is not needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-13-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 39 ---------------------------------------
1 file changed, 39 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index b3903f5..e227e53 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1128,45 +1128,6 @@ FLOAT_RINT(rint_d, 64)
#define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
#define FLOAT_CLASS_POSITIVE_ZERO 0x200
-#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
- float_status *status) \
-{ \
- if (float ## bits ## _is_signaling_nan(arg, status)) { \
- return FLOAT_CLASS_SIGNALING_NAN; \
- } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
- return FLOAT_CLASS_QUIET_NAN; \
- } else if (float ## bits ## _is_neg(arg)) { \
- if (float ## bits ## _is_infinity(arg)) { \
- return FLOAT_CLASS_NEGATIVE_INFINITY; \
- } else if (float ## bits ## _is_zero(arg)) { \
- return FLOAT_CLASS_NEGATIVE_ZERO; \
- } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
- return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
- } else { \
- return FLOAT_CLASS_NEGATIVE_NORMAL; \
- } \
- } else { \
- if (float ## bits ## _is_infinity(arg)) { \
- return FLOAT_CLASS_POSITIVE_INFINITY; \
- } else if (float ## bits ## _is_zero(arg)) { \
- return FLOAT_CLASS_POSITIVE_ZERO; \
- } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
- return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
- } else { \
- return FLOAT_CLASS_POSITIVE_NORMAL; \
- } \
- } \
-} \
- \
-uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
- uint ## bits ## _t arg) \
-{ \
- return float_ ## name(arg, &env->active_fpu.fp_status); \
-}
-
-#undef FLOAT_CLASS
-
uint64_t float_class_d(uint64_t arg, float_status *status)
{
if (float64_is_signaling_nan(arg, status)) {
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 15/20] target/mips: fpu: Demacro RINT.<D|S>
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (13 preceding siblings ...)
2020-06-09 16:28 ` [PULL 14/20] target/mips: fpu: Remove now unused FLOAT_CLASS macro Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 16/20] target/mips: fpu: Remove now unused FLOAT_RINT macro Aleksandar Markovic
` (5 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
This is just a cosmetic change to enable tools like gcov, gdb,
callgrind, etc. to better display involved source code.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-14-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index e227e53..dae1331 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1113,10 +1113,26 @@ uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
return fdret; \
}
-FLOAT_RINT(rint_s, 32)
-FLOAT_RINT(rint_d, 64)
#undef FLOAT_RINT
+uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
+{
+ uint64_t fdret;
+
+ fdret = float64_round_to_int(fs, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return fdret;
+}
+
+uint32_t helper_float_rint_s(CPUMIPSState *env, uint32_t fs)
+{
+ uint32_t fdret;
+
+ fdret = float32_round_to_int(fs, &env->active_fpu.fp_status);
+ update_fcr31(env, GETPC());
+ return fdret;
+}
+
#define FLOAT_CLASS_SIGNALING_NAN 0x001
#define FLOAT_CLASS_QUIET_NAN 0x002
#define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 16/20] target/mips: fpu: Remove now unused FLOAT_RINT macro
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (14 preceding siblings ...)
2020-06-09 16:28 ` [PULL 15/20] target/mips: fpu: Demacro RINT.<D|S> Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 17/20] target/mips: fpu: Name better paired-single variables Aleksandar Markovic
` (4 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
After demacroing RINT.<D|S>, this macro is not needed anymore.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-15-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index dae1331..56ba491 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1102,19 +1102,6 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
return ((uint64_t)fsth2 << 32) | fst2;
}
-#define FLOAT_RINT(name, bits) \
-uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
- uint ## bits ## _t fs) \
-{ \
- uint ## bits ## _t fdret; \
- \
- fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
- update_fcr31(env, GETPC()); \
- return fdret; \
-}
-
-#undef FLOAT_RINT
-
uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
{
uint64_t fdret;
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 17/20] target/mips: fpu: Name better paired-single variables
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (15 preceding siblings ...)
2020-06-09 16:28 ` [PULL 16/20] target/mips: fpu: Remove now unused FLOAT_RINT macro Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 18/20] target/mips: fpu: Refactor conversion from ieee to mips exception flags Aleksandar Markovic
` (3 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
Use consistently 'l' and 'h' for low and high halves.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-16-aleksandar.qemu.devel@gmail.com>
---
target/mips/fpu_helper.c | 62 ++++++++++++++++++++++++------------------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index 56ba491..dbb8ca5 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -1059,14 +1059,14 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
{
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
- &env->active_fpu.fp_status);
+ fstl2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
+ &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
@@ -1091,15 +1091,15 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
{
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+ fstl2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
- fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_div(float32_one, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rint_d(CPUMIPSState *env, uint64_t fs)
@@ -1367,19 +1367,19 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
uint32_t fsth2 = fdt2 >> 32;
- fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one,
+ fstl2 = float32_chs(float32_sub(fstl2, float32_one,
&env->active_fpu.fp_status));
fsth2 = float32_chs(float32_sub(fsth2, float32_one,
&env->active_fpu.fp_status));
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
@@ -1404,51 +1404,51 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst2 = fdt2 & 0XFFFFFFFF;
+ uint32_t fstl2 = fdt2 & 0XFFFFFFFF;
uint32_t fsth2 = fdt2 >> 32;
- fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fstl2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
+ fstl2 = float32_sub(fstl2, float32_one, &env->active_fpu.fp_status);
fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ fstl2 = float32_chs(float32_div(fstl2, FLOAT_TWO32,
&env->active_fpu.fp_status));
fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
&env->active_fpu.fp_status));
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
uint32_t fsth1 = fdt1 >> 32;
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
+ fstl2 = float32_add(fstl0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_add(fstl1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
{
- uint32_t fst0 = fdt0 & 0XFFFFFFFF;
+ uint32_t fstl0 = fdt0 & 0XFFFFFFFF;
uint32_t fsth0 = fdt0 >> 32;
- uint32_t fst1 = fdt1 & 0XFFFFFFFF;
+ uint32_t fstl1 = fdt1 & 0XFFFFFFFF;
uint32_t fsth1 = fdt1 >> 32;
- uint32_t fst2;
+ uint32_t fstl2;
uint32_t fsth2;
- fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
+ fstl2 = float32_mul(fstl0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_mul(fstl1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
- return ((uint64_t)fsth2 << 32) | fst2;
+ return ((uint64_t)fsth2 << 32) | fstl2;
}
#define FLOAT_MINMAX(name, bits, minmaxfunc) \
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 18/20] target/mips: fpu: Refactor conversion from ieee to mips exception flags
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (16 preceding siblings ...)
2020-06-09 16:28 ` [PULL 17/20] target/mips: fpu: Name better paired-single variables Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-09 16:28 ` [PULL 19/20] target/mips: Add Loongson-3 CPU definition Aleksandar Markovic
` (2 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
The original coversion function is used for regular and MSA floating
point instructions handling. Since there are some nuanced differences
between regular and MSA floating point exception handling, provide two
instances of the conversion function, rather than just a single common
one. Inline both instances of this function instances for the sake of
performance. Improve variable naming in surrounding code for clarity.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <20200518200920.17344-17-aleksandar.qemu.devel@gmail.com>
---
target/mips/internal.h | 1 -
target/mips/fpu_helper.c | 55 ++++++++++++++++++----------------
target/mips/msa_helper.c | 77 ++++++++++++++++++++++++++++++++----------------
3 files changed, 82 insertions(+), 51 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 1bf274b..684356e 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -224,7 +224,6 @@ uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);
extern unsigned int ieee_rm[];
-int ieee_ex_to_mips(int xcpt);
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
static inline void restore_rounding_mode(CPUMIPSState *env)
diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c
index dbb8ca5..7a3a61c 100644
--- a/target/mips/fpu_helper.c
+++ b/target/mips/fpu_helper.c
@@ -189,43 +189,48 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
}
}
-int ieee_ex_to_mips(int xcpt)
+static inline int ieee_to_mips_xcpt(int ieee_xcpt)
{
- int ret = 0;
- if (xcpt) {
- if (xcpt & float_flag_invalid) {
- ret |= FP_INVALID;
- }
- if (xcpt & float_flag_overflow) {
- ret |= FP_OVERFLOW;
- }
- if (xcpt & float_flag_underflow) {
- ret |= FP_UNDERFLOW;
- }
- if (xcpt & float_flag_divbyzero) {
- ret |= FP_DIV0;
- }
- if (xcpt & float_flag_inexact) {
- ret |= FP_INEXACT;
- }
+ int mips_xcpt = 0;
+
+ if (ieee_xcpt & float_flag_invalid) {
+ mips_xcpt |= FP_INVALID;
+ }
+ if (ieee_xcpt & float_flag_overflow) {
+ mips_xcpt |= FP_OVERFLOW;
}
- return ret;
+ if (ieee_xcpt & float_flag_underflow) {
+ mips_xcpt |= FP_UNDERFLOW;
+ }
+ if (ieee_xcpt & float_flag_divbyzero) {
+ mips_xcpt |= FP_DIV0;
+ }
+ if (ieee_xcpt & float_flag_inexact) {
+ mips_xcpt |= FP_INEXACT;
+ }
+
+ return mips_xcpt;
}
static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
{
- int tmp = ieee_ex_to_mips(get_float_exception_flags(
- &env->active_fpu.fp_status));
+ int ieee_exception_flags = get_float_exception_flags(
+ &env->active_fpu.fp_status);
+ int mips_exception_flags = 0;
+
+ if (ieee_exception_flags) {
+ mips_exception_flags = ieee_to_mips_xcpt(ieee_exception_flags);
+ }
- SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
+ SET_FP_CAUSE(env->active_fpu.fcr31, mips_exception_flags);
- if (tmp) {
+ if (mips_exception_flags) {
set_float_exception_flags(0, &env->active_fpu.fp_status);
- if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
+ if (GET_FP_ENABLE(env->active_fpu.fcr31) & mips_exception_flags) {
do_raise_exception(env, EXCP_FPE, pc);
} else {
- UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
+ UPDATE_FP_FLAGS(env->active_fpu.fcr31, mips_exception_flags);
}
}
}
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 3c7012c..c3b2719 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -5419,54 +5419,81 @@ static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr)
#define CLEAR_IS_INEXACT 2
#define RECIPROCAL_INEXACT 4
-static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
+
+static inline int ieee_to_mips_xcpt_msa(int ieee_xcpt)
{
- int ieee_ex;
+ int mips_xcpt = 0;
- int c;
+ if (ieee_xcpt & float_flag_invalid) {
+ mips_xcpt |= FP_INVALID;
+ }
+ if (ieee_xcpt & float_flag_overflow) {
+ mips_xcpt |= FP_OVERFLOW;
+ }
+ if (ieee_xcpt & float_flag_underflow) {
+ mips_xcpt |= FP_UNDERFLOW;
+ }
+ if (ieee_xcpt & float_flag_divbyzero) {
+ mips_xcpt |= FP_DIV0;
+ }
+ if (ieee_xcpt & float_flag_inexact) {
+ mips_xcpt |= FP_INEXACT;
+ }
+
+ return mips_xcpt;
+}
+
+static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
+{
+ int ieee_exception_flags;
+ int mips_exception_flags = 0;
int cause;
int enable;
- ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status);
+ ieee_exception_flags = get_float_exception_flags(
+ &env->active_tc.msa_fp_status);
/* QEMU softfloat does not signal all underflow cases */
if (denormal) {
- ieee_ex |= float_flag_underflow;
+ ieee_exception_flags |= float_flag_underflow;
+ }
+ if (ieee_exception_flags) {
+ mips_exception_flags = ieee_to_mips_xcpt_msa(ieee_exception_flags);
}
-
- c = ieee_ex_to_mips(ieee_ex);
enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED;
/* Set Inexact (I) when flushing inputs to zero */
- if ((ieee_ex & float_flag_input_denormal) &&
+ if ((ieee_exception_flags & float_flag_input_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
if (action & CLEAR_IS_INEXACT) {
- c &= ~FP_INEXACT;
+ mips_exception_flags &= ~FP_INEXACT;
} else {
- c |= FP_INEXACT;
+ mips_exception_flags |= FP_INEXACT;
}
}
/* Set Inexact (I) and Underflow (U) when flushing outputs to zero */
- if ((ieee_ex & float_flag_output_denormal) &&
+ if ((ieee_exception_flags & float_flag_output_denormal) &&
(env->active_tc.msacsr & MSACSR_FS_MASK) != 0) {
- c |= FP_INEXACT;
+ mips_exception_flags |= FP_INEXACT;
if (action & CLEAR_FS_UNDERFLOW) {
- c &= ~FP_UNDERFLOW;
+ mips_exception_flags &= ~FP_UNDERFLOW;
} else {
- c |= FP_UNDERFLOW;
+ mips_exception_flags |= FP_UNDERFLOW;
}
}
/* Set Inexact (I) when Overflow (O) is not enabled */
- if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) {
- c |= FP_INEXACT;
+ if ((mips_exception_flags & FP_OVERFLOW) != 0 &&
+ (enable & FP_OVERFLOW) == 0) {
+ mips_exception_flags |= FP_INEXACT;
}
/* Clear Exact Underflow when Underflow (U) is not enabled */
- if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 &&
- (c & FP_INEXACT) == 0) {
- c &= ~FP_UNDERFLOW;
+ if ((mips_exception_flags & FP_UNDERFLOW) != 0 &&
+ (enable & FP_UNDERFLOW) == 0 &&
+ (mips_exception_flags & FP_INEXACT) == 0) {
+ mips_exception_flags &= ~FP_UNDERFLOW;
}
/*
@@ -5474,11 +5501,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* divide by zero
*/
if ((action & RECIPROCAL_INEXACT) &&
- (c & (FP_INVALID | FP_DIV0)) == 0) {
- c = FP_INEXACT;
+ (mips_exception_flags & (FP_INVALID | FP_DIV0)) == 0) {
+ mips_exception_flags = FP_INEXACT;
}
- cause = c & enable; /* all current enabled exceptions */
+ cause = mips_exception_flags & enable; /* all current enabled exceptions */
if (cause == 0) {
/*
@@ -5486,7 +5513,7 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* with all current exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
- (GET_FP_CAUSE(env->active_tc.msacsr) | c));
+ (GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
} else {
/* Current exceptions are enabled */
if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) {
@@ -5495,11 +5522,11 @@ static inline int update_msacsr(CPUMIPSState *env, int action, int denormal)
* with all enabled exceptions
*/
SET_FP_CAUSE(env->active_tc.msacsr,
- (GET_FP_CAUSE(env->active_tc.msacsr) | c));
+ (GET_FP_CAUSE(env->active_tc.msacsr) | mips_exception_flags));
}
}
- return c;
+ return mips_exception_flags;
}
static inline int get_enabled_exceptions(const CPUMIPSState *env, int c)
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 19/20] target/mips: Add Loongson-3 CPU definition
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (17 preceding siblings ...)
2020-06-09 16:28 ` [PULL 18/20] target/mips: fpu: Refactor conversion from ieee to mips exception flags Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-11-29 22:09 ` Philippe Mathieu-Daudé
2020-06-09 16:28 ` [PULL 20/20] target/mips: Enable hardware page table walker and CMGCR features for P5600 Aleksandar Markovic
2020-06-11 14:35 ` [PULL 00/20] MIPS queue for June 9th, 2020 Peter Maydell
20 siblings, 1 reply; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
From: Huacai Chen <zltjiangshi@gmail.com>
Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
Loongson-3A R4 is the newest and its ISA is almost the superset of all
others. To reduce complexity, we just define two CPU types:
1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
suitable for TCG because Loongson-3A R1 has fewest ASE.
2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
suitable for KVM because Loongson-3A R4 has the VZ ASE.
Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.
[AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
improved commit message, fixed checkpatch warnings]
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
---
target/mips/cpu.h | 32 ++++++++++-
target/mips/internal.h | 2 +
target/mips/mips-defs.h | 45 ++++++++-------
target/mips/{lmi_helper.c => lmmi_helper.c} | 0
target/mips/translate.c | 2 +
target/mips/translate_init.inc.c | 86 +++++++++++++++++++++++++++++
target/mips/Makefile.objs | 2 +-
7 files changed, 146 insertions(+), 23 deletions(-)
rename target/mips/{lmi_helper.c => lmmi_helper.c} (100%)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 94d01ea..7cf7f52 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t;
* 3 Config3 WatchLo3 WatchHi
* 4 Config4 WatchLo4 WatchHi
* 5 Config5 WatchLo5 WatchHi
- * 6 WatchLo6 WatchHi
- * 7 WatchLo7 WatchHi
+ * 6 Config6 WatchLo6 WatchHi
+ * 7 Config7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -940,7 +940,35 @@ struct CPUMIPSState {
#define CP0C5_UFR 2
#define CP0C5_NFExists 0
int32_t CP0_Config6;
+ int32_t CP0_Config6_rw_bitmask;
+#define CP0C6_BPPASS 31
+#define CP0C6_KPOS 24
+#define CP0C6_KE 23
+#define CP0C6_VTLBONLY 22
+#define CP0C6_LASX 21
+#define CP0C6_SSEN 20
+#define CP0C6_DISDRTIME 19
+#define CP0C6_PIXNUEN 18
+#define CP0C6_SCRAND 17
+#define CP0C6_LLEXCEN 16
+#define CP0C6_DISVC 15
+#define CP0C6_VCLRU 14
+#define CP0C6_DCLRU 13
+#define CP0C6_PIXUEN 12
+#define CP0C6_DISBLKLYEN 11
+#define CP0C6_UMEMUALEN 10
+#define CP0C6_SFBEN 8
+#define CP0C6_FLTINT 7
+#define CP0C6_VLTINT 6
+#define CP0C6_DISBTB 5
+#define CP0C6_STPREFCTL 2
+#define CP0C6_INSTPREF 1
+#define CP0C6_DATAPREF 0
int32_t CP0_Config7;
+ int64_t CP0_Config7_rw_bitmask;
+#define CP0C7_NAPCGEN 2
+#define CP0C7_UNIMUEN 1
+#define CP0C7_VFPUCGEN 0
uint64_t CP0_LLAddr;
uint64_t CP0_MAAR[MIPS_MAAR_MAX];
int32_t CP0_MAARI;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 684356e..7f159a9 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -36,7 +36,9 @@ struct mips_def_t {
int32_t CP0_Config5;
int32_t CP0_Config5_rw_bitmask;
int32_t CP0_Config6;
+ int32_t CP0_Config6_rw_bitmask;
int32_t CP0_Config7;
+ int32_t CP0_Config7_rw_bitmask;
target_ulong CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
int32_t SYNCI_Step;
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a831bb4..0c12910 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -15,7 +15,7 @@
* ------------------------------------------------
*/
/*
- * bits 0-31: MIPS base instruction sets
+ * bits 0-23: MIPS base instruction sets
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
@@ -34,30 +34,33 @@
#define ISA_MIPS64R6 0x0000000000004000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
/*
- * bits 32-47: MIPS ASEs
+ * bits 24-39: MIPS ASEs
*/
-#define ASE_MIPS16 0x0000000100000000ULL
-#define ASE_MIPS3D 0x0000000200000000ULL
-#define ASE_MDMX 0x0000000400000000ULL
-#define ASE_DSP 0x0000000800000000ULL
-#define ASE_DSP_R2 0x0000001000000000ULL
-#define ASE_DSP_R3 0x0000002000000000ULL
-#define ASE_MT 0x0000004000000000ULL
-#define ASE_SMARTMIPS 0x0000008000000000ULL
-#define ASE_MICROMIPS 0x0000010000000000ULL
-#define ASE_MSA 0x0000020000000000ULL
+#define ASE_MIPS16 0x0000000001000000ULL
+#define ASE_MIPS3D 0x0000000002000000ULL
+#define ASE_MDMX 0x0000000004000000ULL
+#define ASE_DSP 0x0000000008000000ULL
+#define ASE_DSP_R2 0x0000000010000000ULL
+#define ASE_DSP_R3 0x0000000020000000ULL
+#define ASE_MT 0x0000000040000000ULL
+#define ASE_SMARTMIPS 0x0000000080000000ULL
+#define ASE_MICROMIPS 0x0000000100000000ULL
+#define ASE_MSA 0x0000000200000000ULL
/*
- * bits 48-55: vendor-specific base instruction sets
+ * bits 40-51: vendor-specific base instruction sets
*/
-#define INSN_LOONGSON2E 0x0001000000000000ULL
-#define INSN_LOONGSON2F 0x0002000000000000ULL
-#define INSN_VR54XX 0x0004000000000000ULL
-#define INSN_R5900 0x0008000000000000ULL
+#define INSN_VR54XX 0x0000010000000000ULL
+#define INSN_R5900 0x0000020000000000ULL
+#define INSN_LOONGSON2E 0x0000040000000000ULL
+#define INSN_LOONGSON2F 0x0000080000000000ULL
+#define INSN_LOONGSON3A 0x0000100000000000ULL
/*
- * bits 56-63: vendor-specific ASEs
+ * bits 52-63: vendor-specific ASEs
*/
-#define ASE_MMI 0x0100000000000000ULL
-#define ASE_MXU 0x0200000000000000ULL
+#define ASE_MMI 0x0010000000000000ULL
+#define ASE_MXU 0x0020000000000000ULL
+#define ASE_LMMI 0x0040000000000000ULL
+#define ASE_LEXT 0x0080000000000000ULL
/* MIPS CPU defines. */
#define CPU_MIPS1 (ISA_MIPS1)
@@ -94,6 +97,8 @@
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
+#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
+
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.
diff --git a/target/mips/lmi_helper.c b/target/mips/lmmi_helper.c
similarity index 100%
rename from target/mips/lmi_helper.c
rename to target/mips/lmmi_helper.c
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 25b595a..2caf4cb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31206,7 +31206,9 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_Config5 = env->cpu_model->CP0_Config5;
env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
env->CP0_Config6 = env->cpu_model->CP0_Config6;
+ env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
env->CP0_Config7 = env->cpu_model->CP0_Config7;
+ env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
<< env->cpu_model->CP0_LLAddr_shift;
env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 6d145a9..ffae10d 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -802,6 +802,92 @@ const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
+ .name = "Loongson-3A1000",
+ .CP0_PRid = 0x6305,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
+ (3 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x74D8FFFF,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
+ (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
+ (0x1 << FCR0_D) | (0x1 << FCR0_S),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 42,
+ .PABITS = 48,
+ .insn_flags = CPU_LOONGSON3A,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
+ .name = "Loongson-3A4000",
+ .CP0_PRid = 0x14C000,
+ /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
+ (15 << CP0C2_SA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
+ (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
+ (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
+ .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
+ (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
+ (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
+ .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
+ (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
+ (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
+ (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
+ (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
+ (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
+ (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
+ (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
+ (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
+ (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
+ (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
+ (1 << CP0C6_DATAPREF),
+ .CP0_Config7 = 0,
+ .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
+ (1 << CP0C7_VFPUCGEN),
+ .CP0_LLAddr_rw_bitmask = 1,
+ .SYNCI_Step = 16,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x7DDBFFFF,
+ .CP0_PageGrain = (1 << CP0PG_ELPA),
+ .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
+ (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+ .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
+ (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
+ (0x1 << FCR0_D) | (0x1 << FCR0_S),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 48,
+ .PABITS = 48,
+ .insn_flags = CPU_LOONGSON3A,
+ .mmu_type = MMU_TYPE_R4000,
+ },
+ {
/* A generic CPU providing MIPS64 DSP R2 ASE features.
FIXME: Eventually this should be replaced by a real CPU model. */
.name = "mips64dspr2",
diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs
index 91eb691..b820b3b 100644
--- a/target/mips/Makefile.objs
+++ b/target/mips/Makefile.objs
@@ -1,6 +1,6 @@
obj-y += translate.o cpu.o gdbstub.o helper.o
obj-y += op_helper.o cp0_helper.o fpu_helper.o
-obj-y += dsp_helper.o lmi_helper.o msa_helper.o
+obj-y += dsp_helper.o lmmi_helper.o msa_helper.o
obj-$(CONFIG_SOFTMMU) += mips-semi.o
obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
obj-$(CONFIG_KVM) += kvm.o
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 20/20] target/mips: Enable hardware page table walker and CMGCR features for P5600
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (18 preceding siblings ...)
2020-06-09 16:28 ` [PULL 19/20] target/mips: Add Loongson-3 CPU definition Aleksandar Markovic
@ 2020-06-09 16:28 ` Aleksandar Markovic
2020-06-11 14:35 ` [PULL 00/20] MIPS queue for June 9th, 2020 Peter Maydell
20 siblings, 0 replies; 24+ messages in thread
From: Aleksandar Markovic @ 2020-06-09 16:28 UTC (permalink / raw)
To: qemu-devel, peter.maydell; +Cc: aleksandar.qemu.devel
From: Andrea Oliveri <oliveriandrea@gmail.com>
Enable hardware page table walker and CMGCR features for P5600 that
supports both.
Signed-off-by: Andrea Oliveri <oliveriandrea@gmail.com>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <de5adcb9fd0dd607b98026f4bfb34205432b6002.camel@gmail.com>
---
target/mips/translate_init.inc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index ffae10d..637cacc 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -366,7 +366,7 @@ const mips_def_t mips_defs[] =
},
{
/* FIXME:
- * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
+ * Config3: VZ, CTXTC, CDMM, TL
* Config4: MMUExtDef
* Config5: MRP
* FIR(FCR0): Has2008
@@ -380,10 +380,11 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
- (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
- (1 << CP0C3_VInt),
+ (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
+ (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(0x1c << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
--
2.7.4
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PULL 00/20] MIPS queue for June 9th, 2020
2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
` (19 preceding siblings ...)
2020-06-09 16:28 ` [PULL 20/20] target/mips: Enable hardware page table walker and CMGCR features for P5600 Aleksandar Markovic
@ 2020-06-11 14:35 ` Peter Maydell
20 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2020-06-11 14:35 UTC (permalink / raw)
To: Aleksandar Markovic; +Cc: QEMU Developers
On Tue, 9 Jun 2020 at 17:28, Aleksandar Markovic
<aleksandar.qemu.devel@gmail.com> wrote:
>
> The following changes since commit 49ee11555262a256afec592dfed7c5902d5eefd2:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-request' into staging (2020-06-08 11:04:57 +0100)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-jun-09-2020
>
> for you to fetch changes up to 6db06115d246ea6d24755657a98c185ed2a50210:
>
> target/mips: Enable hardware page table walker and CMGCR features for P5600 (2020-06-09 17:32:45 +0200)
>
> ----------------------------------------------------------------
>
> MIPS queue for June 9th, 2020
>
> Highlights:
>
> - Registring change of email address for two contributors
> - Cleanup and improvements of FPU helpers
> - Enabling some features of P5600
> - Adding two Loongson-3A CPU definitions
> - A checkpatch warning is known and should be ignored
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 19/20] target/mips: Add Loongson-3 CPU definition
2020-06-09 16:28 ` [PULL 19/20] target/mips: Add Loongson-3 CPU definition Aleksandar Markovic
@ 2020-11-29 22:09 ` Philippe Mathieu-Daudé
2020-11-30 3:45 ` Jiaxun Yang
0 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-11-29 22:09 UTC (permalink / raw)
To: qemu-devel, peter.maydell, Huacai Chen, Huacai Chen, Jiaxun Yang
Hi Huacai,
On 6/9/20 6:28 PM, Aleksandar Markovic wrote:
> From: Huacai Chen <zltjiangshi@gmail.com>
>
> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
> R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
> Loongson-3A R4 is the newest and its ISA is almost the superset of all
> others. To reduce complexity, we just define two CPU types:
>
> 1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
> suitable for TCG because Loongson-3A R1 has fewest ASE.
> 2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
> suitable for KVM because Loongson-3A R4 has the VZ ASE.
>
> Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.
>
> [AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
> improved commit message, fixed checkpatch warnings]
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
> Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
> ---
> target/mips/cpu.h | 32 ++++++++++-
> target/mips/internal.h | 2 +
> target/mips/mips-defs.h | 45 ++++++++-------
> target/mips/{lmi_helper.c => lmmi_helper.c} | 0
> target/mips/translate.c | 2 +
> target/mips/translate_init.inc.c | 86 +++++++++++++++++++++++++++++
> target/mips/Makefile.objs | 2 +-
> 7 files changed, 146 insertions(+), 23 deletions(-)
> rename target/mips/{lmi_helper.c => lmmi_helper.c} (100%)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 94d01ea..7cf7f52 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t;
> * 3 Config3 WatchLo3 WatchHi
> * 4 Config4 WatchLo4 WatchHi
> * 5 Config5 WatchLo5 WatchHi
> - * 6 WatchLo6 WatchHi
> - * 7 WatchLo7 WatchHi
> + * 6 Config6 WatchLo6 WatchHi
> + * 7 Config7 WatchLo7 WatchHi
> *
> *
> * Register 20 Register 21 Register 22 Register 23
> @@ -940,7 +940,35 @@ struct CPUMIPSState {
> #define CP0C5_UFR 2
> #define CP0C5_NFExists 0
> int32_t CP0_Config6;
> + int32_t CP0_Config6_rw_bitmask;
> +#define CP0C6_BPPASS 31
> +#define CP0C6_KPOS 24
> +#define CP0C6_KE 23
> +#define CP0C6_VTLBONLY 22
> +#define CP0C6_LASX 21
> +#define CP0C6_SSEN 20
> +#define CP0C6_DISDRTIME 19
> +#define CP0C6_PIXNUEN 18
> +#define CP0C6_SCRAND 17
> +#define CP0C6_LLEXCEN 16
> +#define CP0C6_DISVC 15
> +#define CP0C6_VCLRU 14
> +#define CP0C6_DCLRU 13
> +#define CP0C6_PIXUEN 12
> +#define CP0C6_DISBLKLYEN 11
> +#define CP0C6_UMEMUALEN 10
> +#define CP0C6_SFBEN 8
> +#define CP0C6_FLTINT 7
> +#define CP0C6_VLTINT 6
> +#define CP0C6_DISBTB 5
> +#define CP0C6_STPREFCTL 2
> +#define CP0C6_INSTPREF 1
> +#define CP0C6_DATAPREF 0
> int32_t CP0_Config7;
> + int64_t CP0_Config7_rw_bitmask;
> +#define CP0C7_NAPCGEN 2
> +#define CP0C7_UNIMUEN 1
> +#define CP0C7_VFPUCGEN 0
> uint64_t CP0_LLAddr;
> uint64_t CP0_MAAR[MIPS_MAAR_MAX];
> int32_t CP0_MAARI;
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index 684356e..7f159a9 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -36,7 +36,9 @@ struct mips_def_t {
> int32_t CP0_Config5;
> int32_t CP0_Config5_rw_bitmask;
> int32_t CP0_Config6;
> + int32_t CP0_Config6_rw_bitmask;
> int32_t CP0_Config7;
> + int32_t CP0_Config7_rw_bitmask;
> target_ulong CP0_LLAddr_rw_bitmask;
> int CP0_LLAddr_shift;
> int32_t SYNCI_Step;
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index a831bb4..0c12910 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -15,7 +15,7 @@
> * ------------------------------------------------
> */
> /*
> - * bits 0-31: MIPS base instruction sets
> + * bits 0-23: MIPS base instruction sets
> */
> #define ISA_MIPS1 0x0000000000000001ULL
> #define ISA_MIPS2 0x0000000000000002ULL
> @@ -34,30 +34,33 @@
> #define ISA_MIPS64R6 0x0000000000004000ULL
> #define ISA_NANOMIPS32 0x0000000000008000ULL
> /*
> - * bits 32-47: MIPS ASEs
> + * bits 24-39: MIPS ASEs
> */
> -#define ASE_MIPS16 0x0000000100000000ULL
> -#define ASE_MIPS3D 0x0000000200000000ULL
> -#define ASE_MDMX 0x0000000400000000ULL
> -#define ASE_DSP 0x0000000800000000ULL
> -#define ASE_DSP_R2 0x0000001000000000ULL
> -#define ASE_DSP_R3 0x0000002000000000ULL
> -#define ASE_MT 0x0000004000000000ULL
> -#define ASE_SMARTMIPS 0x0000008000000000ULL
> -#define ASE_MICROMIPS 0x0000010000000000ULL
> -#define ASE_MSA 0x0000020000000000ULL
> +#define ASE_MIPS16 0x0000000001000000ULL
> +#define ASE_MIPS3D 0x0000000002000000ULL
> +#define ASE_MDMX 0x0000000004000000ULL
> +#define ASE_DSP 0x0000000008000000ULL
> +#define ASE_DSP_R2 0x0000000010000000ULL
> +#define ASE_DSP_R3 0x0000000020000000ULL
> +#define ASE_MT 0x0000000040000000ULL
> +#define ASE_SMARTMIPS 0x0000000080000000ULL
> +#define ASE_MICROMIPS 0x0000000100000000ULL
> +#define ASE_MSA 0x0000000200000000ULL
> /*
> - * bits 48-55: vendor-specific base instruction sets
> + * bits 40-51: vendor-specific base instruction sets
> */
> -#define INSN_LOONGSON2E 0x0001000000000000ULL
> -#define INSN_LOONGSON2F 0x0002000000000000ULL
> -#define INSN_VR54XX 0x0004000000000000ULL
> -#define INSN_R5900 0x0008000000000000ULL
> +#define INSN_VR54XX 0x0000010000000000ULL
> +#define INSN_R5900 0x0000020000000000ULL
> +#define INSN_LOONGSON2E 0x0000040000000000ULL
> +#define INSN_LOONGSON2F 0x0000080000000000ULL
> +#define INSN_LOONGSON3A 0x0000100000000000ULL
> /*
> - * bits 56-63: vendor-specific ASEs
> + * bits 52-63: vendor-specific ASEs
> */
> -#define ASE_MMI 0x0100000000000000ULL
> -#define ASE_MXU 0x0200000000000000ULL
> +#define ASE_MMI 0x0010000000000000ULL
> +#define ASE_MXU 0x0020000000000000ULL
> +#define ASE_LMMI 0x0040000000000000ULL
> +#define ASE_LEXT 0x0080000000000000ULL
>
> /* MIPS CPU defines. */
> #define CPU_MIPS1 (ISA_MIPS1)
> @@ -94,6 +97,8 @@
> /* Wave Computing: "nanoMIPS" */
> #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
>
> +#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
> +
> /*
> * Strictly follow the architecture standard:
> * - Disallow "special" instruction handling for PMON/SPIM.
> diff --git a/target/mips/lmi_helper.c b/target/mips/lmmi_helper.c
> similarity index 100%
> rename from target/mips/lmi_helper.c
> rename to target/mips/lmmi_helper.c
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 25b595a..2caf4cb 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -31206,7 +31206,9 @@ void cpu_state_reset(CPUMIPSState *env)
> env->CP0_Config5 = env->cpu_model->CP0_Config5;
> env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
> env->CP0_Config6 = env->cpu_model->CP0_Config6;
> + env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
> env->CP0_Config7 = env->cpu_model->CP0_Config7;
> + env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
> env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
> << env->cpu_model->CP0_LLAddr_shift;
> env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
> diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
> index 6d145a9..ffae10d 100644
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -802,6 +802,92 @@ const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_R4000,
> },
> {
> + .name = "Loongson-3A1000",
> + .CP0_PRid = 0x6305,
> + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
> + (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
> + (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
> + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> + .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
> + (3 << CP0C2_SA),
> + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
> + .CP0_LLAddr_rw_bitmask = 0,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x74D8FFFF,
> + .CP0_PageGrain = (1 << CP0PG_ELPA),
> + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
> + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
> + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
> + (0x1 << FCR0_D) | (0x1 << FCR0_S),
> + .CP1_fcr31 = 0,
> + .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> + .SEGBITS = 42,
> + .PABITS = 48,
> + .insn_flags = CPU_LOONGSON3A,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> + {
> + .name = "Loongson-3A4000",
> + .CP0_PRid = 0x14C000,
> + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
> + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
> + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
> + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> + .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
> + (15 << CP0C2_SA),
> + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
Here you set the MSA bit in Config3, ...
> + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
> + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
> + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
> + (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
> + .CP0_Config4_rw_bitmask = 0,
> + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
> + .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
> + (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
> + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
> + .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
> + (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
> + (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
> + .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
> + (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
> + (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
> + (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
> + (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
> + (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
> + (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
> + (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
> + (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
> + (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
> + (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
> + (1 << CP0C6_DATAPREF),
> + .CP0_Config7 = 0,
> + .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
> + (1 << CP0C7_VFPUCGEN),
> + .CP0_LLAddr_rw_bitmask = 1,
> + .SYNCI_Step = 16,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x7DDBFFFF,
> + .CP0_PageGrain = (1 << CP0PG_ELPA),
> + .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
> + (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
> + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
> + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
> + (0x1 << FCR0_D) | (0x1 << FCR0_S),
> + .CP1_fcr31 = 0,
> + .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
> + .SEGBITS = 48,
> + .PABITS = 48,
> + .insn_flags = CPU_LOONGSON3A,
... but the MSA instructions are not allowed.
Looking at '龙芯 3A1000 处理器用户手册 下册 GS464 处理器核 V1.4'
Chapter 3.22 'Config 3 寄存器(16,3)', Table 3-24, it seems the
MSA bit is not set (which would make sense to me since the
GS464 has the Loong-SIMD opcodes).
Can you confirm CP0C3_MSAP bit should not be set in the 3A4000
(actually, any GS464-based)?
Thanks,
Phil.
> + .mmu_type = MMU_TYPE_R4000,
> + },
> + {
> /* A generic CPU providing MIPS64 DSP R2 ASE features.
> FIXME: Eventually this should be replaced by a real CPU model. */
> .name = "mips64dspr2",
> diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs
> index 91eb691..b820b3b 100644
> --- a/target/mips/Makefile.objs
> +++ b/target/mips/Makefile.objs
> @@ -1,6 +1,6 @@
> obj-y += translate.o cpu.o gdbstub.o helper.o
> obj-y += op_helper.o cp0_helper.o fpu_helper.o
> -obj-y += dsp_helper.o lmi_helper.o msa_helper.o
> +obj-y += dsp_helper.o lmmi_helper.o msa_helper.o
> obj-$(CONFIG_SOFTMMU) += mips-semi.o
> obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
> obj-$(CONFIG_KVM) += kvm.o
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 19/20] target/mips: Add Loongson-3 CPU definition
2020-11-29 22:09 ` Philippe Mathieu-Daudé
@ 2020-11-30 3:45 ` Jiaxun Yang
0 siblings, 0 replies; 24+ messages in thread
From: Jiaxun Yang @ 2020-11-30 3:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
qemu-devel, peter.maydell, Huacai Chen, Huacai Chen
在 2020/11/30 上午6:09, Philippe Mathieu-Daudé 写道:
> Hi Huacai,
>
> On 6/9/20 6:28 PM, Aleksandar Markovic wrote:
>> From: Huacai Chen <zltjiangshi@gmail.com>
>>
>> Loongson-3 CPU family include Loongson-3A R1/R2/R3/R4 and Loongson-3B
>> R1/R2. Loongson-3A R1 is the oldest and its ISA is the smallest, while
>> Loongson-3A R4 is the newest and its ISA is almost the superset of all
>> others. To reduce complexity, we just define two CPU types:
>>
>> 1) "Loongson-3A1000" CPU which is corresponding to Loongson-3A R1. It is
>> suitable for TCG because Loongson-3A R1 has fewest ASE.
>> 2) "Loongson-3A4000" CPU which is corresponding to Loongson-3A R4. It is
>> suitable for KVM because Loongson-3A R4 has the VZ ASE.
>>
>> Loongson-3A has CONFIG6 and CONFIG7, so add their bit-fields as well.
>>
>> [AM: Rearranged insn_flags, added comments, renamed lmi_helper.c,
>> improved commit message, fixed checkpatch warnings]
>>
>> Signed-off-by: Huacai Chen <chenhc@lemote.com>
>> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
>> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
>> Message-Id: <1591065557-9174-3-git-send-email-chenhc@lemote.com>
>> ---
>> target/mips/cpu.h | 32 ++++++++++-
>> target/mips/internal.h | 2 +
>> target/mips/mips-defs.h | 45 ++++++++-------
>> target/mips/{lmi_helper.c => lmmi_helper.c} | 0
>> target/mips/translate.c | 2 +
>> target/mips/translate_init.inc.c | 86 +++++++++++++++++++++++++++++
>> target/mips/Makefile.objs | 2 +-
>> 7 files changed, 146 insertions(+), 23 deletions(-)
>> rename target/mips/{lmi_helper.c => lmmi_helper.c} (100%)
>>
>> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
>> index 94d01ea..7cf7f52 100644
>> --- a/target/mips/cpu.h
>> +++ b/target/mips/cpu.h
>> @@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t;
>> * 3 Config3 WatchLo3 WatchHi
>> * 4 Config4 WatchLo4 WatchHi
>> * 5 Config5 WatchLo5 WatchHi
>> - * 6 WatchLo6 WatchHi
>> - * 7 WatchLo7 WatchHi
>> + * 6 Config6 WatchLo6 WatchHi
>> + * 7 Config7 WatchLo7 WatchHi
>> *
>> *
>> * Register 20 Register 21 Register 22 Register 23
>> @@ -940,7 +940,35 @@ struct CPUMIPSState {
>> #define CP0C5_UFR 2
>> #define CP0C5_NFExists 0
>> int32_t CP0_Config6;
>> + int32_t CP0_Config6_rw_bitmask;
>> +#define CP0C6_BPPASS 31
>> +#define CP0C6_KPOS 24
>> +#define CP0C6_KE 23
>> +#define CP0C6_VTLBONLY 22
>> +#define CP0C6_LASX 21
>> +#define CP0C6_SSEN 20
>> +#define CP0C6_DISDRTIME 19
>> +#define CP0C6_PIXNUEN 18
>> +#define CP0C6_SCRAND 17
>> +#define CP0C6_LLEXCEN 16
>> +#define CP0C6_DISVC 15
>> +#define CP0C6_VCLRU 14
>> +#define CP0C6_DCLRU 13
>> +#define CP0C6_PIXUEN 12
>> +#define CP0C6_DISBLKLYEN 11
>> +#define CP0C6_UMEMUALEN 10
>> +#define CP0C6_SFBEN 8
>> +#define CP0C6_FLTINT 7
>> +#define CP0C6_VLTINT 6
>> +#define CP0C6_DISBTB 5
>> +#define CP0C6_STPREFCTL 2
>> +#define CP0C6_INSTPREF 1
>> +#define CP0C6_DATAPREF 0
>> int32_t CP0_Config7;
>> + int64_t CP0_Config7_rw_bitmask;
>> +#define CP0C7_NAPCGEN 2
>> +#define CP0C7_UNIMUEN 1
>> +#define CP0C7_VFPUCGEN 0
>> uint64_t CP0_LLAddr;
>> uint64_t CP0_MAAR[MIPS_MAAR_MAX];
>> int32_t CP0_MAARI;
>> diff --git a/target/mips/internal.h b/target/mips/internal.h
>> index 684356e..7f159a9 100644
>> --- a/target/mips/internal.h
>> +++ b/target/mips/internal.h
>> @@ -36,7 +36,9 @@ struct mips_def_t {
>> int32_t CP0_Config5;
>> int32_t CP0_Config5_rw_bitmask;
>> int32_t CP0_Config6;
>> + int32_t CP0_Config6_rw_bitmask;
>> int32_t CP0_Config7;
>> + int32_t CP0_Config7_rw_bitmask;
>> target_ulong CP0_LLAddr_rw_bitmask;
>> int CP0_LLAddr_shift;
>> int32_t SYNCI_Step;
>> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
>> index a831bb4..0c12910 100644
>> --- a/target/mips/mips-defs.h
>> +++ b/target/mips/mips-defs.h
>> @@ -15,7 +15,7 @@
>> * ------------------------------------------------
>> */
>> /*
>> - * bits 0-31: MIPS base instruction sets
>> + * bits 0-23: MIPS base instruction sets
>> */
>> #define ISA_MIPS1 0x0000000000000001ULL
>> #define ISA_MIPS2 0x0000000000000002ULL
>> @@ -34,30 +34,33 @@
>> #define ISA_MIPS64R6 0x0000000000004000ULL
>> #define ISA_NANOMIPS32 0x0000000000008000ULL
>> /*
>> - * bits 32-47: MIPS ASEs
>> + * bits 24-39: MIPS ASEs
>> */
>> -#define ASE_MIPS16 0x0000000100000000ULL
>> -#define ASE_MIPS3D 0x0000000200000000ULL
>> -#define ASE_MDMX 0x0000000400000000ULL
>> -#define ASE_DSP 0x0000000800000000ULL
>> -#define ASE_DSP_R2 0x0000001000000000ULL
>> -#define ASE_DSP_R3 0x0000002000000000ULL
>> -#define ASE_MT 0x0000004000000000ULL
>> -#define ASE_SMARTMIPS 0x0000008000000000ULL
>> -#define ASE_MICROMIPS 0x0000010000000000ULL
>> -#define ASE_MSA 0x0000020000000000ULL
>> +#define ASE_MIPS16 0x0000000001000000ULL
>> +#define ASE_MIPS3D 0x0000000002000000ULL
>> +#define ASE_MDMX 0x0000000004000000ULL
>> +#define ASE_DSP 0x0000000008000000ULL
>> +#define ASE_DSP_R2 0x0000000010000000ULL
>> +#define ASE_DSP_R3 0x0000000020000000ULL
>> +#define ASE_MT 0x0000000040000000ULL
>> +#define ASE_SMARTMIPS 0x0000000080000000ULL
>> +#define ASE_MICROMIPS 0x0000000100000000ULL
>> +#define ASE_MSA 0x0000000200000000ULL
>> /*
>> - * bits 48-55: vendor-specific base instruction sets
>> + * bits 40-51: vendor-specific base instruction sets
>> */
>> -#define INSN_LOONGSON2E 0x0001000000000000ULL
>> -#define INSN_LOONGSON2F 0x0002000000000000ULL
>> -#define INSN_VR54XX 0x0004000000000000ULL
>> -#define INSN_R5900 0x0008000000000000ULL
>> +#define INSN_VR54XX 0x0000010000000000ULL
>> +#define INSN_R5900 0x0000020000000000ULL
>> +#define INSN_LOONGSON2E 0x0000040000000000ULL
>> +#define INSN_LOONGSON2F 0x0000080000000000ULL
>> +#define INSN_LOONGSON3A 0x0000100000000000ULL
>> /*
>> - * bits 56-63: vendor-specific ASEs
>> + * bits 52-63: vendor-specific ASEs
>> */
>> -#define ASE_MMI 0x0100000000000000ULL
>> -#define ASE_MXU 0x0200000000000000ULL
>> +#define ASE_MMI 0x0010000000000000ULL
>> +#define ASE_MXU 0x0020000000000000ULL
>> +#define ASE_LMMI 0x0040000000000000ULL
>> +#define ASE_LEXT 0x0080000000000000ULL
>>
>> /* MIPS CPU defines. */
>> #define CPU_MIPS1 (ISA_MIPS1)
>> @@ -94,6 +97,8 @@
>> /* Wave Computing: "nanoMIPS" */
>> #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
>>
>> +#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
>> +
>> /*
>> * Strictly follow the architecture standard:
>> * - Disallow "special" instruction handling for PMON/SPIM.
>> diff --git a/target/mips/lmi_helper.c b/target/mips/lmmi_helper.c
>> similarity index 100%
>> rename from target/mips/lmi_helper.c
>> rename to target/mips/lmmi_helper.c
>> diff --git a/target/mips/translate.c b/target/mips/translate.c
>> index 25b595a..2caf4cb 100644
>> --- a/target/mips/translate.c
>> +++ b/target/mips/translate.c
>> @@ -31206,7 +31206,9 @@ void cpu_state_reset(CPUMIPSState *env)
>> env->CP0_Config5 = env->cpu_model->CP0_Config5;
>> env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask;
>> env->CP0_Config6 = env->cpu_model->CP0_Config6;
>> + env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask;
>> env->CP0_Config7 = env->cpu_model->CP0_Config7;
>> + env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask;
>> env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask
>> << env->cpu_model->CP0_LLAddr_shift;
>> env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift;
>> diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
>> index 6d145a9..ffae10d 100644
>> --- a/target/mips/translate_init.inc.c
>> +++ b/target/mips/translate_init.inc.c
>> @@ -802,6 +802,92 @@ const mips_def_t mips_defs[] =
>> .mmu_type = MMU_TYPE_R4000,
>> },
>> {
>> + .name = "Loongson-3A1000",
>> + .CP0_PRid = 0x6305,
>> + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
>> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
>> + (MMU_TYPE_R4000 << CP0C0_MT),
>> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
>> + (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
>> + (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>> + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>> + .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
>> + (3 << CP0C2_SA),
>> + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
>> + .CP0_LLAddr_rw_bitmask = 0,
>> + .SYNCI_Step = 32,
>> + .CCRes = 2,
>> + .CP0_Status_rw_bitmask = 0x74D8FFFF,
>> + .CP0_PageGrain = (1 << CP0PG_ELPA),
>> + .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
>> + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
>> + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
>> + (0x1 << FCR0_D) | (0x1 << FCR0_S),
>> + .CP1_fcr31 = 0,
>> + .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
>> + .SEGBITS = 42,
>> + .PABITS = 48,
>> + .insn_flags = CPU_LOONGSON3A,
>> + .mmu_type = MMU_TYPE_R4000,
>> + },
>> + {
>> + .name = "Loongson-3A4000",
>> + .CP0_PRid = 0x14C000,
>> + /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
>> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
>> + (MMU_TYPE_R4000 << CP0C0_MT),
>> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
>> + (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
>> + (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
>> + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>> + .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
>> + (15 << CP0C2_SA),
>> + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
> Here you set the MSA bit in Config3, ...
>
>> + (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
>> + (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
>> + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
>> + (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
>> + .CP0_Config4_rw_bitmask = 0,
>> + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
>> + .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
>> + (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
>> + (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
>> + .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
>> + (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
>> + (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
>> + .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
>> + (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
>> + (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
>> + (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
>> + (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
>> + (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
>> + (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
>> + (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
>> + (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
>> + (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
>> + (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
>> + (1 << CP0C6_DATAPREF),
>> + .CP0_Config7 = 0,
>> + .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
>> + (1 << CP0C7_VFPUCGEN),
>> + .CP0_LLAddr_rw_bitmask = 1,
>> + .SYNCI_Step = 16,
>> + .CCRes = 2,
>> + .CP0_Status_rw_bitmask = 0x7DDBFFFF,
>> + .CP0_PageGrain = (1 << CP0PG_ELPA),
>> + .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
>> + (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
>> + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
>> + (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
>> + (0x1 << FCR0_D) | (0x1 << FCR0_S),
>> + .CP1_fcr31 = 0,
>> + .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
>> + .SEGBITS = 48,
>> + .PABITS = 48,
>> + .insn_flags = CPU_LOONGSON3A,
> ... but the MSA instructions are not allowed.
>
> Looking at '龙芯 3A1000 处理器用户手册 下册 GS464 处理器核 V1.4'
> Chapter 3.22 'Config 3 寄存器(16,3)', Table 3-24, it seems the
> MSA bit is not set (which would make sense to me since the
> GS464 has the Loong-SIMD opcodes).
>
> Can you confirm CP0C3_MSAP bit should not be set in the 3A4000
> (actually, any GS464-based)?
Loongson 3A4000 is actually a GS464V-based processor with MIPS MSA
ASE.
Unfortunately no document from Loongson was released to describe it's
CP0 register values but I can confirm MIPS MSA is present on real hardware~
Actually there are few more ASE extensions in GS464V. But as they're not
presented
in public documents and toolchain, we're not going to implement it in QEMU.
(Probably we should implement CPUCFG instruction in QEMU, which is used to
probe features on Loongson-3A4000 just like cpuid for x86)
Thanks.
- Jiaxun
>
> Thanks,
>
> Phil.
>
>> + .mmu_type = MMU_TYPE_R4000,
>> + },
>> + {
>> /* A generic CPU providing MIPS64 DSP R2 ASE features.
>> FIXME: Eventually this should be replaced by a real CPU model. */
>> .name = "mips64dspr2",
>> diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs
>> index 91eb691..b820b3b 100644
>> --- a/target/mips/Makefile.objs
>> +++ b/target/mips/Makefile.objs
>> @@ -1,6 +1,6 @@
>> obj-y += translate.o cpu.o gdbstub.o helper.o
>> obj-y += op_helper.o cp0_helper.o fpu_helper.o
>> -obj-y += dsp_helper.o lmi_helper.o msa_helper.o
>> +obj-y += dsp_helper.o lmmi_helper.o msa_helper.o
>> obj-$(CONFIG_SOFTMMU) += mips-semi.o
>> obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
>> obj-$(CONFIG_KVM) += kvm.o
>>
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2020-11-30 3:46 UTC | newest]
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2020-06-09 16:28 [PULL 00/20] MIPS queue for June 9th, 2020 Aleksandar Markovic
2020-06-09 16:28 ` [PULL 01/20] mailmap: Change email address of Filip Bozuta Aleksandar Markovic
2020-06-09 16:28 ` [PULL 02/20] mailmap: Change email address of Stefan Brankovic Aleksandar Markovic
2020-06-09 16:28 ` [PULL 03/20] target/mips: fpu: Demacro ADD.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 04/20] target/mips: fpu: Demacro SUB.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 05/20] target/mips: fpu: Demacro MUL.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 06/20] target/mips: fpu: Demacro DIV.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 07/20] target/mips: fpu: Remove now unused macro FLOAT_BINOP Aleksandar Markovic
2020-06-09 16:28 ` [PULL 08/20] target/mips: fpu: Demacro MADD.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 09/20] target/mips: fpu: Demacro MSUB.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 10/20] target/mips: fpu: Demacro NMADD.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 11/20] target/mips: fpu: Demacro NMSUB.<D|S|PS> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 12/20] target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros Aleksandar Markovic
2020-06-09 16:28 ` [PULL 13/20] target/mips: fpu: Demacro CLASS.<D|S> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 14/20] target/mips: fpu: Remove now unused FLOAT_CLASS macro Aleksandar Markovic
2020-06-09 16:28 ` [PULL 15/20] target/mips: fpu: Demacro RINT.<D|S> Aleksandar Markovic
2020-06-09 16:28 ` [PULL 16/20] target/mips: fpu: Remove now unused FLOAT_RINT macro Aleksandar Markovic
2020-06-09 16:28 ` [PULL 17/20] target/mips: fpu: Name better paired-single variables Aleksandar Markovic
2020-06-09 16:28 ` [PULL 18/20] target/mips: fpu: Refactor conversion from ieee to mips exception flags Aleksandar Markovic
2020-06-09 16:28 ` [PULL 19/20] target/mips: Add Loongson-3 CPU definition Aleksandar Markovic
2020-11-29 22:09 ` Philippe Mathieu-Daudé
2020-11-30 3:45 ` Jiaxun Yang
2020-06-09 16:28 ` [PULL 20/20] target/mips: Enable hardware page table walker and CMGCR features for P5600 Aleksandar Markovic
2020-06-11 14:35 ` [PULL 00/20] MIPS queue for June 9th, 2020 Peter Maydell
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