* [PULL 0/5] tcg patch queue
@ 2020-03-17 19:00 Richard Henderson
2020-03-17 19:00 ` [PULL 1/5] tcg/i386: Bound shift count expanding sari_vec Richard Henderson
` (6 more replies)
0 siblings, 7 replies; 22+ messages in thread
From: Richard Henderson @ 2020-03-17 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 40c67636f67c2a89745f2e698522fe917326a952:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20200317-pull-request' into staging (2020-03-17 14:00:56 +0000)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-20200317
for you to fetch changes up to 0270bd503e3699b7202200a2d693ad1feb57473f:
tcg: Remove tcg-runtime-gvec.c DO_CMP0 (2020-03-17 08:41:07 -0700)
----------------------------------------------------------------
Fix tcg/i386 bug vs sari_vec.
Fix tcg-runtime-gvec.c vs i386 without avx.
----------------------------------------------------------------
Richard Henderson (5):
tcg/i386: Bound shift count expanding sari_vec
tcg: Remove CONFIG_VECTOR16
tcg: Tidy tcg-runtime-gvec.c types
tcg: Tidy tcg-runtime-gvec.c DUP*
tcg: Remove tcg-runtime-gvec.c DO_CMP0
configure | 56 --------
accel/tcg/tcg-runtime-gvec.c | 298 +++++++++++++++++--------------------------
tcg/i386/tcg-target.inc.c | 9 +-
3 files changed, 122 insertions(+), 241 deletions(-)
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PULL 1/5] tcg/i386: Bound shift count expanding sari_vec
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
@ 2020-03-17 19:00 ` Richard Henderson
2020-03-17 19:00 ` [PULL 2/5] tcg: Remove CONFIG_VECTOR16 Richard Henderson
` (5 subsequent siblings)
6 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-03-17 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
A given RISU testcase for SVE can produce
tcg-op-vec.c:511: do_shifti: Assertion `i >= 0 && i < (8 << vece)' failed.
because expand_vec_sari gave a shift count of 32 to a MO_32
vector shift.
In 44f1441dbe1, we changed from direct expansion of vector opcodes
to re-use of the tcg expanders. So while the comment correctly notes
that the hw will handle such a shift count, we now have to take our
own sanity checks into account. Which is easy in this particular case.
Fixes: 44f1441dbe1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.inc.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index cdedcb2b25..223dba9c8c 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -3391,12 +3391,15 @@ static void expand_vec_sari(TCGType type, unsigned vece,
case MO_64:
if (imm <= 32) {
- /* We can emulate a small sign extend by performing an arithmetic
+ /*
+ * We can emulate a small sign extend by performing an arithmetic
* 32-bit shift and overwriting the high half of a 64-bit logical
- * shift (note that the ISA says shift of 32 is valid).
+ * shift. Note that the ISA says shift of 32 is valid, but TCG
+ * does not, so we have to bound the smaller shift -- we get the
+ * same result in the high half either way.
*/
t1 = tcg_temp_new_vec(type);
- tcg_gen_sari_vec(MO_32, t1, v1, imm);
+ tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
tcg_gen_shri_vec(MO_64, v0, v1, imm);
vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
tcgv_vec_arg(v0), tcgv_vec_arg(v0),
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PULL 2/5] tcg: Remove CONFIG_VECTOR16
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
2020-03-17 19:00 ` [PULL 1/5] tcg/i386: Bound shift count expanding sari_vec Richard Henderson
@ 2020-03-17 19:00 ` Richard Henderson
2020-03-17 19:00 ` [PULL 3/5] tcg: Tidy tcg-runtime-gvec.c types Richard Henderson
` (4 subsequent siblings)
6 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-03-17 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The comment in tcg-runtime-gvec.c about CONFIG_VECTOR16 says that
tcg-op-gvec.c has eliminated size 8 vectors, and only passes on
multiples of 16. This may have been true of the first few operations,
but is not true of all operations.
In particular, multiply, shift by scalar, and compare of 8- and 16-bit
elements are not expanded inline if host vector operations are not
supported.
For an x86_64 host that does not support AVX, this means that we will
fall back to the helper, which will attempt to use SSE instructions,
which will SEGV on an invalid 8-byte aligned memory operation.
This patch simply removes the CONFIG_VECTOR16 code and configuration
without further simplification.
Buglink: https://bugs.launchpad.net/bugs/1863508
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
configure | 56 ------------------------------------
accel/tcg/tcg-runtime-gvec.c | 35 +---------------------
2 files changed, 1 insertion(+), 90 deletions(-)
diff --git a/configure b/configure
index eb49bb6680..47b8dea78a 100755
--- a/configure
+++ b/configure
@@ -5711,58 +5711,6 @@ if test "$plugins" = "yes" &&
"for this purpose. You can't build with --static."
fi
-########################################
-# See if 16-byte vector operations are supported.
-# Even without a vector unit the compiler may expand these.
-# There is a bug in old GCC for PPC that crashes here.
-# Unfortunately it's the system compiler for Centos 7.
-
-cat > $TMPC << EOF
-typedef unsigned char U1 __attribute__((vector_size(16)));
-typedef unsigned short U2 __attribute__((vector_size(16)));
-typedef unsigned int U4 __attribute__((vector_size(16)));
-typedef unsigned long long U8 __attribute__((vector_size(16)));
-typedef signed char S1 __attribute__((vector_size(16)));
-typedef signed short S2 __attribute__((vector_size(16)));
-typedef signed int S4 __attribute__((vector_size(16)));
-typedef signed long long S8 __attribute__((vector_size(16)));
-static U1 a1, b1;
-static U2 a2, b2;
-static U4 a4, b4;
-static U8 a8, b8;
-static S1 c1;
-static S2 c2;
-static S4 c4;
-static S8 c8;
-static int i;
-void helper(void *d, void *a, int shift, int i);
-void helper(void *d, void *a, int shift, int i)
-{
- *(U1 *)(d + i) = *(U1 *)(a + i) << shift;
- *(U2 *)(d + i) = *(U2 *)(a + i) << shift;
- *(U4 *)(d + i) = *(U4 *)(a + i) << shift;
- *(U8 *)(d + i) = *(U8 *)(a + i) << shift;
-}
-int main(void)
-{
- a1 += b1; a2 += b2; a4 += b4; a8 += b8;
- a1 -= b1; a2 -= b2; a4 -= b4; a8 -= b8;
- a1 *= b1; a2 *= b2; a4 *= b4; a8 *= b8;
- a1 &= b1; a2 &= b2; a4 &= b4; a8 &= b8;
- a1 |= b1; a2 |= b2; a4 |= b4; a8 |= b8;
- a1 ^= b1; a2 ^= b2; a4 ^= b4; a8 ^= b8;
- a1 <<= i; a2 <<= i; a4 <<= i; a8 <<= i;
- a1 >>= i; a2 >>= i; a4 >>= i; a8 >>= i;
- c1 >>= i; c2 >>= i; c4 >>= i; c8 >>= i;
- return 0;
-}
-EOF
-
-vector16=no
-if compile_prog "" "" ; then
- vector16=yes
-fi
-
########################################
# See if __attribute__((alias)) is supported.
# This false for Xcode 9, but has been remedied for Xcode 10.
@@ -7383,10 +7331,6 @@ if test "$atomic64" = "yes" ; then
echo "CONFIG_ATOMIC64=y" >> $config_host_mak
fi
-if test "$vector16" = "yes" ; then
- echo "CONFIG_VECTOR16=y" >> $config_host_mak
-fi
-
if test "$attralias" = "yes" ; then
echo "CONFIG_ATTRIBUTE_ALIAS=y" >> $config_host_mak
fi
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 5b1902d591..00da0938a5 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -24,32 +24,6 @@
#include "tcg/tcg-gvec-desc.h"
-/* Virtually all hosts support 16-byte vectors. Those that don't can emulate
- * them via GCC's generic vector extension. This turns out to be simpler and
- * more reliable than getting the compiler to autovectorize.
- *
- * In tcg-op-gvec.c, we asserted that both the size and alignment of the data
- * are multiples of 16.
- *
- * When the compiler does not support all of the operations we require, the
- * loops are written so that we can always fall back on the base types.
- */
-#ifdef CONFIG_VECTOR16
-typedef uint8_t vec8 __attribute__((vector_size(16)));
-typedef uint16_t vec16 __attribute__((vector_size(16)));
-typedef uint32_t vec32 __attribute__((vector_size(16)));
-typedef uint64_t vec64 __attribute__((vector_size(16)));
-
-typedef int8_t svec8 __attribute__((vector_size(16)));
-typedef int16_t svec16 __attribute__((vector_size(16)));
-typedef int32_t svec32 __attribute__((vector_size(16)));
-typedef int64_t svec64 __attribute__((vector_size(16)));
-
-#define DUP16(X) { X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X }
-#define DUP8(X) { X, X, X, X, X, X, X, X }
-#define DUP4(X) { X, X, X, X }
-#define DUP2(X) { X, X }
-#else
typedef uint8_t vec8;
typedef uint16_t vec16;
typedef uint32_t vec32;
@@ -64,7 +38,6 @@ typedef int64_t svec64;
#define DUP8(X) X
#define DUP4(X) X
#define DUP2(X) X
-#endif /* CONFIG_VECTOR16 */
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
{
@@ -917,13 +890,7 @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
-/* If vectors are enabled, the compiler fills in -1 for true.
- Otherwise, we must take care of this by hand. */
-#ifdef CONFIG_VECTOR16
-# define DO_CMP0(X) X
-#else
-# define DO_CMP0(X) -(X)
-#endif
+#define DO_CMP0(X) -(X)
#define DO_CMP1(NAME, TYPE, OP) \
void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PULL 3/5] tcg: Tidy tcg-runtime-gvec.c types
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
2020-03-17 19:00 ` [PULL 1/5] tcg/i386: Bound shift count expanding sari_vec Richard Henderson
2020-03-17 19:00 ` [PULL 2/5] tcg: Remove CONFIG_VECTOR16 Richard Henderson
@ 2020-03-17 19:00 ` Richard Henderson
2020-03-17 19:00 ` [PULL 4/5] tcg: Tidy tcg-runtime-gvec.c DUP* Richard Henderson
` (3 subsequent siblings)
6 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-03-17 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the vec* types with their scalar expansions.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime-gvec.c | 270 +++++++++++++++++------------------
1 file changed, 130 insertions(+), 140 deletions(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 00da0938a5..97852b515b 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -24,16 +24,6 @@
#include "tcg/tcg-gvec-desc.h"
-typedef uint8_t vec8;
-typedef uint16_t vec16;
-typedef uint32_t vec32;
-typedef uint64_t vec64;
-
-typedef int8_t svec8;
-typedef int16_t svec16;
-typedef int32_t svec32;
-typedef int64_t svec64;
-
#define DUP16(X) X
#define DUP8(X) X
#define DUP4(X) X
@@ -56,8 +46,8 @@ void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + *(uint8_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -67,8 +57,8 @@ void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + *(uint16_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -78,8 +68,8 @@ void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + *(uint32_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -89,8 +79,8 @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -98,11 +88,11 @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec8 vecb = (vec8)DUP16(b);
+ uint8_t vecb = (uint8_t)DUP16(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + vecb;
}
clear_high(d, oprsz, desc);
}
@@ -110,11 +100,11 @@ void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec16 vecb = (vec16)DUP8(b);
+ uint16_t vecb = (uint16_t)DUP8(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + vecb;
}
clear_high(d, oprsz, desc);
}
@@ -122,11 +112,11 @@ void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec32 vecb = (vec32)DUP4(b);
+ uint32_t vecb = (uint32_t)DUP4(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + vecb;
}
clear_high(d, oprsz, desc);
}
@@ -134,11 +124,11 @@ void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_adds64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
+ uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) + vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + vecb;
}
clear_high(d, oprsz, desc);
}
@@ -148,8 +138,8 @@ void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - *(uint8_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -159,8 +149,8 @@ void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - *(uint16_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -170,8 +160,8 @@ void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - *(uint32_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -181,8 +171,8 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -190,11 +180,11 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec8 vecb = (vec8)DUP16(b);
+ uint8_t vecb = (uint8_t)DUP16(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - vecb;
}
clear_high(d, oprsz, desc);
}
@@ -202,11 +192,11 @@ void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec16 vecb = (vec16)DUP8(b);
+ uint16_t vecb = (uint16_t)DUP8(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - vecb;
}
clear_high(d, oprsz, desc);
}
@@ -214,11 +204,11 @@ void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec32 vecb = (vec32)DUP4(b);
+ uint32_t vecb = (uint32_t)DUP4(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - vecb;
}
clear_high(d, oprsz, desc);
}
@@ -226,11 +216,11 @@ void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_subs64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
+ uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) - vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - vecb;
}
clear_high(d, oprsz, desc);
}
@@ -240,8 +230,8 @@ void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) * *(vec8 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * *(uint8_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -251,8 +241,8 @@ void HELPER(gvec_mul16)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) * *(vec16 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * *(uint16_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -262,8 +252,8 @@ void HELPER(gvec_mul32)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) * *(vec32 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * *(uint32_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -273,8 +263,8 @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) * *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -282,11 +272,11 @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec8 vecb = (vec8)DUP16(b);
+ uint8_t vecb = (uint8_t)DUP16(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * vecb;
}
clear_high(d, oprsz, desc);
}
@@ -294,11 +284,11 @@ void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec16 vecb = (vec16)DUP8(b);
+ uint16_t vecb = (uint16_t)DUP8(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * vecb;
}
clear_high(d, oprsz, desc);
}
@@ -306,11 +296,11 @@ void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec32 vecb = (vec32)DUP4(b);
+ uint32_t vecb = (uint32_t)DUP4(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * vecb;
}
clear_high(d, oprsz, desc);
}
@@ -318,11 +308,11 @@ void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_muls64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
+ uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) * vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * vecb;
}
clear_high(d, oprsz, desc);
}
@@ -332,8 +322,8 @@ void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = -*(vec8 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = -*(uint8_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -343,8 +333,8 @@ void HELPER(gvec_neg16)(void *d, void *a, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = -*(vec16 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = -*(uint16_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -354,8 +344,8 @@ void HELPER(gvec_neg32)(void *d, void *a, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = -*(vec32 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = -*(uint32_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -365,8 +355,8 @@ void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = -*(vec64 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = -*(uint64_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -472,8 +462,8 @@ void HELPER(gvec_not)(void *d, void *a, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~*(vec64 *)(a + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~*(uint64_t *)(a + i);
}
clear_high(d, oprsz, desc);
}
@@ -483,8 +473,8 @@ void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -494,8 +484,8 @@ void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -505,8 +495,8 @@ void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -516,8 +506,8 @@ void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) &~ *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -527,8 +517,8 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) |~ *(uint64_t *)(b + i);
}
clear_high(d, oprsz, desc);
}
@@ -538,8 +528,8 @@ void HELPER(gvec_nand)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) & *(vec64 *)(b + i));
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) & *(uint64_t *)(b + i));
}
clear_high(d, oprsz, desc);
}
@@ -549,8 +539,8 @@ void HELPER(gvec_nor)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) | *(vec64 *)(b + i));
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) | *(uint64_t *)(b + i));
}
clear_high(d, oprsz, desc);
}
@@ -560,8 +550,8 @@ void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = ~(*(vec64 *)(a + i) ^ *(vec64 *)(b + i));
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = ~(*(uint64_t *)(a + i) ^ *(uint64_t *)(b + i));
}
clear_high(d, oprsz, desc);
}
@@ -569,11 +559,11 @@ void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
+ uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) & vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & vecb;
}
clear_high(d, oprsz, desc);
}
@@ -581,11 +571,11 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
+ uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ vecb;
}
clear_high(d, oprsz, desc);
}
@@ -593,11 +583,11 @@ void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_ors)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- vec64 vecb = (vec64)DUP2(b);
+ uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) | vecb;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | vecb;
}
clear_high(d, oprsz, desc);
}
@@ -608,8 +598,8 @@ void HELPER(gvec_shl8i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -620,8 +610,8 @@ void HELPER(gvec_shl16i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -632,8 +622,8 @@ void HELPER(gvec_shl32i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -644,8 +634,8 @@ void HELPER(gvec_shl64i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) << shift;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) << shift;
}
clear_high(d, oprsz, desc);
}
@@ -656,8 +646,8 @@ void HELPER(gvec_shr8i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(vec8 *)(d + i) = *(vec8 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -668,8 +658,8 @@ void HELPER(gvec_shr16i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(vec16 *)(d + i) = *(vec16 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -680,8 +670,8 @@ void HELPER(gvec_shr32i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(vec32 *)(d + i) = *(vec32 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -692,8 +682,8 @@ void HELPER(gvec_shr64i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(vec64 *)(d + i) = *(vec64 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -704,8 +694,8 @@ void HELPER(gvec_sar8i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec8)) {
- *(svec8 *)(d + i) = *(svec8 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
+ *(int8_t *)(d + i) = *(int8_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -716,8 +706,8 @@ void HELPER(gvec_sar16i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec16)) {
- *(svec16 *)(d + i) = *(svec16 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
+ *(int16_t *)(d + i) = *(int16_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -728,8 +718,8 @@ void HELPER(gvec_sar32i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec32)) {
- *(svec32 *)(d + i) = *(svec32 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(int32_t *)(d + i) = *(int32_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -740,8 +730,8 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
int shift = simd_data(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- *(svec64 *)(d + i) = *(svec64 *)(a + i) >> shift;
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(int64_t *)(d + i) = *(int64_t *)(a + i) >> shift;
}
clear_high(d, oprsz, desc);
}
@@ -904,12 +894,12 @@ void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
}
#define DO_CMP2(SZ) \
- DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \
- DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \
- DO_CMP1(gvec_lt##SZ, svec##SZ, <) \
- DO_CMP1(gvec_le##SZ, svec##SZ, <=) \
- DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \
- DO_CMP1(gvec_leu##SZ, vec##SZ, <=)
+ DO_CMP1(gvec_eq##SZ, uint##SZ##_t, ==) \
+ DO_CMP1(gvec_ne##SZ, uint##SZ##_t, !=) \
+ DO_CMP1(gvec_lt##SZ, int##SZ##_t, <) \
+ DO_CMP1(gvec_le##SZ, int##SZ##_t, <=) \
+ DO_CMP1(gvec_ltu##SZ, uint##SZ##_t, <) \
+ DO_CMP1(gvec_leu##SZ, uint##SZ##_t, <=)
DO_CMP2(8)
DO_CMP2(16)
@@ -1417,11 +1407,11 @@ void HELPER(gvec_bitsel)(void *d, void *a, void *b, void *c, uint32_t desc)
intptr_t oprsz = simd_oprsz(desc);
intptr_t i;
- for (i = 0; i < oprsz; i += sizeof(vec64)) {
- vec64 aa = *(vec64 *)(a + i);
- vec64 bb = *(vec64 *)(b + i);
- vec64 cc = *(vec64 *)(c + i);
- *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa);
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ uint64_t aa = *(uint64_t *)(a + i);
+ uint64_t bb = *(uint64_t *)(b + i);
+ uint64_t cc = *(uint64_t *)(c + i);
+ *(uint64_t *)(d + i) = (bb & aa) | (cc & ~aa);
}
clear_high(d, oprsz, desc);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PULL 4/5] tcg: Tidy tcg-runtime-gvec.c DUP*
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2020-03-17 19:00 ` [PULL 3/5] tcg: Tidy tcg-runtime-gvec.c types Richard Henderson
@ 2020-03-17 19:00 ` Richard Henderson
2020-03-17 19:00 ` [PULL 5/5] tcg: Remove tcg-runtime-gvec.c DO_CMP0 Richard Henderson
` (2 subsequent siblings)
6 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-03-17 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace the DUP* expansions with the scalar argument.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime-gvec.c | 50 +++++++++++-------------------------
1 file changed, 15 insertions(+), 35 deletions(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 97852b515b..f2199f14b4 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -24,11 +24,6 @@
#include "tcg/tcg-gvec-desc.h"
-#define DUP16(X) X
-#define DUP8(X) X
-#define DUP4(X) X
-#define DUP2(X) X
-
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
{
intptr_t maxsz = simd_maxsz(desc);
@@ -88,11 +83,10 @@ void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint8_t vecb = (uint8_t)DUP16(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
- *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + vecb;
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) + (uint8_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -100,11 +94,10 @@ void HELPER(gvec_adds8)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint16_t vecb = (uint16_t)DUP8(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
- *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + vecb;
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) + (uint16_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -112,11 +105,10 @@ void HELPER(gvec_adds16)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint32_t vecb = (uint32_t)DUP4(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
- *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + vecb;
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) + (uint32_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -124,11 +116,10 @@ void HELPER(gvec_adds32)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_adds64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
- *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + vecb;
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) + b;
}
clear_high(d, oprsz, desc);
}
@@ -180,11 +171,10 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint8_t vecb = (uint8_t)DUP16(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
- *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - vecb;
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) - (uint8_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -192,11 +182,10 @@ void HELPER(gvec_subs8)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint16_t vecb = (uint16_t)DUP8(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
- *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - vecb;
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) - (uint16_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -204,11 +193,10 @@ void HELPER(gvec_subs16)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint32_t vecb = (uint32_t)DUP4(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
- *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - vecb;
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) - (uint32_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -216,11 +204,10 @@ void HELPER(gvec_subs32)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_subs64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
- *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - vecb;
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) - b;
}
clear_high(d, oprsz, desc);
}
@@ -272,11 +259,10 @@ void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint8_t vecb = (uint8_t)DUP16(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
- *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * vecb;
+ *(uint8_t *)(d + i) = *(uint8_t *)(a + i) * (uint8_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -284,11 +270,10 @@ void HELPER(gvec_muls8)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint16_t vecb = (uint16_t)DUP8(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
- *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * vecb;
+ *(uint16_t *)(d + i) = *(uint16_t *)(a + i) * (uint16_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -296,11 +281,10 @@ void HELPER(gvec_muls16)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint32_t vecb = (uint32_t)DUP4(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
- *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * vecb;
+ *(uint32_t *)(d + i) = *(uint32_t *)(a + i) * (uint32_t)b;
}
clear_high(d, oprsz, desc);
}
@@ -308,11 +292,10 @@ void HELPER(gvec_muls32)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_muls64)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
- *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * vecb;
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) * b;
}
clear_high(d, oprsz, desc);
}
@@ -559,11 +542,10 @@ void HELPER(gvec_eqv)(void *d, void *a, void *b, uint32_t desc)
void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
- *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & vecb;
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & b;
}
clear_high(d, oprsz, desc);
}
@@ -571,11 +553,10 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
- *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ vecb;
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) ^ b;
}
clear_high(d, oprsz, desc);
}
@@ -583,11 +564,10 @@ void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
void HELPER(gvec_ors)(void *d, void *a, uint64_t b, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
- uint64_t vecb = (uint64_t)DUP2(b);
intptr_t i;
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
- *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | vecb;
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) | b;
}
clear_high(d, oprsz, desc);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PULL 5/5] tcg: Remove tcg-runtime-gvec.c DO_CMP0
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2020-03-17 19:00 ` [PULL 4/5] tcg: Tidy tcg-runtime-gvec.c DUP* Richard Henderson
@ 2020-03-17 19:00 ` Richard Henderson
2020-03-17 23:34 ` [PULL 0/5] tcg patch queue no-reply
2020-03-19 10:17 ` Peter Maydell
6 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2020-03-17 19:00 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Partial cleanup from the CONFIG_VECTOR16 removal.
Replace DO_CMP0 with its scalar expansion, a simple negation.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime-gvec.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index f2199f14b4..ca449702e6 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -860,15 +860,13 @@ void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
-#define DO_CMP0(X) -(X)
-
#define DO_CMP1(NAME, TYPE, OP) \
void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
{ \
intptr_t oprsz = simd_oprsz(desc); \
intptr_t i; \
for (i = 0; i < oprsz; i += sizeof(TYPE)) { \
- *(TYPE *)(d + i) = DO_CMP0(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \
+ *(TYPE *)(d + i) = -(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \
} \
clear_high(d, oprsz, desc); \
}
@@ -886,7 +884,6 @@ DO_CMP2(16)
DO_CMP2(32)
DO_CMP2(64)
-#undef DO_CMP0
#undef DO_CMP1
#undef DO_CMP2
--
2.20.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2020-03-17 19:00 ` [PULL 5/5] tcg: Remove tcg-runtime-gvec.c DO_CMP0 Richard Henderson
@ 2020-03-17 23:34 ` no-reply
2020-03-19 10:17 ` Peter Maydell
6 siblings, 0 replies; 22+ messages in thread
From: no-reply @ 2020-03-17 23:34 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel
Patchew URL: https://patchew.org/QEMU/20200317190013.25036-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PULL 0/5] tcg patch queue
Message-id: 20200317190013.25036-1-richard.henderson@linaro.org
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
83eaadd tcg: Remove tcg-runtime-gvec.c DO_CMP0
e0008a5 tcg: Tidy tcg-runtime-gvec.c DUP*
8e7d6d3 tcg: Tidy tcg-runtime-gvec.c types
44bd3c5 tcg: Remove CONFIG_VECTOR16
f410c29 tcg/i386: Bound shift count expanding sari_vec
=== OUTPUT BEGIN ===
1/5 Checking commit f410c296b774 (tcg/i386: Bound shift count expanding sari_vec)
2/5 Checking commit 44bd3c5fbbdb (tcg: Remove CONFIG_VECTOR16)
3/5 Checking commit 8e7d6d39c529 (tcg: Tidy tcg-runtime-gvec.c types)
ERROR: spaces required around that '&' (ctx:WxO)
#442: FILE: accel/tcg/tcg-runtime-gvec.c:510:
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) &~ *(uint64_t *)(b + i);
^
ERROR: space prohibited after that '~' (ctx:OxW)
#442: FILE: accel/tcg/tcg-runtime-gvec.c:510:
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) &~ *(uint64_t *)(b + i);
^
ERROR: spaces required around that '|' (ctx:WxO)
#453: FILE: accel/tcg/tcg-runtime-gvec.c:521:
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) |~ *(uint64_t *)(b + i);
^
ERROR: space prohibited after that '~' (ctx:OxW)
#453: FILE: accel/tcg/tcg-runtime-gvec.c:521:
+ *(uint64_t *)(d + i) = *(uint64_t *)(a + i) |~ *(uint64_t *)(b + i);
^
ERROR: spaces required around that '==' (ctx:WxB)
#677: FILE: accel/tcg/tcg-runtime-gvec.c:897:
+ DO_CMP1(gvec_eq##SZ, uint##SZ##_t, ==) \
^
ERROR: spaces required around that '!=' (ctx:WxB)
#678: FILE: accel/tcg/tcg-runtime-gvec.c:898:
+ DO_CMP1(gvec_ne##SZ, uint##SZ##_t, !=) \
^
ERROR: spaces required around that '<' (ctx:WxB)
#679: FILE: accel/tcg/tcg-runtime-gvec.c:899:
+ DO_CMP1(gvec_lt##SZ, int##SZ##_t, <) \
^
ERROR: spaces required around that '<=' (ctx:WxB)
#680: FILE: accel/tcg/tcg-runtime-gvec.c:900:
+ DO_CMP1(gvec_le##SZ, int##SZ##_t, <=) \
^
ERROR: spaces required around that '<' (ctx:WxB)
#681: FILE: accel/tcg/tcg-runtime-gvec.c:901:
+ DO_CMP1(gvec_ltu##SZ, uint##SZ##_t, <) \
^
ERROR: spaces required around that '<=' (ctx:WxB)
#682: FILE: accel/tcg/tcg-runtime-gvec.c:902:
+ DO_CMP1(gvec_leu##SZ, uint##SZ##_t, <=)
^
total: 10 errors, 0 warnings, 630 lines checked
Patch 3/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/5 Checking commit e0008a500fbb (tcg: Tidy tcg-runtime-gvec.c DUP*)
5/5 Checking commit 83eaadd6af23 (tcg: Remove tcg-runtime-gvec.c DO_CMP0)
ERROR: spaces required around that '*' (ctx:WxV)
#30: FILE: accel/tcg/tcg-runtime-gvec.c:869:
+ *(TYPE *)(d + i) = -(*(TYPE *)(a + i) OP *(TYPE *)(b + i)); \
^
total: 1 errors, 0 warnings, 23 lines checked
Patch 5/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20200317190013.25036-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2020-03-17 23:34 ` [PULL 0/5] tcg patch queue no-reply
@ 2020-03-19 10:17 ` Peter Maydell
6 siblings, 0 replies; 22+ messages in thread
From: Peter Maydell @ 2020-03-19 10:17 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Tue, 17 Mar 2020 at 19:00, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 40c67636f67c2a89745f2e698522fe917326a952:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/usb-20200317-pull-request' into staging (2020-03-17 14:00:56 +0000)
>
> are available in the Git repository at:
>
> https://github.com/rth7680/qemu.git tags/pull-tcg-20200317
>
> for you to fetch changes up to 0270bd503e3699b7202200a2d693ad1feb57473f:
>
> tcg: Remove tcg-runtime-gvec.c DO_CMP0 (2020-03-17 08:41:07 -0700)
>
> ----------------------------------------------------------------
> Fix tcg/i386 bug vs sari_vec.
> Fix tcg-runtime-gvec.c vs i386 without avx.
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-20 9:41 ` Thomas Huth
2023-01-20 10:50 ` Alex Bennée
2023-01-20 10:53 ` Ilya Leoshkevich
@ 2023-01-21 6:07 ` Richard Henderson
2 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2023-01-21 6:07 UTC (permalink / raw)
To: Thomas Huth, qemu-devel, Ilya Leoshkevich; +Cc: peter.maydell
On 1/19/23 23:41, Thomas Huth wrote:
> On 16/01/2023 23.36, Richard Henderson wrote:
>> The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>>
>> tests/qtest/qom-test: Do not print tested properties by default (2023-01-16 15:00:57
>> +0000)
>>
>> are available in the Git repository at:
>>
>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
>>
>> for you to fetch changes up to 61710a7e23a63546da0071ea32adb96476fa5d07:
>>
>> accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12 -1000)
>>
>> ----------------------------------------------------------------
>> - Reorg cpu_tb_exec around setjmp.
>> - Use __attribute__((target)) for buffer_is_zero.
>> - Add perfmap and jitdump for perf support.
>>
>> ----------------------------------------------------------------
>> Ilya Leoshkevich (3):
>> linux-user: Clean up when exiting due to a signal
>> accel/tcg: Add debuginfo support
>> tcg: add perfmap and jitdump
>>
>> Richard Henderson (2):
>> util/bufferiszero: Use __attribute__((target)) for avx2/avx512
>> accel/tcg: Split out cpu_exec_{setjmp,loop}
>
> Hi Richard, hi Ilya,
>
> with the recent QEMU master branch (commit 701ed34), I'm now seeing failures in Travis:
>
> https://app.travis-ci.com/github/huth/qemu/jobs/593786529#L14411
>
> Everything was still fine a couple of days ago (commit fb7e799):
>
> https://app.travis-ci.com/github/huth/qemu/builds/259755664
>
> ... so it seems this is likely related to this pull request. Could you please have a look?
Thankfully our s390x.ci.qemu.org has the same version gcc installed, and I was able to
reproduce this. But only once -- it's irregular and very low frequency.
The code generated by gcc is correct and easy to inspect, since cpu_exec_setjmp is now
quite small:
00000000000f3250 <cpu_exec_setjmp.isra.0>:
f3250: eb 6f f0 30 00 24 stmg %r6,%r15,48(%r15)
f3256: a7 39 00 00 lghi %r3,0
f325a: e3 f0 ff 58 ff 71 lay %r15,-168(%r15)
// Save cpu to stack+160.
f3260: e3 20 f0 a0 00 24 stg %r2,160(%r15)
f3266: 41 20 20 f0 la %r2,240(%r2)
f326a: c0 e5 ff fb 10 eb brasl %r14,55440 <__sigsetjmp@plt>
f3270: ec 26 00 0d 00 7e cijne %r2,0,f328a <cpu_exec_setjmp.isra.0+0x3a>
// Reload cpu for cpu_exec_loop().
f3276: e3 20 f0 a0 00 04 lg %r2,160(%r15)
f327c: c0 e5 ff ff fb ee brasl %r14,f2a58 <cpu_exec_loop.isra.0>
f3282: eb 6f f0 d8 00 04 lmg %r6,%r15,216(%r15)
f3288: 07 fe br %r14
// Load tls pointer and current_cpu address.
f328a: b2 4f 00 10 ear %r1,%a0
f328e: c0 20 00 0a 35 9d larl %r2,239dc8 <current_cpu@@Base+0x239dc8>
f3294: eb 11 00 20 00 0d sllg %r1,%r1,32
f329a: e3 20 20 00 00 04 lg %r2,0(%r2)
f32a0: b2 4f 00 11 ear %r1,%a1
// Reload cpu for comparison
f32a4: e3 30 f0 a0 00 04 lg %r3,160(%r15)
// cpu == current_cpu
f32aa: e3 32 10 00 00 20 cg %r3,0(%r2,%r1)
f32b0: a7 84 00 12 je f32d4 <cpu_exec_setjmp.isra.0+0x84>
...
The only way I can imagine that this comparison fails is if we have corrupted the stack in
some way. I have not been able to induce failure under any sort of debugging, and I can't
imagine where irregular corruption would have come from.
r~
r~
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-20 12:51 ` Thomas Huth
@ 2023-01-20 16:49 ` Alex Bennée
0 siblings, 0 replies; 22+ messages in thread
From: Alex Bennée @ 2023-01-20 16:49 UTC (permalink / raw)
To: Thomas Huth
Cc: Ilya Leoshkevich, Richard Henderson, qemu-devel, peter.maydell
Thomas Huth <thuth@redhat.com> writes:
> On 20/01/2023 11.53, Ilya Leoshkevich wrote:
>> On Fri, 2023-01-20 at 10:41 +0100, Thomas Huth wrote:
>>> On 16/01/2023 23.36, Richard Henderson wrote:
>>>> The following changes since commit
>>>> fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>>>>
>>>> tests/qtest/qom-test: Do not print tested properties by default
>>>> (2023-01-16 15:00:57 +0000)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
>>>>
>>>> for you to fetch changes up to
>>>> 61710a7e23a63546da0071ea32adb96476fa5d07:
>>>>
>>>> accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12
>>>> -1000)
>>>>
>>>> ----------------------------------------------------------------
>>>> - Reorg cpu_tb_exec around setjmp.
>>>> - Use __attribute__((target)) for buffer_is_zero.
>>>> - Add perfmap and jitdump for perf support.
>>>>
>>>> ----------------------------------------------------------------
>>>> Ilya Leoshkevich (3):
>>>> linux-user: Clean up when exiting due to a signal
>>>> accel/tcg: Add debuginfo support
>>>> tcg: add perfmap and jitdump
>>>>
>>>> Richard Henderson (2):
>>>> util/bufferiszero: Use __attribute__((target)) for
>>>> avx2/avx512
>>>> accel/tcg: Split out cpu_exec_{setjmp,loop}
>>>
>>> Hi Richard, hi Ilya,
>>>
>>> with the recent QEMU master branch (commit 701ed34), I'm now seeing
>>> failures
>>> in Travis:
>>>
>>> https://app.travis-ci.com/github/huth/qemu/jobs/593786529#L14411
>>>
>>> Everything was still fine a couple of days ago (commit fb7e799):
>>>
>>> https://app.travis-ci.com/github/huth/qemu/builds/259755664
>>>
>>> ... so it seems this is likely related to this pull request. Could
>>> you
>>> please have a look?
>>>
>>> Thanks,
>>> Thomas
>>>
>> I would expect this to be (temporarily) fixed by [1], but we
>> probably
>> don't set GITLAB_CI in Travis. Would it make sense to set it? It looks
>> as if this variable is currently used only to skip certain tests.
>> If not, then maybe split it into QEMU_CI, GITLAB_CI and TRAVIS_CI?
>> https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04438.html
>
> Ah, ok, so this test has issues in gitlab, too!
*sigh* yeah the test is flaky but this is a subtly different failure
mode. All the gitlab failures I saw where the test triggering the abort
rather than the assert catch we have here.
>
> For Travis, I think we should either check the CI or TRAVIS
> environment variables:
>
>
> https://docs.travis-ci.com/user/environment-variables/#default-environment-variables
>
> Thomas
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-20 10:53 ` Ilya Leoshkevich
@ 2023-01-20 12:51 ` Thomas Huth
2023-01-20 16:49 ` Alex Bennée
0 siblings, 1 reply; 22+ messages in thread
From: Thomas Huth @ 2023-01-20 12:51 UTC (permalink / raw)
To: Ilya Leoshkevich, Richard Henderson, Alex Bennée, qemu-devel
Cc: peter.maydell
On 20/01/2023 11.53, Ilya Leoshkevich wrote:
> On Fri, 2023-01-20 at 10:41 +0100, Thomas Huth wrote:
>> On 16/01/2023 23.36, Richard Henderson wrote:
>>> The following changes since commit
>>> fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>>>
>>> tests/qtest/qom-test: Do not print tested properties by default
>>> (2023-01-16 15:00:57 +0000)
>>>
>>> are available in the Git repository at:
>>>
>>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
>>>
>>> for you to fetch changes up to
>>> 61710a7e23a63546da0071ea32adb96476fa5d07:
>>>
>>> accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12
>>> -1000)
>>>
>>> ----------------------------------------------------------------
>>> - Reorg cpu_tb_exec around setjmp.
>>> - Use __attribute__((target)) for buffer_is_zero.
>>> - Add perfmap and jitdump for perf support.
>>>
>>> ----------------------------------------------------------------
>>> Ilya Leoshkevich (3):
>>> linux-user: Clean up when exiting due to a signal
>>> accel/tcg: Add debuginfo support
>>> tcg: add perfmap and jitdump
>>>
>>> Richard Henderson (2):
>>> util/bufferiszero: Use __attribute__((target)) for
>>> avx2/avx512
>>> accel/tcg: Split out cpu_exec_{setjmp,loop}
>>
>> Hi Richard, hi Ilya,
>>
>> with the recent QEMU master branch (commit 701ed34), I'm now seeing
>> failures
>> in Travis:
>>
>> https://app.travis-ci.com/github/huth/qemu/jobs/593786529#L14411
>>
>> Everything was still fine a couple of days ago (commit fb7e799):
>>
>> https://app.travis-ci.com/github/huth/qemu/builds/259755664
>>
>> ... so it seems this is likely related to this pull request. Could
>> you
>> please have a look?
>>
>> Thanks,
>> Thomas
>>
>
> I would expect this to be (temporarily) fixed by [1], but we probably
> don't set GITLAB_CI in Travis. Would it make sense to set it? It looks
> as if this variable is currently used only to skip certain tests.
>
> If not, then maybe split it into QEMU_CI, GITLAB_CI and TRAVIS_CI?
>
> https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04438.html
Ah, ok, so this test has issues in gitlab, too!
For Travis, I think we should either check the CI or TRAVIS environment
variables:
https://docs.travis-ci.com/user/environment-variables/#default-environment-variables
Thomas
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-20 9:41 ` Thomas Huth
2023-01-20 10:50 ` Alex Bennée
@ 2023-01-20 10:53 ` Ilya Leoshkevich
2023-01-20 12:51 ` Thomas Huth
2023-01-21 6:07 ` Richard Henderson
2 siblings, 1 reply; 22+ messages in thread
From: Ilya Leoshkevich @ 2023-01-20 10:53 UTC (permalink / raw)
To: Thomas Huth, Richard Henderson, Alex Bennée, qemu-devel
Cc: peter.maydell
On Fri, 2023-01-20 at 10:41 +0100, Thomas Huth wrote:
> On 16/01/2023 23.36, Richard Henderson wrote:
> > The following changes since commit
> > fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
> >
> > tests/qtest/qom-test: Do not print tested properties by default
> > (2023-01-16 15:00:57 +0000)
> >
> > are available in the Git repository at:
> >
> > https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
> >
> > for you to fetch changes up to
> > 61710a7e23a63546da0071ea32adb96476fa5d07:
> >
> > accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12
> > -1000)
> >
> > ----------------------------------------------------------------
> > - Reorg cpu_tb_exec around setjmp.
> > - Use __attribute__((target)) for buffer_is_zero.
> > - Add perfmap and jitdump for perf support.
> >
> > ----------------------------------------------------------------
> > Ilya Leoshkevich (3):
> > linux-user: Clean up when exiting due to a signal
> > accel/tcg: Add debuginfo support
> > tcg: add perfmap and jitdump
> >
> > Richard Henderson (2):
> > util/bufferiszero: Use __attribute__((target)) for
> > avx2/avx512
> > accel/tcg: Split out cpu_exec_{setjmp,loop}
>
> Hi Richard, hi Ilya,
>
> with the recent QEMU master branch (commit 701ed34), I'm now seeing
> failures
> in Travis:
>
> https://app.travis-ci.com/github/huth/qemu/jobs/593786529#L14411
>
> Everything was still fine a couple of days ago (commit fb7e799):
>
> https://app.travis-ci.com/github/huth/qemu/builds/259755664
>
> ... so it seems this is likely related to this pull request. Could
> you
> please have a look?
>
> Thanks,
> Thomas
>
I would expect this to be (temporarily) fixed by [1], but we probably
don't set GITLAB_CI in Travis. Would it make sense to set it? It looks
as if this variable is currently used only to skip certain tests.
If not, then maybe split it into QEMU_CI, GITLAB_CI and TRAVIS_CI?
https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04438.html
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-20 9:41 ` Thomas Huth
@ 2023-01-20 10:50 ` Alex Bennée
2023-01-20 10:53 ` Ilya Leoshkevich
2023-01-21 6:07 ` Richard Henderson
2 siblings, 0 replies; 22+ messages in thread
From: Alex Bennée @ 2023-01-20 10:50 UTC (permalink / raw)
To: Thomas Huth
Cc: Richard Henderson, Ilya Leoshkevich, peter.maydell, qemu-devel
Thomas Huth <thuth@redhat.com> writes:
> On 16/01/2023 23.36, Richard Henderson wrote:
>> The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>> tests/qtest/qom-test: Do not print tested properties by default
>> (2023-01-16 15:00:57 +0000)
>> are available in the Git repository at:
>> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
>> for you to fetch changes up to
>> 61710a7e23a63546da0071ea32adb96476fa5d07:
>> accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12
>> -1000)
>> ----------------------------------------------------------------
>> - Reorg cpu_tb_exec around setjmp.
>> - Use __attribute__((target)) for buffer_is_zero.
>> - Add perfmap and jitdump for perf support.
>> ----------------------------------------------------------------
>> Ilya Leoshkevich (3):
>> linux-user: Clean up when exiting due to a signal
>> accel/tcg: Add debuginfo support
>> tcg: add perfmap and jitdump
>> Richard Henderson (2):
>> util/bufferiszero: Use __attribute__((target)) for avx2/avx512
>> accel/tcg: Split out cpu_exec_{setjmp,loop}
>
> Hi Richard, hi Ilya,
>
> with the recent QEMU master branch (commit 701ed34), I'm now seeing
> failures in Travis:
>
> https://app.travis-ci.com/github/huth/qemu/jobs/593786529#L14411
>
> Everything was still fine a couple of days ago (commit fb7e799):
>
> https://app.travis-ci.com/github/huth/qemu/builds/259755664
>
> ... so it seems this is likely related to this pull request. Could you
> please have a look?
Hmm maybe the code motion has revealed another form of the compiler bug.
I guess these bugs don't die, they just refract.
>
> Thanks,
> Thomas
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-16 22:36 Richard Henderson
2023-01-17 15:47 ` Peter Maydell
@ 2023-01-20 9:41 ` Thomas Huth
2023-01-20 10:50 ` Alex Bennée
` (2 more replies)
1 sibling, 3 replies; 22+ messages in thread
From: Thomas Huth @ 2023-01-20 9:41 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, Ilya Leoshkevich; +Cc: peter.maydell
On 16/01/2023 23.36, Richard Henderson wrote:
> The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>
> tests/qtest/qom-test: Do not print tested properties by default (2023-01-16 15:00:57 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
>
> for you to fetch changes up to 61710a7e23a63546da0071ea32adb96476fa5d07:
>
> accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12 -1000)
>
> ----------------------------------------------------------------
> - Reorg cpu_tb_exec around setjmp.
> - Use __attribute__((target)) for buffer_is_zero.
> - Add perfmap and jitdump for perf support.
>
> ----------------------------------------------------------------
> Ilya Leoshkevich (3):
> linux-user: Clean up when exiting due to a signal
> accel/tcg: Add debuginfo support
> tcg: add perfmap and jitdump
>
> Richard Henderson (2):
> util/bufferiszero: Use __attribute__((target)) for avx2/avx512
> accel/tcg: Split out cpu_exec_{setjmp,loop}
Hi Richard, hi Ilya,
with the recent QEMU master branch (commit 701ed34), I'm now seeing failures
in Travis:
https://app.travis-ci.com/github/huth/qemu/jobs/593786529#L14411
Everything was still fine a couple of days ago (commit fb7e799):
https://app.travis-ci.com/github/huth/qemu/builds/259755664
... so it seems this is likely related to this pull request. Could you
please have a look?
Thanks,
Thomas
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2023-01-16 22:36 Richard Henderson
@ 2023-01-17 15:47 ` Peter Maydell
2023-01-20 9:41 ` Thomas Huth
1 sibling, 0 replies; 22+ messages in thread
From: Peter Maydell @ 2023-01-17 15:47 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, 16 Jan 2023 at 22:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
>
> tests/qtest/qom-test: Do not print tested properties by default (2023-01-16 15:00:57 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
>
> for you to fetch changes up to 61710a7e23a63546da0071ea32adb96476fa5d07:
>
> accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12 -1000)
>
> ----------------------------------------------------------------
> - Reorg cpu_tb_exec around setjmp.
> - Use __attribute__((target)) for buffer_is_zero.
> - Add perfmap and jitdump for perf support.
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PULL 0/5] tcg patch queue
@ 2023-01-16 22:36 Richard Henderson
2023-01-17 15:47 ` Peter Maydell
2023-01-20 9:41 ` Thomas Huth
0 siblings, 2 replies; 22+ messages in thread
From: Richard Henderson @ 2023-01-16 22:36 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
tests/qtest/qom-test: Do not print tested properties by default (2023-01-16 15:00:57 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
for you to fetch changes up to 61710a7e23a63546da0071ea32adb96476fa5d07:
accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12 -1000)
----------------------------------------------------------------
- Reorg cpu_tb_exec around setjmp.
- Use __attribute__((target)) for buffer_is_zero.
- Add perfmap and jitdump for perf support.
----------------------------------------------------------------
Ilya Leoshkevich (3):
linux-user: Clean up when exiting due to a signal
accel/tcg: Add debuginfo support
tcg: add perfmap and jitdump
Richard Henderson (2):
util/bufferiszero: Use __attribute__((target)) for avx2/avx512
accel/tcg: Split out cpu_exec_{setjmp,loop}
docs/devel/tcg.rst | 23 +++
meson.build | 16 +-
accel/tcg/debuginfo.h | 77 ++++++++++
accel/tcg/perf.h | 49 ++++++
accel/tcg/cpu-exec.c | 111 +++++++-------
accel/tcg/debuginfo.c | 96 ++++++++++++
accel/tcg/perf.c | 375 ++++++++++++++++++++++++++++++++++++++++++++++
accel/tcg/translate-all.c | 7 +
hw/core/loader.c | 5 +
linux-user/elfload.c | 3 +
linux-user/exit.c | 2 +
linux-user/main.c | 15 ++
linux-user/signal.c | 8 +-
softmmu/vl.c | 11 ++
tcg/tcg.c | 2 +
util/bufferiszero.c | 41 +----
accel/tcg/meson.build | 2 +
linux-user/meson.build | 1 +
qemu-options.hx | 20 +++
19 files changed, 763 insertions(+), 101 deletions(-)
create mode 100644 accel/tcg/debuginfo.h
create mode 100644 accel/tcg/perf.h
create mode 100644 accel/tcg/debuginfo.c
create mode 100644 accel/tcg/perf.c
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PULL 0/5] tcg patch queue
@ 2023-01-16 22:36 Richard Henderson
0 siblings, 0 replies; 22+ messages in thread
From: Richard Henderson @ 2023-01-16 22:36 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit fb7e7990342e59cf67dbd895c1a1e3fb1741df7a:
tests/qtest/qom-test: Do not print tested properties by default (2023-01-16 15:00:57 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230116
for you to fetch changes up to 61710a7e23a63546da0071ea32adb96476fa5d07:
accel/tcg: Split out cpu_exec_{setjmp,loop} (2023-01-16 10:14:12 -1000)
----------------------------------------------------------------
- Reorg cpu_tb_exec around setjmp.
- Use __attribute__((target)) for buffer_is_zero.
- Add perfmap and jitdump for perf support.
----------------------------------------------------------------
Ilya Leoshkevich (3):
linux-user: Clean up when exiting due to a signal
accel/tcg: Add debuginfo support
tcg: add perfmap and jitdump
Richard Henderson (2):
util/bufferiszero: Use __attribute__((target)) for avx2/avx512
accel/tcg: Split out cpu_exec_{setjmp,loop}
docs/devel/tcg.rst | 23 +++
meson.build | 16 +-
accel/tcg/debuginfo.h | 77 ++++++++++
accel/tcg/perf.h | 49 ++++++
accel/tcg/cpu-exec.c | 111 +++++++-------
accel/tcg/debuginfo.c | 96 ++++++++++++
accel/tcg/perf.c | 375 ++++++++++++++++++++++++++++++++++++++++++++++
accel/tcg/translate-all.c | 7 +
hw/core/loader.c | 5 +
linux-user/elfload.c | 3 +
linux-user/exit.c | 2 +
linux-user/main.c | 15 ++
linux-user/signal.c | 8 +-
softmmu/vl.c | 11 ++
tcg/tcg.c | 2 +
util/bufferiszero.c | 41 +----
accel/tcg/meson.build | 2 +
linux-user/meson.build | 1 +
qemu-options.hx | 20 +++
19 files changed, 763 insertions(+), 101 deletions(-)
create mode 100644 accel/tcg/debuginfo.h
create mode 100644 accel/tcg/perf.h
create mode 100644 accel/tcg/debuginfo.c
create mode 100644 accel/tcg/perf.c
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2021-05-01 18:51 Richard Henderson
2021-05-01 19:27 ` no-reply
@ 2021-05-02 13:32 ` Peter Maydell
1 sibling, 0 replies; 22+ messages in thread
From: Peter Maydell @ 2021-05-02 13:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Sat, 1 May 2021 at 19:51, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging (2021-04-30 16:02:00 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501
>
> for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:
>
> decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 -0700)
>
> ----------------------------------------------------------------
> Include cleanups.
> Decodetree enhancements for power10.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2021-05-01 18:51 Richard Henderson
@ 2021-05-01 19:27 ` no-reply
2021-05-02 13:32 ` Peter Maydell
1 sibling, 0 replies; 22+ messages in thread
From: no-reply @ 2021-05-01 19:27 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel
Patchew URL: https://patchew.org/QEMU/20210501185116.1338875-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210501185116.1338875-1-richard.henderson@linaro.org
Subject: [PULL 0/5] tcg patch queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20210501185116.1338875-1-richard.henderson@linaro.org -> patchew/20210501185116.1338875-1-richard.henderson@linaro.org
Switched to a new branch 'test'
3f52d0d decodetree: Extend argument set syntax to allow types
2f170a4 decodetree: Add support for 64-bit instructions
6567eed decodetree: More use of f-strings
95caca8 decodetree: Introduce whex and whexC helpers
b9a64b1 exec: Remove accel/tcg/ from include paths
=== OUTPUT BEGIN ===
1/5 Checking commit b9a64b13ad89 (exec: Remove accel/tcg/ from include paths)
2/5 Checking commit 95caca818e08 (decodetree: Introduce whex and whexC helpers)
ERROR: line over 90 characters
#52: FILE: scripts/decodetree.py:495:
+ output(ind, f'if ((insn & {whexC(innermask)}) == {whexC(innerbits)}) {{\n')
WARNING: line over 80 characters
#53: FILE: scripts/decodetree.py:496:
+ output(ind, f' /* {str_match_bits(p.fixedbits, p.fixedmask)} */\n')
total: 1 errors, 1 warnings, 136 lines checked
Patch 2/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/5 Checking commit 6567eed04461 (decodetree: More use of f-strings)
4/5 Checking commit 2f170a408195 (decodetree: Add support for 64-bit instructions)
WARNING: line over 80 characters
#75: FILE: scripts/decodetree.py:236:
+ ret = f'deposit{bitop_width}({ret}, {pos}, {bitop_width - pos}, {ext})'
total: 0 errors, 1 warnings, 63 lines checked
Patch 4/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/5 Checking commit 3f52d0d96c42 (decodetree: Extend argument set syntax to allow types)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#156:
new file mode 100644
total: 0 errors, 1 warnings, 121 lines checked
Patch 5/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210501185116.1338875-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PULL 0/5] tcg patch queue
@ 2021-05-01 18:51 Richard Henderson
2021-05-01 19:27 ` no-reply
2021-05-02 13:32 ` Peter Maydell
0 siblings, 2 replies; 22+ messages in thread
From: Richard Henderson @ 2021-05-01 18:51 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 8f860d2633baf9c2b6261f703f86e394c6bc22ca:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into staging (2021-04-30 16:02:00 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210501
for you to fetch changes up to af93ccacc772019298be4c3e47251cdaa60d0c21:
decodetree: Extend argument set syntax to allow types (2021-05-01 11:45:35 -0700)
----------------------------------------------------------------
Include cleanups.
Decodetree enhancements for power10.
----------------------------------------------------------------
Luis Fernando Fujita Pires (1):
decodetree: Add support for 64-bit instructions
Philippe Mathieu-Daudé (1):
exec: Remove accel/tcg/ from include paths
Richard Henderson (3):
decodetree: Introduce whex and whexC helpers
decodetree: More use of f-strings
decodetree: Extend argument set syntax to allow types
docs/devel/decodetree.rst | 11 ++-
meson.build | 1 -
include/exec/helper-gen.h | 4 +-
include/exec/helper-proto.h | 4 +-
include/exec/helper-tcg.h | 4 +-
tests/decode/succ_argset_type1.decode | 1 +
scripts/decodetree.py | 172 +++++++++++++++++++---------------
7 files changed, 112 insertions(+), 85 deletions(-)
create mode 100644 tests/decode/succ_argset_type1.decode
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PULL 0/5] tcg patch queue
2020-09-03 21:40 Richard Henderson
@ 2020-09-06 13:07 ` Peter Maydell
0 siblings, 0 replies; 22+ messages in thread
From: Peter Maydell @ 2020-09-06 13:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On Thu, 3 Sep 2020 at 22:41, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 3dd23a4fb8fd72d2220a90a809f213999ffe7f3a:
>
> Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' into staging (2020-09-03 14:12:48 +0100)
>
> are available in the Git repository at:
>
> https://github.com/rth7680/qemu.git tags/pull-tcg-20200903
>
> for you to fetch changes up to fe4b0b5bfa96c38ad1cad0689a86cca9f307e353:
>
> tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem (2020-09-03 13:13:58 -0700)
>
> ----------------------------------------------------------------
> Improve inlining in cputlb.c.
> Fix vector abs fallback.
> Only set parallel_cpus for SMP.
> Add vector dupm for 256-bit elements.
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PULL 0/5] tcg patch queue
@ 2020-09-03 21:40 Richard Henderson
2020-09-06 13:07 ` Peter Maydell
0 siblings, 1 reply; 22+ messages in thread
From: Richard Henderson @ 2020-09-03 21:40 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 3dd23a4fb8fd72d2220a90a809f213999ffe7f3a:
Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' into staging (2020-09-03 14:12:48 +0100)
are available in the Git repository at:
https://github.com/rth7680/qemu.git tags/pull-tcg-20200903
for you to fetch changes up to fe4b0b5bfa96c38ad1cad0689a86cca9f307e353:
tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem (2020-09-03 13:13:58 -0700)
----------------------------------------------------------------
Improve inlining in cputlb.c.
Fix vector abs fallback.
Only set parallel_cpus for SMP.
Add vector dupm for 256-bit elements.
----------------------------------------------------------------
Richard Henderson (4):
cputlb: Make store_helper less fragile to compiler optimizations
softmmu/cpus: Only set parallel_cpus for SMP
tcg: Eliminate one store for in-place 128-bit dup_mem
tcg: Implement 256-bit dup for tcg_gen_gvec_dup_mem
Stephen Long (1):
tcg: Fix tcg gen for vectorized absolute value
accel/tcg/cputlb.c | 138 ++++++++++++++++++++++++++++++-----------------------
softmmu/cpus.c | 11 ++++-
tcg/tcg-op-gvec.c | 61 ++++++++++++++++++++---
3 files changed, 143 insertions(+), 67 deletions(-)
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2023-01-21 6:08 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-17 19:00 [PULL 0/5] tcg patch queue Richard Henderson
2020-03-17 19:00 ` [PULL 1/5] tcg/i386: Bound shift count expanding sari_vec Richard Henderson
2020-03-17 19:00 ` [PULL 2/5] tcg: Remove CONFIG_VECTOR16 Richard Henderson
2020-03-17 19:00 ` [PULL 3/5] tcg: Tidy tcg-runtime-gvec.c types Richard Henderson
2020-03-17 19:00 ` [PULL 4/5] tcg: Tidy tcg-runtime-gvec.c DUP* Richard Henderson
2020-03-17 19:00 ` [PULL 5/5] tcg: Remove tcg-runtime-gvec.c DO_CMP0 Richard Henderson
2020-03-17 23:34 ` [PULL 0/5] tcg patch queue no-reply
2020-03-19 10:17 ` Peter Maydell
2020-09-03 21:40 Richard Henderson
2020-09-06 13:07 ` Peter Maydell
2021-05-01 18:51 Richard Henderson
2021-05-01 19:27 ` no-reply
2021-05-02 13:32 ` Peter Maydell
2023-01-16 22:36 Richard Henderson
2023-01-16 22:36 Richard Henderson
2023-01-17 15:47 ` Peter Maydell
2023-01-20 9:41 ` Thomas Huth
2023-01-20 10:50 ` Alex Bennée
2023-01-20 10:53 ` Ilya Leoshkevich
2023-01-20 12:51 ` Thomas Huth
2023-01-20 16:49 ` Alex Bennée
2023-01-21 6:07 ` Richard Henderson
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