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From: Peter Maydell <peter.maydell@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PULL 00/28] MIPS patches for 2021-08-25
Date: Thu, 26 Aug 2021 10:41:43 +0100	[thread overview]
Message-ID: <CAFEAcA-mgT7zL2-HBAgfMeF-DxAU7xpcrvMB-y57u-K5tOhjWA@mail.gmail.com> (raw)
In-Reply-To: <20210825130211.1542338-1-f4bug@amsat.org>

On Wed, 25 Aug 2021 at 14:06, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The following changes since commit d42685765653ec155fdf60910662f8830bdb2cef:
>
>   Open 6.2 development tree (2021-08-25 10:25:12 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/philmd/qemu.git tags/mips-20210825
>
> for you to fetch changes up to bf78469cc8ddb117b6db4a353e59fb4664a96de4:
>
>   target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() (2021-08-25 13:02:14 +0200)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - minor simplifications in PREF / JR opcodes
> - merge 32-bit/64-bit Release6 decodetree definitions
> - converted NEC Vr54xx extension opcodes to decodetree
> - housekeeping in gen_helper() macros
> - replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
> - allow Loongson 3A1000 to use up to 48-bit VAddr
>
> ----------------------------------------------------------------


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.2
for any user-visible changes.

-- PMM


      parent reply	other threads:[~2021-08-26  9:43 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 13:01 [PULL 00/28] MIPS patches for 2021-08-25 Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 01/28] target/mips: Remove JR opcode unused arguments Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 02/28] target/mips: Simplify PREF opcode Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 05/28] target/mips: Rename 'rtype' as 'r' Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 11/28] target/mips: Convert Vr54xx MUL* " Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 12/28] target/mips: Convert Vr54xx MSA* " Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 13/28] target/mips: Document Loongson-3A CPU definitions Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 16/28] target/mips: Remove gen_helper_0e3i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 17/28] target/mips: Remove gen_helper_1e2i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 21/28] target/mips: Inline gen_helper_0e0i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 23/28] target/mips: Define gen_helper() macros in translate.h Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 24/28] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 25/28] target/mips: Replace GET_LMASK() macro by get_lmask(32) function Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 26/28] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 27/28] target/mips: Store CP0_Config0 in DisasContext Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 28/28] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() Philippe Mathieu-Daudé
2021-08-26  9:41 ` Peter Maydell [this message]

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