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From: Peter Maydell <peter.maydell@linaro.org>
To: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Cc: QEMU Trivial <qemu-trivial@nongnu.org>,
	qemu-arm <qemu-arm@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue
Date: Thu, 28 Jan 2021 14:38:08 +0000	[thread overview]
Message-ID: <CAFEAcA-tj9+WETE-Jsq0Wt5xHZcX2ysx7BB-jNrVY1X4xravHA@mail.gmail.com> (raw)
In-Reply-To: <20210128143102.7834-1-michael.nawrocki@gtri.gatech.edu>

On Thu, 28 Jan 2021 at 14:31, Mike Nawrocki
<michael.nawrocki@gtri.gatech.edu> wrote:
>
> The SCR_EL3 register reset value (0)  and the value produced when
> writing 0 via the scr_write function (set as writefn in the register
> struct) differ. This causes migration to fail.
>
> I believe the solution is to specify a raw_writefn for that register.
>
> Failing invocation:
> $ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic
> QEMU 5.2.0 monitor - type 'help' for more information
> (qemu) migrate "exec:cat > img"
> (qemu) q
> $ qemu-system-arm -machine vexpress-a9 -cpu cortex-a9 -nographic -incoming "exec:cat img"
> qemu-system-arm: error while loading state for instance 0x0 of device 'cpu'
> qemu-system-arm: load of migration failed: Operation not permitted

I'll review the patch later, but for the moment just a note that
I'm pretty sure this is not the only issue you'll run into with
trying to migrate an AArch32 TrustZone-enabled CPU.
https://bugs.launchpad.net/qemu/+bug/1839807 has the details
but in summary we aren't migrating the Secure banked contents
of cp15 registers which are banked Secure/Non-Secure. The
symptom will be that migration succeeds but the guest doesn't
behave correctly on the destination/after state restore.

thanks
-- PMM


  parent reply	other threads:[~2021-01-28 14:40 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-28 14:31 [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue michael.nawrocki--- via
2021-01-28 14:31 ` [PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register michael.nawrocki--- via
2021-02-02 11:29   ` Peter Maydell
2021-02-03 14:50     ` michael.nawrocki--- via
2021-02-03 15:04       ` Peter Maydell
2021-02-03 16:58         ` michael.nawrocki--- via
2021-01-28 14:38 ` Peter Maydell [this message]
2021-02-03 16:28 ` [PATCH 0/1] target/arm: Fix SCR_EL3 migration issue Philippe Mathieu-Daudé

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