[Qemu-devel] [PATCH+RFC 0/6] target/arm: Define cortex-a{73, 75, 76}

[Qemu-devel] [PATCH+RFC 0/6] target/arm: Define cortex-a{73, 75, 76}

[Richard Henderson]

There have been several announcements since the a72.

The a75 and a76 entries are RFC because, while they boot with a 3.15
kernel, they do not boot with a 5.0-rc7 kernel.  I'm really not sure
where things have gone off the rails.  It'll take some more serious
tracing to figure out what went wrong.

I post this now mostly to get feedback on patch 5.  Should we do
more to elide *all* of the aa32 system registers for that case?


r~


Richard Henderson (6):
  target/arm: Implement ID_PFR2
  target/arm: Define cortex-a73
  target/arm: Implement ID_AA64MMFR2
  target/arm: Define cortex-a75
  target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert
  target/arm: Define cortex-a76

 target/arm/cpu.h    |  18 +++++
 hw/arm/virt.c       |   3 +
 target/arm/cpu64.c  | 179 +++++++++++++++++++++++++++++++++++++++++++-
 target/arm/helper.c |  66 ++++++++++------
 target/arm/kvm64.c  |   2 +
 5 files changed, 240 insertions(+), 28 deletions(-)

-- 
2.17.2

[Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2

[Richard Henderson]

This was defined at some point before ARMv8.4, and will
shortly be used by new processor descriptions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    | 1 +
 target/arm/helper.c | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 84ae6849c2..c57f8e9ba8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -863,6 +863,7 @@ struct ARMCPU {
     uint32_t reset_sctlr;
     uint32_t id_pfr0;
     uint32_t id_pfr1;
+    uint32_t id_pfr2;
     uint32_t id_dfr0;
     uint64_t pmceid0;
     uint64_t pmceid1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a018eb23fe..8903cc13d8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6092,10 +6092,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = 0 },
-            { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
               .access = PL1_R, .type = ARM_CP_CONST,
-              .resetvalue = 0 },
+              .resetvalue = cpu->id_pfr2 },
             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
               .access = PL1_R, .type = ARM_CP_CONST,
-- 
2.17.2

[Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73

[Richard Henderson]

There are new field definitions, CSV2 and CSV3, that do not yet
appear in the main ARM ARM.  Define the ID_AA64PF0 versions,
since we already define the rest of those bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h   |  2 ++
 hw/arm/virt.c      |  1 +
 target/arm/cpu64.c | 63 +++++++++++++++++++++++++++++++++++++++++++---
 3 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c57f8e9ba8..c2899f0bed 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1694,6 +1694,8 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
 FIELD(ID_AA64PFR0, GIC, 24, 4)
 FIELD(ID_AA64PFR0, RAS, 28, 4)
 FIELD(ID_AA64PFR0, SVE, 32, 4)
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
 
 FIELD(ID_AA64PFR1, BT, 0, 4)
 FIELD(ID_AA64PFR1, SBSS, 4, 4)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 99c2b6e60d..c69a734878 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -173,6 +173,7 @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a53"),
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
+    ARM_CPU_TYPE_NAME("cortex-a73"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index eff0f164dd..d34aa3af75 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -51,7 +51,8 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 }
 #endif
 
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
+/* These extra registers are used by (most of?) the cortex-a* series.  */
+static const ARMCPRegInfo cortex_aXX_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
     { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
@@ -149,7 +150,7 @@ static void aarch64_a57_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
 static void aarch64_a53_initfn(Object *obj)
@@ -203,7 +204,7 @@ static void aarch64_a53_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
 static void aarch64_a72_initfn(Object *obj)
@@ -255,7 +256,60 @@ static void aarch64_a72_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+    define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
+}
+
+static void aarch64_a73_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a73";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_VFP4);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x411fd090;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x41034091;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x12111111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x84448004;
+    cpu->reset_sctlr = 0x00c50838;
+    cpu->id_pfr0 = 0x00010131;
+    cpu->id_pfr1 = 0x00011011;
+    cpu->id_pfr2 = 0x00000001;
+    cpu->id_dfr0 = 0x03010066;
+    cpu->id_afr0 = 0x00000000;
+    cpu->id_mmfr0 = 0x10201105;
+    cpu->id_mmfr1 = 0x40000000;
+    cpu->id_mmfr2 = 0x01260000;
+    cpu->id_mmfr3 = 0x02102211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_aa64pfr0 = 0x1100000000002222ull;
+    cpu->id_aa64dfr0 = 0x10305106;
+    cpu->isar.id_aa64isar0 = 0x00011120;
+    cpu->isar.id_aa64mmfr0 = 0x00101122;
+    cpu->dbgdidr = 0x3516d000;
+    cpu->clidr = 0x0a200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
@@ -378,6 +432,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
+    { .name = "cortex-a73",         .initfn = aarch64_a73_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
     { .name = NULL }
 };
-- 
2.17.2

[Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2

[Richard Henderson]

This was res0 before ARMv8.2, but will shortly be used by
new processor definitions.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    | 15 +++++++++++++++
 target/arm/helper.c |  4 ++--
 target/arm/kvm64.c  |  2 ++
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c2899f0bed..02642a7db3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -855,6 +855,7 @@ struct ARMCPU {
         uint64_t id_aa64pfr1;
         uint64_t id_aa64mmfr0;
         uint64_t id_aa64mmfr1;
+        uint64_t id_aa64mmfr2;
     } isar;
     uint32_t midr;
     uint32_t revidr;
@@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
 FIELD(ID_AA64MMFR1, XNX, 28, 4)
 
+FIELD(ID_AA64MMFR2, CNP, 0, 4)
+FIELD(ID_AA64MMFR2, UAO, 4, 4)
+FIELD(ID_AA64MMFR2, LSM, 8, 4)
+FIELD(ID_AA64MMFR2, IESB, 12, 4)
+FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
+FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
+FIELD(ID_AA64MMFR2, NV, 24, 4)
+FIELD(ID_AA64MMFR2, ST, 28, 4)
+FIELD(ID_AA64MMFR2, AT, 32, 4)
+FIELD(ID_AA64MMFR2, IDS, 36, 4)
+FIELD(ID_AA64MMFR2, FWB, 40, 4)
+FIELD(ID_AA64MMFR2, TTL, 48, 4)
+FIELD(ID_AA64MMFR2, BBM, 52, 4)
+
 FIELD(ID_DFR0, COPDBG, 0, 4)
 FIELD(ID_DFR0, COPSDBG, 4, 4)
 FIELD(ID_DFR0, MMAPDBG, 8, 4)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8903cc13d8..fbdca9324b 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6052,10 +6052,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
               .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->isar.id_aa64mmfr1 },
-            { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+            { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
               .access = PL1_R, .type = ARM_CP_CONST,
-              .resetvalue = 0 },
+              .resetvalue = cpu->isar.id_aa64mmfr2 },
             { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
               .access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index e3ba149248..c3d421b53b 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -542,6 +542,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
                               ARM64_SYS_REG(3, 0, 0, 7, 0));
         err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
                               ARM64_SYS_REG(3, 0, 0, 7, 1));
+        err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
+                              ARM64_SYS_REG(3, 0, 0, 7, 2));
 
         /*
          * Note that if AArch32 support is not present in the host,
-- 
2.17.2

[Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/virt.c      |  1 +
 target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index c69a734878..06a155724c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -174,6 +174,7 @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a57"),
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a73"),
+    ARM_CPU_TYPE_NAME("cortex-a75"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index d34aa3af75..325e0ecf17 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
+static void aarch64_a75_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a75";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_VFP4);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+    cpu->midr = 0x413fd0a1;
+    cpu->revidr = 0x00000000;
+    cpu->reset_fpsid = 0x410340a2;
+    cpu->isar.mvfr0 = 0x10110222;
+    cpu->isar.mvfr1 = 0x13211111;
+    cpu->isar.mvfr2 = 0x00000043;
+    cpu->ctr = 0x84448004;
+    cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */
+    cpu->id_pfr0 = 0x00010131;
+    cpu->id_pfr1 = 0x00011011;
+    cpu->id_pfr2 = 0x00000001;
+    cpu->id_dfr0 = 0x04010088;
+    cpu->id_afr0 = 0x00000000;
+    cpu->id_mmfr0 = 0x10201105;
+    cpu->id_mmfr1 = 0x40000000;
+    cpu->id_mmfr2 = 0x01260000;
+    cpu->id_mmfr3 = 0x02122211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_aa64pfr0 = 0x1100000010112222ull;
+    cpu->id_aa64dfr0 = 0x10305408;
+    cpu->isar.id_aa64isar0 = 0x10211120;
+    cpu->isar.id_aa64isar1 = 0x00100001;
+    cpu->isar.id_aa64mmfr0 = 0x00101124;
+    cpu->isar.id_aa64mmfr1 = 0x10212122;
+    cpu->isar.id_aa64mmfr2 = 0x00001011;
+    cpu->dbgdidr = 0x3518d000;
+    cpu->clidr = 0x08200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
+}
+
 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
                                void *opaque, Error **errp)
 {
@@ -433,6 +490,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a73",         .initfn = aarch64_a73_initfn },
+    { .name = "cortex-a75",         .initfn = aarch64_a75_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
     { .name = NULL }
 };
-- 
2.17.2

[Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert

[Richard Henderson]

Only perform the assert when both registers exist.
Extract the variables from ID_AA64DFR0_EL1 for AArch64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/helper.c | 58 +++++++++++++++++++++++++++++----------------
 1 file changed, 38 insertions(+), 20 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index fbdca9324b..1d8c8998c4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5544,32 +5544,50 @@ static void define_debug_regs(ARMCPU *cpu)
     /* Define v7 and v8 architectural debug registers.
      * These are just dummy implementations for now.
      */
-    int i;
-    int wrps, brps, ctx_cmps;
-    ARMCPRegInfo dbgdidr = {
-        .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
-        .access = PL0_R, .accessfn = access_tda,
-        .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
-    };
+    int i, wrps, brps, ctx_cmps;
+    bool have_aa32;
 
-    /* Note that all these register fields hold "number of Xs minus 1". */
-    brps = extract32(cpu->dbgdidr, 24, 4);
-    wrps = extract32(cpu->dbgdidr, 28, 4);
-    ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
-
-    assert(ctx_cmps <= brps);
-
-    /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
+    /*
+     * The DBGDIDR and ID_AA64DFR0_EL1 define various properties
      * of the debug registers such as number of breakpoints;
      * check that if they both exist then they agree.
+     *
+     * Note that all these register fields hold "number of Xs minus 1".
      */
     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
-        assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
-        assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
-    }
+        brps = extract32(cpu->id_aa64dfr0, 12, 4);
+        wrps = extract32(cpu->id_aa64dfr0, 20, 4);
+        ctx_cmps = extract32(cpu->id_aa64dfr0, 28, 4);
 
-    define_one_arm_cp_reg(cpu, &dbgdidr);
+        /*
+         * There are cpus with aarch32 only at EL0, and which do not
+         * have the 32-bit system registers.
+         */
+        have_aa32
+            = (FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2 ||
+               FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL2) >= 2 ||
+               FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3) >= 2);
+        if (have_aa32) {
+            assert(extract32(cpu->dbgdidr, 24, 4) == brps);
+            assert(extract32(cpu->dbgdidr, 28, 4) == wrps);
+            assert(extract32(cpu->dbgdidr, 20, 4) == ctx_cmps);
+        }
+    } else {
+        have_aa32 = true;
+        brps = extract32(cpu->dbgdidr, 24, 4);
+        wrps = extract32(cpu->dbgdidr, 28, 4);
+        ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
+    }
+    assert(ctx_cmps <= brps);
+
+    if (have_aa32) {
+        ARMCPRegInfo dbgdidr = {
+            .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
+            .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tda,
+            .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
+        };
+        define_one_arm_cp_reg(cpu, &dbgdidr);
+    }
     define_arm_cp_regs(cpu, debug_cp_reginfo);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
-- 
2.17.2

[Qemu-devel] [RFC 6/6] target/arm: Define cortex-a76

[Richard Henderson]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/virt.c      |  1 +
 target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 06a155724c..4495ce8918 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -175,6 +175,7 @@ static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("cortex-a73"),
     ARM_CPU_TYPE_NAME("cortex-a75"),
+    ARM_CPU_TYPE_NAME("cortex-a76"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
 };
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 325e0ecf17..4a92d7656a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -369,6 +369,63 @@ static void aarch64_a75_initfn(Object *obj)
     define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
 }
 
+static void aarch64_a76_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    cpu->dtb_compatible = "arm,cortex-a76";
+    set_feature(&cpu->env, ARM_FEATURE_V8);
+    set_feature(&cpu->env, ARM_FEATURE_VFP4);
+    set_feature(&cpu->env, ARM_FEATURE_NEON);
+    set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+    set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+    set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+    set_feature(&cpu->env, ARM_FEATURE_EL2);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
+    set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+    /*
+     * Note that the A76 only supports AA32 at EL0, so the
+     * AA32-only EL1 id registers do not exist.
+     */
+    cpu->midr = 0x413fd0b1;
+    cpu->revidr = 0x00000000;
+    cpu->ctr = 0x8444C004;
+    cpu->reset_sctlr = 0x30d50838;
+    cpu->id_pfr0 = 0x10010131;
+    cpu->id_pfr1 = 0x10010000;
+    cpu->id_pfr2 = 0x00000011;
+    cpu->id_dfr0 = 0x04010088;
+    cpu->id_afr0 = 0x00000000;
+    cpu->id_mmfr0 = 0x10201105;
+    cpu->id_mmfr1 = 0x40000000;
+    cpu->id_mmfr2 = 0x01260000;
+    cpu->id_mmfr3 = 0x02122211;
+    cpu->isar.id_isar0 = 0x02101110;
+    cpu->isar.id_isar1 = 0x13112111;
+    cpu->isar.id_isar2 = 0x21232042;
+    cpu->isar.id_isar3 = 0x01112131;
+    cpu->isar.id_isar4 = 0x00011142;
+    cpu->isar.id_isar5 = 0x00011121;
+    cpu->isar.id_isar6 = 0x00000010;
+    cpu->isar.id_aa64pfr0 = 0x1100000010111112ull;
+    cpu->id_aa64dfr0 = 0x10305408;
+    cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+    cpu->isar.id_aa64isar1 = 0x00100001;
+    cpu->isar.id_aa64mmfr0 = 0x00101122;
+    cpu->isar.id_aa64mmfr1 = 0x10212122;
+    cpu->isar.id_aa64mmfr2 = 0x00001011;
+    cpu->clidr = 0x08200023;
+    cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+    cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+    cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+    cpu->dcz_blocksize = 4; /* 64 bytes */
+    cpu->gic_num_lrs = 4;
+    cpu->gic_vpribits = 5;
+    cpu->gic_vprebits = 5;
+    define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
+}
+
 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
                                void *opaque, Error **errp)
 {
@@ -491,6 +548,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
     { .name = "cortex-a73",         .initfn = aarch64_a73_initfn },
     { .name = "cortex-a75",         .initfn = aarch64_a75_initfn },
+    { .name = "cortex-a76",         .initfn = aarch64_a76_initfn },
     { .name = "max",                .initfn = aarch64_max_initfn },
     { .name = NULL }
 };
-- 
2.17.2

Re: [Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This was defined at some point before ARMv8.4, and will
> shortly be used by new processor descriptions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h    | 1 +
>  target/arm/helper.c | 4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This was defined at some point before ARMv8.4, and will
> shortly be used by new processor descriptions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h    | 1 +
>  target/arm/helper.c | 4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There are new field definitions, CSV2 and CSV3, that do not yet
> appear in the main ARM ARM.  Define the ID_AA64PF0 versions,

"ID_AA64PFR0"

> since we already define the rest of those bits.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> --

otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There are new field definitions, CSV2 and CSV3, that do not yet
> appear in the main ARM ARM.  Define the ID_AA64PF0 versions,

"ID_AA64PFR0"

> since we already define the rest of those bits.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> --

otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This was res0 before ARMv8.2, but will shortly be used by
> new processor definitions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h    | 15 +++++++++++++++
>  target/arm/helper.c |  4 ++--
>  target/arm/kvm64.c  |  2 ++
>  3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index c2899f0bed..02642a7db3 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -855,6 +855,7 @@ struct ARMCPU {
>          uint64_t id_aa64pfr1;
>          uint64_t id_aa64mmfr0;
>          uint64_t id_aa64mmfr1;
> +        uint64_t id_aa64mmfr2;
>      } isar;
>      uint32_t midr;
>      uint32_t revidr;
> @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
>  FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
>  FIELD(ID_AA64MMFR1, XNX, 28, 4)
>
> +FIELD(ID_AA64MMFR2, CNP, 0, 4)
> +FIELD(ID_AA64MMFR2, UAO, 4, 4)
> +FIELD(ID_AA64MMFR2, LSM, 8, 4)
> +FIELD(ID_AA64MMFR2, IESB, 12, 4)
> +FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
> +FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
> +FIELD(ID_AA64MMFR2, NV, 24, 4)
> +FIELD(ID_AA64MMFR2, ST, 28, 4)
> +FIELD(ID_AA64MMFR2, AT, 32, 4)
> +FIELD(ID_AA64MMFR2, IDS, 36, 4)
> +FIELD(ID_AA64MMFR2, FWB, 40, 4)
> +FIELD(ID_AA64MMFR2, TTL, 48, 4)
> +FIELD(ID_AA64MMFR2, BBM, 52, 4)

While we're here:
FIELD(ID_AA64MMFR2, EVT, 56, 4)
FIELD(ID_AA64MMFR2, E0PD, 60, 4)

(from arm v8.5, see
https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64mmfr2_el1
)

otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This was res0 before ARMv8.2, but will shortly be used by
> new processor definitions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.h    | 15 +++++++++++++++
>  target/arm/helper.c |  4 ++--
>  target/arm/kvm64.c  |  2 ++
>  3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index c2899f0bed..02642a7db3 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -855,6 +855,7 @@ struct ARMCPU {
>          uint64_t id_aa64pfr1;
>          uint64_t id_aa64mmfr0;
>          uint64_t id_aa64mmfr1;
> +        uint64_t id_aa64mmfr2;
>      } isar;
>      uint32_t midr;
>      uint32_t revidr;
> @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
>  FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
>  FIELD(ID_AA64MMFR1, XNX, 28, 4)
>
> +FIELD(ID_AA64MMFR2, CNP, 0, 4)
> +FIELD(ID_AA64MMFR2, UAO, 4, 4)
> +FIELD(ID_AA64MMFR2, LSM, 8, 4)
> +FIELD(ID_AA64MMFR2, IESB, 12, 4)
> +FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
> +FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
> +FIELD(ID_AA64MMFR2, NV, 24, 4)
> +FIELD(ID_AA64MMFR2, ST, 28, 4)
> +FIELD(ID_AA64MMFR2, AT, 32, 4)
> +FIELD(ID_AA64MMFR2, IDS, 36, 4)
> +FIELD(ID_AA64MMFR2, FWB, 40, 4)
> +FIELD(ID_AA64MMFR2, TTL, 48, 4)
> +FIELD(ID_AA64MMFR2, BBM, 52, 4)

While we're here:
FIELD(ID_AA64MMFR2, EVT, 56, 4)
FIELD(ID_AA64MMFR2, E0PD, 60, 4)

(from arm v8.5, see
https://developer.arm.com/docs/ddi0595/b/aarch64-system-registers/id_aa64mmfr2_el1
)

otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Only perform the assert when both registers exist.
> Extract the variables from ID_AA64DFR0_EL1 for AArch64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> +    if (have_aa32) {
> +        ARMCPRegInfo dbgdidr = {
> +            .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
> +            .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tda,
> +            .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
> +        };
> +        define_one_arm_cp_reg(cpu, &dbgdidr);
> +    }

So if only EL0 has AArch32 it doesn't architecturally require
that this AArch32 system register doesn't exist, because the
register is still readable from EL0. The Arm ARM says that
"implementation of this register is optional and deprecated".
I would suggest that we should probably go with "implement the
register if cpu->dbgdidr is non-zero", since at least bit 15
must be set so zero isn't a valid real value for it.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Only perform the assert when both registers exist.
> Extract the variables from ID_AA64DFR0_EL1 for AArch64.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> +    if (have_aa32) {
> +        ARMCPRegInfo dbgdidr = {
> +            .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0,
> +            .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tda,
> +            .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
> +        };
> +        define_one_arm_cp_reg(cpu, &dbgdidr);
> +    }

So if only EL0 has AArch32 it doesn't architecturally require
that this AArch32 system register doesn't exist, because the
register is still readable from EL0. The Arm ARM says that
"implementation of this register is optional and deprecated".
I would suggest that we should probably go with "implement the
register if cpu->dbgdidr is non-zero", since at least bit 15
must be set so zero isn't a valid real value for it.

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

Re: [Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  hw/arm/virt.c      |  1 +
>  target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index c69a734878..06a155724c 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -174,6 +174,7 @@ static const char *valid_cpus[] = {
>      ARM_CPU_TYPE_NAME("cortex-a57"),
>      ARM_CPU_TYPE_NAME("cortex-a72"),
>      ARM_CPU_TYPE_NAME("cortex-a73"),
> +    ARM_CPU_TYPE_NAME("cortex-a75"),
>      ARM_CPU_TYPE_NAME("host"),
>      ARM_CPU_TYPE_NAME("max"),
>  };
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index d34aa3af75..325e0ecf17 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj)
>      define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
>  }
>
> +static void aarch64_a75_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
>


> +    cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */

There are a couple of things interacting here.
Firstly, I think that architecturally the reset values
(and how much is actually a defined value rather than
UNKNOWN) can differ between SCTLR_EL1/2/3, plus the 32-bit
vs 64-bit have different values for a few bits, but we try
to just shoehorn everything into a single reset_sctlr field
(see https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg01559.html
and surrounding messages in that thread for discussion).

Secondly, for the cortex-a75,
https://developer.arm.com/docs/100403/latest/part-b-register-descriptions/aarch64-system-registers/sctlr_el3-system-control-register-el3

does specify the reset value for SCTLR_EL3:
bit 25 is controlled by an external signal (aka a
QOM property for us), bits 12 2 and 0 are specified
to reset to 0, and every other bit resets to an
UNKNOWN value. I would suggest that we make the
RES0 bits 0, the RES1 bits 1, and use 0 for all the
other UNKNOWN bits.

SCTLR_EL1 is similar (if resetting into EL1)
https://developer.arm.com/docs/100403/latest/part-b-register-descriptions/aarch64-system-registers/sctlr_el1-system-control-register-el1
with the slight wrinkle that you need to also check
the architectural spec for some bits, eg bit 0 has
no reset value listed in the TRM but architecturally
is required to reset to 0 if resetting into EL1.

thanks
-- PMM

Re: [Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  hw/arm/virt.c      |  1 +
>  target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 59 insertions(+)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index c69a734878..06a155724c 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -174,6 +174,7 @@ static const char *valid_cpus[] = {
>      ARM_CPU_TYPE_NAME("cortex-a57"),
>      ARM_CPU_TYPE_NAME("cortex-a72"),
>      ARM_CPU_TYPE_NAME("cortex-a73"),
> +    ARM_CPU_TYPE_NAME("cortex-a75"),
>      ARM_CPU_TYPE_NAME("host"),
>      ARM_CPU_TYPE_NAME("max"),
>  };
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index d34aa3af75..325e0ecf17 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj)
>      define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo);
>  }
>
> +static void aarch64_a75_initfn(Object *obj)
> +{
> +    ARMCPU *cpu = ARM_CPU(obj);
>


> +    cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */

There are a couple of things interacting here.
Firstly, I think that architecturally the reset values
(and how much is actually a defined value rather than
UNKNOWN) can differ between SCTLR_EL1/2/3, plus the 32-bit
vs 64-bit have different values for a few bits, but we try
to just shoehorn everything into a single reset_sctlr field
(see https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg01559.html
and surrounding messages in that thread for discussion).

Secondly, for the cortex-a75,
https://developer.arm.com/docs/100403/latest/part-b-register-descriptions/aarch64-system-registers/sctlr_el3-system-control-register-el3

does specify the reset value for SCTLR_EL3:
bit 25 is controlled by an external signal (aka a
QOM property for us), bits 12 2 and 0 are specified
to reset to 0, and every other bit resets to an
UNKNOWN value. I would suggest that we make the
RES0 bits 0, the RES1 bits 1, and use 0 for all the
other UNKNOWN bits.

SCTLR_EL1 is similar (if resetting into EL1)
https://developer.arm.com/docs/100403/latest/part-b-register-descriptions/aarch64-system-registers/sctlr_el1-system-control-register-el1
with the slight wrinkle that you need to also check
the architectural spec for some bits, eg bit 0 has
no reset value listed in the TRM but architecturally
is required to reset to 0 if resetting into EL1.

thanks
-- PMM

Re: [Qemu-devel] [PATCH+RFC 0/6] target/arm: Define cortex-a{73, 75, 76}

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There have been several announcements since the a72.
>
> The a75 and a76 entries are RFC because, while they boot with a 3.15
> kernel, they do not boot with a 5.0-rc7 kernel.  I'm really not sure
> where things have gone off the rails.  It'll take some more serious
> tracing to figure out what went wrong.
>
> I post this now mostly to get feedback on patch 5.  Should we do
> more to elide *all* of the aa32 system registers for that case?

We should make sure we don't expose non-existent sysregs to
EL0, but it's harmless to define aa32 PL1_RW sysregs in
an AArch64-only-for-EL1-and-up CPU -- the guest is just never
able to access them. (This is the inverse of the way we define
a lot of AArch64 sysregs for AArch32 CPUs).

The thing to watch out for here is that where we have AArch32 and
AArch64 aliases of each other, we tend to define one as the
"real thing" and the other as the alias, which matters for
migration. If we've used the AArch32 version as the "real thing"
then we can't just skip the definition or we'll drop the register
state from the migration stream entirely.

thanks
-- PMM

Re: [Qemu-devel] [PATCH+RFC 0/6] target/arm: Define cortex-a{73, 75, 76}

[Peter Maydell]

On Sat, 23 Feb 2019 at 02:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There have been several announcements since the a72.
>
> The a75 and a76 entries are RFC because, while they boot with a 3.15
> kernel, they do not boot with a 5.0-rc7 kernel.  I'm really not sure
> where things have gone off the rails.  It'll take some more serious
> tracing to figure out what went wrong.
>
> I post this now mostly to get feedback on patch 5.  Should we do
> more to elide *all* of the aa32 system registers for that case?

We should make sure we don't expose non-existent sysregs to
EL0, but it's harmless to define aa32 PL1_RW sysregs in
an AArch64-only-for-EL1-and-up CPU -- the guest is just never
able to access them. (This is the inverse of the way we define
a lot of AArch64 sysregs for AArch32 CPUs).

The thing to watch out for here is that where we have AArch32 and
AArch64 aliases of each other, we tend to define one as the
"real thing" and the other as the alias, which matters for
migration. If we've used the AArch32 version as the "real thing"
then we can't just skip the definition or we'll drop the register
state from the migration stream entirely.

thanks
-- PMM