* [PATCH v3 00/27] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Hi,
This series is inspired on Claudio TCG work.
Instead of separate TCG from other accelerators, here we
separate sysemu operations (system VS user).
Patches 1-6 are generic cleanups.
Patches 7-15 move from CPUClass to SysemuCPUOps
Patch 16 restricts SysemuCPUOps to sysemu
Patches 17-25 remove watchpoint code from user emulation
Patches 26-27 remove USER_ONLY #ifdef'ry from "cpu.h"
Since v2:
- fixed lm32/unicore32
- remove USER_ONLY ifdef'ry from "cpu.h" (Claudio)
Since v1:
- Name 'sysemu' (Claudio)
- change each field progressively (Richard)
$ git backport-diff -u v2
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respective=
ly
001/27:[----] [--] 'target: Set CPUClass::vmsd instead of DeviceClass::vmsd'
002/27:[----] [--] 'cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from=
_attrs'
003/27:[----] [--] 'cpu: Introduce cpu_virtio_is_big_endian()'
004/27:[----] [--] 'cpu: Directly use cpu_write_elf*() fallback handlers in p=
lace'
005/27:[----] [--] 'cpu: Directly use get_paging_enabled() fallback handlers =
in place'
006/27:[----] [--] 'cpu: Directly use get_memory_mapping() fallback handlers =
in place'
007/27:[----] [--] 'cpu: Introduce SysemuCPUOps structure'
008/27:[----] [--] 'cpu: Move CPUClass::vmsd to SysemuCPUOps'
009/27:[----] [--] 'cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps'
010/27:[----] [--] 'cpu: Move CPUClass::get_crash_info to SysemuCPUOps'
011/27:[----] [--] 'cpu: Move CPUClass::write_elf* to SysemuCPUOps'
012/27:[----] [--] 'cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps'
013/27:[----] [--] 'cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps'
014/27:[----] [--] 'cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps'
015/27:[----] [--] 'cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps'
016/27:[0084] [FC] 'cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c'
017/27:[down] 'linux-user: Remove dead code'
018/27:[down] 'gdbstub: Remove watchpoint dead code in gdbserver_fork()'
019/27:[down] 'target/arm/internals: Fix code style for checkpatch.pl'
020/27:[down] 'target/arm: Move code blocks around'
021/27:[down] 'target/arm: Refactor some function bodies'
022/27:[down] 'target/arm: Restrict watchpoint code to system emulation'
023/27:[down] 'target/i386: Restrict watchpoint code to system emulation'
024/27:[down] 'accel/tcg/cpu-exec: Restrict watchpoint code to system emulati=
on'
025/27:[down] 'cpu: Remove watchpoint stubs for user emulation'
026/27:[down] 'cpu: Fix code style for checkpatch.pl'
027/27:[down] 'cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h''
Regards,
Phil.
Supersedes: <20210301215110.772346-1-f4bug@amsat.org>
Philippe Mathieu-Daud=C3=A9 (27):
target: Set CPUClass::vmsd instead of DeviceClass::vmsd
cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
cpu: Introduce cpu_virtio_is_big_endian()
cpu: Directly use cpu_write_elf*() fallback handlers in place
cpu: Directly use get_paging_enabled() fallback handlers in place
cpu: Directly use get_memory_mapping() fallback handlers in place
cpu: Introduce SysemuCPUOps structure
cpu: Move CPUClass::vmsd to SysemuCPUOps
cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
cpu: Move CPUClass::get_crash_info to SysemuCPUOps
cpu: Move CPUClass::write_elf* to SysemuCPUOps
cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
linux-user: Remove dead code
gdbstub: Remove watchpoint dead code in gdbserver_fork()
target/arm/internals: Fix code style for checkpatch.pl
target/arm: Move code blocks around
target/arm: Refactor some function bodies
target/arm: Restrict watchpoint code to system emulation
target/i386: Restrict watchpoint code to system emulation
accel/tcg/cpu-exec: Restrict watchpoint code to system emulation
cpu: Remove watchpoint stubs for user emulation
cpu: Fix code style for checkpatch.pl
cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h'
include/hw/core/cpu.h | 258 +------------------------------
include/hw/core/sysemu-cpu-ops.h | 244 +++++++++++++++++++++++++++++
target/alpha/cpu.h | 3 +
target/arm/cpu.h | 3 +
target/arm/internals.h | 34 ++--
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +
target/hexagon/cpu.h | 3 +
target/hppa/cpu.h | 3 +
target/i386/cpu.h | 3 +
target/lm32/cpu.h | 3 +
target/m68k/cpu.h | 3 +
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +
target/moxie/cpu.h | 3 +
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +
target/ppc/cpu.h | 3 +
target/riscv/cpu.h | 3 +
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +
target/sh4/cpu.h | 3 +
target/sparc/cpu.h | 3 +
target/tilegx/cpu.h | 3 +
target/tricore/cpu.h | 3 +
target/unicore32/cpu.h | 3 +
target/xtensa/cpu.h | 3 +
accel/tcg/cpu-exec.c | 5 +-
cpu.c | 19 ++-
gdbstub.c | 2 +-
hw/core/cpu.c | 113 ++++++++------
hw/virtio/virtio.c | 4 +-
linux-user/main.c | 5 -
softmmu/physmem.c | 1 +
target/alpha/cpu.c | 10 +-
target/arm/cpu.c | 22 ++-
target/arm/debug_helper.c | 102 ++++++------
target/arm/helper.c | 9 +-
target/avr/cpu.c | 8 +-
target/cris/cpu.c | 10 +-
target/hppa/cpu.c | 10 +-
target/i386/cpu.c | 31 ++--
target/lm32/cpu.c | 10 +-
target/m68k/cpu.c | 10 +-
target/microblaze/cpu.c | 10 +-
target/mips/cpu.c | 10 +-
target/moxie/cpu.c | 10 +-
target/nios2/cpu.c | 15 +-
target/openrisc/cpu.c | 10 +-
target/riscv/cpu.c | 12 +-
target/rx/cpu.c | 16 +-
target/s390x/cpu.c | 14 +-
target/sh4/cpu.c | 10 +-
target/sparc/cpu.c | 10 +-
target/tricore/cpu.c | 13 +-
target/unicore32/cpu.c | 8 +-
target/xtensa/cpu.c | 10 +-
target/ppc/translate_init.c.inc | 20 +--
58 files changed, 686 insertions(+), 453 deletions(-)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
--=20
2.26.2
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
The cpu model is the single device available in user-mode.
Since we want to restrict some fields to user-mode emulation,
we prefer to set the vmsd field of CPUClass, rather than the
DeviceClass one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/alpha/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e22..faabffe0796 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_alpha_cpu;
+ cc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fca..29a865b75d2 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_cris_cpu;
+ cc->vmsd = &vmstate_cris_cpu;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1fe..4f142de6e45 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_hppa_cpu;
+ cc->vmsd = &vmstate_hppa_cpu;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 37d2ed9dc79..c98fb1e33be 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_m68k_cpu;
+ cc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba202037..335dfdc734e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- dc->vmsd = &vmstate_mb_cpu;
+ cc->vmsd = &vmstate_mb_cpu;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46b..79d246d1930 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_openrisc_cpu;
+ cc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f8..bd44de53729 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- dc->vmsd = &vmstate_sh_cpu;
+ cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f845..12894ffac6a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_uc32_cpu;
+ cc->vmsd = &vmstate_uc32_cpu;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c1..6bedd5b97b8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
+ cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
The cpu model is the single device available in user-mode.
Since we want to restrict some fields to user-mode emulation,
we prefer to set the vmsd field of CPUClass, rather than the
DeviceClass one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/alpha/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 27192b62e22..faabffe0796 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -237,7 +237,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_alpha_cpu;
+ cc->vmsd = &vmstate_alpha_cpu;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index ed983380fca..29a865b75d2 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -293,7 +293,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_cris_cpu;
+ cc->vmsd = &vmstate_cris_cpu;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index d8fad52d1fe..4f142de6e45 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -162,7 +162,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_hppa_cpu;
+ cc->vmsd = &vmstate_hppa_cpu;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 37d2ed9dc79..c98fb1e33be 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -533,7 +533,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_m68k_cpu;
+ cc->vmsd = &vmstate_m68k_cpu;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 433ba202037..335dfdc734e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -387,7 +387,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- dc->vmsd = &vmstate_mb_cpu;
+ cc->vmsd = &vmstate_mb_cpu;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 2c64842f46b..79d246d1930 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -204,7 +204,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_openrisc_cpu;
+ cc->vmsd = &vmstate_openrisc_cpu;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ac65c88f1f8..bd44de53729 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -262,7 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- dc->vmsd = &vmstate_sh_cpu;
+ cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 0258884f845..12894ffac6a 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -146,7 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- dc->vmsd = &vmstate_uc32_cpu;
+ cc->vmsd = &vmstate_uc32_cpu;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index e2b2c7a71c1..6bedd5b97b8 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -218,7 +218,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- dc->vmsd = &vmstate_xtensa_cpu;
+ cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-04-21 22:03 ` Eduardo Habkost
-1 siblings, 0 replies; 56+ messages in thread
From: Eduardo Habkost @ 2021-04-21 22:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Sarah Harris, Cornelia Huck, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland, qemu-devel,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, qemu-ppc,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, qemu-riscv, Bastian Koppelmann,
Chris Wulff, Laurent Vivier, Michael Walle, Palmer Dabbelt,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno
On Tue, Mar 02, 2021 at 03:57:52PM +0100, Philippe Mathieu-Daudé wrote:
> The cpu model is the single device available in user-mode.
> Since we want to restrict some fields to user-mode emulation,
> we prefer to set the vmsd field of CPUClass, rather than the
> DeviceClass one.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Is this going to have an externally visible effect?
If it does, how can we make sure it's safe?
If it does not, do you know why CPUClass::vmsd exists in the
first place?
Do you think it would be simpler to just squash this patch into
[PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
?
--
Eduardo
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-21 22:03 ` Eduardo Habkost
0 siblings, 0 replies; 56+ messages in thread
From: Eduardo Habkost @ 2021-04-21 22:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel, Peter Maydell, Sarah Harris, Chris Wulff,
Sagar Karandikar, David Hildenbrand, Anthony Green,
Mark Cave-Ayland, Aleksandar Rikalo, Max Filippov,
Taylor Simpson, Alistair Francis, Edgar E. Iglesias, Guan Xuetao,
Marek Vasut, Yoshinori Sato, Michael S. Tsirkin, Claudio Fontana,
Palmer Dabbelt, Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, qemu-riscv, Bastian Koppelmann,
Cornelia Huck, Laurent Vivier, Michael Walle, qemu-ppc,
Paolo Bonzini, Aurelien Jarno
On Tue, Mar 02, 2021 at 03:57:52PM +0100, Philippe Mathieu-Daudé wrote:
> The cpu model is the single device available in user-mode.
> Since we want to restrict some fields to user-mode emulation,
> we prefer to set the vmsd field of CPUClass, rather than the
> DeviceClass one.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Is this going to have an externally visible effect?
If it does, how can we make sure it's safe?
If it does not, do you know why CPUClass::vmsd exists in the
first place?
Do you think it would be simpler to just squash this patch into
[PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
?
--
Eduardo
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-04-21 22:03 ` Eduardo Habkost
@ 2021-04-22 9:55 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 9:55 UTC (permalink / raw)
To: Eduardo Habkost, Juan Quintela
Cc: Peter Maydell, Sarah Harris, Cornelia Huck, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland, qemu-devel,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, qemu-ppc,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, qemu-riscv, Bastian Koppelmann,
Chris Wulff, Laurent Vivier, Michael Walle, Palmer Dabbelt,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno
+Juan
On 4/22/21 12:03 AM, Eduardo Habkost wrote:
> On Tue, Mar 02, 2021 at 03:57:52PM +0100, Philippe Mathieu-Daudé wrote:
>> The cpu model is the single device available in user-mode.
>> Since we want to restrict some fields to user-mode emulation,
>> we prefer to set the vmsd field of CPUClass, rather than the
>> DeviceClass one.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Is this going to have an externally visible effect?
On system emulation, no, because unchanged.
On user emulation migration it is not used, the symbol is here
to satisfy linking:
include/hw/core/cpu.h-1070-#ifdef CONFIG_SOFTMMU
include/hw/core/cpu.h-1071-extern const VMStateDescription
vmstate_cpu_common;
include/hw/core/cpu.h-1072-#else
include/hw/core/cpu.h:1073:#define vmstate_cpu_common vmstate_dummy
include/hw/core/cpu.h-1074-#endif
include/migration/vmstate.h:197:extern const VMStateDescription
vmstate_dummy;
stubs/vmstate.c:4:const VMStateDescription vmstate_dummy = {};
> If it does, how can we make sure it's safe?
>
> If it does not, do you know why CPUClass::vmsd exists in the
> first place?
My guess is CPUState is the only device used in user emulation,
so it would be a way to restrict the vmstate_dummy to CPU and
not to any DeviceState?
But looking at the introductory commit:
commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
Author: Andreas Färber <afaerber@suse.de>
Date: Sun Jan 20 20:23:22 2013 +0100
cpu: Register VMStateDescription through CPUState
In comparison to DeviceClass::vmsd, CPU VMState is split in two,
"cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
Therefore add a CPU-specific CPUClass::vmsd field.
Unlike the legacy CPUArchState registration, rather register CPUState.
Juan, do you remember?
>
> Do you think it would be simpler to just squash this patch into
> [PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
> ?
Certainly cleaner, I'll respin!
Thanks,
Phil.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-22 9:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 9:55 UTC (permalink / raw)
To: Eduardo Habkost, Juan Quintela
Cc: qemu-devel, Peter Maydell, Sarah Harris, Chris Wulff,
Sagar Karandikar, David Hildenbrand, Anthony Green,
Mark Cave-Ayland, Aleksandar Rikalo, Max Filippov,
Taylor Simpson, Alistair Francis, Edgar E. Iglesias, Guan Xuetao,
Marek Vasut, Yoshinori Sato, Michael S. Tsirkin, Claudio Fontana,
Palmer Dabbelt, Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, qemu-riscv, Bastian Koppelmann,
Cornelia Huck, Laurent Vivier, Michael Walle, qemu-ppc,
Paolo Bonzini, Aurelien Jarno
+Juan
On 4/22/21 12:03 AM, Eduardo Habkost wrote:
> On Tue, Mar 02, 2021 at 03:57:52PM +0100, Philippe Mathieu-Daudé wrote:
>> The cpu model is the single device available in user-mode.
>> Since we want to restrict some fields to user-mode emulation,
>> we prefer to set the vmsd field of CPUClass, rather than the
>> DeviceClass one.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Is this going to have an externally visible effect?
On system emulation, no, because unchanged.
On user emulation migration it is not used, the symbol is here
to satisfy linking:
include/hw/core/cpu.h-1070-#ifdef CONFIG_SOFTMMU
include/hw/core/cpu.h-1071-extern const VMStateDescription
vmstate_cpu_common;
include/hw/core/cpu.h-1072-#else
include/hw/core/cpu.h:1073:#define vmstate_cpu_common vmstate_dummy
include/hw/core/cpu.h-1074-#endif
include/migration/vmstate.h:197:extern const VMStateDescription
vmstate_dummy;
stubs/vmstate.c:4:const VMStateDescription vmstate_dummy = {};
> If it does, how can we make sure it's safe?
>
> If it does not, do you know why CPUClass::vmsd exists in the
> first place?
My guess is CPUState is the only device used in user emulation,
so it would be a way to restrict the vmstate_dummy to CPU and
not to any DeviceState?
But looking at the introductory commit:
commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
Author: Andreas Färber <afaerber@suse.de>
Date: Sun Jan 20 20:23:22 2013 +0100
cpu: Register VMStateDescription through CPUState
In comparison to DeviceClass::vmsd, CPU VMState is split in two,
"cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
Therefore add a CPU-specific CPUClass::vmsd field.
Unlike the legacy CPUArchState registration, rather register CPUState.
Juan, do you remember?
>
> Do you think it would be simpler to just squash this patch into
> [PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
> ?
Certainly cleaner, I'll respin!
Thanks,
Phil.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-04-22 9:55 ` Philippe Mathieu-Daudé
@ 2021-04-22 10:28 ` Peter Maydell
-1 siblings, 0 replies; 56+ messages in thread
From: Peter Maydell @ 2021-04-22 10:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Sarah Harris, Cornelia Huck, Sagar Karandikar,
Michael S. Tsirkin, Anthony Green, Mark Cave-Ayland,
QEMU Developers, Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Juan Quintela, David Hildenbrand, Claudio Fontana, Thomas Huth,
qemu-ppc, Philippe Mathieu-Daudé,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
open list:RISC-V, Bastian Koppelmann, Chris Wulff,
Laurent Vivier, Michael Walle, Palmer Dabbelt, Paolo Bonzini,
Aurelien Jarno
On Thu, 22 Apr 2021 at 10:55, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> My guess is CPUState is the only device used in user emulation,
> so it would be a way to restrict the vmstate_dummy to CPU and
> not to any DeviceState?
>
> But looking at the introductory commit:
>
> commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
> Author: Andreas Färber <afaerber@suse.de>
> Date: Sun Jan 20 20:23:22 2013 +0100
>
> cpu: Register VMStateDescription through CPUState
>
> In comparison to DeviceClass::vmsd, CPU VMState is split in two,
> "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
> Therefore add a CPU-specific CPUClass::vmsd field.
>
> Unlike the legacy CPUArchState registration, rather register CPUState.
>
> Juan, do you remember?
Oh yes, I remember this. There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common
directly to handle the cpu-common fields, and the cc->vmsd to handle
the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
thanks
-- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-22 10:28 ` Peter Maydell
0 siblings, 0 replies; 56+ messages in thread
From: Peter Maydell @ 2021-04-22 10:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Eduardo Habkost, Juan Quintela, QEMU Developers, Sarah Harris,
Chris Wulff, Sagar Karandikar, David Hildenbrand, Anthony Green,
Mark Cave-Ayland, Aleksandar Rikalo, Max Filippov,
Taylor Simpson, Alistair Francis, Edgar E. Iglesias, Guan Xuetao,
Marek Vasut, Yoshinori Sato, Michael S. Tsirkin, Claudio Fontana,
Palmer Dabbelt, Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Richard Henderson, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, open list:RISC-V,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
On Thu, 22 Apr 2021 at 10:55, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> My guess is CPUState is the only device used in user emulation,
> so it would be a way to restrict the vmstate_dummy to CPU and
> not to any DeviceState?
>
> But looking at the introductory commit:
>
> commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
> Author: Andreas Färber <afaerber@suse.de>
> Date: Sun Jan 20 20:23:22 2013 +0100
>
> cpu: Register VMStateDescription through CPUState
>
> In comparison to DeviceClass::vmsd, CPU VMState is split in two,
> "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
> Therefore add a CPU-specific CPUClass::vmsd field.
>
> Unlike the legacy CPUArchState registration, rather register CPUState.
>
> Juan, do you remember?
Oh yes, I remember this. There are two ways to handle migration for
a CPU object:
(1) like any other device, so it has a dc->vmsd that covers
migration for the whole object. As usual for objects that are a
subclass of a parent that has state, the first entry in the
VMStateDescription field list is VMSTATE_CPU(), which migrates
the cpu_common fields, followed by whatever the CPU's own migration
fields are.
(2) a backwards-compatible mechanism for CPUs that were
originally migrated using manual "write fields to the migration
stream structures". The on-the-wire migration format
for those is based on the 'env' pointer (which isn't a QOM object),
and the cpu_common part of the migration data is elsewhere.
cpu_exec_realizefn() handles both possibilities:
* for type 1, dc->vmsd is set and cc->vmsd is not,
so cpu_exec_realizefn() does nothing, and the standard
"register dc->vmsd for a device" code does everything needed
* for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common
directly to handle the cpu-common fields, and the cc->vmsd to handle
the per-CPU stuff
You can't change a CPU from one type to the other without breaking
migration compatibility, which is why some guest architectures
are stuck on the cc->vmsd form. New targets should use dc->vmsd.
thanks
-- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-04-22 10:28 ` Peter Maydell
@ 2021-04-22 11:01 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 11:01 UTC (permalink / raw)
To: Peter Maydell
Cc: Sarah Harris, Chris Wulff, Sagar Karandikar, Michael S. Tsirkin,
Anthony Green, Mark Cave-Ayland, QEMU Developers, Max Filippov,
Taylor Simpson, Alistair Francis, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Juan Quintela, David Hildenbrand,
Claudio Fontana, Thomas Huth, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, David Gibson, open list:RISC-V,
Bastian Koppelmann, Cornelia Huck, Laurent Vivier, Michael Walle,
qemu-ppc, Paolo Bonzini, Aurelien Jarno
On 4/22/21 12:28 PM, Peter Maydell wrote:
> On Thu, 22 Apr 2021 at 10:55, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> My guess is CPUState is the only device used in user emulation,
>> so it would be a way to restrict the vmstate_dummy to CPU and
>> not to any DeviceState?
>>
>> But looking at the introductory commit:
>>
>> commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
>> Author: Andreas Färber <afaerber@suse.de>
>> Date: Sun Jan 20 20:23:22 2013 +0100
>>
>> cpu: Register VMStateDescription through CPUState
>>
>> In comparison to DeviceClass::vmsd, CPU VMState is split in two,
>> "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
>> Therefore add a CPU-specific CPUClass::vmsd field.
>>
>> Unlike the legacy CPUArchState registration, rather register CPUState.
>>
>> Juan, do you remember?
>
> Oh yes, I remember this. There are two ways to handle migration for
> a CPU object:
>
> (1) like any other device, so it has a dc->vmsd that covers
> migration for the whole object. As usual for objects that are a
> subclass of a parent that has state, the first entry in the
> VMStateDescription field list is VMSTATE_CPU(), which migrates
> the cpu_common fields, followed by whatever the CPU's own migration
> fields are.
> (2) a backwards-compatible mechanism for CPUs that were
> originally migrated using manual "write fields to the migration
> stream structures". The on-the-wire migration format
> for those is based on the 'env' pointer (which isn't a QOM object),
> and the cpu_common part of the migration data is elsewhere.
>
> cpu_exec_realizefn() handles both possibilities:
> * for type 1, dc->vmsd is set and cc->vmsd is not,
> so cpu_exec_realizefn() does nothing, and the standard
> "register dc->vmsd for a device" code does everything needed
> * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common
> directly to handle the cpu-common fields, and the cc->vmsd to handle
> the per-CPU stuff
>
> You can't change a CPU from one type to the other without breaking
> migration compatibility, which is why some guest architectures
> are stuck on the cc->vmsd form. New targets should use dc->vmsd.
Doh I just post v5. I guess I'll have to revisit patch #7, because
I likely blew type 2 migration:
https://patchew.org/QEMU/20210422104705.2454166-1-f4bug@amsat.org/20210422104705.2454166-8-f4bug@amsat.org/
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-22 11:01 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 11:01 UTC (permalink / raw)
To: Peter Maydell
Cc: Sarah Harris, Cornelia Huck, Sagar Karandikar,
Michael S. Tsirkin, Anthony Green, Mark Cave-Ayland,
QEMU Developers, Max Filippov, Taylor Simpson, Alistair Francis,
Guan Xuetao, Marek Vasut, Yoshinori Sato, Juan Quintela,
David Hildenbrand, Claudio Fontana, Thomas Huth, qemu-ppc,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, David Gibson, open list:RISC-V,
Bastian Koppelmann, Chris Wulff, Laurent Vivier, Michael Walle,
Palmer Dabbelt, Paolo Bonzini, Aurelien Jarno
On 4/22/21 12:28 PM, Peter Maydell wrote:
> On Thu, 22 Apr 2021 at 10:55, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> My guess is CPUState is the only device used in user emulation,
>> so it would be a way to restrict the vmstate_dummy to CPU and
>> not to any DeviceState?
>>
>> But looking at the introductory commit:
>>
>> commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
>> Author: Andreas Färber <afaerber@suse.de>
>> Date: Sun Jan 20 20:23:22 2013 +0100
>>
>> cpu: Register VMStateDescription through CPUState
>>
>> In comparison to DeviceClass::vmsd, CPU VMState is split in two,
>> "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
>> Therefore add a CPU-specific CPUClass::vmsd field.
>>
>> Unlike the legacy CPUArchState registration, rather register CPUState.
>>
>> Juan, do you remember?
>
> Oh yes, I remember this. There are two ways to handle migration for
> a CPU object:
>
> (1) like any other device, so it has a dc->vmsd that covers
> migration for the whole object. As usual for objects that are a
> subclass of a parent that has state, the first entry in the
> VMStateDescription field list is VMSTATE_CPU(), which migrates
> the cpu_common fields, followed by whatever the CPU's own migration
> fields are.
> (2) a backwards-compatible mechanism for CPUs that were
> originally migrated using manual "write fields to the migration
> stream structures". The on-the-wire migration format
> for those is based on the 'env' pointer (which isn't a QOM object),
> and the cpu_common part of the migration data is elsewhere.
>
> cpu_exec_realizefn() handles both possibilities:
> * for type 1, dc->vmsd is set and cc->vmsd is not,
> so cpu_exec_realizefn() does nothing, and the standard
> "register dc->vmsd for a device" code does everything needed
> * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common
> directly to handle the cpu-common fields, and the cc->vmsd to handle
> the per-CPU stuff
>
> You can't change a CPU from one type to the other without breaking
> migration compatibility, which is why some guest architectures
> are stuck on the cc->vmsd form. New targets should use dc->vmsd.
Doh I just post v5. I guess I'll have to revisit patch #7, because
I likely blew type 2 migration:
https://patchew.org/QEMU/20210422104705.2454166-1-f4bug@amsat.org/20210422104705.2454166-8-f4bug@amsat.org/
^ permalink raw reply [flat|nested] 56+ messages in thread
* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-04-22 11:01 ` Philippe Mathieu-Daudé
@ 2021-04-22 15:41 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 15:41 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Peter Maydell, Markus Armbruster, Eduardo Habkost,
Dr. David Alan Gilbert
Cc: Sarah Harris, Chris Wulff, Sagar Karandikar, Michael S. Tsirkin,
Anthony Green, Mark Cave-Ayland, QEMU Developers, Max Filippov,
Taylor Simpson, Alistair Francis, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Juan Quintela, David Hildenbrand,
Claudio Fontana, Palmer Dabbelt, Artyom Tarasenko, Thomas Huth,
Eduardo Habkost, Richard Henderson, Greg Kurz, qemu-s390x,
qemu-arm, Michael Rolnik, Stafford Horne, David Gibson,
open list:RISC-V, Bastian Koppelmann, Cornelia Huck,
Laurent Vivier, Michael Walle, qemu-ppc, Paolo Bonzini,
Aleksandar Rikalo, Aurelien Jarno
On 4/22/21 1:01 PM, Philippe Mathieu-Daudé wrote:
> On 4/22/21 12:28 PM, Peter Maydell wrote:
>> On Thu, 22 Apr 2021 at 10:55, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>> My guess is CPUState is the only device used in user emulation,
>>> so it would be a way to restrict the vmstate_dummy to CPU and
>>> not to any DeviceState?
>>>
>>> But looking at the introductory commit:
>>>
>>> commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
>>> Author: Andreas Färber <afaerber@suse.de>
>>> Date: Sun Jan 20 20:23:22 2013 +0100
>>>
>>> cpu: Register VMStateDescription through CPUState
>>>
>>> In comparison to DeviceClass::vmsd, CPU VMState is split in two,
>>> "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
>>> Therefore add a CPU-specific CPUClass::vmsd field.
>>>
>>> Unlike the legacy CPUArchState registration, rather register CPUState.
>>>
>>> Juan, do you remember?
>>
>> Oh yes, I remember this. There are two ways to handle migration for
>> a CPU object:
>>
>> (1) like any other device, so it has a dc->vmsd that covers
>> migration for the whole object. As usual for objects that are a
>> subclass of a parent that has state, the first entry in the
>> VMStateDescription field list is VMSTATE_CPU(), which migrates
>> the cpu_common fields, followed by whatever the CPU's own migration
>> fields are.
target/alpha/cpu.c:240: dc->vmsd = &vmstate_alpha_cpu;
target/cris/cpu.c:296: dc->vmsd = &vmstate_cris_cpu;
target/hppa/cpu.c:165: dc->vmsd = &vmstate_hppa_cpu;
target/m68k/cpu.c:537: dc->vmsd = &vmstate_m68k_cpu;
target/microblaze/cpu.c:390: dc->vmsd = &vmstate_mb_cpu;
target/openrisc/cpu.c:207: dc->vmsd = &vmstate_openrisc_cpu;
target/sh4/cpu.c:265: dc->vmsd = &vmstate_sh_cpu;
target/unicore32/cpu.c:149: dc->vmsd = &vmstate_uc32_cpu;
target/xtensa/cpu.c:221: dc->vmsd = &vmstate_xtensa_cpu;
>> (2) a backwards-compatible mechanism for CPUs that were
>> originally migrated using manual "write fields to the migration
>> stream structures". The on-the-wire migration format
>> for those is based on the 'env' pointer (which isn't a QOM object),
>> and the cpu_common part of the migration data is elsewhere.
target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
>> cpu_exec_realizefn() handles both possibilities:
>> * for type 1, dc->vmsd is set and cc->vmsd is not,
>> so cpu_exec_realizefn() does nothing, and the standard
>> "register dc->vmsd for a device" code does everything needed
>> * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common
>> directly to handle the cpu-common fields, and the cc->vmsd to handle
>> the per-CPU stuff
>>
>> You can't change a CPU from one type to the other without breaking
>> migration compatibility, which is why some guest architectures
>> are stuck on the cc->vmsd form. New targets should use dc->vmsd.
IOW new targets should use type 1.
Looking at type 2:
a) targets added 'recently' with the incorrect type 2:
target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
b) targets where migration isn't really an issue:
target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
c) targets where migration could be broken:
target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
d) KVM targets ("security boundary" or Tier-1) are left:
target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
Isn't "machine type" what allows us to change migration stream?
All targets in d) do support that.
How could we enforce no new type 2 targets?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-22 15:41 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 15:41 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Peter Maydell, Markus Armbruster, Eduardo Habkost,
Dr. David Alan Gilbert
Cc: Sarah Harris, Cornelia Huck, Sagar Karandikar,
Michael S. Tsirkin, Anthony Green, Mark Cave-Ayland,
QEMU Developers, Max Filippov, Taylor Simpson, Alistair Francis,
Guan Xuetao, Marek Vasut, Yoshinori Sato, Juan Quintela,
David Hildenbrand, Claudio Fontana, Thomas Huth, qemu-ppc,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, David Gibson, open list:RISC-V,
Bastian Koppelmann, Chris Wulff, Laurent Vivier, Michael Walle,
Palmer Dabbelt, Paolo Bonzini, Aurelien Jarno
On 4/22/21 1:01 PM, Philippe Mathieu-Daudé wrote:
> On 4/22/21 12:28 PM, Peter Maydell wrote:
>> On Thu, 22 Apr 2021 at 10:55, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>> My guess is CPUState is the only device used in user emulation,
>>> so it would be a way to restrict the vmstate_dummy to CPU and
>>> not to any DeviceState?
>>>
>>> But looking at the introductory commit:
>>>
>>> commit b170fce3dd06372f7bfec9a780ebcb1fce6d57e4
>>> Author: Andreas Färber <afaerber@suse.de>
>>> Date: Sun Jan 20 20:23:22 2013 +0100
>>>
>>> cpu: Register VMStateDescription through CPUState
>>>
>>> In comparison to DeviceClass::vmsd, CPU VMState is split in two,
>>> "cpu_common" and "cpu", and uses cpu_index as instance_id instead of -1.
>>> Therefore add a CPU-specific CPUClass::vmsd field.
>>>
>>> Unlike the legacy CPUArchState registration, rather register CPUState.
>>>
>>> Juan, do you remember?
>>
>> Oh yes, I remember this. There are two ways to handle migration for
>> a CPU object:
>>
>> (1) like any other device, so it has a dc->vmsd that covers
>> migration for the whole object. As usual for objects that are a
>> subclass of a parent that has state, the first entry in the
>> VMStateDescription field list is VMSTATE_CPU(), which migrates
>> the cpu_common fields, followed by whatever the CPU's own migration
>> fields are.
target/alpha/cpu.c:240: dc->vmsd = &vmstate_alpha_cpu;
target/cris/cpu.c:296: dc->vmsd = &vmstate_cris_cpu;
target/hppa/cpu.c:165: dc->vmsd = &vmstate_hppa_cpu;
target/m68k/cpu.c:537: dc->vmsd = &vmstate_m68k_cpu;
target/microblaze/cpu.c:390: dc->vmsd = &vmstate_mb_cpu;
target/openrisc/cpu.c:207: dc->vmsd = &vmstate_openrisc_cpu;
target/sh4/cpu.c:265: dc->vmsd = &vmstate_sh_cpu;
target/unicore32/cpu.c:149: dc->vmsd = &vmstate_uc32_cpu;
target/xtensa/cpu.c:221: dc->vmsd = &vmstate_xtensa_cpu;
>> (2) a backwards-compatible mechanism for CPUs that were
>> originally migrated using manual "write fields to the migration
>> stream structures". The on-the-wire migration format
>> for those is based on the 'env' pointer (which isn't a QOM object),
>> and the cpu_common part of the migration data is elsewhere.
target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
>> cpu_exec_realizefn() handles both possibilities:
>> * for type 1, dc->vmsd is set and cc->vmsd is not,
>> so cpu_exec_realizefn() does nothing, and the standard
>> "register dc->vmsd for a device" code does everything needed
>> * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common
>> directly to handle the cpu-common fields, and the cc->vmsd to handle
>> the per-CPU stuff
>>
>> You can't change a CPU from one type to the other without breaking
>> migration compatibility, which is why some guest architectures
>> are stuck on the cc->vmsd form. New targets should use dc->vmsd.
IOW new targets should use type 1.
Looking at type 2:
a) targets added 'recently' with the incorrect type 2:
target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
b) targets where migration isn't really an issue:
target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
c) targets where migration could be broken:
target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
d) KVM targets ("security boundary" or Tier-1) are left:
target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
Isn't "machine type" what allows us to change migration stream?
All targets in d) do support that.
How could we enforce no new type 2 targets?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-04-22 15:41 ` Philippe Mathieu-Daudé
@ 2021-04-22 15:53 ` Peter Maydell
-1 siblings, 0 replies; 56+ messages in thread
From: Peter Maydell @ 2021-04-22 15:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Sarah Harris, Chris Wulff, Sagar Karandikar, Michael S. Tsirkin,
Anthony Green, Mark Cave-Ayland, QEMU Developers, Max Filippov,
Taylor Simpson, Alistair Francis, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Juan Quintela, David Hildenbrand,
Markus Armbruster, Claudio Fontana, Palmer Dabbelt,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Dr. David Alan Gilbert, Greg Kurz, qemu-s390x,
qemu-arm, Michael Rolnik, Stafford Horne, David Gibson,
open list:RISC-V, Bastian Koppelmann, Cornelia Huck,
Laurent Vivier, Michael Walle, qemu-ppc, Paolo Bonzini,
Aleksandar Rikalo, Aurelien Jarno
On Thu, 22 Apr 2021 at 16:41, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> IOW new targets should use type 1.
>
>
> Looking at type 2:
>
> a) targets added 'recently' with the incorrect type 2:
>
> target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
> target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
>
> b) targets where migration isn't really an issue:
>
> target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
> target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
>
> c) targets where migration could be broken:
>
> target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
> target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
>
> d) KVM targets ("security boundary" or Tier-1) are left:
>
> target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
> target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
> target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
> target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
>
>
> Isn't "machine type" what allows us to change migration stream?
> All targets in d) do support that.
Versioned machine types allow us to change the migration stream
if we do it in a forwards-compatible way (and if we're feeling
kind to RH as a downstream perhaps even backwards-compatible);
but new QEMU still has to be able to read the migration stream
produced by old QEMU for the "virt-5.2" board, or whatever.
In some cases I think we also like to maintain migration
compat on a "best-effort" basis; I think Mark likes to handle
the SPARC guests that way.
thanks
-- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-22 15:53 ` Peter Maydell
0 siblings, 0 replies; 56+ messages in thread
From: Peter Maydell @ 2021-04-22 15:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Markus Armbruster, Eduardo Habkost, Dr. David Alan Gilbert,
Sarah Harris, Cornelia Huck, Sagar Karandikar,
Michael S. Tsirkin, Anthony Green, Mark Cave-Ayland,
QEMU Developers, Max Filippov, Taylor Simpson, Alistair Francis,
Guan Xuetao, Marek Vasut, Yoshinori Sato, Juan Quintela,
David Hildenbrand, Claudio Fontana, Thomas Huth, qemu-ppc,
Artyom Tarasenko, Aleksandar Rikalo, Richard Henderson,
Greg Kurz, qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
David Gibson, open list:RISC-V, Bastian Koppelmann, Chris Wulff,
Laurent Vivier, Michael Walle, Palmer Dabbelt, Paolo Bonzini,
Aurelien Jarno
On Thu, 22 Apr 2021 at 16:41, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> IOW new targets should use type 1.
>
>
> Looking at type 2:
>
> a) targets added 'recently' with the incorrect type 2:
>
> target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
> target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
>
> b) targets where migration isn't really an issue:
>
> target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
> target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
>
> c) targets where migration could be broken:
>
> target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
> target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
>
> d) KVM targets ("security boundary" or Tier-1) are left:
>
> target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
> target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
> target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
> target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
>
>
> Isn't "machine type" what allows us to change migration stream?
> All targets in d) do support that.
Versioned machine types allow us to change the migration stream
if we do it in a forwards-compatible way (and if we're feeling
kind to RH as a downstream perhaps even backwards-compatible);
but new QEMU still has to be able to read the migration stream
produced by old QEMU for the "virt-5.2" board, or whatever.
In some cases I think we also like to maintain migration
compat on a "best-effort" basis; I think Mark likes to handle
the SPARC guests that way.
thanks
-- PMM
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
2021-04-22 15:53 ` Peter Maydell
@ 2021-04-22 16:05 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 16:05 UTC (permalink / raw)
To: Peter Maydell
Cc: Sarah Harris, Cornelia Huck, Sagar Karandikar,
Michael S. Tsirkin, Anthony Green, Mark Cave-Ayland,
QEMU Developers, Max Filippov, Taylor Simpson, Alistair Francis,
Guan Xuetao, Marek Vasut, Yoshinori Sato, Juan Quintela,
David Hildenbrand, Markus Armbruster, Claudio Fontana, qemu-ppc,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Dr. David Alan Gilbert, Greg Kurz, qemu-s390x,
qemu-arm, Michael Rolnik, Stafford Horne, David Gibson,
open list:RISC-V, Bastian Koppelmann, Chris Wulff,
Laurent Vivier, Michael Walle, Palmer Dabbelt, Paolo Bonzini,
Aleksandar Rikalo, Aurelien Jarno
On 4/22/21 5:53 PM, Peter Maydell wrote:
> On Thu, 22 Apr 2021 at 16:41, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> IOW new targets should use type 1.
>>
>>
>> Looking at type 2:
>>
>> a) targets added 'recently' with the incorrect type 2:
>>
>> target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
>> target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
>>
>> b) targets where migration isn't really an issue:
>>
>> target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
>> target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
>>
>> c) targets where migration could be broken:
>>
>> target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
>> target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
>>
>> d) KVM targets ("security boundary" or Tier-1) are left:
>>
>> target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
>> target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
>> target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
>> target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
>>
>>
>> Isn't "machine type" what allows us to change migration stream?
>> All targets in d) do support that.
>
> Versioned machine types allow us to change the migration stream
> if we do it in a forwards-compatible way (and if we're feeling
> kind to RH as a downstream perhaps even backwards-compatible);
> but new QEMU still has to be able to read the migration stream
> produced by old QEMU for the "virt-5.2" board, or whatever.
>
> In some cases I think we also like to maintain migration
> compat on a "best-effort" basis; I think Mark likes to handle
> the SPARC guests that way.
What I don't understand if is there is a possibility to eventually
remove the CPUClass::vmsd (even long and painful), or if it is
directly impossible and we are doomed to keep maintaining both.
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 01/27] target: Set CPUClass::vmsd instead of DeviceClass::vmsd
@ 2021-04-22 16:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-04-22 16:05 UTC (permalink / raw)
To: Peter Maydell
Cc: Sarah Harris, Chris Wulff, Sagar Karandikar, Michael S. Tsirkin,
Anthony Green, Mark Cave-Ayland, QEMU Developers, Max Filippov,
Taylor Simpson, Alistair Francis, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Juan Quintela, David Hildenbrand,
Markus Armbruster, Claudio Fontana, Palmer Dabbelt,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Dr. David Alan Gilbert, Greg Kurz, qemu-s390x,
qemu-arm, Michael Rolnik, Stafford Horne, David Gibson,
open list:RISC-V, Bastian Koppelmann, Cornelia Huck,
Laurent Vivier, Michael Walle, qemu-ppc, Paolo Bonzini,
Aleksandar Rikalo, Aurelien Jarno
On 4/22/21 5:53 PM, Peter Maydell wrote:
> On Thu, 22 Apr 2021 at 16:41, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> IOW new targets should use type 1.
>>
>>
>> Looking at type 2:
>>
>> a) targets added 'recently' with the incorrect type 2:
>>
>> target/avr/cpu.c:216: cc->vmsd = &vms_avr_cpu;
>> target/riscv/cpu.c:627: cc->vmsd = &vmstate_riscv_cpu;
>>
>> b) targets where migration isn't really an issue:
>>
>> target/lm32/cpu.c:244: cc->vmsd = &vmstate_lm32_cpu;
>> target/moxie/cpu.c:125: cc->vmsd = &vmstate_moxie_cpu;
>>
>> c) targets where migration could be broken:
>>
>> target/mips/cpu.c:723: cc->vmsd = &vmstate_mips_cpu;
>> target/sparc/cpu.c:892: cc->vmsd = &vmstate_sparc_cpu;
>>
>> d) KVM targets ("security boundary" or Tier-1) are left:
>>
>> target/arm/cpu.c:1985: cc->vmsd = &vmstate_arm_cpu;
>> target/i386/cpu.c:7434: cc->vmsd = &vmstate_x86_cpu;
>> target/ppc/translate_init.c.inc:10923: cc->vmsd = &vmstate_ppc_cpu;
>> target/s390x/cpu.c:520: cc->vmsd = &vmstate_s390_cpu;
>>
>>
>> Isn't "machine type" what allows us to change migration stream?
>> All targets in d) do support that.
>
> Versioned machine types allow us to change the migration stream
> if we do it in a forwards-compatible way (and if we're feeling
> kind to RH as a downstream perhaps even backwards-compatible);
> but new QEMU still has to be able to read the migration stream
> produced by old QEMU for the "virt-5.2" board, or whatever.
>
> In some cases I think we also like to maintain migration
> compat on a "best-effort" basis; I think Mark likes to handle
> the SPARC guests that way.
What I don't understand if is there is a possibility to eventually
remove the CPUClass::vmsd (even long and painful), or if it is
directly impossible and we are doomed to keep maintaining both.
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 02/27] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c005d3dc2d8..2d43f78819f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..4dce35f832f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 02/27] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c005d3dc2d8..2d43f78819f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -578,18 +578,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -601,12 +591,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -615,17 +600,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 00330ba07de..4dce35f832f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -94,6 +94,38 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
/* Resetting the IRQ comes from across the code base so we take the
* BQL here if we need to. cpu_interrupt assumes it is held.*/
void cpu_reset_interrupt(CPUState *cpu, int mask)
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 03/27] cpu: Introduce cpu_virtio_is_big_endian()
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu.c | 8 ++++++--
hw/virtio/virtio.c | 4 +---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2d43f78819f..b12028c3c03 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 4dce35f832f..daaff56a79e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
+bool cpu_virtio_is_big_endian(CPUState *cpu)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
return target_words_bigendian();
}
@@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 1fd1917ca0f..fe6a4be99e4 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 03/27] cpu: Introduce cpu_virtio_is_big_endian()
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Introduce the cpu_virtio_is_big_endian() generic helper to avoid
calling CPUClass internal virtio_is_big_endian() one.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 9 +++++++++
hw/core/cpu.c | 8 ++++++--
hw/virtio/virtio.c | 4 +---
3 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2d43f78819f..b12028c3c03 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -602,6 +602,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
*/
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
+/**
+ * cpu_virtio_is_big_endian:
+ * @cpu: CPU
+
+ * Returns %true if a CPU which supports runtime configurable endianness
+ * is currently big-endian.
+ */
+bool cpu_virtio_is_big_endian(CPUState *cpu);
+
#endif /* CONFIG_USER_ONLY */
/**
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 4dce35f832f..daaff56a79e 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -218,8 +218,13 @@ static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
return 0;
}
-static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
+bool cpu_virtio_is_big_endian(CPUState *cpu)
{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->virtio_is_big_endian) {
+ return cc->virtio_is_big_endian(cpu);
+ }
return target_words_bigendian();
}
@@ -438,7 +443,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
- k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
dc->realize = cpu_common_realizefn;
dc->unrealize = cpu_common_unrealizefn;
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 1fd1917ca0f..fe6a4be99e4 100644
--- a/hw/virtio/virtio.c
+++ b/hw/virtio/virtio.c
@@ -1973,9 +1973,7 @@ static enum virtio_device_endian virtio_default_endian(void)
static enum virtio_device_endian virtio_current_cpu_endian(void)
{
- CPUClass *cc = CPU_GET_CLASS(current_cpu);
-
- if (cc->virtio_is_big_endian(current_cpu)) {
+ if (cpu_virtio_is_big_endian(current_cpu)) {
return VIRTIO_DEVICE_ENDIAN_BIG;
} else {
return VIRTIO_DEVICE_ENDIAN_LITTLE;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 04/27] cpu: Directly use cpu_write_elf*() fallback handlers in place
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index daaff56a79e..a9ee2c74ec5 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
return (*cc->write_elf32_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
return (*cc->write_elf64_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 04/27] cpu: Directly use cpu_write_elf*() fallback handlers in place
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
No code directly accesses CPUClass::write_elf*() handlers out
of hw/core/cpu.c (the rest are assignation in target/ code):
$ git grep -F -- '->write_elf'
hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque);
hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque);
hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note;
hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note;
target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note;
target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note;
target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note;
target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note;
target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note;
target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note;
target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 43 ++++++++++++-------------------------------
1 file changed, 12 insertions(+), 31 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index daaff56a79e..a9ee2c74ec5 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -154,60 +154,45 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_qemunote) {
+ return 0;
+ }
return (*cc->write_elf32_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf32_note) {
+ return -1;
+ }
return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_qemunote) {
+ return 0;
+ }
return (*cc->write_elf64_qemunote)(f, cpu, opaque);
}
-static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
- CPUState *cpu, void *opaque)
-{
- return 0;
-}
-
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
int cpuid, void *opaque)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
+ if (!cc->write_elf64_note) {
+ return -1;
+ }
return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
}
-static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
- CPUState *cpu, int cpuid,
- void *opaque)
-{
- return -1;
-}
-
-
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
{
return 0;
@@ -437,10 +422,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
- k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
- k->write_elf32_note = cpu_common_write_elf32_note;
- k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
- k->write_elf64_note = cpu_common_write_elf64_note;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 05/27] cpu: Directly use get_paging_enabled() fallback handlers in place
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index a9ee2c74ec5..1de00bbb474 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- return cc->get_paging_enabled(cpu);
-}
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
return false;
}
@@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 05/27] cpu: Directly use get_paging_enabled() fallback handlers in place
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c:
$ git grep -F -- '->get_paging_enabled'
hw/core/cpu.c:74: return cc->get_paging_enabled(cpu);
hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled;
target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index a9ee2c74ec5..1de00bbb474 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,11 +71,10 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- return cc->get_paging_enabled(cpu);
-}
+ if (cc->get_paging_enabled) {
+ return cc->get_paging_enabled(cpu);
+ }
-static bool cpu_common_get_paging_enabled(const CPUState *cpu)
-{
return false;
}
@@ -420,7 +419,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 06/27] cpu: Directly use get_memory_mapping() fallback handlers in place
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 1de00bbb474..5abf8bed2e4 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->get_memory_mapping(cpu, list, errp);
-}
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
@@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 06/27] cpu: Directly use get_memory_mapping() fallback handlers in place
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c:
$ git grep -F -- '->get_memory_mapping'
hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp);
hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping;
target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping;
Check the handler presence in place and remove the common fallback code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/cpu.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 1de00bbb474..5abf8bed2e4 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,13 +83,11 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- cc->get_memory_mapping(cpu, list, errp);
-}
+ if (cc->get_memory_mapping) {
+ cc->get_memory_mapping(cpu, list, errp);
+ return;
+ }
-static void cpu_common_get_memory_mapping(CPUState *cpu,
- MemoryMappingList *list,
- Error **errp)
-{
error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
}
@@ -419,7 +417,6 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->parse_features = cpu_common_parse_features;
k->get_arch_id = cpu_common_get_arch_id;
k->has_work = cpu_common_has_work;
- k->get_memory_mapping = cpu_common_get_memory_mapping;
k->gdb_read_register = cpu_common_gdb_read_register;
k->gdb_write_register = cpu_common_gdb_write_register;
set_bit(DEVICE_CATEGORY_CPU, dc->categories);
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 07/27] cpu: Introduce SysemuCPUOps structure
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
target/alpha/cpu.c | 6 ++++++
target/arm/cpu.c | 6 ++++++
target/avr/cpu.c | 4 ++++
target/cris/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/i386/cpu.c | 6 ++++++
target/lm32/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/microblaze/cpu.c | 6 ++++++
target/mips/cpu.c | 6 ++++++
target/moxie/cpu.c | 4 ++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/riscv/cpu.c | 6 ++++++
target/rx/cpu.c | 8 ++++++++
target/s390x/cpu.c | 6 ++++++
target/sh4/cpu.c | 6 ++++++
target/sparc/cpu.c | 6 ++++++
target/tricore/cpu.c | 4 ++++
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 6 ++++++
target/ppc/translate_init.c.inc | 6 ++++++
24 files changed, 152 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b12028c3c03..3c26471d0fa 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+#include "hw/core/sysemu-cpu-ops.h"
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -190,6 +192,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
};
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 00000000000..e54a08ea25e
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index faabffe0796..b9b431102f2 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..994e7b344d4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932ba..84f7ad4167e 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+static struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 29a865b75d2..a97ad7c9c65 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4f142de6e45..48946cf6669 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6a53446e6a5..fa517555e73 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c0..2d8d16d5535 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps lm32_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps lm32_tcg_ops = {
@@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
+ cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index c98fb1e33be..5c43981c35d 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 335dfdc734e..34a60edd1cc 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bf70c77295f..ea9259896f2 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36c..dbc9e022b61 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+static struct SysemuCPUOps moxie_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps moxie_tcg_ops = {
@@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a389..57023e38cb8 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,11 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 79d246d1930..e00678ae038 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a342388..fd85e6fc6af 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26b..812cf718732 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1bb..0efb1381647 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index bd44de53729..41f1c7c0507 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps sh4_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps superh_tcg_ops = {
@@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc83..377378ca1f2 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcba..75f8a2d8014 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 12894ffac6a..37e57178657 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = {
.unmigratable = 1,
};
+static struct SysemuCPUOps uc32_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps uc32_tcg_ops = {
@@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_uc32_cpu;
+ cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 6bedd5b97b8..7b925468203 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps xtensa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps xtensa_tcg_ops = {
@@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e7324e85cdb..a835bd86214 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 07/27] cpu: Introduce SysemuCPUOps structure
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Introduce a structure to hold handler specific to sysemu.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 +++++
include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++
target/alpha/cpu.c | 6 ++++++
target/arm/cpu.c | 6 ++++++
target/avr/cpu.c | 4 ++++
target/cris/cpu.c | 6 ++++++
target/hppa/cpu.c | 6 ++++++
target/i386/cpu.c | 6 ++++++
target/lm32/cpu.c | 6 ++++++
target/m68k/cpu.c | 6 ++++++
target/microblaze/cpu.c | 6 ++++++
target/mips/cpu.c | 6 ++++++
target/moxie/cpu.c | 4 ++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 6 ++++++
target/riscv/cpu.c | 6 ++++++
target/rx/cpu.c | 8 ++++++++
target/s390x/cpu.c | 6 ++++++
target/sh4/cpu.c | 6 ++++++
target/sparc/cpu.c | 6 ++++++
target/tricore/cpu.c | 4 ++++
target/unicore32/cpu.c | 4 ++++
target/xtensa/cpu.c | 6 ++++++
target/ppc/translate_init.c.inc | 6 ++++++
24 files changed, 152 insertions(+)
create mode 100644 include/hw/core/sysemu-cpu-ops.h
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index b12028c3c03..3c26471d0fa 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,6 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
+#include "hw/core/sysemu-cpu-ops.h"
+
/**
* CPUClass:
* @class_by_name: Callback to map -cpu command line model name to an
@@ -190,6 +192,9 @@ struct CPUClass {
bool gdb_stop_before_watchpoint;
struct AccelCPUClass *accel_cpu;
+ /* when system emulation is not available, this pointer is NULL */
+ const struct SysemuCPUOps *sysemu_ops;
+
/* when TCG is not available, this pointer is NULL */
struct TCGCPUOps *tcg_ops;
};
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
new file mode 100644
index 00000000000..e54a08ea25e
--- /dev/null
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -0,0 +1,21 @@
+/*
+ * CPU operations specific to system emulation
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef SYSEMU_CPU_OPS_H
+#define SYSEMU_CPU_OPS_H
+
+#include "hw/core/cpu.h"
+
+/*
+ * struct SysemuCPUOps: System operations specific to a CPU class
+ */
+typedef struct SysemuCPUOps {
+} SysemuCPUOps;
+
+#endif /* SYSEMU_CPU_OPS_H */
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index faabffe0796..b9b431102f2 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps alpha_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps alpha_tcg_ops = {
@@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_alpha_cpu;
+ cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b8bc89e71fc..994e7b344d4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
return g_strdup("arm");
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps arm_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
static struct TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
@@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
+ cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
cc->gdb_core_xml_file = "arm-core.xml";
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 0f4596932ba..84f7ad4167e 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "\n");
}
+static struct SysemuCPUOps avr_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps avr_tcg_ops = {
@@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->vmsd = &vms_avr_cpu;
+ cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
cc->gdb_write_register = avr_cpu_gdb_write_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 29a865b75d2..a97ad7c9c65 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps cris_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps crisv10_tcg_ops = {
@@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_cris_cpu;
+ cc->sysemu_ops = &cris_sysemu_ops;
#endif
cc->gdb_num_core_regs = 49;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 4f142de6e45..48946cf6669 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_HPPA_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps hppa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps hppa_tcg_ops = {
@@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_hppa_cpu;
+ cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
cc->gdb_num_core_regs = 128;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6a53446e6a5..fa517555e73 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps i386_sysemu_ops = {
+};
+#endif
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->vmsd = &vmstate_x86_cpu;
+ cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
cc->gdb_arch_name = x86_gdb_arch_name;
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index c23d72874c0..2d8d16d5535 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
return oc;
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps lm32_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps lm32_tcg_ops = {
@@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
+ cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
cc->gdb_stop_before_watchpoint = true;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index c98fb1e33be..5c43981c35d 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu = {
};
#endif
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps m68k_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps m68k_tcg_ops = {
@@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_m68k_cpu;
+ cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 335dfdc734e..34a60edd1cc 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
return object_class_by_name(TYPE_MICROBLAZE_CPU);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps mb_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps mb_tcg_ops = {
@@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->vmsd = &vmstate_mb_cpu;
+ cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 27;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bf70c77295f..ea9259896f2 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps mips_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_mips_cpu;
+ cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
cc->gdb_num_core_regs = 73;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 83bec34d36c..dbc9e022b61 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
return oc;
}
+static struct SysemuCPUOps moxie_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps moxie_tcg_ops = {
@@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
+ cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
}
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index e9c9fc3a389..57023e38cb8 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -207,6 +207,11 @@ static Property nios2_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps nios2_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps nios2_tcg_ops = {
@@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
cc->gdb_write_register = nios2_cpu_gdb_write_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 79d246d1930..e00678ae038 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj)
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps openrisc_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps openrisc_tcg_ops = {
@@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_openrisc_cpu;
+ cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->disas_set_info = openrisc_disas_set_info;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a342388..fd85e6fc6af 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
return NULL;
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps riscv_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps riscv_tcg_ops = {
@@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
+ cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 7ac6618b26b..812cf718732 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj)
qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps rx_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps rx_tcg_ops = {
@@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
cc->dump_state = rx_cpu_dump_state;
cc->set_pc = rx_cpu_set_pc;
+#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &rx_sysemu_ops;
+#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index d35eb39a1bb..0efb1381647 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev)
return s390_cpu_reset(s, S390_CPU_RESET_CLEAR);
}
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps s390_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
+ cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
cc->gdb_num_core_regs = S390_NUM_CORE_REGS;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index bd44de53729..41f1c7c0507 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps sh4_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps superh_tcg_ops = {
@@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index aece2c7dc83..377378ca1f2 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps sparc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_sparc_cpu;
+ cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 0b1e139bcba..75f8a2d8014 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static struct SysemuCPUOps tricore_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps tricore_tcg_ops = {
@@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
+ cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 12894ffac6a..37e57178657 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = {
.unmigratable = 1,
};
+static struct SysemuCPUOps uc32_sysemu_ops = {
+};
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps uc32_tcg_ops = {
@@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_uc32_cpu;
+ cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 6bedd5b97b8..7b925468203 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu = {
.unmigratable = 1,
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps xtensa_sysemu_ops = {
+};
+#endif
+
#include "hw/core/tcg-cpu-ops.h"
static struct TCGCPUOps xtensa_tcg_ops = {
@@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
+ cc->sysemu_ops = &xtensa_sysemu_ops;
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index e7324e85cdb..a835bd86214 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+#ifndef CONFIG_USER_ONLY
+static struct SysemuCPUOps ppc_sysemu_ops = {
+};
+#endif
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
+ cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
cc->write_elf64_note = ppc64_cpu_write_elf64_note;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v3 07/27] cpu: Introduce SysemuCPUOps structure
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-03 5:18 ` Richard Henderson
-1 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-03-03 5:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Max Filippov, Taylor Simpson,
Alistair Francis, Edgar E. Iglesias, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Michael S. Tsirkin, Claudio Fontana,
Palmer Dabbelt, Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost, Greg Kurz,
qemu-s390x, qemu-arm, Michael Rolnik, Stafford Horne,
Alex Bennée, David Gibson, qemu-riscv, Bastian Koppelmann,
Cornelia Huck, Laurent Vivier, Michael Walle, qemu-ppc,
Paolo Bonzini, Aurelien Jarno
On 3/2/21 6:57 AM, Philippe Mathieu-Daudé wrote:
> +static struct SysemuCPUOps alpha_sysemu_ops = {
const, for all of them.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 07/27] cpu: Introduce SysemuCPUOps structure
@ 2021-03-03 5:18 ` Richard Henderson
0 siblings, 0 replies; 56+ messages in thread
From: Richard Henderson @ 2021-03-03 5:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Laurent Vivier, Paolo Bonzini, Greg Kurz, Stafford Horne,
qemu-ppc, Anthony Green, Aurelien Jarno, Jiaxun Yang,
Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, qemu-s390x, Sarah Harris, Eduardo Habkost,
Bastian Koppelmann, qemu-riscv, Mark Cave-Ayland,
Michael S. Tsirkin, Yoshinori Sato, Taylor Simpson
On 3/2/21 6:57 AM, Philippe Mathieu-Daudé wrote:
> +static struct SysemuCPUOps alpha_sysemu_ops = {
const, for all of them.
r~
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Migration is specific to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
cpu.c | 18 ++++++++----------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 7 +++++++
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 4 ++--
target/rx/cpu.c | 6 ++++++
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 4 ++--
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 7 +++++++
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 4 ++--
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 54 insertions(+), 34 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3c26471d0fa..471c99d9f04 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,7 +124,6 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -179,7 +178,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25e..05f19b22070 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,10 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @vmsd: State description for migration.
+ */
+ const VMStateDescription *vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/cpu.c b/cpu.c
index bfbe5a66f95..64e17537e21 100644
--- a/cpu.c
+++ b/cpu.c
@@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
@@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
}
#endif /* CONFIG_TCG */
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
+#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b9b431102f2..8d7a73d638e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps alpha_sysemu_ops = {
+ .vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 994e7b344d4..e03977e4c3c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2304,7 +2305,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 84f7ad4167e..b455a5e3434 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static struct SysemuCPUOps avr_sysemu_ops = {
+ .vmsd = &vms_avr_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index a97ad7c9c65..3ffd47c488d 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps cris_sysemu_ops = {
+ .vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 48946cf6669..ba6401a4979 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps hppa_sysemu_ops = {
+ .vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fa517555e73..2d1e61da8ea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 2d8d16d5535..bc754034c7e 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps lm32_sysemu_ops = {
+ .vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_lm32_cpu;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 5c43981c35d..1641cf87a52 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps m68k_sysemu_ops = {
+ .vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 34a60edd1cc..f59a1dd8576 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mb_sysemu_ops = {
+ .vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- cc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ea9259896f2..50ab8f2a88c 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mips_sysemu_ops = {
+ .vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index dbc9e022b61..86f6665a048 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static struct SysemuCPUOps moxie_sysemu_ops = {
+ .vmsd = &vmstate_moxie_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 57023e38cb8..971c0d8a00a 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -25,6 +25,7 @@
#include "exec/log.h"
#include "exec/gdbstub.h"
#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -208,7 +209,13 @@ static Property nios2_properties[] = {
};
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_nios2_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static struct SysemuCPUOps nios2_sysemu_ops = {
+ .vmsd = &vmstate_nios2_cpu,
};
#endif
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e00678ae038..55eb195df40 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps openrisc_sysemu_ops = {
+ .vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fd85e6fc6af..3e42f7265eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps riscv_sysemu_ops = {
+ /* For now, mark unmigratable: */
+ .vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -627,8 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 812cf718732..cb8718a58dc 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj)
}
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_rx_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static struct SysemuCPUOps rx_sysemu_ops = {
+ .vmsd = &vmstate_rx_cpu,
};
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 0efb1381647..a480f4abbaf 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
+ .vmsd = &vmstate_s390_cpu,
};
#endif
@@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 41f1c7c0507..038dfa25e84 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps sh4_sysemu_ops = {
+ .vmsd = &vmstate_sh_cpu,
};
#endif
@@ -268,7 +269,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 377378ca1f2..6a324c2765b 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps sparc_sysemu_ops = {
+ .vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 75f8a2d8014..f1f72be8281 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/error-report.h"
+#include "migration/vmstate.h"
static inline void set_feature(CPUTriCoreState *env, int feature)
{
@@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const VMStateDescription vmstate_tricore_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static struct SysemuCPUOps tricore_sysemu_ops = {
+ .vmsd = &vmstate_tricore_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 37e57178657..50a61ac0b83 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static struct SysemuCPUOps uc32_sysemu_ops = {
+ .vmsd = &vmstate_uc32_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_uc32_cpu;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7b925468203..7efe5b4f207 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps xtensa_sysemu_ops = {
+ .vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -224,7 +225,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index a835bd86214..b5ed1dbfd26 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10890,7 +10891,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 08/27] cpu: Move CPUClass::vmsd to SysemuCPUOps
@ 2021-03-02 14:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:57 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Migration is specific to system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
cpu.c | 18 ++++++++----------
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 2 +-
target/nios2/cpu.c | 7 +++++++
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 4 ++--
target/rx/cpu.c | 6 ++++++
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 4 ++--
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 7 +++++++
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 4 ++--
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 54 insertions(+), 34 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3c26471d0fa..471c99d9f04 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -124,7 +124,6 @@ struct AccelCPUClass;
* 32-bit VM coredump.
* @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
* note to a 32-bit VM coredump.
- * @vmsd: State description for migration.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -179,7 +178,6 @@ struct CPUClass {
int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
void *opaque);
- const VMStateDescription *vmsd;
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index e54a08ea25e..05f19b22070 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,10 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @vmsd: State description for migration.
+ */
+ const VMStateDescription *vmsd;
} SysemuCPUOps;
#endif /* SYSEMU_CPU_OPS_H */
diff --git a/cpu.c b/cpu.c
index bfbe5a66f95..64e17537e21 100644
--- a/cpu.c
+++ b/cpu.c
@@ -126,7 +126,9 @@ const VMStateDescription vmstate_cpu_common = {
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
+#endif
cpu_list_add(cpu);
@@ -137,27 +139,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
}
#endif /* CONFIG_TCG */
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
+#ifndef CONFIG_USER_ONLY
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
}
- if (cc->vmsd != NULL) {
- vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->vmsd, cpu);
}
#endif /* CONFIG_USER_ONLY */
}
void cpu_exec_unrealizefn(CPUState *cpu)
{
+#ifndef CONFIG_USER_ONLY
CPUClass *cc = CPU_GET_CLASS(cpu);
-#ifdef CONFIG_USER_ONLY
- assert(cc->vmsd == NULL);
-#else
- if (cc->vmsd != NULL) {
- vmstate_unregister(NULL, cc->vmsd, cpu);
+ if (cc->sysemu_ops->vmsd != NULL) {
+ vmstate_unregister(NULL, cc->sysemu_ops->vmsd, cpu);
}
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index b9b431102f2..8d7a73d638e 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps alpha_sysemu_ops = {
+ .vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 994e7b344d4..e03977e4c3c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2304,7 +2305,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->vmsd = &vmstate_arm_cpu;
cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 84f7ad4167e..b455a5e3434 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static struct SysemuCPUOps avr_sysemu_ops = {
+ .vmsd = &vms_avr_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
- cc->vmsd = &vms_avr_cpu;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index a97ad7c9c65..3ffd47c488d 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps cris_sysemu_ops = {
+ .vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_cris_cpu;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 48946cf6669..ba6401a4979 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps hppa_sysemu_ops = {
+ .vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_hppa_cpu;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fa517555e73..2d1e61da8ea 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
- cc->vmsd = &vmstate_x86_cpu;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index 2d8d16d5535..bc754034c7e 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps lm32_sysemu_ops = {
+ .vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_lm32_cpu;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 5c43981c35d..1641cf87a52 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps m68k_sysemu_ops = {
+ .vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_m68k_cpu;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 34a60edd1cc..f59a1dd8576 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mb_sysemu_ops = {
+ .vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
- cc->vmsd = &vmstate_mb_cpu;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index ea9259896f2..50ab8f2a88c 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mips_sysemu_ops = {
+ .vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_mips_cpu;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index dbc9e022b61..86f6665a048 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static struct SysemuCPUOps moxie_sysemu_ops = {
+ .vmsd = &vmstate_moxie_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -125,7 +126,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = moxie_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_moxie_cpu;
#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 57023e38cb8..971c0d8a00a 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -25,6 +25,7 @@
#include "exec/log.h"
#include "exec/gdbstub.h"
#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -208,7 +209,13 @@ static Property nios2_properties[] = {
};
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_nios2_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static struct SysemuCPUOps nios2_sysemu_ops = {
+ .vmsd = &vmstate_nios2_cpu,
};
#endif
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e00678ae038..55eb195df40 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps openrisc_sysemu_ops = {
+ .vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_openrisc_cpu;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fd85e6fc6af..3e42f7265eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps riscv_sysemu_ops = {
+ /* For now, mark unmigratable: */
+ .vmsd = &vmstate_riscv_cpu,
};
#endif
@@ -627,8 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
- /* For now, mark unmigratable: */
- cc->vmsd = &vmstate_riscv_cpu;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 812cf718732..cb8718a58dc 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -174,7 +174,13 @@ static void rx_cpu_init(Object *obj)
}
#ifndef CONFIG_USER_ONLY
+static const VMStateDescription vmstate_rx_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static struct SysemuCPUOps rx_sysemu_ops = {
+ .vmsd = &vmstate_rx_cpu,
};
#endif
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 0efb1381647..a480f4abbaf 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
+ .vmsd = &vmstate_s390_cpu,
};
#endif
@@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_s390_cpu;
cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 41f1c7c0507..038dfa25e84 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -218,13 +218,14 @@ static void superh_cpu_initfn(Object *obj)
env->movcal_backup_tail = &(env->movcal_backup);
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_sh_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps sh4_sysemu_ops = {
+ .vmsd = &vmstate_sh_cpu,
};
#endif
@@ -268,7 +269,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_num_core_regs = 59;
- cc->vmsd = &vmstate_sh_cpu;
cc->tcg_ops = &superh_tcg_ops;
}
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 377378ca1f2..6a324c2765b 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps sparc_sysemu_ops = {
+ .vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_sparc_cpu;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 75f8a2d8014..f1f72be8281 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -22,6 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/error-report.h"
+#include "migration/vmstate.h"
static inline void set_feature(CPUTriCoreState *env, int feature)
{
@@ -142,7 +143,13 @@ static void tc27x_initfn(Object *obj)
set_feature(&cpu->env, TRICORE_FEATURE_161);
}
+static const VMStateDescription vmstate_tricore_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static struct SysemuCPUOps tricore_sysemu_ops = {
+ .vmsd = &vmstate_tricore_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 37e57178657..50a61ac0b83 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static struct SysemuCPUOps uc32_sysemu_ops = {
+ .vmsd = &vmstate_uc32_cpu,
};
#include "hw/core/tcg-cpu-ops.h"
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_uc32_cpu;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7b925468203..7efe5b4f207 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -176,13 +176,14 @@ static void xtensa_cpu_initfn(Object *obj)
#endif
}
+#ifndef CONFIG_USER_ONLY
static const VMStateDescription vmstate_xtensa_cpu = {
.name = "cpu",
.unmigratable = 1,
};
-#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps xtensa_sysemu_ops = {
+ .vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -224,7 +225,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
- cc->vmsd = &vmstate_xtensa_cpu;
cc->tcg_ops = &xtensa_tcg_ops;
}
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index a835bd86214..b5ed1dbfd26 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10890,7 +10891,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
- cc->vmsd = &vmstate_ppc_cpu;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
#if defined(CONFIG_SOFTMMU)
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 09/27] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
VirtIO devices are only meaningful with system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 8 ++++++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 4 +---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 471c99d9f04..dfb50b60128 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,10 +89,6 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -151,7 +147,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 05f19b22070..9c3ac4f2280 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,14 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @vmsd: State description for migration.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 5abf8bed2e4..09eaa3fa49f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e03977e4c3c..2bad6307cce 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2305,7 +2306,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b5ed1dbfd26..2dd4f47adbb 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10913,9 +10914,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 09/27] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
VirtIO devices are only meaningful with system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 5 -----
include/hw/core/sysemu-cpu-ops.h | 8 ++++++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 4 +---
5 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 471c99d9f04..dfb50b60128 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -89,10 +89,6 @@ struct AccelCPUClass;
* @parse_features: Callback to parse command line arguments.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
* @has_work: Callback for checking if there is work to do.
- * @virtio_is_big_endian: Callback to return %true if a CPU which supports
- * runtime configurable endianness is currently big-endian. Non-configurable
- * CPUs can use the default implementation of this method. This method should
- * not be used by any callers other than the pre-1.0 virtio devices.
* @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
@@ -151,7 +147,6 @@ struct CPUClass {
int reset_dump_flags;
bool (*has_work)(CPUState *cpu);
- bool (*virtio_is_big_endian)(CPUState *cpu);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 05f19b22070..9c3ac4f2280 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,14 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @virtio_is_big_endian: Callback to return %true if a CPU which supports
+ * runtime configurable endianness is currently big-endian.
+ * Non-configurable CPUs can use the default implementation of this method.
+ * This method should not be used by any callers other than the pre-1.0
+ * virtio devices.
+ */
+ bool (*virtio_is_big_endian)(CPUState *cpu);
/**
* @vmsd: State description for migration.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 5abf8bed2e4..09eaa3fa49f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -204,8 +204,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->virtio_is_big_endian) {
- return cc->virtio_is_big_endian(cpu);
+ if (cc->sysemu_ops->virtio_is_big_endian) {
+ return cc->sysemu_ops->virtio_is_big_endian(cpu);
}
return target_words_bigendian();
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e03977e4c3c..2bad6307cce 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
#endif
@@ -2305,7 +2306,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
cc->write_elf64_note = arm_cpu_write_elf64_note;
cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index b5ed1dbfd26..2dd4f47adbb 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
#endif
@@ -10913,9 +10914,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_core_xml_file = "power64-core.xml";
#else
cc->gdb_core_xml_file = "power-core.xml";
-#endif
-#ifndef CONFIG_USER_ONLY
- cc->virtio_is_big_endian = ppc_cpu_is_big_endian;
#endif
cc->disas_set_info = ppc_disas_set_info;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 10/27] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index dfb50b60128..781cd8fc42b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -150,7 +150,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 9c3ac4f2280..b9ffca07665 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 09eaa3fa49f..0aebc18c41f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2d1e61da8ea..b7672a7accc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7427,7 +7428,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index a480f4abbaf..04c14fcd9da 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 10/27] cpu: Move CPUClass::get_crash_info to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
cpu_get_crash_info() is called on GUEST_PANICKED events,
which only occur in system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 1 -
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
5 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index dfb50b60128..781cd8fc42b 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -150,7 +150,6 @@ struct CPUClass {
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *, int flags);
- GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 9c3ac4f2280..b9ffca07665 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_crash_info: Callback for reporting guest crash information in
+ * GUEST_PANICKED events.
+ */
+ GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 09eaa3fa49f..0aebc18c41f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -220,8 +220,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
CPUClass *cc = CPU_GET_CLASS(cpu);
GuestPanicInformation *res = NULL;
- if (cc->get_crash_info) {
- res = cc->get_crash_info(cpu);
+ if (cc->sysemu_ops->get_crash_info) {
+ res = cc->sysemu_ops->get_crash_info(cpu);
}
return res;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2d1e61da8ea..b7672a7accc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .get_crash_info = x86_cpu_get_crash_info,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7427,7 +7428,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->get_crash_info = x86_cpu_get_crash_info;
cc->write_elf64_note = x86_cpu_write_elf64_note;
cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
cc->write_elf32_note = x86_cpu_write_elf32_note;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index a480f4abbaf..04c14fcd9da 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
+ .get_crash_info = s390_cpu_get_crash_info,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->get_crash_info = s390_cpu_get_crash_info;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 11/27] cpu: Move CPUClass::write_elf* to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/s390x/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 6 ++----
7 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 781cd8fc42b..0a2c29c3735 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -112,14 +112,6 @@ struct AccelCPUClass;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -163,15 +155,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index b9ffca07665..60c667801ef 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 0aebc18c41f..c74390aafbf 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2bad6307cce..7dc6956f2cc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
@@ -2306,8 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b7672a7accc..b26905b22a3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7389,6 +7389,10 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7428,10 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 04c14fcd9da..92b7a66d3c3 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 2dd4f47adbb..068f4a4012e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,8 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
@@ -10894,10 +10896,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 11/27] cpu: Move CPUClass::write_elf* to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
The write_elf*() handlers are used to dump vmcore images.
This feature is only meaningful for system emulation.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 17 -----------------
include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++
hw/core/cpu.c | 16 ++++++++--------
target/arm/cpu.c | 4 ++--
target/i386/cpu.c | 8 ++++----
target/s390x/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 6 ++----
7 files changed, 41 insertions(+), 36 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 781cd8fc42b..0a2c29c3735 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -112,14 +112,6 @@ struct AccelCPUClass;
* a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
- * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
- * 64-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
- * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
- * 32-bit VM coredump.
- * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
- * note to a 32-bit VM coredump.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
* @gdb_core_xml_file: File name for core registers GDB XML description.
* @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop
@@ -163,15 +155,6 @@ struct CPUClass {
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
- int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
- int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
- int cpuid, void *opaque);
- int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
- void *opaque);
-
const char *gdb_core_xml_file;
gchar * (*gdb_arch_name)(CPUState *cpu);
const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index b9ffca07665..60c667801ef 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,30 @@ typedef struct SysemuCPUOps {
* GUEST_PANICKED events.
*/
GuestPanicInformation* (*get_crash_info)(CPUState *cpu);
+ /**
+ * @write_elf32_note: Callback for writing a CPU-specific ELF note to a
+ * 32-bit VM coredump.
+ */
+ int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf64_note: Callback for writing a CPU-specific ELF note to a
+ * 64-bit VM coredump.
+ */
+ int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
+ int cpuid, void *opaque);
+ /**
+ * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 32-bit VM coredump.
+ */
+ int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
+ /**
+ * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specific ELF
+ * note to a 64-bit VM coredump.
+ */
+ int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
+ void *opaque);
/**
* @virtio_is_big_endian: Callback to return %true if a CPU which supports
* runtime configurable endianness is currently big-endian.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 0aebc18c41f..c74390aafbf 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -151,10 +151,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_qemunote) {
+ if (!cc->sysemu_ops->write_elf32_qemunote) {
return 0;
}
- return (*cc->write_elf32_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque);
}
int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -162,10 +162,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf32_note) {
+ if (!cc->sysemu_ops->write_elf32_note) {
return -1;
}
- return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque);
}
int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
@@ -173,10 +173,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_qemunote) {
+ if (!cc->sysemu_ops->write_elf64_qemunote) {
return 0;
}
- return (*cc->write_elf64_qemunote)(f, cpu, opaque);
+ return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque);
}
int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
@@ -184,10 +184,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (!cc->write_elf64_note) {
+ if (!cc->sysemu_ops->write_elf64_note) {
return -1;
}
- return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
+ return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque);
}
static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2bad6307cce..7dc6956f2cc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .write_elf32_note = arm_cpu_write_elf32_note,
+ .write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
.vmsd = &vmstate_arm_cpu,
};
@@ -2306,8 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->asidx_from_attrs = arm_asidx_from_attrs;
- cc->write_elf64_note = arm_cpu_write_elf64_note;
- cc->write_elf32_note = arm_cpu_write_elf32_note;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b7672a7accc..b26905b22a3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7389,6 +7389,10 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
.get_crash_info = x86_cpu_get_crash_info,
+ .write_elf32_note = x86_cpu_write_elf32_note,
+ .write_elf64_note = x86_cpu_write_elf64_note,
+ .write_elf32_qemunote = x86_cpu_write_elf32_qemunote,
+ .write_elf64_qemunote = x86_cpu_write_elf64_qemunote,
.vmsd = &vmstate_x86_cpu,
};
#endif
@@ -7428,10 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
- cc->write_elf64_note = x86_cpu_write_elf64_note;
- cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
- cc->write_elf32_note = x86_cpu_write_elf32_note;
- cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 04c14fcd9da..92b7a66d3c3 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -480,6 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
.get_crash_info = s390_cpu_get_crash_info,
+ .write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
};
#endif
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
- cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 2dd4f47adbb..068f4a4012e 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,8 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .write_elf32_note = ppc32_cpu_write_elf32_note,
+ .write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
.vmsd = &vmstate_ppc_cpu,
};
@@ -10894,10 +10896,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
-#if defined(CONFIG_SOFTMMU)
- cc->write_elf64_note = ppc64_cpu_write_elf64_note;
- cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-#endif
cc->gdb_num_core_regs = 71;
#ifndef CONFIG_USER_ONLY
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 12/27] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0a2c29c3735..6713a615916 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 60c667801ef..3c3f211136d 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7dc6956f2cc..acaa3ab68da 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b26905b22a3..10884540610 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 12/27] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/arm/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
5 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 0a2c29c3735..6713a615916 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -108,8 +108,6 @@ struct AccelCPUClass;
* associated memory transaction attributes to use for the access.
* CPUs which use memory transaction attributes should implement this
* instead of get_phys_page_debug.
- * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
- * a memory access with the specified memory transaction attributes.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -151,7 +149,6 @@ struct CPUClass {
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
MemTxAttrs *attrs);
- int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 60c667801ef..3c3f211136d 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
+ * a memory access with the specified memory transaction attributes.
+ */
+ int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs);
/**
* @get_crash_info: Callback for reporting guest crash information in
* GUEST_PANICKED events.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c74390aafbf..c44229205ff 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -116,8 +116,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
CPUClass *cc = CPU_GET_CLASS(cpu);
int ret = 0;
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
+ if (cc->sysemu_ops->asidx_from_attrs) {
+ ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
assert(ret < cpu->num_ases && ret >= 0);
}
return ret;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7dc6956f2cc..acaa3ab68da 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
.virtio_is_big_endian = arm_cpu_virtio_is_big_endian,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
- cc->asidx_from_attrs = arm_asidx_from_attrs;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b26905b22a3..10884540610 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
.write_elf64_note = x86_cpu_write_elf64_note,
@@ -7429,7 +7430,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->asidx_from_attrs = x86_asidx_from_attrs;
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 13/27] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 4 +---
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 6713a615916..9a86c707cf7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -103,11 +103,6 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -146,9 +141,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 3c3f211136d..0c8f616a565 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c44229205ff..6932781425a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 8d7a73d638e..d9a51d9f647 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
.vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index acaa3ab68da..6cd546213de 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index b455a5e3434..040d3526995 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
.vmsd = &vms_avr_cpu,
};
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 3ffd47c488d..77f821f4d9a 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
.vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index ba6401a4979..7de37aadd4d 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
.vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 10884540610..c7a18cd8e4f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index bc754034c7e..c80cae9ff3b 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps lm32_sysemu_ops = {
+ .get_phys_page_debug = lm32_cpu_get_phys_page_debug,
.vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 1641cf87a52..eaf5f34d22c 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
.vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f59a1dd8576..a21f15192ae 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
.vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 50ab8f2a88c..285564b4d5b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 86f6665a048..47b8735bb75 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static struct SysemuCPUOps moxie_sysemu_ops = {
+ .get_phys_page_debug = moxie_cpu_get_phys_page_debug,
.vmsd = &vmstate_moxie_cpu,
};
@@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = moxie_cpu_has_work;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
-#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
-#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 971c0d8a00a..e5cbf43d6ee 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu = {
};
static struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
.vmsd = &vmstate_nios2_cpu,
};
#endif
@@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 55eb195df40..c666e86e919 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
.vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3e42f7265eb..eaf7c13e5a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
/* For now, mark unmigratable: */
.vmsd = &vmstate_riscv_cpu,
};
@@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index cb8718a58dc..d1a7a5f6877 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu = {
};
static struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
.vmsd = &vmstate_rx_cpu,
};
#endif
@@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 92b7a66d3c3..30117fc8cd7 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 038dfa25e84..843f39de41c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = {
};
static struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
.vmsd = &vmstate_sh_cpu,
};
#endif
@@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 6a324c2765b..c8a115c886a 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index f1f72be8281..0c4b5021e79 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu = {
};
static struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
.vmsd = &vmstate_tricore_cpu,
};
@@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 50a61ac0b83..610fb5393ae 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static struct SysemuCPUOps uc32_sysemu_ops = {
+ .get_phys_page_debug = uc32_cpu_get_phys_page_debug,
.vmsd = &vmstate_uc32_cpu,
};
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7efe5b4f207..44a4524bc0a 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
};
static struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
.vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops = &xtensa_tcg_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 068f4a4012e..d38d194fe87 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 13/27] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 8 --------
include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++
hw/core/cpu.c | 6 +++---
target/alpha/cpu.c | 2 +-
target/arm/cpu.c | 2 +-
target/avr/cpu.c | 2 +-
target/cris/cpu.c | 2 +-
target/hppa/cpu.c | 2 +-
target/i386/cpu.c | 2 +-
target/lm32/cpu.c | 2 +-
target/m68k/cpu.c | 2 +-
target/microblaze/cpu.c | 2 +-
target/mips/cpu.c | 2 +-
target/moxie/cpu.c | 4 +---
target/nios2/cpu.c | 2 +-
target/openrisc/cpu.c | 2 +-
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 2 +-
target/s390x/cpu.c | 2 +-
target/sh4/cpu.c | 2 +-
target/sparc/cpu.c | 2 +-
target/tricore/cpu.c | 2 +-
target/unicore32/cpu.c | 2 +-
target/xtensa/cpu.c | 2 +-
target/ppc/translate_init.c.inc | 2 +-
25 files changed, 38 insertions(+), 35 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 6713a615916..9a86c707cf7 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -103,11 +103,6 @@ struct AccelCPUClass;
* If the target behaviour here is anything other than "set
* the PC register to the value passed in" then the target must
* also implement the synchronize_from_tb hook.
- * @get_phys_page_debug: Callback for obtaining a physical address.
- * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
- * associated memory transaction attributes to use for the access.
- * CPUs which use memory transaction attributes should implement this
- * instead of get_phys_page_debug.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
* @gdb_num_core_regs: Number of core registers accessible to GDB.
@@ -146,9 +141,6 @@ struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
- hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
- hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 3c3f211136d..0c8f616a565 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,19 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_phys_page_debug: Callback for obtaining a physical address.
+ */
+ hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+ /**
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address
+ * and the associated memory transaction attributes to use for the
+ * access.
+ * CPUs which use memory transaction attributes should implement this
+ * instead of get_phys_page_debug.
+ */
+ hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* @asidx_from_attrs: Callback to return the CPU AddressSpace to use for
* a memory access with the specified memory transaction attributes.
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index c44229205ff..6932781425a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -96,12 +96,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ if (cc->sysemu_ops->get_phys_page_attrs_debug) {
+ return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs);
}
/* Fallback for CPUs which don't implement the _attrs_ hook */
*attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
+ return cc->sysemu_ops->get_phys_page_debug(cpu, addr);
}
hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 8d7a73d638e..d9a51d9f647 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps alpha_sysemu_ops = {
+ .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
.vmsd = &vmstate_alpha_cpu,
};
#endif
@@ -242,7 +243,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
cc->sysemu_ops = &alpha_sysemu_ops;
#endif
cc->disas_set_info = alpha_cpu_disas_set_info;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index acaa3ab68da..6cd546213de 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2262,6 +2262,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps arm_sysemu_ops = {
+ .get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = arm_asidx_from_attrs,
.write_elf32_note = arm_cpu_write_elf32_note,
.write_elf64_note = arm_cpu_write_elf64_note,
@@ -2307,7 +2308,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &arm_sysemu_ops;
#endif
cc->gdb_num_core_regs = 26;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index b455a5e3434..040d3526995 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
static struct SysemuCPUOps avr_sysemu_ops = {
+ .get_phys_page_debug = avr_cpu_get_phys_page_debug,
.vmsd = &vms_avr_cpu,
};
@@ -216,7 +217,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = avr_cpu_dump_state;
cc->set_pc = avr_cpu_set_pc;
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
- cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->sysemu_ops = &avr_sysemu_ops;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->gdb_read_register = avr_cpu_gdb_read_register;
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 3ffd47c488d..77f821f4d9a 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps cris_sysemu_ops = {
+ .get_phys_page_debug = cris_cpu_get_phys_page_debug,
.vmsd = &vmstate_cris_cpu,
};
#endif
@@ -298,7 +299,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
cc->sysemu_ops = &cris_sysemu_ops;
#endif
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index ba6401a4979..7de37aadd4d 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps hppa_sysemu_ops = {
+ .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
.vmsd = &vmstate_hppa_cpu,
};
#endif
@@ -167,7 +168,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = hppa_cpu_gdb_read_register;
cc->gdb_write_register = hppa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
cc->sysemu_ops = &hppa_sysemu_ops;
#endif
cc->disas_set_info = hppa_cpu_disas_set_info;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 10884540610..c7a18cd8e4f 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
.write_elf32_note = x86_cpu_write_elf32_note,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
#ifndef CONFIG_USER_ONLY
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
- cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index bc754034c7e..c80cae9ff3b 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -212,6 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps lm32_sysemu_ops = {
+ .get_phys_page_debug = lm32_cpu_get_phys_page_debug,
.vmsd = &vmstate_lm32_cpu,
};
#endif
@@ -246,7 +247,6 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->sysemu_ops = &lm32_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 7;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 1641cf87a52..eaf5f34d22c 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -504,6 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps m68k_sysemu_ops = {
+ .get_phys_page_debug = m68k_cpu_get_phys_page_debug,
.vmsd = &vmstate_m68k_cpu,
};
#endif
@@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#if defined(CONFIG_SOFTMMU)
- cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
cc->sysemu_ops = &m68k_sysemu_ops;
#endif
cc->disas_set_info = m68k_cpu_disas_set_info;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f59a1dd8576..a21f15192ae 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mb_sysemu_ops = {
+ .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
.vmsd = &vmstate_mb_cpu,
};
#endif
@@ -392,7 +393,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug;
cc->sysemu_ops = &mb_sysemu_ops;
#endif
device_class_set_props(dc, mb_properties);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 50ab8f2a88c..285564b4d5b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -682,6 +682,7 @@ static Property mips_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps mips_sysemu_ops = {
+ .get_phys_page_debug = mips_cpu_get_phys_page_debug,
.vmsd = &vmstate_mips_cpu,
};
#endif
@@ -725,7 +726,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
cc->sysemu_ops = &mips_sysemu_ops;
#endif
cc->disas_set_info = mips_cpu_disas_set_info;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 86f6665a048..47b8735bb75 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -95,6 +95,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model)
}
static struct SysemuCPUOps moxie_sysemu_ops = {
+ .get_phys_page_debug = moxie_cpu_get_phys_page_debug,
.vmsd = &vmstate_moxie_cpu,
};
@@ -124,9 +125,6 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = moxie_cpu_has_work;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
-#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
-#endif
cc->disas_set_info = moxie_cpu_disas_set_info;
cc->sysemu_ops = &moxie_sysemu_ops;
cc->tcg_ops = &moxie_tcg_ops;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 971c0d8a00a..e5cbf43d6ee 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -215,6 +215,7 @@ static const VMStateDescription vmstate_nios2_cpu = {
};
static struct SysemuCPUOps nios2_sysemu_ops = {
+ .get_phys_page_debug = nios2_cpu_get_phys_page_debug,
.vmsd = &vmstate_nios2_cpu,
};
#endif
@@ -249,7 +250,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = nios2_cpu_set_pc;
cc->disas_set_info = nios2_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug;
cc->sysemu_ops = &nios2_sysemu_ops;
#endif
cc->gdb_read_register = nios2_cpu_gdb_read_register;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 55eb195df40..c666e86e919 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps openrisc_sysemu_ops = {
+ .get_phys_page_debug = openrisc_cpu_get_phys_page_debug,
.vmsd = &vmstate_openrisc_cpu,
};
#endif
@@ -209,7 +210,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
cc->sysemu_ops = &openrisc_sysemu_ops;
#endif
cc->gdb_num_core_regs = 32 + 3;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3e42f7265eb..eaf7c13e5a6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -582,6 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps riscv_sysemu_ops = {
+ .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
/* For now, mark unmigratable: */
.vmsd = &vmstate_riscv_cpu,
};
@@ -628,7 +629,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
cc->sysemu_ops = &riscv_sysemu_ops;
#endif
cc->gdb_arch_name = riscv_gdb_arch_name;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index cb8718a58dc..d1a7a5f6877 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -180,6 +180,7 @@ static const VMStateDescription vmstate_rx_cpu = {
};
static struct SysemuCPUOps rx_sysemu_ops = {
+ .get_phys_page_debug = rx_cpu_get_phys_page_debug,
.vmsd = &vmstate_rx_cpu,
};
#endif
@@ -218,7 +219,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
#endif
cc->gdb_read_register = rx_cpu_gdb_read_register;
cc->gdb_write_register = rx_cpu_gdb_write_register;
- cc->get_phys_page_debug = rx_cpu_get_phys_page_debug;
cc->disas_set_info = rx_cpu_disas_set_info;
cc->gdb_num_core_regs = 26;
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 92b7a66d3c3..30117fc8cd7 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev)
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps s390_sysemu_ops = {
+ .get_phys_page_debug = s390_cpu_get_phys_page_debug,
.get_crash_info = s390_cpu_get_crash_info,
.write_elf64_note = s390_cpu_write_elf64_note,
.vmsd = &vmstate_s390_cpu,
@@ -524,7 +525,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->sysemu_ops = &s390_sysemu_ops;
#endif
cc->disas_set_info = s390_cpu_disas_set_info;
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 038dfa25e84..843f39de41c 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = {
};
static struct SysemuCPUOps sh4_sysemu_ops = {
+ .get_phys_page_debug = superh_cpu_get_phys_page_debug,
.vmsd = &vmstate_sh_cpu,
};
#endif
@@ -262,7 +263,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
cc->sysemu_ops = &sh4_sysemu_ops;
#endif
cc->disas_set_info = superh_cpu_disas_set_info;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 6a324c2765b..c8a115c886a 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps sparc_sysemu_ops = {
+ .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
.vmsd = &vmstate_sparc_cpu,
};
#endif
@@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
cc->sysemu_ops = &sparc_sysemu_ops;
#endif
cc->disas_set_info = cpu_sparc_disas_set_info;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index f1f72be8281..0c4b5021e79 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -149,6 +149,7 @@ static const VMStateDescription vmstate_tricore_cpu = {
};
static struct SysemuCPUOps tricore_sysemu_ops = {
+ .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
.vmsd = &vmstate_tricore_cpu,
};
@@ -180,7 +181,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = tricore_cpu_dump_state;
cc->set_pc = tricore_cpu_set_pc;
- cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug;
cc->sysemu_ops = &tricore_sysemu_ops;
cc->tcg_ops = &tricore_tcg_ops;
}
diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c
index 50a61ac0b83..610fb5393ae 100644
--- a/target/unicore32/cpu.c
+++ b/target/unicore32/cpu.c
@@ -121,6 +121,7 @@ static const VMStateDescription vmstate_uc32_cpu = {
};
static struct SysemuCPUOps uc32_sysemu_ops = {
+ .get_phys_page_debug = uc32_cpu_get_phys_page_debug,
.vmsd = &vmstate_uc32_cpu,
};
@@ -149,7 +150,6 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
- cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
cc->sysemu_ops = &uc32_sysemu_ops;
cc->tcg_ops = &uc32_tcg_ops;
}
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7efe5b4f207..44a4524bc0a 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = {
};
static struct SysemuCPUOps xtensa_sysemu_ops = {
+ .get_phys_page_debug = xtensa_cpu_get_phys_page_debug,
.vmsd = &vmstate_xtensa_cpu,
};
#endif
@@ -222,7 +223,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_stop_before_watchpoint = true;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &xtensa_sysemu_ops;
- cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
#endif
cc->disas_set_info = xtensa_cpu_disas_set_info;
cc->tcg_ops = &xtensa_tcg_ops;
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 068f4a4012e..d38d194fe87 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -10845,6 +10845,7 @@ static Property ppc_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps ppc_sysemu_ops = {
+ .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
.write_elf32_note = ppc32_cpu_write_elf32_note,
.write_elf64_note = ppc64_cpu_write_elf64_note,
.virtio_is_big_endian = ppc_cpu_is_big_endian,
@@ -10893,7 +10894,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
- cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->sysemu_ops = &ppc_sysemu_ops;
#endif
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 14/27] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9a86c707cf7..8af78cdde23 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct AccelCPUClass;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -138,8 +137,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 0c8f616a565..460e7d63b0c 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 6932781425a..339bdfadd7a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c7a18cd8e4f..d33ee9f831e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 14/27] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ---
include/hw/core/sysemu-cpu-ops.h | 5 +++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 2 +-
4 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 9a86c707cf7..8af78cdde23 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -94,7 +94,6 @@ struct AccelCPUClass;
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
- * @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -138,8 +137,6 @@ struct CPUClass {
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
- void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
- Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 0c8f616a565..460e7d63b0c 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -16,6 +16,11 @@
* struct SysemuCPUOps: System operations specific to a CPU class
*/
typedef struct SysemuCPUOps {
+ /**
+ * @get_memory_mapping: Callback for obtaining the memory mappings.
+ */
+ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
+ Error **errp);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 6932781425a..339bdfadd7a 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -83,8 +83,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_memory_mapping) {
- cc->get_memory_mapping(cpu, list, errp);
+ if (cc->sysemu_ops->get_memory_mapping) {
+ cc->sysemu_ops->get_memory_mapping(cpu, list, errp);
return;
}
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c7a18cd8e4f..d33ee9f831e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7388,6 +7388,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
+ .get_memory_mapping = x86_cpu_get_memory_mapping,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7431,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
- cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->sysemu_ops = &i386_sysemu_ops;
#endif /* !CONFIG_USER_ONLY */
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 15/27] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8af78cdde23..960846d2b64 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -93,7 +93,6 @@ struct AccelCPUClass;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -136,7 +135,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 460e7d63b0c..3f9a5199dd1 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 339bdfadd7a..7a8487d468f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d33ee9f831e..3519cef8fba 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7157,12 +7157,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -7389,6 +7391,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7429,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 15/27] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 2 --
include/hw/core/sysemu-cpu-ops.h | 4 ++++
hw/core/cpu.c | 4 ++--
target/i386/cpu.c | 4 +++-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 8af78cdde23..960846d2b64 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -93,7 +93,6 @@ struct AccelCPUClass;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
- * @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @set_pc: Callback for setting the Program Counter register. This
* should have the semantics used by the target architecture when
* setting the PC from a source such as an ELF file entry point;
@@ -136,7 +135,6 @@ struct CPUClass {
void (*dump_state)(CPUState *cpu, FILE *, int flags);
void (*dump_statistics)(CPUState *cpu, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
- bool (*get_paging_enabled)(const CPUState *cpu);
void (*set_pc)(CPUState *cpu, vaddr value);
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 460e7d63b0c..3f9a5199dd1 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -21,6 +21,10 @@ typedef struct SysemuCPUOps {
*/
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
+ /**
+ * @get_paging_enabled: Callback for inquiring whether paging is enabled.
+ */
+ bool (*get_paging_enabled)(const CPUState *cpu);
/**
* @get_phys_page_debug: Callback for obtaining a physical address.
*/
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 339bdfadd7a..7a8487d468f 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -71,8 +71,8 @@ bool cpu_paging_enabled(const CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
- if (cc->get_paging_enabled) {
- return cc->get_paging_enabled(cpu);
+ if (cc->sysemu_ops->get_paging_enabled) {
+ return cc->sysemu_ops->get_paging_enabled(cpu);
}
return false;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index d33ee9f831e..3519cef8fba 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7157,12 +7157,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
return cpu->apic_id;
}
+#if !defined(CONFIG_USER_ONLY)
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
return cpu->env.cr[0] & CR0_PG_MASK;
}
+#endif /* !CONFIG_USER_ONLY */
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -7389,6 +7391,7 @@ static Property x86_cpu_properties[] = {
#ifndef CONFIG_USER_ONLY
static struct SysemuCPUOps i386_sysemu_ops = {
.get_memory_mapping = x86_cpu_get_memory_mapping,
+ .get_paging_enabled = x86_cpu_get_paging_enabled,
.get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug,
.asidx_from_attrs = x86_asidx_from_attrs,
.get_crash_info = x86_cpu_get_crash_info,
@@ -7429,7 +7432,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
- cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &i386_sysemu_ops;
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 16/27] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
tcg-cpu-ops.h, keep a pointer in CPUClass"):
We cannot in principle make the SysEmu Operations field definitions
conditional on CONFIG_SOFTMMU in code that is included by both
common_ss and specific_ss modules.
Therefore, what we can do safely to restrict the SysEmu fields to
system emulation builds, is to move all sysemu operations into a
separate header file, which is only included by system-specific code.
This leaves just a NULL pointer in the cpu.h for the user-mode builds.
Inspired-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
target/alpha/cpu.h | 3 +++
target/arm/cpu.h | 3 +++
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +++
target/hexagon/cpu.h | 3 +++
target/hppa/cpu.h | 3 +++
target/i386/cpu.h | 3 +++
target/lm32/cpu.h | 3 +++
target/m68k/cpu.h | 3 +++
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +++
target/moxie/cpu.h | 3 +++
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +++
target/ppc/cpu.h | 3 +++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +++
target/sh4/cpu.h | 3 +++
target/sparc/cpu.h | 3 +++
target/tilegx/cpu.h | 3 +++
target/tricore/cpu.h | 3 +++
target/unicore32/cpu.h | 3 +++
target/xtensa/cpu.h | 3 +++
cpu.c | 1 +
hw/core/cpu.c | 1 +
27 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 960846d2b64..fe4206b540f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,7 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
-#include "hw/core/sysemu-cpu-ops.h"
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
/**
* CPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..f1218a27706 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa1618c4d5..265d00d55dd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d148e8c75a4..e0419649fa7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -23,6 +23,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..4450f2268ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define EXCP_NMI 1
#define EXCP_GURU 2
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c8..2a878e77f08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 61178fa6a2a..94d2d4701c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8be39cfb62e..11941f5f37e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -25,6 +25,9 @@
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index ea7c01ca8b0..034183dad30 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPULM32State CPULM32State;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7c3feeaf8a6..4b0a19bdf44 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define OS_BYTE 0
#define OS_WORD 1
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..3f5c2e048e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -26,6 +26,7 @@
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..923ab71f8d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -6,6 +6,9 @@
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index bd6ab66084d..7a0a5e95d01 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc713..1b88b027063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -27,6 +27,7 @@
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..2a6f9f48547 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68d..f889c28e548 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..254eefaf824 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,9 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..d9b7b63716a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -25,6 +25,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
/* PSW define */
REG32(PSW, 0)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 60d434d5edd..2ca6a4f559f 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,6 +28,9 @@
#include "cpu-qom.h"
#include "cpu_models.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define ELF_MACHINE_UNAME "S390X"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 714e3b56413..07ed2f3e206 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..237ffc4fe66 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,6 +4,9 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 7d8e44d12e4..54bdbf0ca1e 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index b82349d1b10..cb0b989953e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
struct tricore_boot_info;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 7a32e086ed3..de475d0fc2e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -14,6 +14,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..ea4ee5338f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/cpu.c b/cpu.c
index 64e17537e21..29dafee581f 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7a8487d468f..da7543be514 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -35,6 +35,7 @@
#include "trace/trace-root.h"
#include "qemu/plugin.h"
#include "sysemu/hw_accel.h"
+#include "hw/core/sysemu-cpu-ops.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 16/27] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to
tcg-cpu-ops.h, keep a pointer in CPUClass"):
We cannot in principle make the SysEmu Operations field definitions
conditional on CONFIG_SOFTMMU in code that is included by both
common_ss and specific_ss modules.
Therefore, what we can do safely to restrict the SysEmu fields to
system emulation builds, is to move all sysemu operations into a
separate header file, which is only included by system-specific code.
This leaves just a NULL pointer in the cpu.h for the user-mode builds.
Inspired-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 3 ++-
target/alpha/cpu.h | 3 +++
target/arm/cpu.h | 3 +++
target/avr/cpu.h | 1 +
target/cris/cpu.h | 3 +++
target/hexagon/cpu.h | 3 +++
target/hppa/cpu.h | 3 +++
target/i386/cpu.h | 3 +++
target/lm32/cpu.h | 3 +++
target/m68k/cpu.h | 3 +++
target/microblaze/cpu.h | 1 +
target/mips/cpu.h | 3 +++
target/moxie/cpu.h | 3 +++
target/nios2/cpu.h | 1 +
target/openrisc/cpu.h | 3 +++
target/ppc/cpu.h | 3 +++
target/riscv/cpu.h | 3 +++
target/rx/cpu.h | 1 +
target/s390x/cpu.h | 3 +++
target/sh4/cpu.h | 3 +++
target/sparc/cpu.h | 3 +++
target/tilegx/cpu.h | 3 +++
target/tricore/cpu.h | 3 +++
target/unicore32/cpu.h | 3 +++
target/xtensa/cpu.h | 3 +++
cpu.c | 1 +
hw/core/cpu.c | 1 +
27 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 960846d2b64..fe4206b540f 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -80,7 +80,8 @@ struct TCGCPUOps;
/* see accel-cpu.h */
struct AccelCPUClass;
-#include "hw/core/sysemu-cpu-ops.h"
+/* see sysemu-cpu-ops.h */
+struct SysemuCPUOps;
/**
* CPUClass:
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 82df108967b..f1218a27706 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index efa1618c4d5..265d00d55dd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -25,6 +25,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index d148e8c75a4..e0419649fa7 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -23,6 +23,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
#ifdef CONFIG_USER_ONLY
#error "AVR 8-bit does not support user mode"
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index d3b64929096..4450f2268ea 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define EXCP_NMI 1
#define EXCP_GURU 2
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index e04eac591c8..2a878e77f08 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState;
#include "qemu-common.h"
#include "exec/cpu-defs.h"
#include "hex_regs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 61178fa6a2a..94d2d4701c4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "exec/memory.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8be39cfb62e..11941f5f37e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -25,6 +25,9 @@
#include "kvm/hyperv-proto.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index ea7c01ca8b0..034183dad30 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPULM32State CPULM32State;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 7c3feeaf8a6..4b0a19bdf44 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define OS_BYTE 0
#define OS_WORD 1
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e4bba8a7551..3f5c2e048e5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -26,6 +26,7 @@
typedef struct CPUMBState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 075c24abdad..923ab71f8d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -6,6 +6,9 @@
#include "fpu/softfloat-types.h"
#include "hw/clock.h"
#include "mips-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index bd6ab66084d..7a0a5e95d01 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 2ab82fdc713..1b88b027063 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -27,6 +27,7 @@
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
+#include "hw/core/sysemu-cpu-ops.h"
#include "mmu.h"
#endif
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 82cbaeb4f84..2a6f9f48547 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -23,6 +23,9 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e73416da68d..f889c28e548 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -24,6 +24,9 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 02758ae0eb4..254eefaf824 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -25,6 +25,9 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 0b4b998c7be..d9b7b63716a 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -25,6 +25,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#include "hw/core/sysemu-cpu-ops.h"
/* PSW define */
REG32(PSW, 0)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 60d434d5edd..2ca6a4f559f 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -28,6 +28,9 @@
#include "cpu-qom.h"
#include "cpu_models.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#define ELF_MACHINE_UNAME "S390X"
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 714e3b56413..07ed2f3e206 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -22,6 +22,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* CPU Subtypes */
#define SH_CPU_SH7750 (1 << 0)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4b2290650be..237ffc4fe66 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -4,6 +4,9 @@
#include "qemu/bswap.h"
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
#if !defined(TARGET_SPARC64)
#define TARGET_DPREGS 16
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 7d8e44d12e4..54bdbf0ca1e 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -22,6 +22,9 @@
#include "exec/cpu-defs.h"
#include "qom/object.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index b82349d1b10..cb0b989953e 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -23,6 +23,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "tricore-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
struct tricore_boot_info;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 7a32e086ed3..de475d0fc2e 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -14,6 +14,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
typedef struct CPUUniCore32State {
/* Regs for current mode. */
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 3bd4f691c1a..ea4ee5338f3 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -31,6 +31,9 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "xtensa-isa.h"
+#ifndef CONFIG_USER_ONLY
+#include "hw/core/sysemu-cpu-ops.h"
+#endif
/* Xtensa processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
diff --git a/cpu.c b/cpu.c
index 64e17537e21..29dafee581f 100644
--- a/cpu.c
+++ b/cpu.c
@@ -29,6 +29,7 @@
#ifdef CONFIG_USER_ONLY
#include "qemu.h"
#else
+#include "hw/core/sysemu-cpu-ops.h"
#include "exec/address-spaces.h"
#endif
#include "sysemu/tcg.h"
diff --git a/hw/core/cpu.c b/hw/core/cpu.c
index 7a8487d468f..da7543be514 100644
--- a/hw/core/cpu.c
+++ b/hw/core/cpu.c
@@ -35,6 +35,7 @@
#include "trace/trace-root.h"
#include "qemu/plugin.h"
#include "sysemu/hw_accel.h"
+#include "hw/core/sysemu-cpu-ops.h"
CPUState *cpu_by_arch_id(int64_t id)
{
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread
* [PATCH v3 17/27] linux-user: Remove dead code
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. This code is expanded as empty stub in "hw/core/cpu.h"
anyway, so we can drop it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/main.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 81f48ff54ed..d7af3ffbc22 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
CPUState *new_cpu = cpu_create(cpu_type);
CPUArchState *new_env = new_cpu->env_ptr;
CPUBreakpoint *bp;
- CPUWatchpoint *wp;
/* Reset non arch specific state */
cpu_reset(new_cpu);
@@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
QTAILQ_INIT(&new_cpu->breakpoints);
- QTAILQ_INIT(&new_cpu->watchpoints);
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
}
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
- }
return new_env;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 17/27] linux-user: Remove dead code
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
We can not use watchpoints in user-mode emulation because we
need the softmmu slow path to detect accesses to watchpointed
memory. This code is expanded as empty stub in "hw/core/cpu.h"
anyway, so we can drop it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/main.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 81f48ff54ed..d7af3ffbc22 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
CPUState *new_cpu = cpu_create(cpu_type);
CPUArchState *new_env = new_cpu->env_ptr;
CPUBreakpoint *bp;
- CPUWatchpoint *wp;
/* Reset non arch specific state */
cpu_reset(new_cpu);
@@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
QTAILQ_INIT(&new_cpu->breakpoints);
- QTAILQ_INIT(&new_cpu->watchpoints);
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
}
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
- }
return new_env;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* Re: [PATCH v3 17/27] linux-user: Remove dead code
2021-03-02 14:58 ` Philippe Mathieu-Daudé
@ 2021-03-03 15:17 ` Laurent Vivier
-1 siblings, 0 replies; 56+ messages in thread
From: Laurent Vivier @ 2021-03-03 15:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Sarah Harris, Cornelia Huck, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland, Thomas Huth,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, qemu-ppc,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Aleksandar Rikalo, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Chris Wulff, Palmer Dabbelt,
Paolo Bonzini, Aurelien Jarno
Le 02/03/2021 à 15:58, Philippe Mathieu-Daudé a écrit :
> We can not use watchpoints in user-mode emulation because we
> need the softmmu slow path to detect accesses to watchpointed
> memory. This code is expanded as empty stub in "hw/core/cpu.h"
> anyway, so we can drop it.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> linux-user/main.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 81f48ff54ed..d7af3ffbc22 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
> CPUState *new_cpu = cpu_create(cpu_type);
> CPUArchState *new_env = new_cpu->env_ptr;
> CPUBreakpoint *bp;
> - CPUWatchpoint *wp;
>
> /* Reset non arch specific state */
> cpu_reset(new_cpu);
> @@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
> Note: Once we support ptrace with hw-debug register access, make sure
> BP_CPU break/watchpoints are handled correctly on clone. */
> QTAILQ_INIT(&new_cpu->breakpoints);
> - QTAILQ_INIT(&new_cpu->watchpoints);
> QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
> }
> - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
> - cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
> - }
>
> return new_env;
> }
>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 56+ messages in thread* Re: [PATCH v3 17/27] linux-user: Remove dead code
@ 2021-03-03 15:17 ` Laurent Vivier
0 siblings, 0 replies; 56+ messages in thread
From: Laurent Vivier @ 2021-03-03 15:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Max Filippov, Taylor Simpson,
Alistair Francis, Edgar E. Iglesias, Guan Xuetao, Marek Vasut,
Yoshinori Sato, Michael S. Tsirkin, Claudio Fontana,
Palmer Dabbelt, Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, qemu-ppc,
Paolo Bonzini, Aurelien Jarno
Le 02/03/2021 à 15:58, Philippe Mathieu-Daudé a écrit :
> We can not use watchpoints in user-mode emulation because we
> need the softmmu slow path to detect accesses to watchpointed
> memory. This code is expanded as empty stub in "hw/core/cpu.h"
> anyway, so we can drop it.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> linux-user/main.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 81f48ff54ed..d7af3ffbc22 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -200,7 +200,6 @@ CPUArchState *cpu_copy(CPUArchState *env)
> CPUState *new_cpu = cpu_create(cpu_type);
> CPUArchState *new_env = new_cpu->env_ptr;
> CPUBreakpoint *bp;
> - CPUWatchpoint *wp;
>
> /* Reset non arch specific state */
> cpu_reset(new_cpu);
> @@ -211,13 +210,9 @@ CPUArchState *cpu_copy(CPUArchState *env)
> Note: Once we support ptrace with hw-debug register access, make sure
> BP_CPU break/watchpoints are handled correctly on clone. */
> QTAILQ_INIT(&new_cpu->breakpoints);
> - QTAILQ_INIT(&new_cpu->watchpoints);
> QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
> }
> - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
> - cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
> - }
>
> return new_env;
> }
>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 56+ messages in thread
* [PATCH v3 18/27] gdbstub: Remove watchpoint dead code in gdbserver_fork()
2021-03-02 14:57 ` Philippe Mathieu-Daudé
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Sarah Harris, Chris Wulff, Sagar Karandikar,
David Hildenbrand, Anthony Green, Mark Cave-Ayland,
Aleksandar Rikalo, Philippe Mathieu-Daudé,
Max Filippov, Taylor Simpson, Alistair Francis,
Edgar E. Iglesias, Guan Xuetao, Marek Vasut, Yoshinori Sato,
Michael S. Tsirkin, Claudio Fontana, Palmer Dabbelt,
Philippe Mathieu-Daudé,
Artyom Tarasenko, Thomas Huth, Eduardo Habkost,
Richard Henderson, Greg Kurz, qemu-s390x, qemu-arm,
Michael Rolnik, Stafford Horne, Alex Bennée, David Gibson,
qemu-riscv, Bastian Koppelmann, Cornelia Huck, Laurent Vivier,
Michael Walle, qemu-ppc, Paolo Bonzini, Aurelien Jarno
gdbserver_fork() is only used in user emulation where we can not
use watchpoints because we need the softmmu slow path to detect
accesses to watchpointed memory. This code doesn't do anything as
declared as stubs in "hw/core/cpu.h". Drop it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
gdbstub.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gdbstub.c b/gdbstub.c
index 759bb00bcf0..eee4301b5e6 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -3349,7 +3349,6 @@ void gdbserver_fork(CPUState *cpu)
close(gdbserver_state.fd);
gdbserver_state.fd = -1;
cpu_breakpoint_remove_all(cpu, BP_GDB);
- cpu_watchpoint_remove_all(cpu, BP_GDB);
}
#else
static int gdb_chr_can_receive(void *opaque)
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread* [PATCH v3 18/27] gdbstub: Remove watchpoint dead code in gdbserver_fork()
@ 2021-03-02 14:58 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 56+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-03-02 14:58 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, qemu-arm, Max Filippov, David Gibson,
Edgar E. Iglesias, Philippe Mathieu-Daudé,
Guan Xuetao, Alistair Francis, Michael Rolnik, Palmer Dabbelt,
Richard Henderson, Laurent Vivier, Paolo Bonzini, Greg Kurz,
Stafford Horne, qemu-ppc, Anthony Green, Aurelien Jarno,
Jiaxun Yang, Cornelia Huck, Claudio Fontana, Sagar Karandikar,
Alex Bennée, Michael Walle, Marek Vasut, Marcel Apfelbaum,
Artyom Tarasenko, Peter Maydell, Aleksandar Rikalo, Chris Wulff,
David Hildenbrand, Philippe Mathieu-Daudé,
qemu-s390x, Sarah Harris, Eduardo Habkost, Bastian Koppelmann,
qemu-riscv, Mark Cave-Ayland, Michael S. Tsirkin, Yoshinori Sato,
Taylor Simpson
gdbserver_fork() is only used in user emulation where we can not
use watchpoints because we need the softmmu slow path to detect
accesses to watchpointed memory. This code doesn't do anything as
declared as stubs in "hw/core/cpu.h". Drop it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
gdbstub.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gdbstub.c b/gdbstub.c
index 759bb00bcf0..eee4301b5e6 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -3349,7 +3349,6 @@ void gdbserver_fork(CPUState *cpu)
close(gdbserver_state.fd);
gdbserver_state.fd = -1;
cpu_breakpoint_remove_all(cpu, BP_GDB);
- cpu_watchpoint_remove_all(cpu, BP_GDB);
}
#else
static int gdb_chr_can_receive(void *opaque)
--
2.26.2
^ permalink raw reply related [flat|nested] 56+ messages in thread