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From: Peter Maydell <peter.maydell@linaro.org>
To: Andrew Jones <drjones@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>,
	xu910121@sina.com, Dave Martin <Dave.Martin@arm.com>,
	kvmarm <kvmarm@lists.cs.columbia.edu>,
	qemu-devel <qemu-devel@nongnu.org>
Subject: Re: Kernel patch cases qemu live migration failed.
Date: Mon, 19 Oct 2020 15:18:11 +0100	[thread overview]
Message-ID: <CAFEAcA8RB6MTnv0qavxWs28=pbT16i9dT1pd+0Dy9HxPVk+bZA@mail.gmail.com> (raw)
In-Reply-To: <20201019134043.vqusmzhqp7owjt6x@kamzik.brq.redhat.com>

On Mon, 19 Oct 2020 at 14:40, Andrew Jones <drjones@redhat.com> wrote:
>
> On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote:
> > Well, ID regs are special in the architecture -- they always exist
> > and must RAZ/WI, even if they're not actually given any fields yet.
> > This is different from other "unused" parts of the system register
> > encoding space, which UNDEF.
>
> Table D12-2 confirms the register should be RAZ, as it says the register
> is "RO, but RAZ if SVE is not implemented". Does "RO" imply "WI", though?
> For the guest we inject an exception on writes, and for userspace we
> require the value to be preserved on write.

Sorry, I mis-spoke. They're RAZ, but not WI, just RO (which is to say
they'll UNDEF if you try to write to them).

> I think we should follow the spec, even for userspace access, and be RAZ
> for when the feature isn't implemented. As for writes, assuming the
> exception injection is what we want for the guest (not WI), then that's
> correct. For userspace, I think we should continue forcing preservation
> (which will force preservation of zero when it's RAZ).

Yes, that sounds right.

thanks
-- PMM


WARNING: multiple messages have this Message-ID (diff)
From: Peter Maydell <peter.maydell@linaro.org>
To: Andrew Jones <drjones@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>,
	xu910121@sina.com, Dave Martin <Dave.Martin@arm.com>,
	kvmarm <kvmarm@lists.cs.columbia.edu>,
	qemu-devel <qemu-devel@nongnu.org>
Subject: Re: Kernel patch cases qemu live migration failed.
Date: Mon, 19 Oct 2020 15:18:11 +0100	[thread overview]
Message-ID: <CAFEAcA8RB6MTnv0qavxWs28=pbT16i9dT1pd+0Dy9HxPVk+bZA@mail.gmail.com> (raw)
In-Reply-To: <20201019134043.vqusmzhqp7owjt6x@kamzik.brq.redhat.com>

On Mon, 19 Oct 2020 at 14:40, Andrew Jones <drjones@redhat.com> wrote:
>
> On Mon, Oct 19, 2020 at 12:43:33PM +0100, Peter Maydell wrote:
> > Well, ID regs are special in the architecture -- they always exist
> > and must RAZ/WI, even if they're not actually given any fields yet.
> > This is different from other "unused" parts of the system register
> > encoding space, which UNDEF.
>
> Table D12-2 confirms the register should be RAZ, as it says the register
> is "RO, but RAZ if SVE is not implemented". Does "RO" imply "WI", though?
> For the guest we inject an exception on writes, and for userspace we
> require the value to be preserved on write.

Sorry, I mis-spoke. They're RAZ, but not WI, just RO (which is to say
they'll UNDEF if you try to write to them).

> I think we should follow the spec, even for userspace access, and be RAZ
> for when the feature isn't implemented. As for writes, assuming the
> exception injection is what we want for the guest (not WI), then that's
> correct. For userspace, I think we should continue forcing preservation
> (which will force preservation of zero when it's RAZ).

Yes, that sounds right.

thanks
-- PMM
_______________________________________________
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  reply	other threads:[~2020-10-19 14:19 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-15  4:06 Kernel patch cases qemu live migration failed 张东旭
2020-10-15  4:06 ` 张东旭
2020-10-15 11:26 ` Marc Zyngier
2020-10-15 11:26   ` Marc Zyngier
2020-10-15 13:35   ` Andrew Jones
2020-10-15 13:35     ` Andrew Jones
2020-10-15 13:52     ` Marc Zyngier
2020-10-15 13:52       ` Marc Zyngier
2020-10-15 14:41       ` Andrew Jones
2020-10-15 14:41         ` Andrew Jones
2020-10-15 14:57         ` Peter Maydell
2020-10-15 14:57           ` Peter Maydell
2020-10-19  9:25           ` Andrew Jones
2020-10-19  9:25             ` Andrew Jones
2020-10-19 11:32             ` Dave Martin
2020-10-19 11:32               ` Dave Martin
2020-10-19 11:43               ` Peter Maydell
2020-10-19 11:43                 ` Peter Maydell
2020-10-19 13:40                 ` Andrew Jones
2020-10-19 13:40                   ` Andrew Jones
2020-10-19 14:18                   ` Peter Maydell [this message]
2020-10-19 14:18                     ` Peter Maydell
2020-10-19 14:58                     ` Dave Martin
2020-10-19 14:58                       ` Dave Martin
2020-10-19 15:23                       ` Andrew Jones
2020-10-19 15:23                         ` Andrew Jones
2020-10-19 16:36                         ` Dave Martin
2020-10-19 16:36                           ` Dave Martin
2020-10-15 13:26 ` Andrew Jones
2020-10-15 13:26   ` Andrew Jones

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