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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm <qemu-arm@nongnu.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Alex Bennée" <alex.bennee@linaro.org>
Cc: Michael Davidsaver <mdavidsaver@gmail.com>,
	"patches@linaro.org" <patches@linaro.org>
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] arm: Fix M profile MSR/MRS
Date: Sat, 18 Mar 2017 17:36:28 +0000	[thread overview]
Message-ID: <CAFEAcA8RHNf-f4iLOJ_i1r+5fAXdaGL4q7fPfzMgSZAf-T2DzA@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-j1NSm=_H=V5xJNx=Hv3_P7M+UdVB6gMpL-dS+5NXL1Q@mail.gmail.com>

Last ping for review; otherwise I'll put them into rc1 anyway
since it's fixing a regression.

thanks
-- PMM

On 14 March 2017 at 11:52, Peter Maydell <peter.maydell@linaro.org> wrote:
> Ping for review -- since this is a bugfix it should go
> into 2.9.
>
> thanks
> -- PMM
>
> On 20 February 2017 at 19:41, Peter Maydell <peter.maydell@linaro.org> wrote:
>> This patchseries fixes up some deficiencies and one nasty
>> bug in the M profile MSR/MRS handling.
>>
>> The first three patches are just cleaning up the decode
>> so that we UNDEF where we should in the MRS/MSR space
>> for M profile -- this won't have caused any problems in
>> practice since real world code doesn't generally execute
>> UNDEFfing instructions on purpose.
>>
>> The fourth patch fixes a nasty bug that I introduced in
>> commit 58117c9bb429cd which broke APSR writes via MSR,
>> and brings them into line with the pseudocode by allowing
>> writes to the APSR GE[3:0] bits when the CPU implements
>> the DSP extensions.
>>
>> Alex -- I should have paid closer attention to your review
>> comments on the patch that became commit 58117c9bb429cd;
>> sorry about that. I knew we didn't get the GE[3:0] stuff
>> right yet but I didn't spot that we'd managed to invert
>> the sense of the SYSm bit 2 test in that patch :-(
>>
>> thanks
>> -- PMM
>>
>> Peter Maydell (4):
>>   arm: HVC and SMC encodings don't exist for M profile
>>   arm: Don't decode MRS(banked) or MSR(banked) for M profile
>>   arm: Enforce should-be-1 bits in MRS decoding
>>   arm: Fix APSR writes via M profile MSR
>>
>>  target/arm/helper.c    | 26 ++++++++++++++++++++++----
>>  target/arm/translate.c | 26 +++++++++++++++++++++++---
>>  2 files changed, 45 insertions(+), 7 deletions(-)

      reply	other threads:[~2017-03-18 17:36 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-20 18:41 [Qemu-devel] [PATCH 0/4] arm: Fix M profile MSR/MRS Peter Maydell
2017-02-20 18:41 ` [Qemu-devel] [PATCH 1/4] arm: HVC and SMC encodings don't exist for M profile Peter Maydell
2017-03-20 10:48   ` Alex Bennée
2017-02-20 18:41 ` [Qemu-devel] [PATCH 2/4] arm: Don't decode MRS(banked) or MSR(banked) " Peter Maydell
2017-03-20 10:57   ` Alex Bennée
2017-03-20 11:05     ` Peter Maydell
2017-02-20 18:41 ` [Qemu-devel] [PATCH 3/4] arm: Enforce should-be-1 bits in MRS decoding Peter Maydell
2017-03-20 10:59   ` Alex Bennée
2017-02-20 18:41 ` [Qemu-devel] [PATCH 4/4] arm: Fix APSR writes via M profile MSR Peter Maydell
2017-03-20 11:01   ` Alex Bennée
2017-03-14 11:52 ` [Qemu-devel] [Qemu-arm] [PATCH 0/4] arm: Fix M profile MSR/MRS Peter Maydell
2017-03-18 17:36   ` Peter Maydell [this message]

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